hw/ppc/ppc440_uc.c

   1 /*
   2  * QEMU PowerPC 440 embedded processors emulation
   3  *
   4  * Copyright (c) 2012 François Revol
   5  * Copyright (c) 2016-2019 BALATON Zoltan
   6  *
   7  * This work is licensed under the GNU GPL license version 2 or later.
   8  *
   9  */
  10
  11 #include "qemu/osdep.h"
  12 #include "qemu/units.h"
  13 #include "qemu/error-report.h"
  14 #include "qapi/error.h"
  15 #include "qemu/log.h"
  16 #include "qemu/module.h"
  17 #include "hw/irq.h"
  18 #include "exec/memory.h"
  19 #include "cpu.h"
  20 #include "hw/ppc/ppc4xx.h"
  21 #include "hw/qdev-properties.h"
  22 #include "hw/pci/pci.h"
  23 #include "sysemu/block-backend.h"
  24 #include "sysemu/reset.h"
  25 #include "ppc440.h"
  26 #include "qom/object.h"
  27 #include "trace.h"
  28
  29 /*****************************************************************************/
  30 /* L2 Cache as SRAM */
  31 /* FIXME:fix names */
  32 enum {
  33     DCR_L2CACHE_BASE  = 0x30,
  34     DCR_L2CACHE_CFG   = DCR_L2CACHE_BASE,
  35     DCR_L2CACHE_CMD,
  36     DCR_L2CACHE_ADDR,
  37     DCR_L2CACHE_DATA,
  38     DCR_L2CACHE_STAT,
  39     DCR_L2CACHE_CVER,
  40     DCR_L2CACHE_SNP0,
  41     DCR_L2CACHE_SNP1,
  42     DCR_L2CACHE_END   = DCR_L2CACHE_SNP1,
  43 };
  44
  45 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */
  46 enum {
  47     DCR_ISRAM0_BASE   = 0x20,
  48     DCR_ISRAM0_SB0CR  = DCR_ISRAM0_BASE,
  49     DCR_ISRAM0_SB1CR,
  50     DCR_ISRAM0_SB2CR,
  51     DCR_ISRAM0_SB3CR,
  52     DCR_ISRAM0_BEAR,
  53     DCR_ISRAM0_BESR0,
  54     DCR_ISRAM0_BESR1,
  55     DCR_ISRAM0_PMEG,
  56     DCR_ISRAM0_CID,
  57     DCR_ISRAM0_REVID,
  58     DCR_ISRAM0_DPC,
  59     DCR_ISRAM0_END    = DCR_ISRAM0_DPC
  60 };
  61
  62 enum {
  63     DCR_ISRAM1_BASE   = 0xb0,
  64     DCR_ISRAM1_SB0CR  = DCR_ISRAM1_BASE,
  65     /* single bank */
  66     DCR_ISRAM1_BEAR   = DCR_ISRAM1_BASE + 0x04,
  67     DCR_ISRAM1_BESR0,
  68     DCR_ISRAM1_BESR1,
  69     DCR_ISRAM1_PMEG,
  70     DCR_ISRAM1_CID,
  71     DCR_ISRAM1_REVID,
  72     DCR_ISRAM1_DPC,
  73     DCR_ISRAM1_END    = DCR_ISRAM1_DPC
  74 };
  75
  76 typedef struct ppc4xx_l2sram_t {
  77     MemoryRegion bank[4];
  78     uint32_t l2cache[8];
  79     uint32_t isram0[11];
  80 } ppc4xx_l2sram_t;
  81
  82 #ifdef MAP_L2SRAM
  83 static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram,
  84                                    uint32_t isarc, uint32_t isacntl,
  85                                    uint32_t dsarc, uint32_t dsacntl)
  86 {
  87     if (l2sram->isarc != isarc ||
  88         (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
  89         if (l2sram->isacntl & 0x80000000) {
  90             /* Unmap previously assigned memory region */
  91             memory_region_del_subregion(get_system_memory(),
  92                                         &l2sram->isarc_ram);
  93         }
  94         if (isacntl & 0x80000000) {
  95             /* Map new instruction memory region */
  96             memory_region_add_subregion(get_system_memory(), isarc,
  97                                         &l2sram->isarc_ram);
  98         }
  99     }
 100     if (l2sram->dsarc != dsarc ||
 101         (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
 102         if (l2sram->dsacntl & 0x80000000) {
 103             /* Beware not to unmap the region we just mapped */
 104             if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) {
 105                 /* Unmap previously assigned memory region */
 106                 memory_region_del_subregion(get_system_memory(),
 107                                             &l2sram->dsarc_ram);
 108             }
 109         }
 110         if (dsacntl & 0x80000000) {
 111             /* Beware not to remap the region we just mapped */
 112             if (!(isacntl & 0x80000000) || dsarc != isarc) {
 113                 /* Map new data memory region */
 114                 memory_region_add_subregion(get_system_memory(), dsarc,
 115                                             &l2sram->dsarc_ram);
 116             }
 117         }
 118     }
 119 }
 120 #endif
 121
 122 static uint32_t dcr_read_l2sram(void *opaque, int dcrn)
 123 {
 124     ppc4xx_l2sram_t *l2sram = opaque;
 125     uint32_t ret = 0;
 126
 127     switch (dcrn) {
 128     case DCR_L2CACHE_CFG:
 129     case DCR_L2CACHE_CMD:
 130     case DCR_L2CACHE_ADDR:
 131     case DCR_L2CACHE_DATA:
 132     case DCR_L2CACHE_STAT:
 133     case DCR_L2CACHE_CVER:
 134     case DCR_L2CACHE_SNP0:
 135     case DCR_L2CACHE_SNP1:
 136         ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE];
 137         break;
 138
 139     case DCR_ISRAM0_SB0CR:
 140     case DCR_ISRAM0_SB1CR:
 141     case DCR_ISRAM0_SB2CR:
 142     case DCR_ISRAM0_SB3CR:
 143     case DCR_ISRAM0_BEAR:
 144     case DCR_ISRAM0_BESR0:
 145     case DCR_ISRAM0_BESR1:
 146     case DCR_ISRAM0_PMEG:
 147     case DCR_ISRAM0_CID:
 148     case DCR_ISRAM0_REVID:
 149     case DCR_ISRAM0_DPC:
 150         ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE];
 151         break;
 152
 153     default:
 154         break;
 155     }
 156
 157     return ret;
 158 }
 159
 160 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val)
 161 {
 162     /*ppc4xx_l2sram_t *l2sram = opaque;*/
 163     /* FIXME: Actually handle L2 cache mapping */
 164
 165     switch (dcrn) {
 166     case DCR_L2CACHE_CFG:
 167     case DCR_L2CACHE_CMD:
 168     case DCR_L2CACHE_ADDR:
 169     case DCR_L2CACHE_DATA:
 170     case DCR_L2CACHE_STAT:
 171     case DCR_L2CACHE_CVER:
 172     case DCR_L2CACHE_SNP0:
 173     case DCR_L2CACHE_SNP1:
 174         /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/
 175         break;
 176
 177     case DCR_ISRAM0_SB0CR:
 178     case DCR_ISRAM0_SB1CR:
 179     case DCR_ISRAM0_SB2CR:
 180     case DCR_ISRAM0_SB3CR:
 181     case DCR_ISRAM0_BEAR:
 182     case DCR_ISRAM0_BESR0:
 183     case DCR_ISRAM0_BESR1:
 184     case DCR_ISRAM0_PMEG:
 185     case DCR_ISRAM0_CID:
 186     case DCR_ISRAM0_REVID:
 187     case DCR_ISRAM0_DPC:
 188         /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/
 189         break;
 190
 191     case DCR_ISRAM1_SB0CR:
 192     case DCR_ISRAM1_BEAR:
 193     case DCR_ISRAM1_BESR0:
 194     case DCR_ISRAM1_BESR1:
 195     case DCR_ISRAM1_PMEG:
 196     case DCR_ISRAM1_CID:
 197     case DCR_ISRAM1_REVID:
 198     case DCR_ISRAM1_DPC:
 199         /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/
 200         break;
 201     }
 202     /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
 203 }
 204
 205 static void l2sram_reset(void *opaque)
 206 {
 207     ppc4xx_l2sram_t *l2sram = opaque;
 208
 209     memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache));
 210     l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000;
 211     memset(l2sram->isram0, 0, sizeof(l2sram->isram0));
 212     /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/
 213 }
 214
 215 void ppc4xx_l2sram_init(CPUPPCState *env)
 216 {
 217     ppc4xx_l2sram_t *l2sram;
 218
 219     l2sram = g_malloc0(sizeof(*l2sram));
 220     /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */
 221     memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0",
 222                            64 * KiB, &error_abort);
 223     memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1",
 224                            64 * KiB, &error_abort);
 225     memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2",
 226                            64 * KiB, &error_abort);
 227     memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3",
 228                            64 * KiB, &error_abort);
 229     qemu_register_reset(&l2sram_reset, l2sram);
 230     ppc_dcr_register(env, DCR_L2CACHE_CFG,
 231                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 232     ppc_dcr_register(env, DCR_L2CACHE_CMD,
 233                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 234     ppc_dcr_register(env, DCR_L2CACHE_ADDR,
 235                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 236     ppc_dcr_register(env, DCR_L2CACHE_DATA,
 237                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 238     ppc_dcr_register(env, DCR_L2CACHE_STAT,
 239                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 240     ppc_dcr_register(env, DCR_L2CACHE_CVER,
 241                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 242     ppc_dcr_register(env, DCR_L2CACHE_SNP0,
 243                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 244     ppc_dcr_register(env, DCR_L2CACHE_SNP1,
 245                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 246
 247     ppc_dcr_register(env, DCR_ISRAM0_SB0CR,
 248                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 249     ppc_dcr_register(env, DCR_ISRAM0_SB1CR,
 250                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 251     ppc_dcr_register(env, DCR_ISRAM0_SB2CR,
 252                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 253     ppc_dcr_register(env, DCR_ISRAM0_SB3CR,
 254                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 255     ppc_dcr_register(env, DCR_ISRAM0_PMEG,
 256                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 257     ppc_dcr_register(env, DCR_ISRAM0_DPC,
 258                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 259
 260     ppc_dcr_register(env, DCR_ISRAM1_SB0CR,
 261                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 262     ppc_dcr_register(env, DCR_ISRAM1_PMEG,
 263                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 264     ppc_dcr_register(env, DCR_ISRAM1_DPC,
 265                      l2sram, &dcr_read_l2sram, &dcr_write_l2sram);
 266 }
 267
 268 /*****************************************************************************/
 269 /* Clocking Power on Reset */
 270 enum {
 271     CPR0_CFGADDR = 0xC,
 272     CPR0_CFGDATA = 0xD,
 273
 274     CPR0_PLLD = 0x060,
 275     CPR0_PLBED = 0x080,
 276     CPR0_OPBD = 0x0C0,
 277     CPR0_PERD = 0x0E0,
 278     CPR0_AHBD = 0x100,
 279 };
 280
 281 typedef struct ppc4xx_cpr_t {
 282     uint32_t addr;
 283 } ppc4xx_cpr_t;
 284
 285 static uint32_t dcr_read_cpr(void *opaque, int dcrn)
 286 {
 287     ppc4xx_cpr_t *cpr = opaque;
 288     uint32_t ret = 0;
 289
 290     switch (dcrn) {
 291     case CPR0_CFGADDR:
 292         ret = cpr->addr;
 293         break;
 294     case CPR0_CFGDATA:
 295         switch (cpr->addr) {
 296         case CPR0_PLLD:
 297             ret = (0xb5 << 24) | (1 << 16) | (9 << 8);
 298             break;
 299         case CPR0_PLBED:
 300             ret = (5 << 24);
 301             break;
 302         case CPR0_OPBD:
 303             ret = (2 << 24);
 304             break;
 305         case CPR0_PERD:
 306         case CPR0_AHBD:
 307             ret = (1 << 24);
 308             break;
 309         default:
 310             break;
 311         }
 312         break;
 313     default:
 314         break;
 315     }
 316
 317     return ret;
 318 }
 319
 320 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val)
 321 {
 322     ppc4xx_cpr_t *cpr = opaque;
 323
 324     switch (dcrn) {
 325     case CPR0_CFGADDR:
 326         cpr->addr = val;
 327         break;
 328     case CPR0_CFGDATA:
 329         break;
 330     default:
 331         break;
 332     }
 333 }
 334
 335 static void ppc4xx_cpr_reset(void *opaque)
 336 {
 337     ppc4xx_cpr_t *cpr = opaque;
 338
 339     cpr->addr = 0;
 340 }
 341
 342 void ppc4xx_cpr_init(CPUPPCState *env)
 343 {
 344     ppc4xx_cpr_t *cpr;
 345
 346     cpr = g_malloc0(sizeof(*cpr));
 347     ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr);
 348     ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr);
 349     qemu_register_reset(ppc4xx_cpr_reset, cpr);
 350 }
 351
 352 /*****************************************************************************/
 353 /* System DCRs */
 354 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t;
 355 struct ppc4xx_sdr_t {
 356     uint32_t addr;
 357 };
 358
 359 enum {
 360     SDR0_CFGADDR = 0x00e,
 361     SDR0_CFGDATA,
 362     SDR0_STRP0 = 0x020,
 363     SDR0_STRP1,
 364     SDR0_102 = 0x66,
 365     SDR0_103,
 366     SDR0_128 = 0x80,
 367     SDR0_ECID3 = 0x083,
 368     SDR0_DDR0 = 0x0e1,
 369     SDR0_USB0 = 0x320,
 370 };
 371
 372 enum {
 373     PESDR0_LOOP = 0x303,
 374     PESDR0_RCSSET,
 375     PESDR0_RCSSTS,
 376     PESDR0_RSTSTA = 0x310,
 377     PESDR1_LOOP = 0x343,
 378     PESDR1_RCSSET,
 379     PESDR1_RCSSTS,
 380     PESDR1_RSTSTA = 0x365,
 381 };
 382
 383 #define SDR0_DDR0_DDRM_ENCODE(n)  ((((unsigned long)(n)) & 0x03) << 29)
 384 #define SDR0_DDR0_DDRM_DDR1       0x20000000
 385 #define SDR0_DDR0_DDRM_DDR2       0x40000000
 386
 387 static uint32_t dcr_read_sdr(void *opaque, int dcrn)
 388 {
 389     ppc4xx_sdr_t *sdr = opaque;
 390     uint32_t ret = 0;
 391
 392     switch (dcrn) {
 393     case SDR0_CFGADDR:
 394         ret = sdr->addr;
 395         break;
 396     case SDR0_CFGDATA:
 397         switch (sdr->addr) {
 398         case SDR0_STRP0:
 399             ret = (0xb5 << 8) | (1 << 4) | 9;
 400             break;
 401         case SDR0_STRP1:
 402             ret = (5 << 29) | (2 << 26) | (1 << 24);
 403             break;
 404         case SDR0_ECID3:
 405             ret = 1 << 20; /* No Security/Kasumi support */
 406             break;
 407         case SDR0_DDR0:
 408             ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
 409             break;
 410         case PESDR0_RCSSET:
 411         case PESDR1_RCSSET:
 412             ret = (1 << 24) | (1 << 16);
 413             break;
 414         case PESDR0_RCSSTS:
 415         case PESDR1_RCSSTS:
 416             ret = (1 << 16) | (1 << 12);
 417             break;
 418         case PESDR0_RSTSTA:
 419         case PESDR1_RSTSTA:
 420             ret = 1;
 421             break;
 422         case PESDR0_LOOP:
 423         case PESDR1_LOOP:
 424             ret = 1 << 12;
 425             break;
 426         default:
 427             break;
 428         }
 429         break;
 430     default:
 431         break;
 432     }
 433
 434     return ret;
 435 }
 436
 437 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val)
 438 {
 439     ppc4xx_sdr_t *sdr = opaque;
 440
 441     switch (dcrn) {
 442     case SDR0_CFGADDR:
 443         sdr->addr = val;
 444         break;
 445     case SDR0_CFGDATA:
 446         switch (sdr->addr) {
 447         case 0x00: /* B0CR */
 448             break;
 449         default:
 450             break;
 451         }
 452         break;
 453     default:
 454         break;
 455     }
 456 }
 457
 458 static void sdr_reset(void *opaque)
 459 {
 460     ppc4xx_sdr_t *sdr = opaque;
 461
 462     sdr->addr = 0;
 463 }
 464
 465 void ppc4xx_sdr_init(CPUPPCState *env)
 466 {
 467     ppc4xx_sdr_t *sdr;
 468
 469     sdr = g_malloc0(sizeof(*sdr));
 470     qemu_register_reset(&sdr_reset, sdr);
 471     ppc_dcr_register(env, SDR0_CFGADDR,
 472                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 473     ppc_dcr_register(env, SDR0_CFGDATA,
 474                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 475     ppc_dcr_register(env, SDR0_102,
 476                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 477     ppc_dcr_register(env, SDR0_103,
 478                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 479     ppc_dcr_register(env, SDR0_128,
 480                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 481     ppc_dcr_register(env, SDR0_USB0,
 482                      sdr, &dcr_read_sdr, &dcr_write_sdr);
 483 }
 484
 485 /*****************************************************************************/
 486 /* SDRAM controller */
 487 typedef struct ppc440_sdram_t {
 488     uint32_t addr;
 489     uint32_t mcopt2;
 490     int nbanks;
 491     Ppc4xxSdramBank bank[4];
 492 } ppc440_sdram_t;
 493
 494 enum {
 495     SDRAM0_CFGADDR = 0x10,
 496     SDRAM0_CFGDATA,
 497     SDRAM_R0BAS = 0x40,
 498     SDRAM_R1BAS,
 499     SDRAM_R2BAS,
 500     SDRAM_R3BAS,
 501     SDRAM_CONF1HB = 0x45,
 502     SDRAM_PLBADDULL = 0x4a,
 503     SDRAM_CONF1LL = 0x4b,
 504     SDRAM_CONFPATHB = 0x4f,
 505     SDRAM_PLBADDUHB = 0x50,
 506 };
 507
 508 static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size)
 509 {
 510     uint32_t bcr;
 511
 512     switch (ram_size) {
 513     case (8 * MiB):
 514         bcr = 0xffc0;
 515         break;
 516     case (16 * MiB):
 517         bcr = 0xff80;
 518         break;
 519     case (32 * MiB):
 520         bcr = 0xff00;
 521         break;
 522     case (64 * MiB):
 523         bcr = 0xfe00;
 524         break;
 525     case (128 * MiB):
 526         bcr = 0xfc00;
 527         break;
 528     case (256 * MiB):
 529         bcr = 0xf800;
 530         break;
 531     case (512 * MiB):
 532         bcr = 0xf000;
 533         break;
 534     case (1 * GiB):
 535         bcr = 0xe000;
 536         break;
 537     case (2 * GiB):
 538         bcr = 0xc000;
 539         break;
 540     case (4 * GiB):
 541         bcr = 0x8000;
 542         break;
 543     default:
 544         error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
 545         return 0;
 546     }
 547     bcr |= ram_base >> 2 & 0xffe00000;
 548     bcr |= 1;
 549
 550     return bcr;
 551 }
 552
 553 static inline hwaddr sdram_base(uint32_t bcr)
 554 {
 555     return (bcr & 0xffe00000) << 2;
 556 }
 557
 558 static uint64_t sdram_size(uint32_t bcr)
 559 {
 560     uint64_t size;
 561     int sh;
 562
 563     sh = 1024 - ((bcr >> 6) & 0x3ff);
 564     size = 8 * MiB * sh;
 565
 566     return size;
 567 }
 568
 569 static void sdram_bank_map(Ppc4xxSdramBank *bank)
 570 {
 571     memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
 572     memory_region_add_subregion(&bank->container, 0, &bank->ram);
 573     memory_region_add_subregion(get_system_memory(), bank->base,
 574                                 &bank->container);
 575 }
 576
 577 static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
 578 {
 579     memory_region_del_subregion(get_system_memory(), &bank->container);
 580     memory_region_del_subregion(&bank->container, &bank->ram);
 581     object_unparent(OBJECT(&bank->container));
 582 }
 583
 584 static void sdram_set_bcr(ppc440_sdram_t *sdram, int i,
 585                           uint32_t bcr, int enabled)
 586 {
 587     if (sdram->bank[i].bcr & 1) {
 588         /* First unmap RAM if enabled */
 589         trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr),
 590                                  sdram_size(sdram->bank[i].bcr));
 591         sdram_bank_unmap(&sdram->bank[i]);
 592     }
 593     sdram->bank[i].bcr = bcr & 0xffe0ffc1;
 594     if (enabled && (bcr & 1)) {
 595         trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr));
 596         sdram_bank_map(&sdram->bank[i]);
 597     }
 598 }
 599
 600 static void sdram_map_bcr(ppc440_sdram_t *sdram)
 601 {
 602     int i;
 603
 604     for (i = 0; i < sdram->nbanks; i++) {
 605         if (sdram->bank[i].size) {
 606             sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base,
 607                                               sdram->bank[i].size), 1);
 608         } else {
 609             sdram_set_bcr(sdram, i, 0, 0);
 610         }
 611     }
 612 }
 613
 614 static void sdram_unmap_bcr(ppc440_sdram_t *sdram)
 615 {
 616     int i;
 617
 618     for (i = 0; i < sdram->nbanks; i++) {
 619         if (sdram->bank[i].size) {
 620             sdram_set_bcr(sdram, i, sdram->bank[i].bcr & ~1, 0);
 621         }
 622     }
 623 }
 624
 625 static uint32_t dcr_read_sdram(void *opaque, int dcrn)
 626 {
 627     ppc440_sdram_t *sdram = opaque;
 628     uint32_t ret = 0;
 629
 630     switch (dcrn) {
 631     case SDRAM_R0BAS:
 632     case SDRAM_R1BAS:
 633     case SDRAM_R2BAS:
 634     case SDRAM_R3BAS:
 635         if (sdram->bank[dcrn - SDRAM_R0BAS].size) {
 636             ret = sdram_bcr(sdram->bank[dcrn - SDRAM_R0BAS].base,
 637                             sdram->bank[dcrn - SDRAM_R0BAS].size);
 638         }
 639         break;
 640     case SDRAM_CONF1HB:
 641     case SDRAM_CONF1LL:
 642     case SDRAM_CONFPATHB:
 643     case SDRAM_PLBADDULL:
 644     case SDRAM_PLBADDUHB:
 645         break;
 646     case SDRAM0_CFGADDR:
 647         ret = sdram->addr;
 648         break;
 649     case SDRAM0_CFGDATA:
 650         switch (sdram->addr) {
 651         case 0x14: /* SDRAM_MCSTAT (405EX) */
 652         case 0x1F:
 653             ret = 0x80000000;
 654             break;
 655         case 0x21: /* SDRAM_MCOPT2 */
 656             ret = sdram->mcopt2;
 657             break;
 658         case 0x40: /* SDRAM_MB0CF */
 659             ret = 0x00008001;
 660             break;
 661         case 0x7A: /* SDRAM_DLCR */
 662             ret = 0x02000000;
 663             break;
 664         case 0xE1: /* SDR0_DDR0 */
 665             ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
 666             break;
 667         default:
 668             break;
 669         }
 670         break;
 671     default:
 672         break;
 673     }
 674
 675     return ret;
 676 }
 677
 678 #define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
 679
 680 static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val)
 681 {
 682     ppc440_sdram_t *sdram = opaque;
 683
 684     switch (dcrn) {
 685     case SDRAM_R0BAS:
 686     case SDRAM_R1BAS:
 687     case SDRAM_R2BAS:
 688     case SDRAM_R3BAS:
 689     case SDRAM_CONF1HB:
 690     case SDRAM_CONF1LL:
 691     case SDRAM_CONFPATHB:
 692     case SDRAM_PLBADDULL:
 693     case SDRAM_PLBADDUHB:
 694         break;
 695     case SDRAM0_CFGADDR:
 696         sdram->addr = val;
 697         break;
 698     case SDRAM0_CFGDATA:
 699         switch (sdram->addr) {
 700         case 0x00: /* B0CR */
 701             break;
 702         case 0x21: /* SDRAM_MCOPT2 */
 703             if (!(sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
 704                 (val & SDRAM_DDR2_MCOPT2_DCEN)) {
 705                 trace_ppc4xx_sdram_enable("enable");
 706                 /* validate all RAM mappings */
 707                 sdram_map_bcr(sdram);
 708                 sdram->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
 709             } else if ((sdram->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
 710                        !(val & SDRAM_DDR2_MCOPT2_DCEN)) {
 711                 trace_ppc4xx_sdram_enable("disable");
 712                 /* invalidate all RAM mappings */
 713                 sdram_unmap_bcr(sdram);
 714                 sdram->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
 715             }
 716             break;
 717         default:
 718             break;
 719         }
 720         break;
 721     default:
 722         break;
 723     }
 724 }
 725
 726 static void sdram_reset(void *opaque)
 727 {
 728     ppc440_sdram_t *sdram = opaque;
 729
 730     sdram->addr = 0;
 731     sdram->mcopt2 = 0;
 732 }
 733
 734 void ppc440_sdram_init(CPUPPCState *env, int nbanks,
 735                        Ppc4xxSdramBank *ram_banks)
 736 {
 737     ppc440_sdram_t *s;
 738     int i;
 739
 740     s = g_malloc0(sizeof(*s));
 741     s->nbanks = nbanks;
 742     for (i = 0; i < nbanks; i++) {
 743         s->bank[i].ram = ram_banks[i].ram;
 744         s->bank[i].base = ram_banks[i].base;
 745         s->bank[i].size = ram_banks[i].size;
 746     }
 747     qemu_register_reset(&sdram_reset, s);
 748     ppc_dcr_register(env, SDRAM0_CFGADDR,
 749                      s, &dcr_read_sdram, &dcr_write_sdram);
 750     ppc_dcr_register(env, SDRAM0_CFGDATA,
 751                      s, &dcr_read_sdram, &dcr_write_sdram);
 752
 753     ppc_dcr_register(env, SDRAM_R0BAS,
 754                      s, &dcr_read_sdram, &dcr_write_sdram);
 755     ppc_dcr_register(env, SDRAM_R1BAS,
 756                      s, &dcr_read_sdram, &dcr_write_sdram);
 757     ppc_dcr_register(env, SDRAM_R2BAS,
 758                      s, &dcr_read_sdram, &dcr_write_sdram);
 759     ppc_dcr_register(env, SDRAM_R3BAS,
 760                      s, &dcr_read_sdram, &dcr_write_sdram);
 761     ppc_dcr_register(env, SDRAM_CONF1HB,
 762                      s, &dcr_read_sdram, &dcr_write_sdram);
 763     ppc_dcr_register(env, SDRAM_PLBADDULL,
 764                      s, &dcr_read_sdram, &dcr_write_sdram);
 765     ppc_dcr_register(env, SDRAM_CONF1LL,
 766                      s, &dcr_read_sdram, &dcr_write_sdram);
 767     ppc_dcr_register(env, SDRAM_CONFPATHB,
 768                      s, &dcr_read_sdram, &dcr_write_sdram);
 769     ppc_dcr_register(env, SDRAM_PLBADDUHB,
 770                      s, &dcr_read_sdram, &dcr_write_sdram);
 771 }
 772
 773 void ppc440_sdram_enable(CPUPPCState *env)
 774 {
 775     ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21);
 776     ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000);
 777 }
 778
 779 /*****************************************************************************/
 780 /* PLB to AHB bridge */
 781 enum {
 782     AHB_TOP    = 0xA4,
 783     AHB_BOT    = 0xA5,
 784 };
 785
 786 typedef struct ppc4xx_ahb_t {
 787     uint32_t top;
 788     uint32_t bot;
 789 } ppc4xx_ahb_t;
 790
 791 static uint32_t dcr_read_ahb(void *opaque, int dcrn)
 792 {
 793     ppc4xx_ahb_t *ahb = opaque;
 794     uint32_t ret = 0;
 795
 796     switch (dcrn) {
 797     case AHB_TOP:
 798         ret = ahb->top;
 799         break;
 800     case AHB_BOT:
 801         ret = ahb->bot;
 802         break;
 803     default:
 804         break;
 805     }
 806
 807     return ret;
 808 }
 809
 810 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val)
 811 {
 812     ppc4xx_ahb_t *ahb = opaque;
 813
 814     switch (dcrn) {
 815     case AHB_TOP:
 816         ahb->top = val;
 817         break;
 818     case AHB_BOT:
 819         ahb->bot = val;
 820         break;
 821     }
 822 }
 823
 824 static void ppc4xx_ahb_reset(void *opaque)
 825 {
 826     ppc4xx_ahb_t *ahb = opaque;
 827
 828     /* No error */
 829     ahb->top = 0;
 830     ahb->bot = 0;
 831 }
 832
 833 void ppc4xx_ahb_init(CPUPPCState *env)
 834 {
 835     ppc4xx_ahb_t *ahb;
 836
 837     ahb = g_malloc0(sizeof(*ahb));
 838     ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb);
 839     ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb);
 840     qemu_register_reset(ppc4xx_ahb_reset, ahb);
 841 }
 842
 843 /*****************************************************************************/
 844 /* DMA controller */
 845
 846 #define DMA0_CR_CE  (1 << 31)
 847 #define DMA0_CR_PW  (1 << 26 | 1 << 25)
 848 #define DMA0_CR_DAI (1 << 24)
 849 #define DMA0_CR_SAI (1 << 23)
 850 #define DMA0_CR_DEC (1 << 2)
 851
 852 enum {
 853     DMA0_CR  = 0x00,
 854     DMA0_CT,
 855     DMA0_SAH,
 856     DMA0_SAL,
 857     DMA0_DAH,
 858     DMA0_DAL,
 859     DMA0_SGH,
 860     DMA0_SGL,
 861
 862     DMA0_SR  = 0x20,
 863     DMA0_SGC = 0x23,
 864     DMA0_SLP = 0x25,
 865     DMA0_POL = 0x26,
 866 };
 867
 868 typedef struct {
 869     uint32_t cr;
 870     uint32_t ct;
 871     uint64_t sa;
 872     uint64_t da;
 873     uint64_t sg;
 874 } PPC4xxDmaChnl;
 875
 876 typedef struct {
 877     int base;
 878     PPC4xxDmaChnl ch[4];
 879     uint32_t sr;
 880 } PPC4xxDmaState;
 881
 882 static uint32_t dcr_read_dma(void *opaque, int dcrn)
 883 {
 884     PPC4xxDmaState *dma = opaque;
 885     uint32_t val = 0;
 886     int addr = dcrn - dma->base;
 887     int chnl = addr / 8;
 888
 889     switch (addr) {
 890     case 0x00 ... 0x1f:
 891         switch (addr % 8) {
 892         case DMA0_CR:
 893             val = dma->ch[chnl].cr;
 894             break;
 895         case DMA0_CT:
 896             val = dma->ch[chnl].ct;
 897             break;
 898         case DMA0_SAH:
 899             val = dma->ch[chnl].sa >> 32;
 900             break;
 901         case DMA0_SAL:
 902             val = dma->ch[chnl].sa;
 903             break;
 904         case DMA0_DAH:
 905             val = dma->ch[chnl].da >> 32;
 906             break;
 907         case DMA0_DAL:
 908             val = dma->ch[chnl].da;
 909             break;
 910         case DMA0_SGH:
 911             val = dma->ch[chnl].sg >> 32;
 912             break;
 913         case DMA0_SGL:
 914             val = dma->ch[chnl].sg;
 915             break;
 916         }
 917         break;
 918     case DMA0_SR:
 919         val = dma->sr;
 920         break;
 921     default:
 922         qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
 923                       __func__, dcrn, chnl, addr);
 924     }
 925
 926     return val;
 927 }
 928
 929 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
 930 {
 931     PPC4xxDmaState *dma = opaque;
 932     int addr = dcrn - dma->base;
 933     int chnl = addr / 8;
 934
 935     switch (addr) {
 936     case 0x00 ... 0x1f:
 937         switch (addr % 8) {
 938         case DMA0_CR:
 939             dma->ch[chnl].cr = val;
 940             if (val & DMA0_CR_CE) {
 941                 int count = dma->ch[chnl].ct & 0xffff;
 942
 943                 if (count) {
 944                     int width, i, sidx, didx;
 945                     uint8_t *rptr, *wptr;
 946                     hwaddr rlen, wlen;
 947                     hwaddr xferlen;
 948
 949                     sidx = didx = 0;
 950                     width = 1 << ((val & DMA0_CR_PW) >> 25);
 951                     xferlen = count * width;
 952                     wlen = rlen = xferlen;
 953                     rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen,
 954                                                    false);
 955                     wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen,
 956                                                    true);
 957                     if (rptr && rlen == xferlen && wptr && wlen == xferlen) {
 958                         if (!(val & DMA0_CR_DEC) &&
 959                             val & DMA0_CR_SAI && val & DMA0_CR_DAI) {
 960                             /* optimise common case */
 961                             memmove(wptr, rptr, count * width);
 962                             sidx = didx = count * width;
 963                         } else {
 964                             /* do it the slow way */
 965                             for (sidx = didx = i = 0; i < count; i++) {
 966                                 uint64_t v = ldn_le_p(rptr + sidx, width);
 967                                 stn_le_p(wptr + didx, width, v);
 968                                 if (val & DMA0_CR_SAI) {
 969                                     sidx += width;
 970                                 }
 971                                 if (val & DMA0_CR_DAI) {
 972                                     didx += width;
 973                                 }
 974                             }
 975                         }
 976                     }
 977                     if (wptr) {
 978                         cpu_physical_memory_unmap(wptr, wlen, 1, didx);
 979                     }
 980                     if (rptr) {
 981                         cpu_physical_memory_unmap(rptr, rlen, 0, sidx);
 982                     }
 983                 }
 984             }
 985             break;
 986         case DMA0_CT:
 987             dma->ch[chnl].ct = val;
 988             break;
 989         case DMA0_SAH:
 990             dma->ch[chnl].sa &= 0xffffffffULL;
 991             dma->ch[chnl].sa |= (uint64_t)val << 32;
 992             break;
 993         case DMA0_SAL:
 994             dma->ch[chnl].sa &= 0xffffffff00000000ULL;
 995             dma->ch[chnl].sa |= val;
 996             break;
 997         case DMA0_DAH:
 998             dma->ch[chnl].da &= 0xffffffffULL;
 999             dma->ch[chnl].da |= (uint64_t)val << 32;
1000             break;
1001         case DMA0_DAL:
1002             dma->ch[chnl].da &= 0xffffffff00000000ULL;
1003             dma->ch[chnl].da |= val;
1004             break;
1005         case DMA0_SGH:
1006             dma->ch[chnl].sg &= 0xffffffffULL;
1007             dma->ch[chnl].sg |= (uint64_t)val << 32;
1008             break;
1009         case DMA0_SGL:
1010             dma->ch[chnl].sg &= 0xffffffff00000000ULL;
1011             dma->ch[chnl].sg |= val;
1012             break;
1013         }
1014         break;
1015     case DMA0_SR:
1016         dma->sr &= ~val;
1017         break;
1018     default:
1019         qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
1020                       __func__, dcrn, chnl, addr);
1021     }
1022 }
1023
1024 static void ppc4xx_dma_reset(void *opaque)
1025 {
1026     PPC4xxDmaState *dma = opaque;
1027     int dma_base = dma->base;
1028
1029     memset(dma, 0, sizeof(*dma));
1030     dma->base = dma_base;
1031 }
1032
1033 void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
1034 {
1035     PPC4xxDmaState *dma;
1036     int i;
1037
1038     dma = g_malloc0(sizeof(*dma));
1039     dma->base = dcr_base;
1040     qemu_register_reset(&ppc4xx_dma_reset, dma);
1041     for (i = 0; i < 4; i++) {
1042         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR,
1043                          dma, &dcr_read_dma, &dcr_write_dma);
1044         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT,
1045                          dma, &dcr_read_dma, &dcr_write_dma);
1046         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH,
1047                          dma, &dcr_read_dma, &dcr_write_dma);
1048         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL,
1049                          dma, &dcr_read_dma, &dcr_write_dma);
1050         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH,
1051                          dma, &dcr_read_dma, &dcr_write_dma);
1052         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL,
1053                          dma, &dcr_read_dma, &dcr_write_dma);
1054         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH,
1055                          dma, &dcr_read_dma, &dcr_write_dma);
1056         ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL,
1057                          dma, &dcr_read_dma, &dcr_write_dma);
1058     }
1059     ppc_dcr_register(env, dcr_base + DMA0_SR,
1060                      dma, &dcr_read_dma, &dcr_write_dma);
1061     ppc_dcr_register(env, dcr_base + DMA0_SGC,
1062                      dma, &dcr_read_dma, &dcr_write_dma);
1063     ppc_dcr_register(env, dcr_base + DMA0_SLP,
1064                      dma, &dcr_read_dma, &dcr_write_dma);
1065     ppc_dcr_register(env, dcr_base + DMA0_POL,
1066                      dma, &dcr_read_dma, &dcr_write_dma);
1067 }
1068
1069 /*****************************************************************************/
1070 /* PCI Express controller */
1071 /*
1072  * FIXME: This is not complete and does not work, only implemented partially
1073  * to allow firmware and guests to find an empty bus. Cards should use PCI.
1074  */
1075 #include "hw/pci/pcie_host.h"
1076
1077 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
1078 OBJECT_DECLARE_SIMPLE_TYPE(PPC460EXPCIEState, PPC460EX_PCIE_HOST)
1079
1080 struct PPC460EXPCIEState {
1081     PCIExpressHost host;
1082
1083     MemoryRegion iomem;
1084     qemu_irq irq[4];
1085     int32_t dcrn_base;
1086
1087     uint64_t cfg_base;
1088     uint32_t cfg_mask;
1089     uint64_t msg_base;
1090     uint32_t msg_mask;
1091     uint64_t omr1_base;
1092     uint64_t omr1_mask;
1093     uint64_t omr2_base;
1094     uint64_t omr2_mask;
1095     uint64_t omr3_base;
1096     uint64_t omr3_mask;
1097     uint64_t reg_base;
1098     uint32_t reg_mask;
1099     uint32_t special;
1100     uint32_t cfg;
1101 };
1102
1103 #define DCRN_PCIE0_BASE 0x100
1104 #define DCRN_PCIE1_BASE 0x120
1105
1106 enum {
1107     PEGPL_CFGBAH = 0x0,
1108     PEGPL_CFGBAL,
1109     PEGPL_CFGMSK,
1110     PEGPL_MSGBAH,
1111     PEGPL_MSGBAL,
1112     PEGPL_MSGMSK,
1113     PEGPL_OMR1BAH,
1114     PEGPL_OMR1BAL,
1115     PEGPL_OMR1MSKH,
1116     PEGPL_OMR1MSKL,
1117     PEGPL_OMR2BAH,
1118     PEGPL_OMR2BAL,
1119     PEGPL_OMR2MSKH,
1120     PEGPL_OMR2MSKL,
1121     PEGPL_OMR3BAH,
1122     PEGPL_OMR3BAL,
1123     PEGPL_OMR3MSKH,
1124     PEGPL_OMR3MSKL,
1125     PEGPL_REGBAH,
1126     PEGPL_REGBAL,
1127     PEGPL_REGMSK,
1128     PEGPL_SPECIAL,
1129     PEGPL_CFG,
1130 };
1131
1132 static uint32_t dcr_read_pcie(void *opaque, int dcrn)
1133 {
1134     PPC460EXPCIEState *state = opaque;
1135     uint32_t ret = 0;
1136
1137     switch (dcrn - state->dcrn_base) {
1138     case PEGPL_CFGBAH:
1139         ret = state->cfg_base >> 32;
1140         break;
1141     case PEGPL_CFGBAL:
1142         ret = state->cfg_base;
1143         break;
1144     case PEGPL_CFGMSK:
1145         ret = state->cfg_mask;
1146         break;
1147     case PEGPL_MSGBAH:
1148         ret = state->msg_base >> 32;
1149         break;
1150     case PEGPL_MSGBAL:
1151         ret = state->msg_base;
1152         break;
1153     case PEGPL_MSGMSK:
1154         ret = state->msg_mask;
1155         break;
1156     case PEGPL_OMR1BAH:
1157         ret = state->omr1_base >> 32;
1158         break;
1159     case PEGPL_OMR1BAL:
1160         ret = state->omr1_base;
1161         break;
1162     case PEGPL_OMR1MSKH:
1163         ret = state->omr1_mask >> 32;
1164         break;
1165     case PEGPL_OMR1MSKL:
1166         ret = state->omr1_mask;
1167         break;
1168     case PEGPL_OMR2BAH:
1169         ret = state->omr2_base >> 32;
1170         break;
1171     case PEGPL_OMR2BAL:
1172         ret = state->omr2_base;
1173         break;
1174     case PEGPL_OMR2MSKH:
1175         ret = state->omr2_mask >> 32;
1176         break;
1177     case PEGPL_OMR2MSKL:
1178         ret = state->omr3_mask;
1179         break;
1180     case PEGPL_OMR3BAH:
1181         ret = state->omr3_base >> 32;
1182         break;
1183     case PEGPL_OMR3BAL:
1184         ret = state->omr3_base;
1185         break;
1186     case PEGPL_OMR3MSKH:
1187         ret = state->omr3_mask >> 32;
1188         break;
1189     case PEGPL_OMR3MSKL:
1190         ret = state->omr3_mask;
1191         break;
1192     case PEGPL_REGBAH:
1193         ret = state->reg_base >> 32;
1194         break;
1195     case PEGPL_REGBAL:
1196         ret = state->reg_base;
1197         break;
1198     case PEGPL_REGMSK:
1199         ret = state->reg_mask;
1200         break;
1201     case PEGPL_SPECIAL:
1202         ret = state->special;
1203         break;
1204     case PEGPL_CFG:
1205         ret = state->cfg;
1206         break;
1207     }
1208
1209     return ret;
1210 }
1211
1212 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val)
1213 {
1214     PPC460EXPCIEState *s = opaque;
1215     uint64_t size;
1216
1217     switch (dcrn - s->dcrn_base) {
1218     case PEGPL_CFGBAH:
1219         s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff);
1220         break;
1221     case PEGPL_CFGBAL:
1222         s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val;
1223         break;
1224     case PEGPL_CFGMSK:
1225         s->cfg_mask = val;
1226         size = ~(val & 0xfffffffe) + 1;
1227         /*
1228          * Firmware sets this register to E0000001. Why we are not sure,
1229          * but the current guess is anything above PCIE_MMCFG_SIZE_MAX is
1230          * ignored.
1231          */
1232         if (size > PCIE_MMCFG_SIZE_MAX) {
1233             size = PCIE_MMCFG_SIZE_MAX;
1234         }
1235         pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size);
1236         break;
1237     case PEGPL_MSGBAH:
1238         s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff);
1239         break;
1240     case PEGPL_MSGBAL:
1241         s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val;
1242         break;
1243     case PEGPL_MSGMSK:
1244         s->msg_mask = val;
1245         break;
1246     case PEGPL_OMR1BAH:
1247         s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff);
1248         break;
1249     case PEGPL_OMR1BAL:
1250         s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val;
1251         break;
1252     case PEGPL_OMR1MSKH:
1253         s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff);
1254         break;
1255     case PEGPL_OMR1MSKL:
1256         s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val;
1257         break;
1258     case PEGPL_OMR2BAH:
1259         s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff);
1260         break;
1261     case PEGPL_OMR2BAL:
1262         s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val;
1263         break;
1264     case PEGPL_OMR2MSKH:
1265         s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff);
1266         break;
1267     case PEGPL_OMR2MSKL:
1268         s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val;
1269         break;
1270     case PEGPL_OMR3BAH:
1271         s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff);
1272         break;
1273     case PEGPL_OMR3BAL:
1274         s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val;
1275         break;
1276     case PEGPL_OMR3MSKH:
1277         s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff);
1278         break;
1279     case PEGPL_OMR3MSKL:
1280         s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val;
1281         break;
1282     case PEGPL_REGBAH:
1283         s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff);
1284         break;
1285     case PEGPL_REGBAL:
1286         s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val;
1287         break;
1288     case PEGPL_REGMSK:
1289         s->reg_mask = val;
1290         /* FIXME: how is size encoded? */
1291         size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1);
1292         break;
1293     case PEGPL_SPECIAL:
1294         s->special = val;
1295         break;
1296     case PEGPL_CFG:
1297         s->cfg = val;
1298         break;
1299     }
1300 }
1301
1302 static void ppc460ex_set_irq(void *opaque, int irq_num, int level)
1303 {
1304        PPC460EXPCIEState *s = opaque;
1305        qemu_set_irq(s->irq[irq_num], level);
1306 }
1307
1308 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp)
1309 {
1310     PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev);
1311     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
1312     int i, id;
1313     char buf[16];
1314
1315     switch (s->dcrn_base) {
1316     case DCRN_PCIE0_BASE:
1317         id = 0;
1318         break;
1319     case DCRN_PCIE1_BASE:
1320         id = 1;
1321         break;
1322     default:
1323         error_setg(errp, "invalid PCIe DCRN base");
1324         return;
1325     }
1326     snprintf(buf, sizeof(buf), "pcie%d-io", id);
1327     memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX);
1328     for (i = 0; i < 4; i++) {
1329         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1330     }
1331     snprintf(buf, sizeof(buf), "pcie.%d", id);
1332     pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq,
1333                                 pci_swizzle_map_irq_fn, s, &s->iomem,
1334                                 get_system_io(), 0, 4, TYPE_PCIE_BUS);
1335 }
1336
1337 static Property ppc460ex_pcie_props[] = {
1338     DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1),
1339     DEFINE_PROP_END_OF_LIST(),
1340 };
1341
1342 static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data)
1343 {
1344     DeviceClass *dc = DEVICE_CLASS(klass);
1345
1346     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
1347     dc->realize = ppc460ex_pcie_realize;
1348     device_class_set_props(dc, ppc460ex_pcie_props);
1349     dc->hotpluggable = false;
1350 }
1351
1352 static const TypeInfo ppc460ex_pcie_host_info = {
1353     .name = TYPE_PPC460EX_PCIE_HOST,
1354     .parent = TYPE_PCIE_HOST_BRIDGE,
1355     .instance_size = sizeof(PPC460EXPCIEState),
1356     .class_init = ppc460ex_pcie_class_init,
1357 };
1358
1359 static void ppc460ex_pcie_register(void)
1360 {
1361     type_register_static(&ppc460ex_pcie_host_info);
1362 }
1363
1364 type_init(ppc460ex_pcie_register)
1365
1366 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env)
1367 {
1368     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s,
1369                      &dcr_read_pcie, &dcr_write_pcie);
1370     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s,
1371                      &dcr_read_pcie, &dcr_write_pcie);
1372     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s,
1373                      &dcr_read_pcie, &dcr_write_pcie);
1374     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s,
1375                      &dcr_read_pcie, &dcr_write_pcie);
1376     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s,
1377                      &dcr_read_pcie, &dcr_write_pcie);
1378     ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s,
1379                      &dcr_read_pcie, &dcr_write_pcie);
1380     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s,
1381                      &dcr_read_pcie, &dcr_write_pcie);
1382     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s,
1383                      &dcr_read_pcie, &dcr_write_pcie);
1384     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s,
1385                      &dcr_read_pcie, &dcr_write_pcie);
1386     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s,
1387                      &dcr_read_pcie, &dcr_write_pcie);
1388     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s,
1389                      &dcr_read_pcie, &dcr_write_pcie);
1390     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s,
1391                      &dcr_read_pcie, &dcr_write_pcie);
1392     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s,
1393                      &dcr_read_pcie, &dcr_write_pcie);
1394     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s,
1395                      &dcr_read_pcie, &dcr_write_pcie);
1396     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s,
1397                      &dcr_read_pcie, &dcr_write_pcie);
1398     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s,
1399                      &dcr_read_pcie, &dcr_write_pcie);
1400     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s,
1401                      &dcr_read_pcie, &dcr_write_pcie);
1402     ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s,
1403                      &dcr_read_pcie, &dcr_write_pcie);
1404     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s,
1405                      &dcr_read_pcie, &dcr_write_pcie);
1406     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s,
1407                      &dcr_read_pcie, &dcr_write_pcie);
1408     ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s,
1409                      &dcr_read_pcie, &dcr_write_pcie);
1410     ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s,
1411                      &dcr_read_pcie, &dcr_write_pcie);
1412     ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s,
1413                      &dcr_read_pcie, &dcr_write_pcie);
1414 }
1415
1416 void ppc460ex_pcie_init(CPUPPCState *env)
1417 {
1418     DeviceState *dev;
1419
1420     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
1421     qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE);
1422     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1423     ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
1424
1425     dev = qdev_new(TYPE_PPC460EX_PCIE_HOST);
1426     qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE);
1427     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1428     ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env);
1429 }