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target/ppc: Update sqrt for new flags
[qemu.git] / target / ppc / fpu_helper.c
blob08f7c8837e1700d7980416493adc8024752232cf
1 /*
2 * PowerPC floating point and SPE emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/helper-proto.h"
22 #include "exec/exec-all.h"
23 #include "internal.h"
24 #include "fpu/softfloat.h"
25
26 static inline float128 float128_snan_to_qnan(float128 x)
27 {
28 float128 r;
29
30 r.high = x.high | 0x0000800000000000;
31 r.low = x.low;
32 return r;
33 }
34
35 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
36 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
37 #define float16_snan_to_qnan(x) ((x) | 0x0200)
38
39 static inline bool fp_exceptions_enabled(CPUPPCState *env)
40 {
41 #ifdef CONFIG_USER_ONLY
42 return true;
43 #else
44 return (env->msr & ((1U << MSR_FE0) | (1U << MSR_FE1))) != 0;
45 #endif
46 }
47
48 /*****************************************************************************/
49 /* Floating point operations helpers */
50
51 /*
52 * This is the non-arithmatic conversion that happens e.g. on loads.
53 * In the Power ISA pseudocode, this is called DOUBLE.
54 */
55 uint64_t helper_todouble(uint32_t arg)
56 {
57 uint32_t abs_arg = arg & 0x7fffffff;
58 uint64_t ret;
59
60 if (likely(abs_arg >= 0x00800000)) {
61 if (unlikely(extract32(arg, 23, 8) == 0xff)) {
62 /* Inf or NAN. */
63 ret = (uint64_t)extract32(arg, 31, 1) << 63;
64 ret |= (uint64_t)0x7ff << 52;
65 ret |= (uint64_t)extract32(arg, 0, 23) << 29;
66 } else {
67 /* Normalized operand. */
68 ret = (uint64_t)extract32(arg, 30, 2) << 62;
69 ret |= ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59;
70 ret |= (uint64_t)extract32(arg, 0, 30) << 29;
71 }
72 } else {
73 /* Zero or Denormalized operand. */
74 ret = (uint64_t)extract32(arg, 31, 1) << 63;
75 if (unlikely(abs_arg != 0)) {
76 /*
77 * Denormalized operand.
78 * Shift fraction so that the msb is in the implicit bit position.
79 * Thus, shift is in the range [1:23].
80 */
81 int shift = clz32(abs_arg) - 8;
82 /*
83 * The first 3 terms compute the float64 exponent. We then bias
84 * this result by -1 so that we can swallow the implicit bit below.
85 */
86 int exp = -126 - shift + 1023 - 1;
87
88 ret |= (uint64_t)exp << 52;
89 ret += (uint64_t)abs_arg << (52 - 23 + shift);
90 }
91 }
92 return ret;
93 }
94
95 /*
96 * This is the non-arithmatic conversion that happens e.g. on stores.
97 * In the Power ISA pseudocode, this is called SINGLE.
98 */
99 uint32_t helper_tosingle(uint64_t arg)
100 {
101 int exp = extract64(arg, 52, 11);
102 uint32_t ret;
103
104 if (likely(exp > 896)) {
105 /* No denormalization required (includes Inf, NaN). */
106 ret = extract64(arg, 62, 2) << 30;
107 ret |= extract64(arg, 29, 30);
108 } else {
109 /*
110 * Zero or Denormal result. If the exponent is in bounds for
111 * a single-precision denormal result, extract the proper
112 * bits. If the input is not zero, and the exponent is out of
113 * bounds, then the result is undefined; this underflows to
114 * zero.
115 */
116 ret = extract64(arg, 63, 1) << 31;
117 if (unlikely(exp >= 874)) {
118 /* Denormal result. */
119 ret |= ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 - exp);
120 }
121 }
122 return ret;
123 }
124
125 static inline int ppc_float32_get_unbiased_exp(float32 f)
126 {
127 return ((f >> 23) & 0xFF) - 127;
128 }
129
130 static inline int ppc_float64_get_unbiased_exp(float64 f)
131 {
132 return ((f >> 52) & 0x7FF) - 1023;
133 }
134
135 /* Classify a floating-point number. */
136 enum {
137 is_normal = 1,
138 is_zero = 2,
139 is_denormal = 4,
140 is_inf = 8,
141 is_qnan = 16,
142 is_snan = 32,
143 is_neg = 64,
144 };
145
146 #define COMPUTE_CLASS(tp) \
147 static int tp##_classify(tp arg) \
148 { \
149 int ret = tp##_is_neg(arg) * is_neg; \
150 if (unlikely(tp##_is_any_nan(arg))) { \
151 float_status dummy = { }; /* snan_bit_is_one = 0 */ \
152 ret |= (tp##_is_signaling_nan(arg, &dummy) \
153 ? is_snan : is_qnan); \
154 } else if (unlikely(tp##_is_infinity(arg))) { \
155 ret |= is_inf; \
156 } else if (tp##_is_zero(arg)) { \
157 ret |= is_zero; \
158 } else if (tp##_is_zero_or_denormal(arg)) { \
159 ret |= is_denormal; \
160 } else { \
161 ret |= is_normal; \
162 } \
163 return ret; \
164 }
165
166 COMPUTE_CLASS(float16)
167 COMPUTE_CLASS(float32)
168 COMPUTE_CLASS(float64)
169 COMPUTE_CLASS(float128)
170
171 static void set_fprf_from_class(CPUPPCState *env, int class)
172 {
173 static const uint8_t fprf[6][2] = {
174 { 0x04, 0x08 }, /* normalized */
175 { 0x02, 0x12 }, /* zero */
176 { 0x14, 0x18 }, /* denormalized */
177 { 0x05, 0x09 }, /* infinity */
178 { 0x11, 0x11 }, /* qnan */
179 { 0x00, 0x00 }, /* snan -- flags are undefined */
180 };
181 bool isneg = class & is_neg;
182
183 env->fpscr &= ~FP_FPRF;
184 env->fpscr |= fprf[ctz32(class)][isneg] << FPSCR_FPRF;
185 }
186
187 #define COMPUTE_FPRF(tp) \
188 void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
189 { \
190 set_fprf_from_class(env, tp##_classify(arg)); \
191 }
192
193 COMPUTE_FPRF(float16)
194 COMPUTE_FPRF(float32)
195 COMPUTE_FPRF(float64)
196 COMPUTE_FPRF(float128)
197
198 /* Floating-point invalid operations exception */
199 static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
200 {
201 /* Update the floating-point invalid operation summary */
202 env->fpscr |= FP_VX;
203 /* Update the floating-point exception summary */
204 env->fpscr |= FP_FX;
205 if (fpscr_ve != 0) {
206 /* Update the floating-point enabled exception summary */
207 env->fpscr |= FP_FEX;
208 if (fp_exceptions_enabled(env)) {
209 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
210 POWERPC_EXCP_FP | op, retaddr);
211 }
212 }
213 }
214
215 static void finish_invalid_op_arith(CPUPPCState *env, int op,
216 bool set_fpcc, uintptr_t retaddr)
217 {
218 env->fpscr &= ~(FP_FR | FP_FI);
219 if (fpscr_ve == 0) {
220 if (set_fpcc) {
221 env->fpscr &= ~FP_FPCC;
222 env->fpscr |= (FP_C | FP_FU);
223 }
224 }
225 finish_invalid_op_excp(env, op, retaddr);
226 }
227
228 /* Signalling NaN */
229 static void float_invalid_op_vxsnan(CPUPPCState *env, uintptr_t retaddr)
230 {
231 env->fpscr |= FP_VXSNAN;
232 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, retaddr);
233 }
234
235 /* Magnitude subtraction of infinities */
236 static void float_invalid_op_vxisi(CPUPPCState *env, bool set_fpcc,
237 uintptr_t retaddr)
238 {
239 env->fpscr |= FP_VXISI;
240 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXISI, set_fpcc, retaddr);
241 }
242
243 /* Division of infinity by infinity */
244 static void float_invalid_op_vxidi(CPUPPCState *env, bool set_fpcc,
245 uintptr_t retaddr)
246 {
247 env->fpscr |= FP_VXIDI;
248 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIDI, set_fpcc, retaddr);
249 }
250
251 /* Division of zero by zero */
252 static void float_invalid_op_vxzdz(CPUPPCState *env, bool set_fpcc,
253 uintptr_t retaddr)
254 {
255 env->fpscr |= FP_VXZDZ;
256 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXZDZ, set_fpcc, retaddr);
257 }
258
259 /* Multiplication of zero by infinity */
260 static void float_invalid_op_vximz(CPUPPCState *env, bool set_fpcc,
261 uintptr_t retaddr)
262 {
263 env->fpscr |= FP_VXIMZ;
264 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXIMZ, set_fpcc, retaddr);
265 }
266
267 /* Square root of a negative number */
268 static void float_invalid_op_vxsqrt(CPUPPCState *env, bool set_fpcc,
269 uintptr_t retaddr)
270 {
271 env->fpscr |= FP_VXSQRT;
272 finish_invalid_op_arith(env, POWERPC_EXCP_FP_VXSQRT, set_fpcc, retaddr);
273 }
274
275 /* Ordered comparison of NaN */
276 static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
277 uintptr_t retaddr)
278 {
279 env->fpscr |= FP_VXVC;
280 if (set_fpcc) {
281 env->fpscr &= ~FP_FPCC;
282 env->fpscr |= (FP_C | FP_FU);
283 }
284 /* Update the floating-point invalid operation summary */
285 env->fpscr |= FP_VX;
286 /* Update the floating-point exception summary */
287 env->fpscr |= FP_FX;
288 /* We must update the target FPR before raising the exception */
289 if (fpscr_ve != 0) {
290 CPUState *cs = env_cpu(env);
291
292 cs->exception_index = POWERPC_EXCP_PROGRAM;
293 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
294 /* Update the floating-point enabled exception summary */
295 env->fpscr |= FP_FEX;
296 /* Exception is deferred */
297 }
298 }
299
300 /* Invalid conversion */
301 static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
302 uintptr_t retaddr)
303 {
304 env->fpscr |= FP_VXCVI;
305 env->fpscr &= ~(FP_FR | FP_FI);
306 if (fpscr_ve == 0) {
307 if (set_fpcc) {
308 env->fpscr &= ~FP_FPCC;
309 env->fpscr |= (FP_C | FP_FU);
310 }
311 }
312 finish_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, retaddr);
313 }
314
315 static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
316 {
317 env->fpscr |= FP_ZX;
318 env->fpscr &= ~(FP_FR | FP_FI);
319 /* Update the floating-point exception summary */
320 env->fpscr |= FP_FX;
321 if (fpscr_ze != 0) {
322 /* Update the floating-point enabled exception summary */
323 env->fpscr |= FP_FEX;
324 if (fp_exceptions_enabled(env)) {
325 raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
326 POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
327 raddr);
328 }
329 }
330 }
331
332 static inline void float_overflow_excp(CPUPPCState *env)
333 {
334 CPUState *cs = env_cpu(env);
335
336 env->fpscr |= FP_OX;
337 /* Update the floating-point exception summary */
338 env->fpscr |= FP_FX;
339 if (fpscr_oe != 0) {
340 /* XXX: should adjust the result */
341 /* Update the floating-point enabled exception summary */
342 env->fpscr |= FP_FEX;
343 /* We must update the target FPR before raising the exception */
344 cs->exception_index = POWERPC_EXCP_PROGRAM;
345 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
346 } else {
347 env->fpscr |= FP_XX;
348 env->fpscr |= FP_FI;
349 }
350 }
351
352 static inline void float_underflow_excp(CPUPPCState *env)
353 {
354 CPUState *cs = env_cpu(env);
355
356 env->fpscr |= FP_UX;
357 /* Update the floating-point exception summary */
358 env->fpscr |= FP_FX;
359 if (fpscr_ue != 0) {
360 /* XXX: should adjust the result */
361 /* Update the floating-point enabled exception summary */
362 env->fpscr |= FP_FEX;
363 /* We must update the target FPR before raising the exception */
364 cs->exception_index = POWERPC_EXCP_PROGRAM;
365 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
366 }
367 }
368
369 static inline void float_inexact_excp(CPUPPCState *env)
370 {
371 CPUState *cs = env_cpu(env);
372
373 env->fpscr |= FP_FI;
374 env->fpscr |= FP_XX;
375 /* Update the floating-point exception summary */
376 env->fpscr |= FP_FX;
377 if (fpscr_xe != 0) {
378 /* Update the floating-point enabled exception summary */
379 env->fpscr |= FP_FEX;
380 /* We must update the target FPR before raising the exception */
381 cs->exception_index = POWERPC_EXCP_PROGRAM;
382 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
383 }
384 }
385
386 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
387 {
388 uint32_t mask = 1u << bit;
389 if (env->fpscr & mask) {
390 ppc_store_fpscr(env, env->fpscr & ~(target_ulong)mask);
391 }
392 }
393
394 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
395 {
396 uint32_t mask = 1u << bit;
397 if (!(env->fpscr & mask)) {
398 ppc_store_fpscr(env, env->fpscr | mask);
399 }
400 }
401
402 void helper_store_fpscr(CPUPPCState *env, uint64_t val, uint32_t nibbles)
403 {
404 target_ulong mask = 0;
405 int i;
406
407 /* TODO: push this extension back to translation time */
408 for (i = 0; i < sizeof(target_ulong) * 2; i++) {
409 if (nibbles & (1 << i)) {
410 mask |= (target_ulong) 0xf << (4 * i);
411 }
412 }
413 val = (val & mask) | (env->fpscr & ~mask);
414 ppc_store_fpscr(env, val);
415 }
416
417 void helper_fpscr_check_status(CPUPPCState *env)
418 {
419 CPUState *cs = env_cpu(env);
420 target_ulong fpscr = env->fpscr;
421 int error = 0;
422
423 if ((fpscr & FP_OX) && (fpscr & FP_OE)) {
424 error = POWERPC_EXCP_FP_OX;
425 } else if ((fpscr & FP_UX) && (fpscr & FP_UE)) {
426 error = POWERPC_EXCP_FP_UX;
427 } else if ((fpscr & FP_XX) && (fpscr & FP_XE)) {
428 error = POWERPC_EXCP_FP_XX;
429 } else if ((fpscr & FP_ZX) && (fpscr & FP_ZE)) {
430 error = POWERPC_EXCP_FP_ZX;
431 } else if (fpscr & FP_VE) {
432 if (fpscr & FP_VXSOFT) {
433 error = POWERPC_EXCP_FP_VXSOFT;
434 } else if (fpscr & FP_VXSNAN) {
435 error = POWERPC_EXCP_FP_VXSNAN;
436 } else if (fpscr & FP_VXISI) {
437 error = POWERPC_EXCP_FP_VXISI;
438 } else if (fpscr & FP_VXIDI) {
439 error = POWERPC_EXCP_FP_VXIDI;
440 } else if (fpscr & FP_VXZDZ) {
441 error = POWERPC_EXCP_FP_VXZDZ;
442 } else if (fpscr & FP_VXIMZ) {
443 error = POWERPC_EXCP_FP_VXIMZ;
444 } else if (fpscr & FP_VXVC) {
445 error = POWERPC_EXCP_FP_VXVC;
446 } else if (fpscr & FP_VXSQRT) {
447 error = POWERPC_EXCP_FP_VXSQRT;
448 } else if (fpscr & FP_VXCVI) {
449 error = POWERPC_EXCP_FP_VXCVI;
450 } else {
451 return;
452 }
453 } else {
454 return;
455 }
456 cs->exception_index = POWERPC_EXCP_PROGRAM;
457 env->error_code = error | POWERPC_EXCP_FP;
458 /* Deferred floating-point exception after target FPSCR update */
459 if (fp_exceptions_enabled(env)) {
460 raise_exception_err_ra(env, cs->exception_index,
461 env->error_code, GETPC());
462 }
463 }
464
465 static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
466 {
467 CPUState *cs = env_cpu(env);
468 int status = get_float_exception_flags(&env->fp_status);
469
470 if (status & float_flag_overflow) {
471 float_overflow_excp(env);
472 } else if (status & float_flag_underflow) {
473 float_underflow_excp(env);
474 }
475 if (status & float_flag_inexact) {
476 float_inexact_excp(env);
477 } else {
478 env->fpscr &= ~FP_FI; /* clear the FPSCR[FI] bit */
479 }
480
481 if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
482 (env->error_code & POWERPC_EXCP_FP)) {
483 /* Deferred floating-point exception after target FPR update */
484 if (fp_exceptions_enabled(env)) {
485 raise_exception_err_ra(env, cs->exception_index,
486 env->error_code, raddr);
487 }
488 }
489 }
490
491 void helper_float_check_status(CPUPPCState *env)
492 {
493 do_float_check_status(env, GETPC());
494 }
495
496 void helper_reset_fpstatus(CPUPPCState *env)
497 {
498 set_float_exception_flags(0, &env->fp_status);
499 }
500
501 static void float_invalid_op_addsub(CPUPPCState *env, int flags,
502 bool set_fpcc, uintptr_t retaddr)
503 {
504 if (flags & float_flag_invalid_isi) {
505 float_invalid_op_vxisi(env, set_fpcc, retaddr);
506 } else if (flags & float_flag_invalid_snan) {
507 float_invalid_op_vxsnan(env, retaddr);
508 }
509 }
510
511 /* fadd - fadd. */
512 float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2)
513 {
514 float64 ret = float64_add(arg1, arg2, &env->fp_status);
515 int flags = get_float_exception_flags(&env->fp_status);
516
517 if (unlikely(flags & float_flag_invalid)) {
518 float_invalid_op_addsub(env, flags, 1, GETPC());
519 }
520
521 return ret;
522 }
523
524 /* fsub - fsub. */
525 float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2)
526 {
527 float64 ret = float64_sub(arg1, arg2, &env->fp_status);
528 int flags = get_float_exception_flags(&env->fp_status);
529
530 if (unlikely(flags & float_flag_invalid)) {
531 float_invalid_op_addsub(env, flags, 1, GETPC());
532 }
533
534 return ret;
535 }
536
537 static void float_invalid_op_mul(CPUPPCState *env, int flags,
538 bool set_fprc, uintptr_t retaddr)
539 {
540 if (flags & float_flag_invalid_imz) {
541 float_invalid_op_vximz(env, set_fprc, retaddr);
542 } else if (flags & float_flag_invalid_snan) {
543 float_invalid_op_vxsnan(env, retaddr);
544 }
545 }
546
547 /* fmul - fmul. */
548 float64 helper_fmul(CPUPPCState *env, float64 arg1, float64 arg2)
549 {
550 float64 ret = float64_mul(arg1, arg2, &env->fp_status);
551 int flags = get_float_exception_flags(&env->fp_status);
552
553 if (unlikely(flags & float_flag_invalid)) {
554 float_invalid_op_mul(env, flags, 1, GETPC());
555 }
556
557 return ret;
558 }
559
560 static void float_invalid_op_div(CPUPPCState *env, int flags,
561 bool set_fprc, uintptr_t retaddr)
562 {
563 if (flags & float_flag_invalid_idi) {
564 float_invalid_op_vxidi(env, set_fprc, retaddr);
565 } else if (flags & float_flag_invalid_zdz) {
566 float_invalid_op_vxzdz(env, set_fprc, retaddr);
567 } else if (flags & float_flag_invalid_snan) {
568 float_invalid_op_vxsnan(env, retaddr);
569 }
570 }
571
572 /* fdiv - fdiv. */
573 float64 helper_fdiv(CPUPPCState *env, float64 arg1, float64 arg2)
574 {
575 float64 ret = float64_div(arg1, arg2, &env->fp_status);
576 int flags = get_float_exception_flags(&env->fp_status);
577
578 if (unlikely(flags & float_flag_invalid)) {
579 float_invalid_op_div(env, flags, 1, GETPC());
580 }
581 if (unlikely(flags & float_flag_divbyzero)) {
582 float_zero_divide_excp(env, GETPC());
583 }
584
585 return ret;
586 }
587
588 static uint64_t float_invalid_cvt(CPUPPCState *env, int flags,
589 uint64_t ret, uint64_t ret_nan,
590 bool set_fprc, uintptr_t retaddr)
591 {
592 /*
593 * VXCVI is different from most in that it sets two exception bits,
594 * VXCVI and VXSNAN for an SNaN input.
595 */
596 if (flags & float_flag_invalid_snan) {
597 env->fpscr |= FP_VXSNAN;
598 }
599 float_invalid_op_vxcvi(env, set_fprc, retaddr);
600
601 return flags & float_flag_invalid_cvti ? ret : ret_nan;
602 }
603
604 #define FPU_FCTI(op, cvt, nanval) \
605 uint64_t helper_##op(CPUPPCState *env, float64 arg) \
606 { \
607 uint64_t ret = float64_to_##cvt(arg, &env->fp_status); \
608 int flags = get_float_exception_flags(&env->fp_status); \
609 if (unlikely(flags & float_flag_invalid)) { \
610 ret = float_invalid_cvt(env, flags, ret, nanval, 1, GETPC()); \
611 } \
612 return ret; \
613 }
614
615 FPU_FCTI(fctiw, int32, 0x80000000U)
616 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
617 FPU_FCTI(fctiwu, uint32, 0x00000000U)
618 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
619 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
620 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
621 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
622 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
623
624 #define FPU_FCFI(op, cvtr, is_single) \
625 uint64_t helper_##op(CPUPPCState *env, uint64_t arg) \
626 { \
627 CPU_DoubleU farg; \
628 \
629 if (is_single) { \
630 float32 tmp = cvtr(arg, &env->fp_status); \
631 farg.d = float32_to_float64(tmp, &env->fp_status); \
632 } else { \
633 farg.d = cvtr(arg, &env->fp_status); \
634 } \
635 do_float_check_status(env, GETPC()); \
636 return farg.ll; \
637 }
638
639 FPU_FCFI(fcfid, int64_to_float64, 0)
640 FPU_FCFI(fcfids, int64_to_float32, 1)
641 FPU_FCFI(fcfidu, uint64_to_float64, 0)
642 FPU_FCFI(fcfidus, uint64_to_float32, 1)
643
644 static uint64_t do_fri(CPUPPCState *env, uint64_t arg,
645 FloatRoundMode rounding_mode)
646 {
647 FloatRoundMode old_rounding_mode = get_float_rounding_mode(&env->fp_status);
648 int flags;
649
650 set_float_rounding_mode(rounding_mode, &env->fp_status);
651 arg = float64_round_to_int(arg, &env->fp_status);
652 set_float_rounding_mode(old_rounding_mode, &env->fp_status);
653
654 flags = get_float_exception_flags(&env->fp_status);
655 if (flags & float_flag_invalid_snan) {
656 float_invalid_op_vxsnan(env, GETPC());
657 }
658
659 /* fri* does not set FPSCR[XX] */
660 set_float_exception_flags(flags & ~float_flag_inexact, &env->fp_status);
661 do_float_check_status(env, GETPC());
662
663 return arg;
664 }
665
666 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
667 {
668 return do_fri(env, arg, float_round_ties_away);
669 }
670
671 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
672 {
673 return do_fri(env, arg, float_round_to_zero);
674 }
675
676 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
677 {
678 return do_fri(env, arg, float_round_up);
679 }
680
681 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
682 {
683 return do_fri(env, arg, float_round_down);
684 }
685
686 static void float_invalid_op_madd(CPUPPCState *env, int flags,
687 bool set_fpcc, uintptr_t retaddr)
688 {
689 if (flags & float_flag_invalid_imz) {
690 float_invalid_op_vximz(env, set_fpcc, retaddr);
691 } else {
692 float_invalid_op_addsub(env, flags, set_fpcc, retaddr);
693 }
694 }
695
696 static float64 do_fmadd(CPUPPCState *env, float64 a, float64 b,
697 float64 c, int madd_flags, uintptr_t retaddr)
698 {
699 float64 ret = float64_muladd(a, b, c, madd_flags, &env->fp_status);
700 int flags = get_float_exception_flags(&env->fp_status);
701
702 if (unlikely(flags & float_flag_invalid)) {
703 float_invalid_op_madd(env, flags, 1, retaddr);
704 }
705 return ret;
706 }
707
708 #define FPU_FMADD(op, madd_flags) \
709 uint64_t helper_##op(CPUPPCState *env, uint64_t arg1, \
710 uint64_t arg2, uint64_t arg3) \
711 { return do_fmadd(env, arg1, arg2, arg3, madd_flags, GETPC()); }
712
713 #define MADD_FLGS 0
714 #define MSUB_FLGS float_muladd_negate_c
715 #define NMADD_FLGS float_muladd_negate_result
716 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
717
718 FPU_FMADD(fmadd, MADD_FLGS)
719 FPU_FMADD(fnmadd, NMADD_FLGS)
720 FPU_FMADD(fmsub, MSUB_FLGS)
721 FPU_FMADD(fnmsub, NMSUB_FLGS)
722
723 /* frsp - frsp. */
724 static uint64_t do_frsp(CPUPPCState *env, uint64_t arg, uintptr_t retaddr)
725 {
726 float32 f32 = float64_to_float32(arg, &env->fp_status);
727 int flags = get_float_exception_flags(&env->fp_status);
728
729 if (unlikely(flags & float_flag_invalid_snan)) {
730 float_invalid_op_vxsnan(env, retaddr);
731 }
732 return helper_todouble(f32);
733 }
734
735 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
736 {
737 return do_frsp(env, arg, GETPC());
738 }
739
740 static void float_invalid_op_sqrt(CPUPPCState *env, int flags,
741 bool set_fpcc, uintptr_t retaddr)
742 {
743 if (unlikely(flags & float_flag_invalid_sqrt)) {
744 float_invalid_op_vxsqrt(env, set_fpcc, retaddr);
745 } else if (unlikely(flags & float_flag_invalid_snan)) {
746 float_invalid_op_vxsnan(env, retaddr);
747 }
748 }
749
750 /* fsqrt - fsqrt. */
751 float64 helper_fsqrt(CPUPPCState *env, float64 arg)
752 {
753 float64 ret = float64_sqrt(arg, &env->fp_status);
754 int flags = get_float_exception_flags(&env->fp_status);
755
756 if (unlikely(flags & float_flag_invalid)) {
757 float_invalid_op_sqrt(env, flags, 1, GETPC());
758 }
759
760 return ret;
761 }
762
763 /* fre - fre. */
764 float64 helper_fre(CPUPPCState *env, float64 arg)
765 {
766 /* "Estimate" the reciprocal with actual division. */
767 float64 ret = float64_div(float64_one, arg, &env->fp_status);
768 int status = get_float_exception_flags(&env->fp_status);
769
770 if (unlikely(status)) {
771 if (status & float_flag_invalid) {
772 if (float64_is_signaling_nan(arg, &env->fp_status)) {
773 /* sNaN reciprocal */
774 float_invalid_op_vxsnan(env, GETPC());
775 }
776 }
777 if (status & float_flag_divbyzero) {
778 float_zero_divide_excp(env, GETPC());
779 /* For FPSCR.ZE == 0, the result is 1/2. */
780 ret = float64_set_sign(float64_half, float64_is_neg(arg));
781 }
782 }
783
784 return ret;
785 }
786
787 /* fres - fres. */
788 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
789 {
790 CPU_DoubleU farg;
791 float32 f32;
792
793 farg.ll = arg;
794
795 if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
796 /* sNaN reciprocal */
797 float_invalid_op_vxsnan(env, GETPC());
798 }
799 farg.d = float64_div(float64_one, farg.d, &env->fp_status);
800 f32 = float64_to_float32(farg.d, &env->fp_status);
801 farg.d = float32_to_float64(f32, &env->fp_status);
802
803 return farg.ll;
804 }
805
806 /* frsqrte - frsqrte. */
807 float64 helper_frsqrte(CPUPPCState *env, float64 arg)
808 {
809 /* "Estimate" the reciprocal with actual division. */
810 float64 rets = float64_sqrt(arg, &env->fp_status);
811 float64 retd = float64_div(float64_one, rets, &env->fp_status);
812 int flags = get_float_exception_flags(&env->fp_status);
813
814 if (unlikely(flags & float_flag_invalid)) {
815 float_invalid_op_sqrt(env, flags, 1, GETPC());
816 }
817 if (unlikely(flags & float_flag_divbyzero)) {
818 /* Reciprocal of (square root of) zero. */
819 float_zero_divide_excp(env, GETPC());
820 }
821
822 return retd;
823 }
824
825 /* fsel - fsel. */
826 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
827 uint64_t arg3)
828 {
829 CPU_DoubleU farg1;
830
831 farg1.ll = arg1;
832
833 if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
834 !float64_is_any_nan(farg1.d)) {
835 return arg2;
836 } else {
837 return arg3;
838 }
839 }
840
841 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
842 {
843 int fe_flag = 0;
844 int fg_flag = 0;
845
846 if (unlikely(float64_is_infinity(fra) ||
847 float64_is_infinity(frb) ||
848 float64_is_zero(frb))) {
849 fe_flag = 1;
850 fg_flag = 1;
851 } else {
852 int e_a = ppc_float64_get_unbiased_exp(fra);
853 int e_b = ppc_float64_get_unbiased_exp(frb);
854
855 if (unlikely(float64_is_any_nan(fra) ||
856 float64_is_any_nan(frb))) {
857 fe_flag = 1;
858 } else if ((e_b <= -1022) || (e_b >= 1021)) {
859 fe_flag = 1;
860 } else if (!float64_is_zero(fra) &&
861 (((e_a - e_b) >= 1023) ||
862 ((e_a - e_b) <= -1021) ||
863 (e_a <= -970))) {
864 fe_flag = 1;
865 }
866
867 if (unlikely(float64_is_zero_or_denormal(frb))) {
868 /* XB is not zero because of the above check and */
869 /* so must be denormalized. */
870 fg_flag = 1;
871 }
872 }
873
874 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
875 }
876
877 uint32_t helper_ftsqrt(uint64_t frb)
878 {
879 int fe_flag = 0;
880 int fg_flag = 0;
881
882 if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
883 fe_flag = 1;
884 fg_flag = 1;
885 } else {
886 int e_b = ppc_float64_get_unbiased_exp(frb);
887
888 if (unlikely(float64_is_any_nan(frb))) {
889 fe_flag = 1;
890 } else if (unlikely(float64_is_zero(frb))) {
891 fe_flag = 1;
892 } else if (unlikely(float64_is_neg(frb))) {
893 fe_flag = 1;
894 } else if (!float64_is_zero(frb) && (e_b <= (-1022 + 52))) {
895 fe_flag = 1;
896 }
897
898 if (unlikely(float64_is_zero_or_denormal(frb))) {
899 /* XB is not zero because of the above check and */
900 /* therefore must be denormalized. */
901 fg_flag = 1;
902 }
903 }
904
905 return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
906 }
907
908 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
909 uint32_t crfD)
910 {
911 CPU_DoubleU farg1, farg2;
912 uint32_t ret = 0;
913
914 farg1.ll = arg1;
915 farg2.ll = arg2;
916
917 if (unlikely(float64_is_any_nan(farg1.d) ||
918 float64_is_any_nan(farg2.d))) {
919 ret = 0x01UL;
920 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
921 ret = 0x08UL;
922 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
923 ret = 0x04UL;
924 } else {
925 ret = 0x02UL;
926 }
927
928 env->fpscr &= ~FP_FPCC;
929 env->fpscr |= ret << FPSCR_FPCC;
930 env->crf[crfD] = ret;
931 if (unlikely(ret == 0x01UL
932 && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
933 float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
934 /* sNaN comparison */
935 float_invalid_op_vxsnan(env, GETPC());
936 }
937 }
938
939 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
940 uint32_t crfD)
941 {
942 CPU_DoubleU farg1, farg2;
943 uint32_t ret = 0;
944
945 farg1.ll = arg1;
946 farg2.ll = arg2;
947
948 if (unlikely(float64_is_any_nan(farg1.d) ||
949 float64_is_any_nan(farg2.d))) {
950 ret = 0x01UL;
951 } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
952 ret = 0x08UL;
953 } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
954 ret = 0x04UL;
955 } else {
956 ret = 0x02UL;
957 }
958
959 env->fpscr &= ~FP_FPCC;
960 env->fpscr |= ret << FPSCR_FPCC;
961 env->crf[crfD] = (uint32_t) ret;
962 if (unlikely(ret == 0x01UL)) {
963 float_invalid_op_vxvc(env, 1, GETPC());
964 if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
965 float64_is_signaling_nan(farg2.d, &env->fp_status)) {
966 /* sNaN comparison */
967 float_invalid_op_vxsnan(env, GETPC());
968 }
969 }
970 }
971
972 /* Single-precision floating-point conversions */
973 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
974 {
975 CPU_FloatU u;
976
977 u.f = int32_to_float32(val, &env->vec_status);
978
979 return u.l;
980 }
981
982 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
983 {
984 CPU_FloatU u;
985
986 u.f = uint32_to_float32(val, &env->vec_status);
987
988 return u.l;
989 }
990
991 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
992 {
993 CPU_FloatU u;
994
995 u.l = val;
996 /* NaN are not treated the same way IEEE 754 does */
997 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
998 return 0;
999 }
1000
1001 return float32_to_int32(u.f, &env->vec_status);
1002 }
1003
1004 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1005 {
1006 CPU_FloatU u;
1007
1008 u.l = val;
1009 /* NaN are not treated the same way IEEE 754 does */
1010 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1011 return 0;
1012 }
1013
1014 return float32_to_uint32(u.f, &env->vec_status);
1015 }
1016
1017 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1018 {
1019 CPU_FloatU u;
1020
1021 u.l = val;
1022 /* NaN are not treated the same way IEEE 754 does */
1023 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1024 return 0;
1025 }
1026
1027 return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1028 }
1029
1030 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1031 {
1032 CPU_FloatU u;
1033
1034 u.l = val;
1035 /* NaN are not treated the same way IEEE 754 does */
1036 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1037 return 0;
1038 }
1039
1040 return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1041 }
1042
1043 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1044 {
1045 CPU_FloatU u;
1046 float32 tmp;
1047
1048 u.f = int32_to_float32(val, &env->vec_status);
1049 tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1050 u.f = float32_div(u.f, tmp, &env->vec_status);
1051
1052 return u.l;
1053 }
1054
1055 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1056 {
1057 CPU_FloatU u;
1058 float32 tmp;
1059
1060 u.f = uint32_to_float32(val, &env->vec_status);
1061 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1062 u.f = float32_div(u.f, tmp, &env->vec_status);
1063
1064 return u.l;
1065 }
1066
1067 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1068 {
1069 CPU_FloatU u;
1070 float32 tmp;
1071
1072 u.l = val;
1073 /* NaN are not treated the same way IEEE 754 does */
1074 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1075 return 0;
1076 }
1077 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1078 u.f = float32_mul(u.f, tmp, &env->vec_status);
1079
1080 return float32_to_int32(u.f, &env->vec_status);
1081 }
1082
1083 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1084 {
1085 CPU_FloatU u;
1086 float32 tmp;
1087
1088 u.l = val;
1089 /* NaN are not treated the same way IEEE 754 does */
1090 if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1091 return 0;
1092 }
1093 tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1094 u.f = float32_mul(u.f, tmp, &env->vec_status);
1095
1096 return float32_to_uint32(u.f, &env->vec_status);
1097 }
1098
1099 #define HELPER_SPE_SINGLE_CONV(name) \
1100 uint32_t helper_e##name(CPUPPCState *env, uint32_t val) \
1101 { \
1102 return e##name(env, val); \
1103 }
1104 /* efscfsi */
1105 HELPER_SPE_SINGLE_CONV(fscfsi);
1106 /* efscfui */
1107 HELPER_SPE_SINGLE_CONV(fscfui);
1108 /* efscfuf */
1109 HELPER_SPE_SINGLE_CONV(fscfuf);
1110 /* efscfsf */
1111 HELPER_SPE_SINGLE_CONV(fscfsf);
1112 /* efsctsi */
1113 HELPER_SPE_SINGLE_CONV(fsctsi);
1114 /* efsctui */
1115 HELPER_SPE_SINGLE_CONV(fsctui);
1116 /* efsctsiz */
1117 HELPER_SPE_SINGLE_CONV(fsctsiz);
1118 /* efsctuiz */
1119 HELPER_SPE_SINGLE_CONV(fsctuiz);
1120 /* efsctsf */
1121 HELPER_SPE_SINGLE_CONV(fsctsf);
1122 /* efsctuf */
1123 HELPER_SPE_SINGLE_CONV(fsctuf);
1124
1125 #define HELPER_SPE_VECTOR_CONV(name) \
1126 uint64_t helper_ev##name(CPUPPCState *env, uint64_t val) \
1127 { \
1128 return ((uint64_t)e##name(env, val >> 32) << 32) | \
1129 (uint64_t)e##name(env, val); \
1130 }
1131 /* evfscfsi */
1132 HELPER_SPE_VECTOR_CONV(fscfsi);
1133 /* evfscfui */
1134 HELPER_SPE_VECTOR_CONV(fscfui);
1135 /* evfscfuf */
1136 HELPER_SPE_VECTOR_CONV(fscfuf);
1137 /* evfscfsf */
1138 HELPER_SPE_VECTOR_CONV(fscfsf);
1139 /* evfsctsi */
1140 HELPER_SPE_VECTOR_CONV(fsctsi);
1141 /* evfsctui */
1142 HELPER_SPE_VECTOR_CONV(fsctui);
1143 /* evfsctsiz */
1144 HELPER_SPE_VECTOR_CONV(fsctsiz);
1145 /* evfsctuiz */
1146 HELPER_SPE_VECTOR_CONV(fsctuiz);
1147 /* evfsctsf */
1148 HELPER_SPE_VECTOR_CONV(fsctsf);
1149 /* evfsctuf */
1150 HELPER_SPE_VECTOR_CONV(fsctuf);
1151
1152 /* Single-precision floating-point arithmetic */
1153 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1154 {
1155 CPU_FloatU u1, u2;
1156
1157 u1.l = op1;
1158 u2.l = op2;
1159 u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1160 return u1.l;
1161 }
1162
1163 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1164 {
1165 CPU_FloatU u1, u2;
1166
1167 u1.l = op1;
1168 u2.l = op2;
1169 u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1170 return u1.l;
1171 }
1172
1173 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1174 {
1175 CPU_FloatU u1, u2;
1176
1177 u1.l = op1;
1178 u2.l = op2;
1179 u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1180 return u1.l;
1181 }
1182
1183 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1184 {
1185 CPU_FloatU u1, u2;
1186
1187 u1.l = op1;
1188 u2.l = op2;
1189 u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1190 return u1.l;
1191 }
1192
1193 #define HELPER_SPE_SINGLE_ARITH(name) \
1194 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1195 { \
1196 return e##name(env, op1, op2); \
1197 }
1198 /* efsadd */
1199 HELPER_SPE_SINGLE_ARITH(fsadd);
1200 /* efssub */
1201 HELPER_SPE_SINGLE_ARITH(fssub);
1202 /* efsmul */
1203 HELPER_SPE_SINGLE_ARITH(fsmul);
1204 /* efsdiv */
1205 HELPER_SPE_SINGLE_ARITH(fsdiv);
1206
1207 #define HELPER_SPE_VECTOR_ARITH(name) \
1208 uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1209 { \
1210 return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) | \
1211 (uint64_t)e##name(env, op1, op2); \
1212 }
1213 /* evfsadd */
1214 HELPER_SPE_VECTOR_ARITH(fsadd);
1215 /* evfssub */
1216 HELPER_SPE_VECTOR_ARITH(fssub);
1217 /* evfsmul */
1218 HELPER_SPE_VECTOR_ARITH(fsmul);
1219 /* evfsdiv */
1220 HELPER_SPE_VECTOR_ARITH(fsdiv);
1221
1222 /* Single-precision floating-point comparisons */
1223 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1224 {
1225 CPU_FloatU u1, u2;
1226
1227 u1.l = op1;
1228 u2.l = op2;
1229 return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1230 }
1231
1232 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1233 {
1234 CPU_FloatU u1, u2;
1235
1236 u1.l = op1;
1237 u2.l = op2;
1238 return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1239 }
1240
1241 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1242 {
1243 CPU_FloatU u1, u2;
1244
1245 u1.l = op1;
1246 u2.l = op2;
1247 return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1248 }
1249
1250 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1251 {
1252 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1253 return efscmplt(env, op1, op2);
1254 }
1255
1256 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1257 {
1258 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1259 return efscmpgt(env, op1, op2);
1260 }
1261
1262 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1263 {
1264 /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1265 return efscmpeq(env, op1, op2);
1266 }
1267
1268 #define HELPER_SINGLE_SPE_CMP(name) \
1269 uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1270 { \
1271 return e##name(env, op1, op2); \
1272 }
1273 /* efststlt */
1274 HELPER_SINGLE_SPE_CMP(fststlt);
1275 /* efststgt */
1276 HELPER_SINGLE_SPE_CMP(fststgt);
1277 /* efststeq */
1278 HELPER_SINGLE_SPE_CMP(fststeq);
1279 /* efscmplt */
1280 HELPER_SINGLE_SPE_CMP(fscmplt);
1281 /* efscmpgt */
1282 HELPER_SINGLE_SPE_CMP(fscmpgt);
1283 /* efscmpeq */
1284 HELPER_SINGLE_SPE_CMP(fscmpeq);
1285
1286 static inline uint32_t evcmp_merge(int t0, int t1)
1287 {
1288 return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1289 }
1290
1291 #define HELPER_VECTOR_SPE_CMP(name) \
1292 uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1293 { \
1294 return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32), \
1295 e##name(env, op1, op2)); \
1296 }
1297 /* evfststlt */
1298 HELPER_VECTOR_SPE_CMP(fststlt);
1299 /* evfststgt */
1300 HELPER_VECTOR_SPE_CMP(fststgt);
1301 /* evfststeq */
1302 HELPER_VECTOR_SPE_CMP(fststeq);
1303 /* evfscmplt */
1304 HELPER_VECTOR_SPE_CMP(fscmplt);
1305 /* evfscmpgt */
1306 HELPER_VECTOR_SPE_CMP(fscmpgt);
1307 /* evfscmpeq */
1308 HELPER_VECTOR_SPE_CMP(fscmpeq);
1309
1310 /* Double-precision floating-point conversion */
1311 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1312 {
1313 CPU_DoubleU u;
1314
1315 u.d = int32_to_float64(val, &env->vec_status);
1316
1317 return u.ll;
1318 }
1319
1320 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1321 {
1322 CPU_DoubleU u;
1323
1324 u.d = int64_to_float64(val, &env->vec_status);
1325
1326 return u.ll;
1327 }
1328
1329 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1330 {
1331 CPU_DoubleU u;
1332
1333 u.d = uint32_to_float64(val, &env->vec_status);
1334
1335 return u.ll;
1336 }
1337
1338 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1339 {
1340 CPU_DoubleU u;
1341
1342 u.d = uint64_to_float64(val, &env->vec_status);
1343
1344 return u.ll;
1345 }
1346
1347 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1348 {
1349 CPU_DoubleU u;
1350
1351 u.ll = val;
1352 /* NaN are not treated the same way IEEE 754 does */
1353 if (unlikely(float64_is_any_nan(u.d))) {
1354 return 0;
1355 }
1356
1357 return float64_to_int32(u.d, &env->vec_status);
1358 }
1359
1360 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1361 {
1362 CPU_DoubleU u;
1363
1364 u.ll = val;
1365 /* NaN are not treated the same way IEEE 754 does */
1366 if (unlikely(float64_is_any_nan(u.d))) {
1367 return 0;
1368 }
1369
1370 return float64_to_uint32(u.d, &env->vec_status);
1371 }
1372
1373 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1374 {
1375 CPU_DoubleU u;
1376
1377 u.ll = val;
1378 /* NaN are not treated the same way IEEE 754 does */
1379 if (unlikely(float64_is_any_nan(u.d))) {
1380 return 0;
1381 }
1382
1383 return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1384 }
1385
1386 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1387 {
1388 CPU_DoubleU u;
1389
1390 u.ll = val;
1391 /* NaN are not treated the same way IEEE 754 does */
1392 if (unlikely(float64_is_any_nan(u.d))) {
1393 return 0;
1394 }
1395
1396 return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1397 }
1398
1399 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1400 {
1401 CPU_DoubleU u;
1402
1403 u.ll = val;
1404 /* NaN are not treated the same way IEEE 754 does */
1405 if (unlikely(float64_is_any_nan(u.d))) {
1406 return 0;
1407 }
1408
1409 return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1410 }
1411
1412 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1413 {
1414 CPU_DoubleU u;
1415
1416 u.ll = val;
1417 /* NaN are not treated the same way IEEE 754 does */
1418 if (unlikely(float64_is_any_nan(u.d))) {
1419 return 0;
1420 }
1421
1422 return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1423 }
1424
1425 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1426 {
1427 CPU_DoubleU u;
1428 float64 tmp;
1429
1430 u.d = int32_to_float64(val, &env->vec_status);
1431 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1432 u.d = float64_div(u.d, tmp, &env->vec_status);
1433
1434 return u.ll;
1435 }
1436
1437 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1438 {
1439 CPU_DoubleU u;
1440 float64 tmp;
1441
1442 u.d = uint32_to_float64(val, &env->vec_status);
1443 tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1444 u.d = float64_div(u.d, tmp, &env->vec_status);
1445
1446 return u.ll;
1447 }
1448
1449 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1450 {
1451 CPU_DoubleU u;
1452 float64 tmp;
1453
1454 u.ll = val;
1455 /* NaN are not treated the same way IEEE 754 does */
1456 if (unlikely(float64_is_any_nan(u.d))) {
1457 return 0;
1458 }
1459 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1460 u.d = float64_mul(u.d, tmp, &env->vec_status);
1461
1462 return float64_to_int32(u.d, &env->vec_status);
1463 }
1464
1465 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1466 {
1467 CPU_DoubleU u;
1468 float64 tmp;
1469
1470 u.ll = val;
1471 /* NaN are not treated the same way IEEE 754 does */
1472 if (unlikely(float64_is_any_nan(u.d))) {
1473 return 0;
1474 }
1475 tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1476 u.d = float64_mul(u.d, tmp, &env->vec_status);
1477
1478 return float64_to_uint32(u.d, &env->vec_status);
1479 }
1480
1481 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1482 {
1483 CPU_DoubleU u1;
1484 CPU_FloatU u2;
1485
1486 u1.ll = val;
1487 u2.f = float64_to_float32(u1.d, &env->vec_status);
1488
1489 return u2.l;
1490 }
1491
1492 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1493 {
1494 CPU_DoubleU u2;
1495 CPU_FloatU u1;
1496
1497 u1.l = val;
1498 u2.d = float32_to_float64(u1.f, &env->vec_status);
1499
1500 return u2.ll;
1501 }
1502
1503 /* Double precision fixed-point arithmetic */
1504 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1505 {
1506 CPU_DoubleU u1, u2;
1507
1508 u1.ll = op1;
1509 u2.ll = op2;
1510 u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1511 return u1.ll;
1512 }
1513
1514 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1515 {
1516 CPU_DoubleU u1, u2;
1517
1518 u1.ll = op1;
1519 u2.ll = op2;
1520 u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1521 return u1.ll;
1522 }
1523
1524 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1525 {
1526 CPU_DoubleU u1, u2;
1527
1528 u1.ll = op1;
1529 u2.ll = op2;
1530 u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1531 return u1.ll;
1532 }
1533
1534 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1535 {
1536 CPU_DoubleU u1, u2;
1537
1538 u1.ll = op1;
1539 u2.ll = op2;
1540 u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1541 return u1.ll;
1542 }
1543
1544 /* Double precision floating point helpers */
1545 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1546 {
1547 CPU_DoubleU u1, u2;
1548
1549 u1.ll = op1;
1550 u2.ll = op2;
1551 return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1552 }
1553
1554 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1555 {
1556 CPU_DoubleU u1, u2;
1557
1558 u1.ll = op1;
1559 u2.ll = op2;
1560 return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1561 }
1562
1563 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1564 {
1565 CPU_DoubleU u1, u2;
1566
1567 u1.ll = op1;
1568 u2.ll = op2;
1569 return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1570 }
1571
1572 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1573 {
1574 /* XXX: TODO: test special values (NaN, infinites, ...) */
1575 return helper_efdtstlt(env, op1, op2);
1576 }
1577
1578 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1579 {
1580 /* XXX: TODO: test special values (NaN, infinites, ...) */
1581 return helper_efdtstgt(env, op1, op2);
1582 }
1583
1584 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1585 {
1586 /* XXX: TODO: test special values (NaN, infinites, ...) */
1587 return helper_efdtsteq(env, op1, op2);
1588 }
1589
1590 #define float64_to_float64(x, env) x
1591
1592
1593 /*
1594 * VSX_ADD_SUB - VSX floating point add/subtract
1595 * name - instruction mnemonic
1596 * op - operation (add or sub)
1597 * nels - number of elements (1, 2 or 4)
1598 * tp - type (float32 or float64)
1599 * fld - vsr_t field (VsrD(*) or VsrW(*))
1600 * sfprf - set FPRF
1601 */
1602 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \
1603 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
1604 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1605 { \
1606 ppc_vsr_t t = *xt; \
1607 int i; \
1608 \
1609 helper_reset_fpstatus(env); \
1610 \
1611 for (i = 0; i < nels; i++) { \
1612 float_status tstat = env->fp_status; \
1613 set_float_exception_flags(0, &tstat); \
1614 t.fld = tp##_##op(xa->fld, xb->fld, &tstat); \
1615 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1616 \
1617 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1618 float_invalid_op_addsub(env, tstat.float_exception_flags, \
1619 sfprf, GETPC()); \
1620 } \
1621 \
1622 if (r2sp) { \
1623 t.fld = do_frsp(env, t.fld, GETPC()); \
1624 } \
1625 \
1626 if (sfprf) { \
1627 helper_compute_fprf_float64(env, t.fld); \
1628 } \
1629 } \
1630 *xt = t; \
1631 do_float_check_status(env, GETPC()); \
1632 }
1633
1634 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1635 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1636 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1637 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1638 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1639 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1640 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1641 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1642
1643 void helper_xsaddqp(CPUPPCState *env, uint32_t opcode,
1644 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1645 {
1646 ppc_vsr_t t = *xt;
1647 float_status tstat;
1648
1649 helper_reset_fpstatus(env);
1650
1651 tstat = env->fp_status;
1652 if (unlikely(Rc(opcode) != 0)) {
1653 tstat.float_rounding_mode = float_round_to_odd;
1654 }
1655
1656 set_float_exception_flags(0, &tstat);
1657 t.f128 = float128_add(xa->f128, xb->f128, &tstat);
1658 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1659
1660 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1661 float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
1662 }
1663
1664 helper_compute_fprf_float128(env, t.f128);
1665
1666 *xt = t;
1667 do_float_check_status(env, GETPC());
1668 }
1669
1670 /*
1671 * VSX_MUL - VSX floating point multiply
1672 * op - instruction mnemonic
1673 * nels - number of elements (1, 2 or 4)
1674 * tp - type (float32 or float64)
1675 * fld - vsr_t field (VsrD(*) or VsrW(*))
1676 * sfprf - set FPRF
1677 */
1678 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp) \
1679 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1680 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1681 { \
1682 ppc_vsr_t t = *xt; \
1683 int i; \
1684 \
1685 helper_reset_fpstatus(env); \
1686 \
1687 for (i = 0; i < nels; i++) { \
1688 float_status tstat = env->fp_status; \
1689 set_float_exception_flags(0, &tstat); \
1690 t.fld = tp##_mul(xa->fld, xb->fld, &tstat); \
1691 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1692 \
1693 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1694 float_invalid_op_mul(env, tstat.float_exception_flags, \
1695 sfprf, GETPC()); \
1696 } \
1697 \
1698 if (r2sp) { \
1699 t.fld = do_frsp(env, t.fld, GETPC()); \
1700 } \
1701 \
1702 if (sfprf) { \
1703 helper_compute_fprf_float64(env, t.fld); \
1704 } \
1705 } \
1706 \
1707 *xt = t; \
1708 do_float_check_status(env, GETPC()); \
1709 }
1710
1711 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1712 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1713 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1714 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1715
1716 void helper_xsmulqp(CPUPPCState *env, uint32_t opcode,
1717 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1718 {
1719 ppc_vsr_t t = *xt;
1720 float_status tstat;
1721
1722 helper_reset_fpstatus(env);
1723 tstat = env->fp_status;
1724 if (unlikely(Rc(opcode) != 0)) {
1725 tstat.float_rounding_mode = float_round_to_odd;
1726 }
1727
1728 set_float_exception_flags(0, &tstat);
1729 t.f128 = float128_mul(xa->f128, xb->f128, &tstat);
1730 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1731
1732 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1733 float_invalid_op_mul(env, tstat.float_exception_flags, 1, GETPC());
1734 }
1735 helper_compute_fprf_float128(env, t.f128);
1736
1737 *xt = t;
1738 do_float_check_status(env, GETPC());
1739 }
1740
1741 /*
1742 * VSX_DIV - VSX floating point divide
1743 * op - instruction mnemonic
1744 * nels - number of elements (1, 2 or 4)
1745 * tp - type (float32 or float64)
1746 * fld - vsr_t field (VsrD(*) or VsrW(*))
1747 * sfprf - set FPRF
1748 */
1749 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp) \
1750 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
1751 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1752 { \
1753 ppc_vsr_t t = *xt; \
1754 int i; \
1755 \
1756 helper_reset_fpstatus(env); \
1757 \
1758 for (i = 0; i < nels; i++) { \
1759 float_status tstat = env->fp_status; \
1760 set_float_exception_flags(0, &tstat); \
1761 t.fld = tp##_div(xa->fld, xb->fld, &tstat); \
1762 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1763 \
1764 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1765 float_invalid_op_div(env, tstat.float_exception_flags, \
1766 sfprf, GETPC()); \
1767 } \
1768 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) { \
1769 float_zero_divide_excp(env, GETPC()); \
1770 } \
1771 \
1772 if (r2sp) { \
1773 t.fld = do_frsp(env, t.fld, GETPC()); \
1774 } \
1775 \
1776 if (sfprf) { \
1777 helper_compute_fprf_float64(env, t.fld); \
1778 } \
1779 } \
1780 \
1781 *xt = t; \
1782 do_float_check_status(env, GETPC()); \
1783 }
1784
1785 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1786 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
1787 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
1788 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
1789
1790 void helper_xsdivqp(CPUPPCState *env, uint32_t opcode,
1791 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
1792 {
1793 ppc_vsr_t t = *xt;
1794 float_status tstat;
1795
1796 helper_reset_fpstatus(env);
1797 tstat = env->fp_status;
1798 if (unlikely(Rc(opcode) != 0)) {
1799 tstat.float_rounding_mode = float_round_to_odd;
1800 }
1801
1802 set_float_exception_flags(0, &tstat);
1803 t.f128 = float128_div(xa->f128, xb->f128, &tstat);
1804 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1805
1806 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1807 float_invalid_op_div(env, tstat.float_exception_flags, 1, GETPC());
1808 }
1809 if (unlikely(tstat.float_exception_flags & float_flag_divbyzero)) {
1810 float_zero_divide_excp(env, GETPC());
1811 }
1812
1813 helper_compute_fprf_float128(env, t.f128);
1814 *xt = t;
1815 do_float_check_status(env, GETPC());
1816 }
1817
1818 /*
1819 * VSX_RE - VSX floating point reciprocal estimate
1820 * op - instruction mnemonic
1821 * nels - number of elements (1, 2 or 4)
1822 * tp - type (float32 or float64)
1823 * fld - vsr_t field (VsrD(*) or VsrW(*))
1824 * sfprf - set FPRF
1825 */
1826 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp) \
1827 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1828 { \
1829 ppc_vsr_t t = *xt; \
1830 int i; \
1831 \
1832 helper_reset_fpstatus(env); \
1833 \
1834 for (i = 0; i < nels; i++) { \
1835 if (unlikely(tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
1836 float_invalid_op_vxsnan(env, GETPC()); \
1837 } \
1838 t.fld = tp##_div(tp##_one, xb->fld, &env->fp_status); \
1839 \
1840 if (r2sp) { \
1841 t.fld = do_frsp(env, t.fld, GETPC()); \
1842 } \
1843 \
1844 if (sfprf) { \
1845 helper_compute_fprf_float64(env, t.fld); \
1846 } \
1847 } \
1848 \
1849 *xt = t; \
1850 do_float_check_status(env, GETPC()); \
1851 }
1852
1853 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
1854 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
1855 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
1856 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
1857
1858 /*
1859 * VSX_SQRT - VSX floating point square root
1860 * op - instruction mnemonic
1861 * nels - number of elements (1, 2 or 4)
1862 * tp - type (float32 or float64)
1863 * fld - vsr_t field (VsrD(*) or VsrW(*))
1864 * sfprf - set FPRF
1865 */
1866 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp) \
1867 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1868 { \
1869 ppc_vsr_t t = *xt; \
1870 int i; \
1871 \
1872 helper_reset_fpstatus(env); \
1873 \
1874 for (i = 0; i < nels; i++) { \
1875 float_status tstat = env->fp_status; \
1876 set_float_exception_flags(0, &tstat); \
1877 t.fld = tp##_sqrt(xb->fld, &tstat); \
1878 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1879 \
1880 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1881 float_invalid_op_sqrt(env, tstat.float_exception_flags, \
1882 sfprf, GETPC()); \
1883 } \
1884 \
1885 if (r2sp) { \
1886 t.fld = do_frsp(env, t.fld, GETPC()); \
1887 } \
1888 \
1889 if (sfprf) { \
1890 helper_compute_fprf_float64(env, t.fld); \
1891 } \
1892 } \
1893 \
1894 *xt = t; \
1895 do_float_check_status(env, GETPC()); \
1896 }
1897
1898 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
1899 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
1900 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
1901 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
1902
1903 /*
1904 *VSX_RSQRTE - VSX floating point reciprocal square root estimate
1905 * op - instruction mnemonic
1906 * nels - number of elements (1, 2 or 4)
1907 * tp - type (float32 or float64)
1908 * fld - vsr_t field (VsrD(*) or VsrW(*))
1909 * sfprf - set FPRF
1910 */
1911 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp) \
1912 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
1913 { \
1914 ppc_vsr_t t = *xt; \
1915 int i; \
1916 \
1917 helper_reset_fpstatus(env); \
1918 \
1919 for (i = 0; i < nels; i++) { \
1920 float_status tstat = env->fp_status; \
1921 set_float_exception_flags(0, &tstat); \
1922 t.fld = tp##_sqrt(xb->fld, &tstat); \
1923 t.fld = tp##_div(tp##_one, t.fld, &tstat); \
1924 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1925 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
1926 float_invalid_op_sqrt(env, tstat.float_exception_flags, \
1927 sfprf, GETPC()); \
1928 } \
1929 if (r2sp) { \
1930 t.fld = do_frsp(env, t.fld, GETPC()); \
1931 } \
1932 \
1933 if (sfprf) { \
1934 helper_compute_fprf_float64(env, t.fld); \
1935 } \
1936 } \
1937 \
1938 *xt = t; \
1939 do_float_check_status(env, GETPC()); \
1940 }
1941
1942 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
1943 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
1944 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
1945 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
1946
1947 /*
1948 * VSX_TDIV - VSX floating point test for divide
1949 * op - instruction mnemonic
1950 * nels - number of elements (1, 2 or 4)
1951 * tp - type (float32 or float64)
1952 * fld - vsr_t field (VsrD(*) or VsrW(*))
1953 * emin - minimum unbiased exponent
1954 * emax - maximum unbiased exponent
1955 * nbits - number of fraction bits
1956 */
1957 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits) \
1958 void helper_##op(CPUPPCState *env, uint32_t opcode, \
1959 ppc_vsr_t *xa, ppc_vsr_t *xb) \
1960 { \
1961 int i; \
1962 int fe_flag = 0; \
1963 int fg_flag = 0; \
1964 \
1965 for (i = 0; i < nels; i++) { \
1966 if (unlikely(tp##_is_infinity(xa->fld) || \
1967 tp##_is_infinity(xb->fld) || \
1968 tp##_is_zero(xb->fld))) { \
1969 fe_flag = 1; \
1970 fg_flag = 1; \
1971 } else { \
1972 int e_a = ppc_##tp##_get_unbiased_exp(xa->fld); \
1973 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
1974 \
1975 if (unlikely(tp##_is_any_nan(xa->fld) || \
1976 tp##_is_any_nan(xb->fld))) { \
1977 fe_flag = 1; \
1978 } else if ((e_b <= emin) || (e_b >= (emax - 2))) { \
1979 fe_flag = 1; \
1980 } else if (!tp##_is_zero(xa->fld) && \
1981 (((e_a - e_b) >= emax) || \
1982 ((e_a - e_b) <= (emin + 1)) || \
1983 (e_a <= (emin + nbits)))) { \
1984 fe_flag = 1; \
1985 } \
1986 \
1987 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
1988 /* \
1989 * XB is not zero because of the above check and so \
1990 * must be denormalized. \
1991 */ \
1992 fg_flag = 1; \
1993 } \
1994 } \
1995 } \
1996 \
1997 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
1998 }
1999
2000 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2001 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2002 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2003
2004 /*
2005 * VSX_TSQRT - VSX floating point test for square root
2006 * op - instruction mnemonic
2007 * nels - number of elements (1, 2 or 4)
2008 * tp - type (float32 or float64)
2009 * fld - vsr_t field (VsrD(*) or VsrW(*))
2010 * emin - minimum unbiased exponent
2011 * emax - maximum unbiased exponent
2012 * nbits - number of fraction bits
2013 */
2014 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits) \
2015 void helper_##op(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb) \
2016 { \
2017 int i; \
2018 int fe_flag = 0; \
2019 int fg_flag = 0; \
2020 \
2021 for (i = 0; i < nels; i++) { \
2022 if (unlikely(tp##_is_infinity(xb->fld) || \
2023 tp##_is_zero(xb->fld))) { \
2024 fe_flag = 1; \
2025 fg_flag = 1; \
2026 } else { \
2027 int e_b = ppc_##tp##_get_unbiased_exp(xb->fld); \
2028 \
2029 if (unlikely(tp##_is_any_nan(xb->fld))) { \
2030 fe_flag = 1; \
2031 } else if (unlikely(tp##_is_zero(xb->fld))) { \
2032 fe_flag = 1; \
2033 } else if (unlikely(tp##_is_neg(xb->fld))) { \
2034 fe_flag = 1; \
2035 } else if (!tp##_is_zero(xb->fld) && \
2036 (e_b <= (emin + nbits))) { \
2037 fe_flag = 1; \
2038 } \
2039 \
2040 if (unlikely(tp##_is_zero_or_denormal(xb->fld))) { \
2041 /* \
2042 * XB is not zero because of the above check and \
2043 * therefore must be denormalized. \
2044 */ \
2045 fg_flag = 1; \
2046 } \
2047 } \
2048 } \
2049 \
2050 env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2051 }
2052
2053 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2054 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2055 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2056
2057 /*
2058 * VSX_MADD - VSX floating point muliply/add variations
2059 * op - instruction mnemonic
2060 * nels - number of elements (1, 2 or 4)
2061 * tp - type (float32 or float64)
2062 * fld - vsr_t field (VsrD(*) or VsrW(*))
2063 * maddflgs - flags for the float*muladd routine that control the
2064 * various forms (madd, msub, nmadd, nmsub)
2065 * sfprf - set FPRF
2066 */
2067 #define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) \
2068 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2069 ppc_vsr_t *xa, ppc_vsr_t *b, ppc_vsr_t *c) \
2070 { \
2071 ppc_vsr_t t = *xt; \
2072 int i; \
2073 \
2074 helper_reset_fpstatus(env); \
2075 \
2076 for (i = 0; i < nels; i++) { \
2077 float_status tstat = env->fp_status; \
2078 set_float_exception_flags(0, &tstat); \
2079 if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2080 /* \
2081 * Avoid double rounding errors by rounding the intermediate \
2082 * result to odd. \
2083 */ \
2084 set_float_rounding_mode(float_round_to_zero, &tstat); \
2085 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2086 maddflgs, &tstat); \
2087 t.fld |= (get_float_exception_flags(&tstat) & \
2088 float_flag_inexact) != 0; \
2089 } else { \
2090 t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
2091 maddflgs, &tstat); \
2092 } \
2093 env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2094 \
2095 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
2096 float_invalid_op_madd(env, tstat.float_exception_flags, \
2097 sfprf, GETPC()); \
2098 } \
2099 \
2100 if (r2sp) { \
2101 t.fld = do_frsp(env, t.fld, GETPC()); \
2102 } \
2103 \
2104 if (sfprf) { \
2105 helper_compute_fprf_float64(env, t.fld); \
2106 } \
2107 } \
2108 *xt = t; \
2109 do_float_check_status(env, GETPC()); \
2110 }
2111
2112 VSX_MADD(xsmadddp, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
2113 VSX_MADD(xsmsubdp, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
2114 VSX_MADD(xsnmadddp, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
2115 VSX_MADD(xsnmsubdp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
2116 VSX_MADD(xsmaddsp, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
2117 VSX_MADD(xsmsubsp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
2118 VSX_MADD(xsnmaddsp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
2119 VSX_MADD(xsnmsubsp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
2120
2121 VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0)
2122 VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0)
2123 VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0)
2124 VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0)
2125
2126 VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0)
2127 VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
2128 VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
2129 VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
2130
2131 /*
2132 * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
2133 * op - instruction mnemonic
2134 * cmp - comparison operation
2135 * exp - expected result of comparison
2136 * svxvc - set VXVC bit
2137 */
2138 #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
2139 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2140 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2141 { \
2142 ppc_vsr_t t = *xt; \
2143 bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
2144 \
2145 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2146 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2147 vxsnan_flag = true; \
2148 if (fpscr_ve == 0 && svxvc) { \
2149 vxvc_flag = true; \
2150 } \
2151 } else if (svxvc) { \
2152 vxvc_flag = float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
2153 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status); \
2154 } \
2155 if (vxsnan_flag) { \
2156 float_invalid_op_vxsnan(env, GETPC()); \
2157 } \
2158 if (vxvc_flag) { \
2159 float_invalid_op_vxvc(env, 0, GETPC()); \
2160 } \
2161 vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
2162 \
2163 if (!vex_flag) { \
2164 if (float64_##cmp(xb->VsrD(0), xa->VsrD(0), \
2165 &env->fp_status) == exp) { \
2166 t.VsrD(0) = -1; \
2167 t.VsrD(1) = 0; \
2168 } else { \
2169 t.VsrD(0) = 0; \
2170 t.VsrD(1) = 0; \
2171 } \
2172 } \
2173 *xt = t; \
2174 do_float_check_status(env, GETPC()); \
2175 }
2176
2177 VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
2178 VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
2179 VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
2180 VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
2181
2182 void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
2183 ppc_vsr_t *xa, ppc_vsr_t *xb)
2184 {
2185 int64_t exp_a, exp_b;
2186 uint32_t cc;
2187
2188 exp_a = extract64(xa->VsrD(0), 52, 11);
2189 exp_b = extract64(xb->VsrD(0), 52, 11);
2190
2191 if (unlikely(float64_is_any_nan(xa->VsrD(0)) ||
2192 float64_is_any_nan(xb->VsrD(0)))) {
2193 cc = CRF_SO;
2194 } else {
2195 if (exp_a < exp_b) {
2196 cc = CRF_LT;
2197 } else if (exp_a > exp_b) {
2198 cc = CRF_GT;
2199 } else {
2200 cc = CRF_EQ;
2201 }
2202 }
2203
2204 env->fpscr &= ~FP_FPCC;
2205 env->fpscr |= cc << FPSCR_FPCC;
2206 env->crf[BF(opcode)] = cc;
2207
2208 do_float_check_status(env, GETPC());
2209 }
2210
2211 void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode,
2212 ppc_vsr_t *xa, ppc_vsr_t *xb)
2213 {
2214 int64_t exp_a, exp_b;
2215 uint32_t cc;
2216
2217 exp_a = extract64(xa->VsrD(0), 48, 15);
2218 exp_b = extract64(xb->VsrD(0), 48, 15);
2219
2220 if (unlikely(float128_is_any_nan(xa->f128) ||
2221 float128_is_any_nan(xb->f128))) {
2222 cc = CRF_SO;
2223 } else {
2224 if (exp_a < exp_b) {
2225 cc = CRF_LT;
2226 } else if (exp_a > exp_b) {
2227 cc = CRF_GT;
2228 } else {
2229 cc = CRF_EQ;
2230 }
2231 }
2232
2233 env->fpscr &= ~FP_FPCC;
2234 env->fpscr |= cc << FPSCR_FPCC;
2235 env->crf[BF(opcode)] = cc;
2236
2237 do_float_check_status(env, GETPC());
2238 }
2239
2240 static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,
2241 int crf_idx, bool ordered)
2242 {
2243 uint32_t cc;
2244 bool vxsnan_flag = false, vxvc_flag = false;
2245
2246 helper_reset_fpstatus(env);
2247
2248 switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) {
2249 case float_relation_less:
2250 cc = CRF_LT;
2251 break;
2252 case float_relation_equal:
2253 cc = CRF_EQ;
2254 break;
2255 case float_relation_greater:
2256 cc = CRF_GT;
2257 break;
2258 case float_relation_unordered:
2259 cc = CRF_SO;
2260
2261 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||
2262 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {
2263 vxsnan_flag = true;
2264 if (fpscr_ve == 0 && ordered) {
2265 vxvc_flag = true;
2266 }
2267 } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||
2268 float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) {
2269 if (ordered) {
2270 vxvc_flag = true;
2271 }
2272 }
2273
2274 break;
2275 default:
2276 g_assert_not_reached();
2277 }
2278
2279 env->fpscr &= ~FP_FPCC;
2280 env->fpscr |= cc << FPSCR_FPCC;
2281 env->crf[crf_idx] = cc;
2282
2283 if (vxsnan_flag) {
2284 float_invalid_op_vxsnan(env, GETPC());
2285 }
2286 if (vxvc_flag) {
2287 float_invalid_op_vxvc(env, 0, GETPC());
2288 }
2289
2290 do_float_check_status(env, GETPC());
2291 }
2292
2293 void helper_xscmpodp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2294 ppc_vsr_t *xb)
2295 {
2296 do_scalar_cmp(env, xa, xb, BF(opcode), true);
2297 }
2298
2299 void helper_xscmpudp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2300 ppc_vsr_t *xb)
2301 {
2302 do_scalar_cmp(env, xa, xb, BF(opcode), false);
2303 }
2304
2305 static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,
2306 ppc_vsr_t *xb, int crf_idx, bool ordered)
2307 {
2308 uint32_t cc;
2309 bool vxsnan_flag = false, vxvc_flag = false;
2310
2311 helper_reset_fpstatus(env);
2312
2313 switch (float128_compare(xa->f128, xb->f128, &env->fp_status)) {
2314 case float_relation_less:
2315 cc = CRF_LT;
2316 break;
2317 case float_relation_equal:
2318 cc = CRF_EQ;
2319 break;
2320 case float_relation_greater:
2321 cc = CRF_GT;
2322 break;
2323 case float_relation_unordered:
2324 cc = CRF_SO;
2325
2326 if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||
2327 float128_is_signaling_nan(xb->f128, &env->fp_status)) {
2328 vxsnan_flag = true;
2329 if (fpscr_ve == 0 && ordered) {
2330 vxvc_flag = true;
2331 }
2332 } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||
2333 float128_is_quiet_nan(xb->f128, &env->fp_status)) {
2334 if (ordered) {
2335 vxvc_flag = true;
2336 }
2337 }
2338
2339 break;
2340 default:
2341 g_assert_not_reached();
2342 }
2343
2344 env->fpscr &= ~FP_FPCC;
2345 env->fpscr |= cc << FPSCR_FPCC;
2346 env->crf[crf_idx] = cc;
2347
2348 if (vxsnan_flag) {
2349 float_invalid_op_vxsnan(env, GETPC());
2350 }
2351 if (vxvc_flag) {
2352 float_invalid_op_vxvc(env, 0, GETPC());
2353 }
2354
2355 do_float_check_status(env, GETPC());
2356 }
2357
2358 void helper_xscmpoqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2359 ppc_vsr_t *xb)
2360 {
2361 do_scalar_cmpq(env, xa, xb, BF(opcode), true);
2362 }
2363
2364 void helper_xscmpuqp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xa,
2365 ppc_vsr_t *xb)
2366 {
2367 do_scalar_cmpq(env, xa, xb, BF(opcode), false);
2368 }
2369
2370 /*
2371 * VSX_MAX_MIN - VSX floating point maximum/minimum
2372 * name - instruction mnemonic
2373 * op - operation (max or min)
2374 * nels - number of elements (1, 2 or 4)
2375 * tp - type (float32 or float64)
2376 * fld - vsr_t field (VsrD(*) or VsrW(*))
2377 */
2378 #define VSX_MAX_MIN(name, op, nels, tp, fld) \
2379 void helper_##name(CPUPPCState *env, ppc_vsr_t *xt, \
2380 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2381 { \
2382 ppc_vsr_t t = *xt; \
2383 int i; \
2384 \
2385 for (i = 0; i < nels; i++) { \
2386 t.fld = tp##_##op(xa->fld, xb->fld, &env->fp_status); \
2387 if (unlikely(tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2388 tp##_is_signaling_nan(xb->fld, &env->fp_status))) { \
2389 float_invalid_op_vxsnan(env, GETPC()); \
2390 } \
2391 } \
2392 \
2393 *xt = t; \
2394 do_float_check_status(env, GETPC()); \
2395 }
2396
2397 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2398 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2399 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2400 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2401 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2402 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2403
2404 #define VSX_MAX_MINC(name, max) \
2405 void helper_##name(CPUPPCState *env, uint32_t opcode, \
2406 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2407 { \
2408 ppc_vsr_t t = *xt; \
2409 bool vxsnan_flag = false, vex_flag = false; \
2410 \
2411 if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
2412 float64_is_any_nan(xb->VsrD(0)))) { \
2413 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
2414 float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2415 vxsnan_flag = true; \
2416 } \
2417 t.VsrD(0) = xb->VsrD(0); \
2418 } else if ((max && \
2419 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2420 (!max && \
2421 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2422 t.VsrD(0) = xa->VsrD(0); \
2423 } else { \
2424 t.VsrD(0) = xb->VsrD(0); \
2425 } \
2426 \
2427 vex_flag = fpscr_ve & vxsnan_flag; \
2428 if (vxsnan_flag) { \
2429 float_invalid_op_vxsnan(env, GETPC()); \
2430 } \
2431 if (!vex_flag) { \
2432 *xt = t; \
2433 } \
2434 } \
2435
2436 VSX_MAX_MINC(xsmaxcdp, 1);
2437 VSX_MAX_MINC(xsmincdp, 0);
2438
2439 #define VSX_MAX_MINJ(name, max) \
2440 void helper_##name(CPUPPCState *env, uint32_t opcode, \
2441 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
2442 { \
2443 ppc_vsr_t t = *xt; \
2444 bool vxsnan_flag = false, vex_flag = false; \
2445 \
2446 if (unlikely(float64_is_any_nan(xa->VsrD(0)))) { \
2447 if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status)) { \
2448 vxsnan_flag = true; \
2449 } \
2450 t.VsrD(0) = xa->VsrD(0); \
2451 } else if (unlikely(float64_is_any_nan(xb->VsrD(0)))) { \
2452 if (float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
2453 vxsnan_flag = true; \
2454 } \
2455 t.VsrD(0) = xb->VsrD(0); \
2456 } else if (float64_is_zero(xa->VsrD(0)) && \
2457 float64_is_zero(xb->VsrD(0))) { \
2458 if (max) { \
2459 if (!float64_is_neg(xa->VsrD(0)) || \
2460 !float64_is_neg(xb->VsrD(0))) { \
2461 t.VsrD(0) = 0ULL; \
2462 } else { \
2463 t.VsrD(0) = 0x8000000000000000ULL; \
2464 } \
2465 } else { \
2466 if (float64_is_neg(xa->VsrD(0)) || \
2467 float64_is_neg(xb->VsrD(0))) { \
2468 t.VsrD(0) = 0x8000000000000000ULL; \
2469 } else { \
2470 t.VsrD(0) = 0ULL; \
2471 } \
2472 } \
2473 } else if ((max && \
2474 !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
2475 (!max && \
2476 float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
2477 t.VsrD(0) = xa->VsrD(0); \
2478 } else { \
2479 t.VsrD(0) = xb->VsrD(0); \
2480 } \
2481 \
2482 vex_flag = fpscr_ve & vxsnan_flag; \
2483 if (vxsnan_flag) { \
2484 float_invalid_op_vxsnan(env, GETPC()); \
2485 } \
2486 if (!vex_flag) { \
2487 *xt = t; \
2488 } \
2489 } \
2490
2491 VSX_MAX_MINJ(xsmaxjdp, 1);
2492 VSX_MAX_MINJ(xsminjdp, 0);
2493
2494 /*
2495 * VSX_CMP - VSX floating point compare
2496 * op - instruction mnemonic
2497 * nels - number of elements (1, 2 or 4)
2498 * tp - type (float32 or float64)
2499 * fld - vsr_t field (VsrD(*) or VsrW(*))
2500 * cmp - comparison operation
2501 * svxvc - set VXVC bit
2502 * exp - expected result of comparison
2503 */
2504 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp) \
2505 uint32_t helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2506 ppc_vsr_t *xa, ppc_vsr_t *xb) \
2507 { \
2508 ppc_vsr_t t = *xt; \
2509 uint32_t crf6 = 0; \
2510 int i; \
2511 int all_true = 1; \
2512 int all_false = 1; \
2513 \
2514 for (i = 0; i < nels; i++) { \
2515 if (unlikely(tp##_is_any_nan(xa->fld) || \
2516 tp##_is_any_nan(xb->fld))) { \
2517 if (tp##_is_signaling_nan(xa->fld, &env->fp_status) || \
2518 tp##_is_signaling_nan(xb->fld, &env->fp_status)) { \
2519 float_invalid_op_vxsnan(env, GETPC()); \
2520 } \
2521 if (svxvc) { \
2522 float_invalid_op_vxvc(env, 0, GETPC()); \
2523 } \
2524 t.fld = 0; \
2525 all_true = 0; \
2526 } else { \
2527 if (tp##_##cmp(xb->fld, xa->fld, &env->fp_status) == exp) { \
2528 t.fld = -1; \
2529 all_false = 0; \
2530 } else { \
2531 t.fld = 0; \
2532 all_true = 0; \
2533 } \
2534 } \
2535 } \
2536 \
2537 *xt = t; \
2538 crf6 = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0); \
2539 return crf6; \
2540 }
2541
2542 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1)
2543 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1, 1)
2544 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1, 1)
2545 VSX_CMP(xvcmpnedp, 2, float64, VsrD(i), eq, 0, 0)
2546 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0, 1)
2547 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1, 1)
2548 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1, 1)
2549 VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0)
2550
2551 /*
2552 * VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2553 * op - instruction mnemonic
2554 * nels - number of elements (1, 2 or 4)
2555 * stp - source type (float32 or float64)
2556 * ttp - target type (float32 or float64)
2557 * sfld - source vsr_t field
2558 * tfld - target vsr_t field (f32 or f64)
2559 * sfprf - set FPRF
2560 */
2561 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2562 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2563 { \
2564 ppc_vsr_t t = *xt; \
2565 int i; \
2566 \
2567 for (i = 0; i < nels; i++) { \
2568 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2569 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2570 &env->fp_status))) { \
2571 float_invalid_op_vxsnan(env, GETPC()); \
2572 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2573 } \
2574 if (sfprf) { \
2575 helper_compute_fprf_##ttp(env, t.tfld); \
2576 } \
2577 } \
2578 \
2579 *xt = t; \
2580 do_float_check_status(env, GETPC()); \
2581 }
2582
2583 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2584 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2585 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
2586 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
2587
2588 /*
2589 * VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
2590 * op - instruction mnemonic
2591 * nels - number of elements (1, 2 or 4)
2592 * stp - source type (float32 or float64)
2593 * ttp - target type (float32 or float64)
2594 * sfld - source vsr_t field
2595 * tfld - target vsr_t field (f32 or f64)
2596 * sfprf - set FPRF
2597 */
2598 #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
2599 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2600 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2601 { \
2602 ppc_vsr_t t = *xt; \
2603 int i; \
2604 \
2605 for (i = 0; i < nels; i++) { \
2606 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2607 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2608 &env->fp_status))) { \
2609 float_invalid_op_vxsnan(env, GETPC()); \
2610 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2611 } \
2612 if (sfprf) { \
2613 helper_compute_fprf_##ttp(env, t.tfld); \
2614 } \
2615 } \
2616 \
2617 *xt = t; \
2618 do_float_check_status(env, GETPC()); \
2619 }
2620
2621 VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
2622
2623 /*
2624 * VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
2625 * involving one half precision value
2626 * op - instruction mnemonic
2627 * nels - number of elements (1, 2 or 4)
2628 * stp - source type
2629 * ttp - target type
2630 * sfld - source vsr_t field
2631 * tfld - target vsr_t field
2632 * sfprf - set FPRF
2633 */
2634 #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2635 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2636 { \
2637 ppc_vsr_t t = { }; \
2638 int i; \
2639 \
2640 for (i = 0; i < nels; i++) { \
2641 t.tfld = stp##_to_##ttp(xb->sfld, 1, &env->fp_status); \
2642 if (unlikely(stp##_is_signaling_nan(xb->sfld, \
2643 &env->fp_status))) { \
2644 float_invalid_op_vxsnan(env, GETPC()); \
2645 t.tfld = ttp##_snan_to_qnan(t.tfld); \
2646 } \
2647 if (sfprf) { \
2648 helper_compute_fprf_##ttp(env, t.tfld); \
2649 } \
2650 } \
2651 \
2652 *xt = t; \
2653 do_float_check_status(env, GETPC()); \
2654 }
2655
2656 VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
2657 VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
2658 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
2659 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
2660
2661 /*
2662 * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
2663 * added to this later.
2664 */
2665 void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
2666 ppc_vsr_t *xt, ppc_vsr_t *xb)
2667 {
2668 ppc_vsr_t t = { };
2669 float_status tstat;
2670
2671 tstat = env->fp_status;
2672 if (unlikely(Rc(opcode) != 0)) {
2673 tstat.float_rounding_mode = float_round_to_odd;
2674 }
2675
2676 t.VsrD(0) = float128_to_float64(xb->f128, &tstat);
2677 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2678 if (unlikely(float128_is_signaling_nan(xb->f128, &tstat))) {
2679 float_invalid_op_vxsnan(env, GETPC());
2680 t.VsrD(0) = float64_snan_to_qnan(t.VsrD(0));
2681 }
2682 helper_compute_fprf_float64(env, t.VsrD(0));
2683
2684 *xt = t;
2685 do_float_check_status(env, GETPC());
2686 }
2687
2688 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2689 {
2690 uint64_t result, sign, exp, frac;
2691
2692 float_status tstat = env->fp_status;
2693 set_float_exception_flags(0, &tstat);
2694
2695 sign = extract64(xb, 63, 1);
2696 exp = extract64(xb, 52, 11);
2697 frac = extract64(xb, 0, 52) | 0x10000000000000ULL;
2698
2699 if (unlikely(exp == 0 && extract64(frac, 0, 52) != 0)) {
2700 /* DP denormal operand. */
2701 /* Exponent override to DP min exp. */
2702 exp = 1;
2703 /* Implicit bit override to 0. */
2704 frac = deposit64(frac, 53, 1, 0);
2705 }
2706
2707 if (unlikely(exp < 897 && frac != 0)) {
2708 /* SP tiny operand. */
2709 if (897 - exp > 63) {
2710 frac = 0;
2711 } else {
2712 /* Denormalize until exp = SP min exp. */
2713 frac >>= (897 - exp);
2714 }
2715 /* Exponent override to SP min exp - 1. */
2716 exp = 896;
2717 }
2718
2719 result = sign << 31;
2720 result |= extract64(exp, 10, 1) << 30;
2721 result |= extract64(exp, 0, 7) << 23;
2722 result |= extract64(frac, 29, 23);
2723
2724 /* hardware replicates result to both words of the doubleword result. */
2725 return (result << 32) | result;
2726 }
2727
2728 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2729 {
2730 float_status tstat = env->fp_status;
2731 set_float_exception_flags(0, &tstat);
2732
2733 return float32_to_float64(xb >> 32, &tstat);
2734 }
2735
2736 /*
2737 * VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2738 * op - instruction mnemonic
2739 * nels - number of elements (1, 2 or 4)
2740 * stp - source type (float32 or float64)
2741 * ttp - target type (int32, uint32, int64 or uint64)
2742 * sfld - source vsr_t field
2743 * tfld - target vsr_t field
2744 * rnan - resulting NaN
2745 */
2746 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan) \
2747 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2748 { \
2749 int all_flags = env->fp_status.float_exception_flags, flags; \
2750 ppc_vsr_t t = *xt; \
2751 int i; \
2752 \
2753 for (i = 0; i < nels; i++) { \
2754 env->fp_status.float_exception_flags = 0; \
2755 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2756 flags = env->fp_status.float_exception_flags; \
2757 if (unlikely(flags & float_flag_invalid)) { \
2758 t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC());\
2759 } \
2760 all_flags |= flags; \
2761 } \
2762 \
2763 *xt = t; \
2764 env->fp_status.float_exception_flags = all_flags; \
2765 do_float_check_status(env, GETPC()); \
2766 }
2767
2768 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2769 0x8000000000000000ULL)
2770 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2771 0x80000000U)
2772 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2773 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2774 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
2775 0x8000000000000000ULL)
2776 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2 * i), \
2777 0x80000000U)
2778 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
2779 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2 * i), 0U)
2780 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), \
2781 0x8000000000000000ULL)
2782 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
2783 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
2784 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
2785
2786 /*
2787 * VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
2788 * op - instruction mnemonic
2789 * stp - source type (float32 or float64)
2790 * ttp - target type (int32, uint32, int64 or uint64)
2791 * sfld - source vsr_t field
2792 * tfld - target vsr_t field
2793 * rnan - resulting NaN
2794 */
2795 #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan) \
2796 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2797 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2798 { \
2799 ppc_vsr_t t = { }; \
2800 int flags; \
2801 \
2802 t.tfld = stp##_to_##ttp##_round_to_zero(xb->sfld, &env->fp_status); \
2803 flags = get_float_exception_flags(&env->fp_status); \
2804 if (flags & float_flag_invalid) { \
2805 t.tfld = float_invalid_cvt(env, flags, t.tfld, rnan, 0, GETPC()); \
2806 } \
2807 \
2808 *xt = t; \
2809 do_float_check_status(env, GETPC()); \
2810 }
2811
2812 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0), \
2813 0x8000000000000000ULL)
2814
2815 VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0), \
2816 0xffffffff80000000ULL)
2817 VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
2818 VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
2819
2820 /*
2821 * VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2822 * op - instruction mnemonic
2823 * nels - number of elements (1, 2 or 4)
2824 * stp - source type (int32, uint32, int64 or uint64)
2825 * ttp - target type (float32 or float64)
2826 * sfld - source vsr_t field
2827 * tfld - target vsr_t field
2828 * jdef - definition of the j index (i or 2*i)
2829 * sfprf - set FPRF
2830 */
2831 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp) \
2832 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2833 { \
2834 ppc_vsr_t t = *xt; \
2835 int i; \
2836 \
2837 for (i = 0; i < nels; i++) { \
2838 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2839 if (r2sp) { \
2840 t.tfld = do_frsp(env, t.tfld, GETPC()); \
2841 } \
2842 if (sfprf) { \
2843 helper_compute_fprf_float64(env, t.tfld); \
2844 } \
2845 } \
2846 \
2847 *xt = t; \
2848 do_float_check_status(env, GETPC()); \
2849 }
2850
2851 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
2852 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
2853 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
2854 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
2855 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
2856 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
2857 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
2858 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
2859 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
2860 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
2861 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
2862 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
2863
2864 /*
2865 * VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
2866 * op - instruction mnemonic
2867 * stp - source type (int32, uint32, int64 or uint64)
2868 * ttp - target type (float32 or float64)
2869 * sfld - source vsr_t field
2870 * tfld - target vsr_t field
2871 */
2872 #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld) \
2873 void helper_##op(CPUPPCState *env, uint32_t opcode, \
2874 ppc_vsr_t *xt, ppc_vsr_t *xb) \
2875 { \
2876 ppc_vsr_t t = *xt; \
2877 \
2878 t.tfld = stp##_to_##ttp(xb->sfld, &env->fp_status); \
2879 helper_compute_fprf_##ttp(env, t.tfld); \
2880 \
2881 *xt = t; \
2882 do_float_check_status(env, GETPC()); \
2883 }
2884
2885 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
2886 VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
2887
2888 /*
2889 * For "use current rounding mode", define a value that will not be
2890 * one of the existing rounding model enums.
2891 */
2892 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
2893 float_round_up + float_round_to_zero)
2894
2895 /*
2896 * VSX_ROUND - VSX floating point round
2897 * op - instruction mnemonic
2898 * nels - number of elements (1, 2 or 4)
2899 * tp - type (float32 or float64)
2900 * fld - vsr_t field (VsrD(*) or VsrW(*))
2901 * rmode - rounding mode
2902 * sfprf - set FPRF
2903 */
2904 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf) \
2905 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
2906 { \
2907 ppc_vsr_t t = *xt; \
2908 int i; \
2909 FloatRoundMode curr_rounding_mode; \
2910 \
2911 if (rmode != FLOAT_ROUND_CURRENT) { \
2912 curr_rounding_mode = get_float_rounding_mode(&env->fp_status); \
2913 set_float_rounding_mode(rmode, &env->fp_status); \
2914 } \
2915 \
2916 for (i = 0; i < nels; i++) { \
2917 if (unlikely(tp##_is_signaling_nan(xb->fld, \
2918 &env->fp_status))) { \
2919 float_invalid_op_vxsnan(env, GETPC()); \
2920 t.fld = tp##_snan_to_qnan(xb->fld); \
2921 } else { \
2922 t.fld = tp##_round_to_int(xb->fld, &env->fp_status); \
2923 } \
2924 if (sfprf) { \
2925 helper_compute_fprf_float64(env, t.fld); \
2926 } \
2927 } \
2928 \
2929 /* \
2930 * If this is not a "use current rounding mode" instruction, \
2931 * then inhibit setting of the XX bit and restore rounding \
2932 * mode from FPSCR \
2933 */ \
2934 if (rmode != FLOAT_ROUND_CURRENT) { \
2935 set_float_rounding_mode(curr_rounding_mode, &env->fp_status); \
2936 env->fp_status.float_exception_flags &= ~float_flag_inexact; \
2937 } \
2938 \
2939 *xt = t; \
2940 do_float_check_status(env, GETPC()); \
2941 }
2942
2943 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
2944 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
2945 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
2946 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
2947 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
2948
2949 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_ties_away, 0)
2950 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
2951 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
2952 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
2953 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
2954
2955 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_ties_away, 0)
2956 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
2957 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
2958 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
2959 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
2960
2961 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
2962 {
2963 helper_reset_fpstatus(env);
2964
2965 uint64_t xt = do_frsp(env, xb, GETPC());
2966
2967 helper_compute_fprf_float64(env, xt);
2968 do_float_check_status(env, GETPC());
2969 return xt;
2970 }
2971
2972 #define VSX_XXPERM(op, indexed) \
2973 void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
2974 ppc_vsr_t *xa, ppc_vsr_t *pcv) \
2975 { \
2976 ppc_vsr_t t = *xt; \
2977 int i, idx; \
2978 \
2979 for (i = 0; i < 16; i++) { \
2980 idx = pcv->VsrB(i) & 0x1F; \
2981 if (indexed) { \
2982 idx = 31 - idx; \
2983 } \
2984 t.VsrB(i) = (idx <= 15) ? xa->VsrB(idx) \
2985 : xt->VsrB(idx - 16); \
2986 } \
2987 *xt = t; \
2988 }
2989
2990 VSX_XXPERM(xxperm, 0)
2991 VSX_XXPERM(xxpermr, 1)
2992
2993 void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
2994 {
2995 ppc_vsr_t t = { };
2996 uint32_t exp, i, fraction;
2997
2998 for (i = 0; i < 4; i++) {
2999 exp = (xb->VsrW(i) >> 23) & 0xFF;
3000 fraction = xb->VsrW(i) & 0x7FFFFF;
3001 if (exp != 0 && exp != 255) {
3002 t.VsrW(i) = fraction | 0x00800000;
3003 } else {
3004 t.VsrW(i) = fraction;
3005 }
3006 }
3007 *xt = t;
3008 }
3009
3010 /*
3011 * VSX_TEST_DC - VSX floating point test data class
3012 * op - instruction mnemonic
3013 * nels - number of elements (1, 2 or 4)
3014 * xbn - VSR register number
3015 * tp - type (float32 or float64)
3016 * fld - vsr_t field (VsrD(*) or VsrW(*))
3017 * tfld - target vsr_t field (VsrD(*) or VsrW(*))
3018 * fld_max - target field max
3019 * scrf - set result in CR and FPCC
3020 */
3021 #define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf) \
3022 void helper_##op(CPUPPCState *env, uint32_t opcode) \
3023 { \
3024 ppc_vsr_t *xt = &env->vsr[xT(opcode)]; \
3025 ppc_vsr_t *xb = &env->vsr[xbn]; \
3026 ppc_vsr_t t = { }; \
3027 uint32_t i, sign, dcmx; \
3028 uint32_t cc, match = 0; \
3029 \
3030 if (!scrf) { \
3031 dcmx = DCMX_XV(opcode); \
3032 } else { \
3033 t = *xt; \
3034 dcmx = DCMX(opcode); \
3035 } \
3036 \
3037 for (i = 0; i < nels; i++) { \
3038 sign = tp##_is_neg(xb->fld); \
3039 if (tp##_is_any_nan(xb->fld)) { \
3040 match = extract32(dcmx, 6, 1); \
3041 } else if (tp##_is_infinity(xb->fld)) { \
3042 match = extract32(dcmx, 4 + !sign, 1); \
3043 } else if (tp##_is_zero(xb->fld)) { \
3044 match = extract32(dcmx, 2 + !sign, 1); \
3045 } else if (tp##_is_zero_or_denormal(xb->fld)) { \
3046 match = extract32(dcmx, 0 + !sign, 1); \
3047 } \
3048 \
3049 if (scrf) { \
3050 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT; \
3051 env->fpscr &= ~FP_FPCC; \
3052 env->fpscr |= cc << FPSCR_FPCC; \
3053 env->crf[BF(opcode)] = cc; \
3054 } else { \
3055 t.tfld = match ? fld_max : 0; \
3056 } \
3057 match = 0; \
3058 } \
3059 if (!scrf) { \
3060 *xt = t; \
3061 } \
3062 }
3063
3064 VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
3065 VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
3066 VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
3067 VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
3068
3069 void helper_xststdcsp(CPUPPCState *env, uint32_t opcode, ppc_vsr_t *xb)
3070 {
3071 uint32_t dcmx, sign, exp;
3072 uint32_t cc, match = 0, not_sp = 0;
3073
3074 dcmx = DCMX(opcode);
3075 exp = (xb->VsrD(0) >> 52) & 0x7FF;
3076
3077 sign = float64_is_neg(xb->VsrD(0));
3078 if (float64_is_any_nan(xb->VsrD(0))) {
3079 match = extract32(dcmx, 6, 1);
3080 } else if (float64_is_infinity(xb->VsrD(0))) {
3081 match = extract32(dcmx, 4 + !sign, 1);
3082 } else if (float64_is_zero(xb->VsrD(0))) {
3083 match = extract32(dcmx, 2 + !sign, 1);
3084 } else if (float64_is_zero_or_denormal(xb->VsrD(0)) ||
3085 (exp > 0 && exp < 0x381)) {
3086 match = extract32(dcmx, 0 + !sign, 1);
3087 }
3088
3089 not_sp = !float64_eq(xb->VsrD(0),
3090 float32_to_float64(
3091 float64_to_float32(xb->VsrD(0), &env->fp_status),
3092 &env->fp_status), &env->fp_status);
3093
3094 cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
3095 env->fpscr &= ~FP_FPCC;
3096 env->fpscr |= cc << FPSCR_FPCC;
3097 env->crf[BF(opcode)] = cc;
3098 }
3099
3100 void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
3101 ppc_vsr_t *xt, ppc_vsr_t *xb)
3102 {
3103 ppc_vsr_t t = { };
3104 uint8_t r = Rrm(opcode);
3105 uint8_t ex = Rc(opcode);
3106 uint8_t rmc = RMC(opcode);
3107 uint8_t rmode = 0;
3108 float_status tstat;
3109
3110 helper_reset_fpstatus(env);
3111
3112 if (r == 0 && rmc == 0) {
3113 rmode = float_round_ties_away;
3114 } else if (r == 0 && rmc == 0x3) {
3115 rmode = fpscr_rn;
3116 } else if (r == 1) {
3117 switch (rmc) {
3118 case 0:
3119 rmode = float_round_nearest_even;
3120 break;
3121 case 1:
3122 rmode = float_round_to_zero;
3123 break;
3124 case 2:
3125 rmode = float_round_up;
3126 break;
3127 case 3:
3128 rmode = float_round_down;
3129 break;
3130 default:
3131 abort();
3132 }
3133 }
3134
3135 tstat = env->fp_status;
3136 set_float_exception_flags(0, &tstat);
3137 set_float_rounding_mode(rmode, &tstat);
3138 t.f128 = float128_round_to_int(xb->f128, &tstat);
3139 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3140
3141 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3142 if (float128_is_signaling_nan(xb->f128, &tstat)) {
3143 float_invalid_op_vxsnan(env, GETPC());
3144 t.f128 = float128_snan_to_qnan(t.f128);
3145 }
3146 }
3147
3148 if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
3149 env->fp_status.float_exception_flags &= ~float_flag_inexact;
3150 }
3151
3152 helper_compute_fprf_float128(env, t.f128);
3153 do_float_check_status(env, GETPC());
3154 *xt = t;
3155 }
3156
3157 void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
3158 ppc_vsr_t *xt, ppc_vsr_t *xb)
3159 {
3160 ppc_vsr_t t = { };
3161 uint8_t r = Rrm(opcode);
3162 uint8_t rmc = RMC(opcode);
3163 uint8_t rmode = 0;
3164 floatx80 round_res;
3165 float_status tstat;
3166
3167 helper_reset_fpstatus(env);
3168
3169 if (r == 0 && rmc == 0) {
3170 rmode = float_round_ties_away;
3171 } else if (r == 0 && rmc == 0x3) {
3172 rmode = fpscr_rn;
3173 } else if (r == 1) {
3174 switch (rmc) {
3175 case 0:
3176 rmode = float_round_nearest_even;
3177 break;
3178 case 1:
3179 rmode = float_round_to_zero;
3180 break;
3181 case 2:
3182 rmode = float_round_up;
3183 break;
3184 case 3:
3185 rmode = float_round_down;
3186 break;
3187 default:
3188 abort();
3189 }
3190 }
3191
3192 tstat = env->fp_status;
3193 set_float_exception_flags(0, &tstat);
3194 set_float_rounding_mode(rmode, &tstat);
3195 round_res = float128_to_floatx80(xb->f128, &tstat);
3196 t.f128 = floatx80_to_float128(round_res, &tstat);
3197 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3198
3199 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3200 if (float128_is_signaling_nan(xb->f128, &tstat)) {
3201 float_invalid_op_vxsnan(env, GETPC());
3202 t.f128 = float128_snan_to_qnan(t.f128);
3203 }
3204 }
3205
3206 helper_compute_fprf_float128(env, t.f128);
3207 *xt = t;
3208 do_float_check_status(env, GETPC());
3209 }
3210
3211 void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode,
3212 ppc_vsr_t *xt, ppc_vsr_t *xb)
3213 {
3214 ppc_vsr_t t = { };
3215 float_status tstat;
3216
3217 helper_reset_fpstatus(env);
3218
3219 tstat = env->fp_status;
3220 if (unlikely(Rc(opcode) != 0)) {
3221 tstat.float_rounding_mode = float_round_to_odd;
3222 }
3223
3224 set_float_exception_flags(0, &tstat);
3225 t.f128 = float128_sqrt(xb->f128, &tstat);
3226 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3227
3228 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3229 float_invalid_op_sqrt(env, tstat.float_exception_flags, 1, GETPC());
3230 }
3231
3232 helper_compute_fprf_float128(env, t.f128);
3233 *xt = t;
3234 do_float_check_status(env, GETPC());
3235 }
3236
3237 void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
3238 ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb)
3239 {
3240 ppc_vsr_t t = *xt;
3241 float_status tstat;
3242
3243 helper_reset_fpstatus(env);
3244
3245 tstat = env->fp_status;
3246 if (unlikely(Rc(opcode) != 0)) {
3247 tstat.float_rounding_mode = float_round_to_odd;
3248 }
3249
3250 set_float_exception_flags(0, &tstat);
3251 t.f128 = float128_sub(xa->f128, xb->f128, &tstat);
3252 env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3253
3254 if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3255 float_invalid_op_addsub(env, tstat.float_exception_flags, 1, GETPC());
3256 }
3257
3258 helper_compute_fprf_float128(env, t.f128);
3259 *xt = t;
3260 do_float_check_status(env, GETPC());
3261 }
QEmu