2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
29 #include "hw/sysbus.h"
30 #include "strongarm.h"
31 #include "qemu/error-report.h"
32 #include "hw/arm/arm.h"
33 #include "sysemu/char.h"
34 #include "sysemu/sysemu.h"
41 - Implement cp15, c14 ?
42 - Implement cp15, c15 !!! (idle used in L)
43 - Implement idle mode handling/DIM
44 - Implement sleep mode/Wake sources
45 - Implement reset control
46 - Implement memory control regs
48 - Maybe support MBGNT/MBREQ
53 - Enhance UART with modem signals
57 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
59 # define DPRINTF(format, ...) do { } while (0)
66 { 0x80010000, SA_PIC_UART1
},
67 { 0x80030000, SA_PIC_UART2
},
68 { 0x80050000, SA_PIC_UART3
},
72 /* Interrupt Controller */
92 #define SA_PIC_SRCS 32
95 static void strongarm_pic_update(void *opaque
)
97 StrongARMPICState
*s
= opaque
;
99 /* FIXME: reflect DIM */
100 qemu_set_irq(s
->fiq
, s
->pending
& s
->enabled
& s
->is_fiq
);
101 qemu_set_irq(s
->irq
, s
->pending
& s
->enabled
& ~s
->is_fiq
);
104 static void strongarm_pic_set_irq(void *opaque
, int irq
, int level
)
106 StrongARMPICState
*s
= opaque
;
109 s
->pending
|= 1 << irq
;
111 s
->pending
&= ~(1 << irq
);
114 strongarm_pic_update(s
);
117 static uint64_t strongarm_pic_mem_read(void *opaque
, hwaddr offset
,
120 StrongARMPICState
*s
= opaque
;
124 return s
->pending
& ~s
->is_fiq
& s
->enabled
;
130 return s
->int_idle
== 0;
132 return s
->pending
& s
->is_fiq
& s
->enabled
;
136 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
142 static void strongarm_pic_mem_write(void *opaque
, hwaddr offset
,
143 uint64_t value
, unsigned size
)
145 StrongARMPICState
*s
= opaque
;
155 s
->int_idle
= (value
& 1) ? 0 : ~0;
158 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
162 strongarm_pic_update(s
);
165 static const MemoryRegionOps strongarm_pic_ops
= {
166 .read
= strongarm_pic_mem_read
,
167 .write
= strongarm_pic_mem_write
,
168 .endianness
= DEVICE_NATIVE_ENDIAN
,
171 static int strongarm_pic_initfn(SysBusDevice
*dev
)
173 StrongARMPICState
*s
= FROM_SYSBUS(StrongARMPICState
, dev
);
175 qdev_init_gpio_in(&dev
->qdev
, strongarm_pic_set_irq
, SA_PIC_SRCS
);
176 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_pic_ops
, s
,
178 sysbus_init_mmio(dev
, &s
->iomem
);
179 sysbus_init_irq(dev
, &s
->irq
);
180 sysbus_init_irq(dev
, &s
->fiq
);
185 static int strongarm_pic_post_load(void *opaque
, int version_id
)
187 strongarm_pic_update(opaque
);
191 static VMStateDescription vmstate_strongarm_pic_regs
= {
192 .name
= "strongarm_pic",
194 .minimum_version_id
= 0,
195 .minimum_version_id_old
= 0,
196 .post_load
= strongarm_pic_post_load
,
197 .fields
= (VMStateField
[]) {
198 VMSTATE_UINT32(pending
, StrongARMPICState
),
199 VMSTATE_UINT32(enabled
, StrongARMPICState
),
200 VMSTATE_UINT32(is_fiq
, StrongARMPICState
),
201 VMSTATE_UINT32(int_idle
, StrongARMPICState
),
202 VMSTATE_END_OF_LIST(),
206 static void strongarm_pic_class_init(ObjectClass
*klass
, void *data
)
208 DeviceClass
*dc
= DEVICE_CLASS(klass
);
209 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
211 k
->init
= strongarm_pic_initfn
;
212 dc
->desc
= "StrongARM PIC";
213 dc
->vmsd
= &vmstate_strongarm_pic_regs
;
216 static const TypeInfo strongarm_pic_info
= {
217 .name
= "strongarm_pic",
218 .parent
= TYPE_SYS_BUS_DEVICE
,
219 .instance_size
= sizeof(StrongARMPICState
),
220 .class_init
= strongarm_pic_class_init
,
223 /* Real-Time Clock */
224 #define RTAR 0x00 /* RTC Alarm register */
225 #define RCNR 0x04 /* RTC Counter register */
226 #define RTTR 0x08 /* RTC Timer Trim register */
227 #define RTSR 0x10 /* RTC Status register */
229 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
230 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
231 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
232 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
234 /* 16 LSB of RTTR are clockdiv for internal trim logic,
235 * trim delete isn't emulated, so
236 * f = 32 768 / (RTTR_trim + 1) */
246 QEMUTimer
*rtc_alarm
;
252 static inline void strongarm_rtc_int_update(StrongARMRTCState
*s
)
254 qemu_set_irq(s
->rtc_irq
, s
->rtsr
& RTSR_AL
);
255 qemu_set_irq(s
->rtc_hz_irq
, s
->rtsr
& RTSR_HZ
);
258 static void strongarm_rtc_hzupdate(StrongARMRTCState
*s
)
260 int64_t rt
= qemu_get_clock_ms(rtc_clock
);
261 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
262 (1000 * ((s
->rttr
& 0xffff) + 1));
266 static inline void strongarm_rtc_timer_update(StrongARMRTCState
*s
)
268 if ((s
->rtsr
& RTSR_HZE
) && !(s
->rtsr
& RTSR_HZ
)) {
269 qemu_mod_timer(s
->rtc_hz
, s
->last_hz
+ 1000);
271 qemu_del_timer(s
->rtc_hz
);
274 if ((s
->rtsr
& RTSR_ALE
) && !(s
->rtsr
& RTSR_AL
)) {
275 qemu_mod_timer(s
->rtc_alarm
, s
->last_hz
+
276 (((s
->rtar
- s
->last_rcnr
) * 1000 *
277 ((s
->rttr
& 0xffff) + 1)) >> 15));
279 qemu_del_timer(s
->rtc_alarm
);
283 static inline void strongarm_rtc_alarm_tick(void *opaque
)
285 StrongARMRTCState
*s
= opaque
;
287 strongarm_rtc_timer_update(s
);
288 strongarm_rtc_int_update(s
);
291 static inline void strongarm_rtc_hz_tick(void *opaque
)
293 StrongARMRTCState
*s
= opaque
;
295 strongarm_rtc_timer_update(s
);
296 strongarm_rtc_int_update(s
);
299 static uint64_t strongarm_rtc_read(void *opaque
, hwaddr addr
,
302 StrongARMRTCState
*s
= opaque
;
312 return s
->last_rcnr
+
313 ((qemu_get_clock_ms(rtc_clock
) - s
->last_hz
) << 15) /
314 (1000 * ((s
->rttr
& 0xffff) + 1));
316 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
321 static void strongarm_rtc_write(void *opaque
, hwaddr addr
,
322 uint64_t value
, unsigned size
)
324 StrongARMRTCState
*s
= opaque
;
329 strongarm_rtc_hzupdate(s
);
331 strongarm_rtc_timer_update(s
);
336 s
->rtsr
= (value
& (RTSR_ALE
| RTSR_HZE
)) |
337 (s
->rtsr
& ~(value
& (RTSR_AL
| RTSR_HZ
)));
339 if (s
->rtsr
!= old_rtsr
) {
340 strongarm_rtc_timer_update(s
);
343 strongarm_rtc_int_update(s
);
348 strongarm_rtc_timer_update(s
);
352 strongarm_rtc_hzupdate(s
);
353 s
->last_rcnr
= value
;
354 strongarm_rtc_timer_update(s
);
358 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
362 static const MemoryRegionOps strongarm_rtc_ops
= {
363 .read
= strongarm_rtc_read
,
364 .write
= strongarm_rtc_write
,
365 .endianness
= DEVICE_NATIVE_ENDIAN
,
368 static int strongarm_rtc_init(SysBusDevice
*dev
)
370 StrongARMRTCState
*s
= FROM_SYSBUS(StrongARMRTCState
, dev
);
376 qemu_get_timedate(&tm
, 0);
378 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
379 s
->last_hz
= qemu_get_clock_ms(rtc_clock
);
381 s
->rtc_alarm
= qemu_new_timer_ms(rtc_clock
, strongarm_rtc_alarm_tick
, s
);
382 s
->rtc_hz
= qemu_new_timer_ms(rtc_clock
, strongarm_rtc_hz_tick
, s
);
384 sysbus_init_irq(dev
, &s
->rtc_irq
);
385 sysbus_init_irq(dev
, &s
->rtc_hz_irq
);
387 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_rtc_ops
, s
,
389 sysbus_init_mmio(dev
, &s
->iomem
);
394 static void strongarm_rtc_pre_save(void *opaque
)
396 StrongARMRTCState
*s
= opaque
;
398 strongarm_rtc_hzupdate(s
);
401 static int strongarm_rtc_post_load(void *opaque
, int version_id
)
403 StrongARMRTCState
*s
= opaque
;
405 strongarm_rtc_timer_update(s
);
406 strongarm_rtc_int_update(s
);
411 static const VMStateDescription vmstate_strongarm_rtc_regs
= {
412 .name
= "strongarm-rtc",
414 .minimum_version_id
= 0,
415 .minimum_version_id_old
= 0,
416 .pre_save
= strongarm_rtc_pre_save
,
417 .post_load
= strongarm_rtc_post_load
,
418 .fields
= (VMStateField
[]) {
419 VMSTATE_UINT32(rttr
, StrongARMRTCState
),
420 VMSTATE_UINT32(rtsr
, StrongARMRTCState
),
421 VMSTATE_UINT32(rtar
, StrongARMRTCState
),
422 VMSTATE_UINT32(last_rcnr
, StrongARMRTCState
),
423 VMSTATE_INT64(last_hz
, StrongARMRTCState
),
424 VMSTATE_END_OF_LIST(),
428 static void strongarm_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
430 DeviceClass
*dc
= DEVICE_CLASS(klass
);
431 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
433 k
->init
= strongarm_rtc_init
;
434 dc
->desc
= "StrongARM RTC Controller";
435 dc
->vmsd
= &vmstate_strongarm_rtc_regs
;
438 static const TypeInfo strongarm_rtc_sysbus_info
= {
439 .name
= "strongarm-rtc",
440 .parent
= TYPE_SYS_BUS_DEVICE
,
441 .instance_size
= sizeof(StrongARMRTCState
),
442 .class_init
= strongarm_rtc_sysbus_class_init
,
455 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo
;
456 struct StrongARMGPIOInfo
{
459 qemu_irq handler
[28];
476 static void strongarm_gpio_irq_update(StrongARMGPIOInfo
*s
)
479 for (i
= 0; i
< 11; i
++) {
480 qemu_set_irq(s
->irqs
[i
], s
->status
& (1 << i
));
483 qemu_set_irq(s
->irqX
, (s
->status
& ~0x7ff));
486 static void strongarm_gpio_set(void *opaque
, int line
, int level
)
488 StrongARMGPIOInfo
*s
= opaque
;
494 s
->status
|= s
->rising
& mask
&
495 ~s
->ilevel
& ~s
->dir
;
498 s
->status
|= s
->falling
& mask
&
503 if (s
->status
& mask
) {
504 strongarm_gpio_irq_update(s
);
508 static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s
)
510 uint32_t level
, diff
;
513 level
= s
->olevel
& s
->dir
;
515 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
517 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
520 s
->prev_level
= level
;
523 static uint64_t strongarm_gpio_read(void *opaque
, hwaddr offset
,
526 StrongARMGPIOInfo
*s
= opaque
;
529 case GPDR
: /* GPIO Pin-Direction registers */
532 case GPSR
: /* GPIO Pin-Output Set registers */
533 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx
"\n",
535 return s
->gpsr
; /* Return last written value. */
537 case GPCR
: /* GPIO Pin-Output Clear registers */
538 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx
"\n",
540 return 31337; /* Specified as unpredictable in the docs. */
542 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
545 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
548 case GAFR
: /* GPIO Alternate Function registers */
551 case GPLR
: /* GPIO Pin-Level registers */
552 return (s
->olevel
& s
->dir
) |
553 (s
->ilevel
& ~s
->dir
);
555 case GEDR
: /* GPIO Edge Detect Status registers */
559 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
565 static void strongarm_gpio_write(void *opaque
, hwaddr offset
,
566 uint64_t value
, unsigned size
)
568 StrongARMGPIOInfo
*s
= opaque
;
571 case GPDR
: /* GPIO Pin-Direction registers */
573 strongarm_gpio_handler_update(s
);
576 case GPSR
: /* GPIO Pin-Output Set registers */
578 strongarm_gpio_handler_update(s
);
582 case GPCR
: /* GPIO Pin-Output Clear registers */
584 strongarm_gpio_handler_update(s
);
587 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
591 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
595 case GAFR
: /* GPIO Alternate Function registers */
599 case GEDR
: /* GPIO Edge Detect Status registers */
601 strongarm_gpio_irq_update(s
);
605 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
609 static const MemoryRegionOps strongarm_gpio_ops
= {
610 .read
= strongarm_gpio_read
,
611 .write
= strongarm_gpio_write
,
612 .endianness
= DEVICE_NATIVE_ENDIAN
,
615 static DeviceState
*strongarm_gpio_init(hwaddr base
,
621 dev
= qdev_create(NULL
, "strongarm-gpio");
622 qdev_init_nofail(dev
);
624 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
625 for (i
= 0; i
< 12; i
++)
626 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
627 qdev_get_gpio_in(pic
, SA_PIC_GPIO0_EDGE
+ i
));
632 static int strongarm_gpio_initfn(SysBusDevice
*dev
)
634 StrongARMGPIOInfo
*s
;
637 s
= FROM_SYSBUS(StrongARMGPIOInfo
, dev
);
639 qdev_init_gpio_in(&dev
->qdev
, strongarm_gpio_set
, 28);
640 qdev_init_gpio_out(&dev
->qdev
, s
->handler
, 28);
642 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_gpio_ops
, s
,
645 sysbus_init_mmio(dev
, &s
->iomem
);
646 for (i
= 0; i
< 11; i
++) {
647 sysbus_init_irq(dev
, &s
->irqs
[i
]);
649 sysbus_init_irq(dev
, &s
->irqX
);
654 static const VMStateDescription vmstate_strongarm_gpio_regs
= {
655 .name
= "strongarm-gpio",
657 .minimum_version_id
= 0,
658 .minimum_version_id_old
= 0,
659 .fields
= (VMStateField
[]) {
660 VMSTATE_UINT32(ilevel
, StrongARMGPIOInfo
),
661 VMSTATE_UINT32(olevel
, StrongARMGPIOInfo
),
662 VMSTATE_UINT32(dir
, StrongARMGPIOInfo
),
663 VMSTATE_UINT32(rising
, StrongARMGPIOInfo
),
664 VMSTATE_UINT32(falling
, StrongARMGPIOInfo
),
665 VMSTATE_UINT32(status
, StrongARMGPIOInfo
),
666 VMSTATE_UINT32(gafr
, StrongARMGPIOInfo
),
667 VMSTATE_END_OF_LIST(),
671 static void strongarm_gpio_class_init(ObjectClass
*klass
, void *data
)
673 DeviceClass
*dc
= DEVICE_CLASS(klass
);
674 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
676 k
->init
= strongarm_gpio_initfn
;
677 dc
->desc
= "StrongARM GPIO controller";
680 static const TypeInfo strongarm_gpio_info
= {
681 .name
= "strongarm-gpio",
682 .parent
= TYPE_SYS_BUS_DEVICE
,
683 .instance_size
= sizeof(StrongARMGPIOInfo
),
684 .class_init
= strongarm_gpio_class_init
,
687 /* Peripheral Pin Controller */
694 typedef struct StrongARMPPCInfo StrongARMPPCInfo
;
695 struct StrongARMPPCInfo
{
698 qemu_irq handler
[28];
710 static void strongarm_ppc_set(void *opaque
, int line
, int level
)
712 StrongARMPPCInfo
*s
= opaque
;
715 s
->ilevel
|= 1 << line
;
717 s
->ilevel
&= ~(1 << line
);
721 static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s
)
723 uint32_t level
, diff
;
726 level
= s
->olevel
& s
->dir
;
728 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
730 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
733 s
->prev_level
= level
;
736 static uint64_t strongarm_ppc_read(void *opaque
, hwaddr offset
,
739 StrongARMPPCInfo
*s
= opaque
;
742 case PPDR
: /* PPC Pin Direction registers */
743 return s
->dir
| ~0x3fffff;
745 case PPSR
: /* PPC Pin State registers */
746 return (s
->olevel
& s
->dir
) |
747 (s
->ilevel
& ~s
->dir
) |
751 return s
->ppar
| ~0x41000;
757 return s
->ppfr
| ~0x7f001;
760 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
766 static void strongarm_ppc_write(void *opaque
, hwaddr offset
,
767 uint64_t value
, unsigned size
)
769 StrongARMPPCInfo
*s
= opaque
;
772 case PPDR
: /* PPC Pin Direction registers */
773 s
->dir
= value
& 0x3fffff;
774 strongarm_ppc_handler_update(s
);
777 case PPSR
: /* PPC Pin State registers */
778 s
->olevel
= value
& s
->dir
& 0x3fffff;
779 strongarm_ppc_handler_update(s
);
783 s
->ppar
= value
& 0x41000;
787 s
->psdr
= value
& 0x3fffff;
791 s
->ppfr
= value
& 0x7f001;
795 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
799 static const MemoryRegionOps strongarm_ppc_ops
= {
800 .read
= strongarm_ppc_read
,
801 .write
= strongarm_ppc_write
,
802 .endianness
= DEVICE_NATIVE_ENDIAN
,
805 static int strongarm_ppc_init(SysBusDevice
*dev
)
809 s
= FROM_SYSBUS(StrongARMPPCInfo
, dev
);
811 qdev_init_gpio_in(&dev
->qdev
, strongarm_ppc_set
, 22);
812 qdev_init_gpio_out(&dev
->qdev
, s
->handler
, 22);
814 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_ppc_ops
, s
,
817 sysbus_init_mmio(dev
, &s
->iomem
);
822 static const VMStateDescription vmstate_strongarm_ppc_regs
= {
823 .name
= "strongarm-ppc",
825 .minimum_version_id
= 0,
826 .minimum_version_id_old
= 0,
827 .fields
= (VMStateField
[]) {
828 VMSTATE_UINT32(ilevel
, StrongARMPPCInfo
),
829 VMSTATE_UINT32(olevel
, StrongARMPPCInfo
),
830 VMSTATE_UINT32(dir
, StrongARMPPCInfo
),
831 VMSTATE_UINT32(ppar
, StrongARMPPCInfo
),
832 VMSTATE_UINT32(psdr
, StrongARMPPCInfo
),
833 VMSTATE_UINT32(ppfr
, StrongARMPPCInfo
),
834 VMSTATE_END_OF_LIST(),
838 static void strongarm_ppc_class_init(ObjectClass
*klass
, void *data
)
840 DeviceClass
*dc
= DEVICE_CLASS(klass
);
841 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
843 k
->init
= strongarm_ppc_init
;
844 dc
->desc
= "StrongARM PPC controller";
847 static const TypeInfo strongarm_ppc_info
= {
848 .name
= "strongarm-ppc",
849 .parent
= TYPE_SYS_BUS_DEVICE
,
850 .instance_size
= sizeof(StrongARMPPCInfo
),
851 .class_init
= strongarm_ppc_class_init
,
863 #define UTCR0_PE (1 << 0) /* Parity enable */
864 #define UTCR0_OES (1 << 1) /* Even parity */
865 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
866 #define UTCR0_DSS (1 << 3) /* 8-bit data */
868 #define UTCR3_RXE (1 << 0) /* Rx enable */
869 #define UTCR3_TXE (1 << 1) /* Tx enable */
870 #define UTCR3_BRK (1 << 2) /* Force Break */
871 #define UTCR3_RIE (1 << 3) /* Rx int enable */
872 #define UTCR3_TIE (1 << 4) /* Tx int enable */
873 #define UTCR3_LBM (1 << 5) /* Loopback */
875 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
876 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
877 #define UTSR0_RID (1 << 2) /* Receiver Idle */
878 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
879 #define UTSR0_REB (1 << 4) /* Receiver end break */
880 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
882 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
883 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
884 #define UTSR1_PRE (1 << 3) /* Parity error */
885 #define UTSR1_FRE (1 << 4) /* Frame error */
886 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
888 #define RX_FIFO_PRE (1 << 8)
889 #define RX_FIFO_FRE (1 << 9)
890 #define RX_FIFO_ROR (1 << 10)
895 CharDriverState
*chr
;
907 uint16_t rx_fifo
[12]; /* value + error flags in high bits */
911 uint64_t char_transmit_time
; /* time to transmit a char in ticks*/
913 QEMUTimer
*rx_timeout_timer
;
915 } StrongARMUARTState
;
917 static void strongarm_uart_update_status(StrongARMUARTState
*s
)
921 if (s
->tx_len
!= 8) {
925 if (s
->rx_len
!= 0) {
926 uint16_t ent
= s
->rx_fifo
[s
->rx_start
];
929 if (ent
& RX_FIFO_PRE
) {
930 s
->utsr1
|= UTSR1_PRE
;
932 if (ent
& RX_FIFO_FRE
) {
933 s
->utsr1
|= UTSR1_FRE
;
935 if (ent
& RX_FIFO_ROR
) {
936 s
->utsr1
|= UTSR1_ROR
;
943 static void strongarm_uart_update_int_status(StrongARMUARTState
*s
)
945 uint16_t utsr0
= s
->utsr0
&
946 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
);
949 if ((s
->utcr3
& UTCR3_TXE
) &&
950 (s
->utcr3
& UTCR3_TIE
) &&
955 if ((s
->utcr3
& UTCR3_RXE
) &&
956 (s
->utcr3
& UTCR3_RIE
) &&
961 for (i
= 0; i
< s
->rx_len
&& i
< 4; i
++)
962 if (s
->rx_fifo
[(s
->rx_start
+ i
) % 12] & ~0xff) {
968 qemu_set_irq(s
->irq
, utsr0
);
971 static void strongarm_uart_update_parameters(StrongARMUARTState
*s
)
973 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
974 QEMUSerialSetParams ssp
;
978 if (s
->utcr0
& UTCR0_PE
) {
981 if (s
->utcr0
& UTCR0_OES
) {
989 if (s
->utcr0
& UTCR0_SBS
) {
995 data_bits
= (s
->utcr0
& UTCR0_DSS
) ? 8 : 7;
996 frame_size
+= data_bits
+ stop_bits
;
997 speed
= 3686400 / 16 / (s
->brd
+ 1);
1000 ssp
.data_bits
= data_bits
;
1001 ssp
.stop_bits
= stop_bits
;
1002 s
->char_transmit_time
= (get_ticks_per_sec() / speed
) * frame_size
;
1004 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
1007 DPRINTF(stderr
, "%s speed=%d parity=%c data=%d stop=%d\n", s
->chr
->label
,
1008 speed
, parity
, data_bits
, stop_bits
);
1011 static void strongarm_uart_rx_to(void *opaque
)
1013 StrongARMUARTState
*s
= opaque
;
1016 s
->utsr0
|= UTSR0_RID
;
1017 strongarm_uart_update_int_status(s
);
1021 static void strongarm_uart_rx_push(StrongARMUARTState
*s
, uint16_t c
)
1023 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1028 if (s
->wait_break_end
) {
1029 s
->utsr0
|= UTSR0_REB
;
1030 s
->wait_break_end
= false;
1033 if (s
->rx_len
< 12) {
1034 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
) % 12] = c
;
1037 s
->rx_fifo
[(s
->rx_start
+ 11) % 12] |= RX_FIFO_ROR
;
1040 static int strongarm_uart_can_receive(void *opaque
)
1042 StrongARMUARTState
*s
= opaque
;
1044 if (s
->rx_len
== 12) {
1047 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1048 if (s
->rx_len
< 8) {
1049 return 8 - s
->rx_len
;
1054 static void strongarm_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
1056 StrongARMUARTState
*s
= opaque
;
1059 for (i
= 0; i
< size
; i
++) {
1060 strongarm_uart_rx_push(s
, buf
[i
]);
1063 /* call the timeout receive callback in 3 char transmit time */
1064 qemu_mod_timer(s
->rx_timeout_timer
,
1065 qemu_get_clock_ns(vm_clock
) + s
->char_transmit_time
* 3);
1067 strongarm_uart_update_status(s
);
1068 strongarm_uart_update_int_status(s
);
1071 static void strongarm_uart_event(void *opaque
, int event
)
1073 StrongARMUARTState
*s
= opaque
;
1074 if (event
== CHR_EVENT_BREAK
) {
1075 s
->utsr0
|= UTSR0_RBB
;
1076 strongarm_uart_rx_push(s
, RX_FIFO_FRE
);
1077 s
->wait_break_end
= true;
1078 strongarm_uart_update_status(s
);
1079 strongarm_uart_update_int_status(s
);
1083 static void strongarm_uart_tx(void *opaque
)
1085 StrongARMUARTState
*s
= opaque
;
1086 uint64_t new_xmit_ts
= qemu_get_clock_ns(vm_clock
);
1088 if (s
->utcr3
& UTCR3_LBM
) /* loopback */ {
1089 strongarm_uart_receive(s
, &s
->tx_fifo
[s
->tx_start
], 1);
1090 } else if (s
->chr
) {
1091 qemu_chr_fe_write(s
->chr
, &s
->tx_fifo
[s
->tx_start
], 1);
1094 s
->tx_start
= (s
->tx_start
+ 1) % 8;
1097 qemu_mod_timer(s
->tx_timer
, new_xmit_ts
+ s
->char_transmit_time
);
1099 strongarm_uart_update_status(s
);
1100 strongarm_uart_update_int_status(s
);
1103 static uint64_t strongarm_uart_read(void *opaque
, hwaddr addr
,
1106 StrongARMUARTState
*s
= opaque
;
1117 return s
->brd
& 0xff;
1123 if (s
->rx_len
!= 0) {
1124 ret
= s
->rx_fifo
[s
->rx_start
];
1125 s
->rx_start
= (s
->rx_start
+ 1) % 12;
1127 strongarm_uart_update_status(s
);
1128 strongarm_uart_update_int_status(s
);
1140 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1145 static void strongarm_uart_write(void *opaque
, hwaddr addr
,
1146 uint64_t value
, unsigned size
)
1148 StrongARMUARTState
*s
= opaque
;
1152 s
->utcr0
= value
& 0x7f;
1153 strongarm_uart_update_parameters(s
);
1157 s
->brd
= (s
->brd
& 0xff) | ((value
& 0xf) << 8);
1158 strongarm_uart_update_parameters(s
);
1162 s
->brd
= (s
->brd
& 0xf00) | (value
& 0xff);
1163 strongarm_uart_update_parameters(s
);
1167 s
->utcr3
= value
& 0x3f;
1168 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1171 if ((s
->utcr3
& UTCR3_TXE
) == 0) {
1174 strongarm_uart_update_status(s
);
1175 strongarm_uart_update_int_status(s
);
1179 if ((s
->utcr3
& UTCR3_TXE
) && s
->tx_len
!= 8) {
1180 s
->tx_fifo
[(s
->tx_start
+ s
->tx_len
) % 8] = value
;
1182 strongarm_uart_update_status(s
);
1183 strongarm_uart_update_int_status(s
);
1184 if (s
->tx_len
== 1) {
1185 strongarm_uart_tx(s
);
1191 s
->utsr0
= s
->utsr0
& ~(value
&
1192 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
));
1193 strongarm_uart_update_int_status(s
);
1197 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1201 static const MemoryRegionOps strongarm_uart_ops
= {
1202 .read
= strongarm_uart_read
,
1203 .write
= strongarm_uart_write
,
1204 .endianness
= DEVICE_NATIVE_ENDIAN
,
1207 static int strongarm_uart_init(SysBusDevice
*dev
)
1209 StrongARMUARTState
*s
= FROM_SYSBUS(StrongARMUARTState
, dev
);
1211 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_uart_ops
, s
,
1213 sysbus_init_mmio(dev
, &s
->iomem
);
1214 sysbus_init_irq(dev
, &s
->irq
);
1216 s
->rx_timeout_timer
= qemu_new_timer_ns(vm_clock
, strongarm_uart_rx_to
, s
);
1217 s
->tx_timer
= qemu_new_timer_ns(vm_clock
, strongarm_uart_tx
, s
);
1220 qemu_chr_add_handlers(s
->chr
,
1221 strongarm_uart_can_receive
,
1222 strongarm_uart_receive
,
1223 strongarm_uart_event
,
1230 static void strongarm_uart_reset(DeviceState
*dev
)
1232 StrongARMUARTState
*s
= DO_UPCAST(StrongARMUARTState
, busdev
.qdev
, dev
);
1234 s
->utcr0
= UTCR0_DSS
; /* 8 data, no parity */
1235 s
->brd
= 23; /* 9600 */
1236 /* enable send & recv - this actually violates spec */
1237 s
->utcr3
= UTCR3_TXE
| UTCR3_RXE
;
1239 s
->rx_len
= s
->tx_len
= 0;
1241 strongarm_uart_update_parameters(s
);
1242 strongarm_uart_update_status(s
);
1243 strongarm_uart_update_int_status(s
);
1246 static int strongarm_uart_post_load(void *opaque
, int version_id
)
1248 StrongARMUARTState
*s
= opaque
;
1250 strongarm_uart_update_parameters(s
);
1251 strongarm_uart_update_status(s
);
1252 strongarm_uart_update_int_status(s
);
1254 /* tx and restart timer */
1256 strongarm_uart_tx(s
);
1259 /* restart rx timeout timer */
1261 qemu_mod_timer(s
->rx_timeout_timer
,
1262 qemu_get_clock_ns(vm_clock
) + s
->char_transmit_time
* 3);
1268 static const VMStateDescription vmstate_strongarm_uart_regs
= {
1269 .name
= "strongarm-uart",
1271 .minimum_version_id
= 0,
1272 .minimum_version_id_old
= 0,
1273 .post_load
= strongarm_uart_post_load
,
1274 .fields
= (VMStateField
[]) {
1275 VMSTATE_UINT8(utcr0
, StrongARMUARTState
),
1276 VMSTATE_UINT16(brd
, StrongARMUARTState
),
1277 VMSTATE_UINT8(utcr3
, StrongARMUARTState
),
1278 VMSTATE_UINT8(utsr0
, StrongARMUARTState
),
1279 VMSTATE_UINT8_ARRAY(tx_fifo
, StrongARMUARTState
, 8),
1280 VMSTATE_UINT8(tx_start
, StrongARMUARTState
),
1281 VMSTATE_UINT8(tx_len
, StrongARMUARTState
),
1282 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMUARTState
, 12),
1283 VMSTATE_UINT8(rx_start
, StrongARMUARTState
),
1284 VMSTATE_UINT8(rx_len
, StrongARMUARTState
),
1285 VMSTATE_BOOL(wait_break_end
, StrongARMUARTState
),
1286 VMSTATE_END_OF_LIST(),
1290 static Property strongarm_uart_properties
[] = {
1291 DEFINE_PROP_CHR("chardev", StrongARMUARTState
, chr
),
1292 DEFINE_PROP_END_OF_LIST(),
1295 static void strongarm_uart_class_init(ObjectClass
*klass
, void *data
)
1297 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1298 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1300 k
->init
= strongarm_uart_init
;
1301 dc
->desc
= "StrongARM UART controller";
1302 dc
->reset
= strongarm_uart_reset
;
1303 dc
->vmsd
= &vmstate_strongarm_uart_regs
;
1304 dc
->props
= strongarm_uart_properties
;
1307 static const TypeInfo strongarm_uart_info
= {
1308 .name
= "strongarm-uart",
1309 .parent
= TYPE_SYS_BUS_DEVICE
,
1310 .instance_size
= sizeof(StrongARMUARTState
),
1311 .class_init
= strongarm_uart_class_init
,
1314 /* Synchronous Serial Ports */
1316 SysBusDevice busdev
;
1324 uint16_t rx_fifo
[8];
1327 } StrongARMSSPState
;
1329 #define SSCR0 0x60 /* SSP Control register 0 */
1330 #define SSCR1 0x64 /* SSP Control register 1 */
1331 #define SSDR 0x6c /* SSP Data register */
1332 #define SSSR 0x74 /* SSP Status register */
1334 /* Bitfields for above registers */
1335 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1336 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1337 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1338 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1339 #define SSCR0_SSE (1 << 7)
1340 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1341 #define SSCR1_RIE (1 << 0)
1342 #define SSCR1_TIE (1 << 1)
1343 #define SSCR1_LBM (1 << 2)
1344 #define SSSR_TNF (1 << 2)
1345 #define SSSR_RNE (1 << 3)
1346 #define SSSR_TFS (1 << 5)
1347 #define SSSR_RFS (1 << 6)
1348 #define SSSR_ROR (1 << 7)
1349 #define SSSR_RW 0x0080
1351 static void strongarm_ssp_int_update(StrongARMSSPState
*s
)
1355 level
|= (s
->sssr
& SSSR_ROR
);
1356 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
1357 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
1358 qemu_set_irq(s
->irq
, level
);
1361 static void strongarm_ssp_fifo_update(StrongARMSSPState
*s
)
1363 s
->sssr
&= ~SSSR_TFS
;
1364 s
->sssr
&= ~SSSR_TNF
;
1365 if (s
->sscr
[0] & SSCR0_SSE
) {
1366 if (s
->rx_level
>= 4) {
1367 s
->sssr
|= SSSR_RFS
;
1369 s
->sssr
&= ~SSSR_RFS
;
1372 s
->sssr
|= SSSR_RNE
;
1374 s
->sssr
&= ~SSSR_RNE
;
1376 /* TX FIFO is never filled, so it is always in underrun
1377 condition if SSP is enabled */
1378 s
->sssr
|= SSSR_TFS
;
1379 s
->sssr
|= SSSR_TNF
;
1382 strongarm_ssp_int_update(s
);
1385 static uint64_t strongarm_ssp_read(void *opaque
, hwaddr addr
,
1388 StrongARMSSPState
*s
= opaque
;
1399 if (~s
->sscr
[0] & SSCR0_SSE
) {
1402 if (s
->rx_level
< 1) {
1403 printf("%s: SSP Rx Underrun\n", __func__
);
1407 retval
= s
->rx_fifo
[s
->rx_start
++];
1409 strongarm_ssp_fifo_update(s
);
1412 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1418 static void strongarm_ssp_write(void *opaque
, hwaddr addr
,
1419 uint64_t value
, unsigned size
)
1421 StrongARMSSPState
*s
= opaque
;
1425 s
->sscr
[0] = value
& 0xffbf;
1426 if ((s
->sscr
[0] & SSCR0_SSE
) && SSCR0_DSS(value
) < 4) {
1427 printf("%s: Wrong data size: %i bits\n", __func__
,
1428 (int)SSCR0_DSS(value
));
1430 if (!(value
& SSCR0_SSE
)) {
1434 strongarm_ssp_fifo_update(s
);
1438 s
->sscr
[1] = value
& 0x2f;
1439 if (value
& SSCR1_LBM
) {
1440 printf("%s: Attempt to use SSP LBM mode\n", __func__
);
1442 strongarm_ssp_fifo_update(s
);
1446 s
->sssr
&= ~(value
& SSSR_RW
);
1447 strongarm_ssp_int_update(s
);
1451 if (SSCR0_UWIRE(s
->sscr
[0])) {
1454 /* Note how 32bits overflow does no harm here */
1455 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
1457 /* Data goes from here to the Tx FIFO and is shifted out from
1458 * there directly to the slave, no need to buffer it.
1460 if (s
->sscr
[0] & SSCR0_SSE
) {
1462 if (s
->sscr
[1] & SSCR1_LBM
) {
1465 readval
= ssi_transfer(s
->bus
, value
);
1468 if (s
->rx_level
< 0x08) {
1469 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0x7] = readval
;
1471 s
->sssr
|= SSSR_ROR
;
1474 strongarm_ssp_fifo_update(s
);
1478 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1483 static const MemoryRegionOps strongarm_ssp_ops
= {
1484 .read
= strongarm_ssp_read
,
1485 .write
= strongarm_ssp_write
,
1486 .endianness
= DEVICE_NATIVE_ENDIAN
,
1489 static int strongarm_ssp_post_load(void *opaque
, int version_id
)
1491 StrongARMSSPState
*s
= opaque
;
1493 strongarm_ssp_fifo_update(s
);
1498 static int strongarm_ssp_init(SysBusDevice
*dev
)
1500 StrongARMSSPState
*s
= FROM_SYSBUS(StrongARMSSPState
, dev
);
1502 sysbus_init_irq(dev
, &s
->irq
);
1504 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_ssp_ops
, s
,
1506 sysbus_init_mmio(dev
, &s
->iomem
);
1508 s
->bus
= ssi_create_bus(&dev
->qdev
, "ssi");
1512 static void strongarm_ssp_reset(DeviceState
*dev
)
1514 StrongARMSSPState
*s
= DO_UPCAST(StrongARMSSPState
, busdev
.qdev
, dev
);
1515 s
->sssr
= 0x03; /* 3 bit data, SPI, disabled */
1520 static const VMStateDescription vmstate_strongarm_ssp_regs
= {
1521 .name
= "strongarm-ssp",
1523 .minimum_version_id
= 0,
1524 .minimum_version_id_old
= 0,
1525 .post_load
= strongarm_ssp_post_load
,
1526 .fields
= (VMStateField
[]) {
1527 VMSTATE_UINT16_ARRAY(sscr
, StrongARMSSPState
, 2),
1528 VMSTATE_UINT16(sssr
, StrongARMSSPState
),
1529 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMSSPState
, 8),
1530 VMSTATE_UINT8(rx_start
, StrongARMSSPState
),
1531 VMSTATE_UINT8(rx_level
, StrongARMSSPState
),
1532 VMSTATE_END_OF_LIST(),
1536 static void strongarm_ssp_class_init(ObjectClass
*klass
, void *data
)
1538 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1539 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1541 k
->init
= strongarm_ssp_init
;
1542 dc
->desc
= "StrongARM SSP controller";
1543 dc
->reset
= strongarm_ssp_reset
;
1544 dc
->vmsd
= &vmstate_strongarm_ssp_regs
;
1547 static const TypeInfo strongarm_ssp_info
= {
1548 .name
= "strongarm-ssp",
1549 .parent
= TYPE_SYS_BUS_DEVICE
,
1550 .instance_size
= sizeof(StrongARMSSPState
),
1551 .class_init
= strongarm_ssp_class_init
,
1554 /* Main CPU functions */
1555 StrongARMState
*sa1110_init(MemoryRegion
*sysmem
,
1556 unsigned int sdram_size
, const char *rev
)
1562 s
= g_malloc0(sizeof(StrongARMState
));
1568 if (strncmp(rev
, "sa1110", 6)) {
1569 error_report("Machine requires a SA1110 processor.");
1573 s
->cpu
= cpu_arm_init(rev
);
1576 error_report("Unable to find CPU definition");
1580 memory_region_init_ram(&s
->sdram
, NULL
, "strongarm.sdram", sdram_size
);
1581 vmstate_register_ram_global(&s
->sdram
);
1582 memory_region_add_subregion(sysmem
, SA_SDCS0
, &s
->sdram
);
1584 pic
= arm_pic_init_cpu(s
->cpu
);
1585 s
->pic
= sysbus_create_varargs("strongarm_pic", 0x90050000,
1586 pic
[ARM_PIC_CPU_IRQ
], pic
[ARM_PIC_CPU_FIQ
], NULL
);
1588 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1589 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC0
),
1590 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC1
),
1591 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC2
),
1592 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC3
),
1595 sysbus_create_simple("strongarm-rtc", 0x90010000,
1596 qdev_get_gpio_in(s
->pic
, SA_PIC_RTC_ALARM
));
1598 s
->gpio
= strongarm_gpio_init(0x90040000, s
->pic
);
1600 s
->ppc
= sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL
);
1602 for (i
= 0; sa_serial
[i
].io_base
; i
++) {
1603 DeviceState
*dev
= qdev_create(NULL
, "strongarm-uart");
1604 qdev_prop_set_chr(dev
, "chardev", serial_hds
[i
]);
1605 qdev_init_nofail(dev
);
1606 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
1607 sa_serial
[i
].io_base
);
1608 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
1609 qdev_get_gpio_in(s
->pic
, sa_serial
[i
].irq
));
1612 s
->ssp
= sysbus_create_varargs("strongarm-ssp", 0x80070000,
1613 qdev_get_gpio_in(s
->pic
, SA_PIC_SSP
), NULL
);
1614 s
->ssp_bus
= (SSIBus
*)qdev_get_child_bus(s
->ssp
, "ssi");
1619 static void strongarm_register_types(void)
1621 type_register_static(&strongarm_pic_info
);
1622 type_register_static(&strongarm_rtc_sysbus_info
);
1623 type_register_static(&strongarm_gpio_info
);
1624 type_register_static(&strongarm_ppc_info
);
1625 type_register_static(&strongarm_uart_info
);
1626 type_register_static(&strongarm_ssp_info
);
1629 type_init(strongarm_register_types
)