hw/ide/piix.c

   1 /*
   2  * QEMU IDE Emulation: PCI PIIX3/4 support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  *
  25  * References:
  26  *  [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR,
  27  *      290550-002, Intel Corporation, April 1997.
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "hw/pci/pci.h"
  32 #include "migration/vmstate.h"
  33 #include "qapi/error.h"
  34 #include "qemu/module.h"
  35 #include "sysemu/block-backend.h"
  36 #include "sysemu/blockdev.h"
  37 #include "sysemu/dma.h"
  38
  39 #include "hw/ide/piix.h"
  40 #include "hw/ide/pci.h"
  41 #include "trace.h"
  42
  43 static uint64_t bmdma_read(void *opaque, hwaddr addr, unsigned size)
  44 {
  45     BMDMAState *bm = opaque;
  46     uint32_t val;
  47
  48     if (size != 1) {
  49         return ((uint64_t)1 << (size * 8)) - 1;
  50     }
  51
  52     switch(addr & 3) {
  53     case 0:
  54         val = bm->cmd;
  55         break;
  56     case 2:
  57         val = bm->status;
  58         break;
  59     default:
  60         val = 0xff;
  61         break;
  62     }
  63
  64     trace_bmdma_read(addr, val);
  65     return val;
  66 }
  67
  68 static void bmdma_write(void *opaque, hwaddr addr,
  69                         uint64_t val, unsigned size)
  70 {
  71     BMDMAState *bm = opaque;
  72
  73     if (size != 1) {
  74         return;
  75     }
  76
  77     trace_bmdma_write(addr, val);
  78
  79     switch(addr & 3) {
  80     case 0:
  81         bmdma_cmd_writeb(bm, val);
  82         break;
  83     case 2:
  84         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
  85         break;
  86     }
  87 }
  88
  89 static const MemoryRegionOps piix_bmdma_ops = {
  90     .read = bmdma_read,
  91     .write = bmdma_write,
  92 };
  93
  94 static void bmdma_setup_bar(PCIIDEState *d)
  95 {
  96     int i;
  97
  98     memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16);
  99     for(i = 0;i < 2; i++) {
 100         BMDMAState *bm = &d->bmdma[i];
 101
 102         memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm,
 103                               "piix-bmdma", 4);
 104         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 105         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 106                               &bmdma_addr_ioport_ops, bm, "bmdma", 4);
 107         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 108     }
 109 }
 110
 111 static void piix_ide_reset(DeviceState *dev)
 112 {
 113     PCIIDEState *d = PCI_IDE(dev);
 114     PCIDevice *pd = PCI_DEVICE(d);
 115     uint8_t *pci_conf = pd->config;
 116     int i;
 117
 118     for (i = 0; i < 2; i++) {
 119         ide_bus_reset(&d->bus[i]);
 120     }
 121
 122     /* PCI command register default value (0000h) per [1, p.48].  */
 123     pci_set_word(pci_conf + PCI_COMMAND, 0x0000);
 124     pci_set_word(pci_conf + PCI_STATUS,
 125                  PCI_STATUS_DEVSEL_MEDIUM | PCI_STATUS_FAST_BACK);
 126     pci_set_byte(pci_conf + 0x20, 0x01);  /* BMIBA: 20-23h */
 127 }
 128
 129 static int pci_piix_init_ports(PCIIDEState *d)
 130 {
 131     static const struct {
 132         int iobase;
 133         int iobase2;
 134         int isairq;
 135     } port_info[] = {
 136         {0x1f0, 0x3f6, 14},
 137         {0x170, 0x376, 15},
 138     };
 139     int i, ret;
 140
 141     for (i = 0; i < 2; i++) {
 142         ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2);
 143         ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase,
 144                               port_info[i].iobase2);
 145         if (ret) {
 146             return ret;
 147         }
 148         ide_init2(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq));
 149
 150         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 151         d->bmdma[i].bus = &d->bus[i];
 152         ide_register_restart_cb(&d->bus[i]);
 153     }
 154
 155     return 0;
 156 }
 157
 158 static void pci_piix_ide_realize(PCIDevice *dev, Error **errp)
 159 {
 160     PCIIDEState *d = PCI_IDE(dev);
 161     uint8_t *pci_conf = dev->config;
 162     int rc;
 163
 164     pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
 165
 166     bmdma_setup_bar(d);
 167     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 168
 169     vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d);
 170
 171     rc = pci_piix_init_ports(d);
 172     if (rc) {
 173         error_setg_errno(errp, -rc, "Failed to realize %s",
 174                          object_get_typename(OBJECT(dev)));
 175     }
 176 }
 177
 178 static void pci_piix_ide_exitfn(PCIDevice *dev)
 179 {
 180     PCIIDEState *d = PCI_IDE(dev);
 181     unsigned i;
 182
 183     for (i = 0; i < 2; ++i) {
 184         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 185         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 186     }
 187 }
 188
 189 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
 190 static void piix3_ide_class_init(ObjectClass *klass, void *data)
 191 {
 192     DeviceClass *dc = DEVICE_CLASS(klass);
 193     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 194
 195     dc->reset = piix_ide_reset;
 196     k->realize = pci_piix_ide_realize;
 197     k->exit = pci_piix_ide_exitfn;
 198     k->vendor_id = PCI_VENDOR_ID_INTEL;
 199     k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1;
 200     k->class_id = PCI_CLASS_STORAGE_IDE;
 201     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 202     dc->hotpluggable = false;
 203 }
 204
 205 static const TypeInfo piix3_ide_info = {
 206     .name          = TYPE_PIIX3_IDE,
 207     .parent        = TYPE_PCI_IDE,
 208     .class_init    = piix3_ide_class_init,
 209 };
 210
 211 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
 212 static void piix4_ide_class_init(ObjectClass *klass, void *data)
 213 {
 214     DeviceClass *dc = DEVICE_CLASS(klass);
 215     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 216
 217     dc->reset = piix_ide_reset;
 218     k->realize = pci_piix_ide_realize;
 219     k->exit = pci_piix_ide_exitfn;
 220     k->vendor_id = PCI_VENDOR_ID_INTEL;
 221     k->device_id = PCI_DEVICE_ID_INTEL_82371AB;
 222     k->class_id = PCI_CLASS_STORAGE_IDE;
 223     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 224     dc->hotpluggable = false;
 225 }
 226
 227 static const TypeInfo piix4_ide_info = {
 228     .name          = TYPE_PIIX4_IDE,
 229     .parent        = TYPE_PCI_IDE,
 230     .class_init    = piix4_ide_class_init,
 231 };
 232
 233 static void piix_ide_register_types(void)
 234 {
 235     type_register_static(&piix3_ide_info);
 236     type_register_static(&piix4_ide_info);
 237 }
 238
 239 type_init(piix_ide_register_types)