target/rx/cpu.c

   1 /*
   2  * QEMU RX CPU
   3  *
   4  * Copyright (c) 2019 Yoshinori Sato
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qemu/qemu-print.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "migration/vmstate.h"
  24 #include "exec/exec-all.h"
  25 #include "hw/loader.h"
  26 #include "fpu/softfloat.h"
  27
  28 static void rx_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     RXCPU *cpu = RX_CPU(cs);
  31
  32     cpu->env.pc = value;
  33 }
  34
  35 static vaddr rx_cpu_get_pc(CPUState *cs)
  36 {
  37     RXCPU *cpu = RX_CPU(cs);
  38
  39     return cpu->env.pc;
  40 }
  41
  42 static void rx_cpu_synchronize_from_tb(CPUState *cs,
  43                                        const TranslationBlock *tb)
  44 {
  45     RXCPU *cpu = RX_CPU(cs);
  46
  47     cpu->env.pc = tb_pc(tb);
  48 }
  49
  50 static bool rx_cpu_has_work(CPUState *cs)
  51 {
  52     return cs->interrupt_request &
  53         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
  54 }
  55
  56 static void rx_cpu_reset(DeviceState *dev)
  57 {
  58     RXCPU *cpu = RX_CPU(dev);
  59     RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu);
  60     CPURXState *env = &cpu->env;
  61     uint32_t *resetvec;
  62
  63     rcc->parent_reset(dev);
  64
  65     memset(env, 0, offsetof(CPURXState, end_reset_fields));
  66
  67     resetvec = rom_ptr(0xfffffffc, 4);
  68     if (resetvec) {
  69         /* In the case of kernel, it is ignored because it is not set. */
  70         env->pc = ldl_p(resetvec);
  71     }
  72     rx_cpu_unpack_psw(env, 0, 1);
  73     env->regs[0] = env->isp = env->usp = 0;
  74     env->fpsw = 0;
  75     set_flush_to_zero(1, &env->fp_status);
  76     set_flush_inputs_to_zero(1, &env->fp_status);
  77 }
  78
  79 static void rx_cpu_list_entry(gpointer data, gpointer user_data)
  80 {
  81     ObjectClass *oc = data;
  82
  83     qemu_printf("  %s\n", object_class_get_name(oc));
  84 }
  85
  86 void rx_cpu_list(void)
  87 {
  88     GSList *list;
  89     list = object_class_get_list_sorted(TYPE_RX_CPU, false);
  90     qemu_printf("Available CPUs:\n");
  91     g_slist_foreach(list, rx_cpu_list_entry, NULL);
  92     g_slist_free(list);
  93 }
  94
  95 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
  96 {
  97     ObjectClass *oc;
  98     char *typename;
  99
 100     oc = object_class_by_name(cpu_model);
 101     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL &&
 102         !object_class_is_abstract(oc)) {
 103         return oc;
 104     }
 105     typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
 106     oc = object_class_by_name(typename);
 107     g_free(typename);
 108     if (oc != NULL && object_class_is_abstract(oc)) {
 109         oc = NULL;
 110     }
 111
 112     return oc;
 113 }
 114
 115 static void rx_cpu_realize(DeviceState *dev, Error **errp)
 116 {
 117     CPUState *cs = CPU(dev);
 118     RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
 119     Error *local_err = NULL;
 120
 121     cpu_exec_realizefn(cs, &local_err);
 122     if (local_err != NULL) {
 123         error_propagate(errp, local_err);
 124         return;
 125     }
 126
 127     qemu_init_vcpu(cs);
 128     cpu_reset(cs);
 129
 130     rcc->parent_realize(dev, errp);
 131 }
 132
 133 static void rx_cpu_set_irq(void *opaque, int no, int request)
 134 {
 135     RXCPU *cpu = opaque;
 136     CPUState *cs = CPU(cpu);
 137     int irq = request & 0xff;
 138
 139     static const int mask[] = {
 140         [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
 141         [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
 142     };
 143     if (irq) {
 144         cpu->env.req_irq = irq;
 145         cpu->env.req_ipl = (request >> 8) & 0x0f;
 146         cpu_interrupt(cs, mask[no]);
 147     } else {
 148         cpu_reset_interrupt(cs, mask[no]);
 149     }
 150 }
 151
 152 static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 153 {
 154     info->mach = bfd_mach_rx;
 155     info->print_insn = print_insn_rx;
 156 }
 157
 158 static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
 159                             MMUAccessType access_type, int mmu_idx,
 160                             bool probe, uintptr_t retaddr)
 161 {
 162     uint32_t address, physical, prot;
 163
 164     /* Linear mapping */
 165     address = physical = addr & TARGET_PAGE_MASK;
 166     prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 167     tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 168     return true;
 169 }
 170
 171 static void rx_cpu_init(Object *obj)
 172 {
 173     CPUState *cs = CPU(obj);
 174     RXCPU *cpu = RX_CPU(obj);
 175     CPURXState *env = &cpu->env;
 176
 177     cpu_set_cpustate_pointers(cpu);
 178     cs->env_ptr = env;
 179     qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
 180 }
 181
 182 #ifndef CONFIG_USER_ONLY
 183 #include "hw/core/sysemu-cpu-ops.h"
 184
 185 static const struct SysemuCPUOps rx_sysemu_ops = {
 186     .get_phys_page_debug = rx_cpu_get_phys_page_debug,
 187 };
 188 #endif
 189
 190 #include "hw/core/tcg-cpu-ops.h"
 191
 192 static const struct TCGCPUOps rx_tcg_ops = {
 193     .initialize = rx_translate_init,
 194     .synchronize_from_tb = rx_cpu_synchronize_from_tb,
 195     .tlb_fill = rx_cpu_tlb_fill,
 196
 197 #ifndef CONFIG_USER_ONLY
 198     .cpu_exec_interrupt = rx_cpu_exec_interrupt,
 199     .do_interrupt = rx_cpu_do_interrupt,
 200 #endif /* !CONFIG_USER_ONLY */
 201 };
 202
 203 static void rx_cpu_class_init(ObjectClass *klass, void *data)
 204 {
 205     DeviceClass *dc = DEVICE_CLASS(klass);
 206     CPUClass *cc = CPU_CLASS(klass);
 207     RXCPUClass *rcc = RX_CPU_CLASS(klass);
 208
 209     device_class_set_parent_realize(dc, rx_cpu_realize,
 210                                     &rcc->parent_realize);
 211     device_class_set_parent_reset(dc, rx_cpu_reset,
 212                                   &rcc->parent_reset);
 213
 214     cc->class_by_name = rx_cpu_class_by_name;
 215     cc->has_work = rx_cpu_has_work;
 216     cc->dump_state = rx_cpu_dump_state;
 217     cc->set_pc = rx_cpu_set_pc;
 218     cc->get_pc = rx_cpu_get_pc;
 219
 220 #ifndef CONFIG_USER_ONLY
 221     cc->sysemu_ops = &rx_sysemu_ops;
 222 #endif
 223     cc->gdb_read_register = rx_cpu_gdb_read_register;
 224     cc->gdb_write_register = rx_cpu_gdb_write_register;
 225     cc->disas_set_info = rx_cpu_disas_set_info;
 226
 227     cc->gdb_num_core_regs = 26;
 228     cc->gdb_core_xml_file = "rx-core.xml";
 229     cc->tcg_ops = &rx_tcg_ops;
 230 }
 231
 232 static const TypeInfo rx_cpu_info = {
 233     .name = TYPE_RX_CPU,
 234     .parent = TYPE_CPU,
 235     .instance_size = sizeof(RXCPU),
 236     .instance_init = rx_cpu_init,
 237     .abstract = true,
 238     .class_size = sizeof(RXCPUClass),
 239     .class_init = rx_cpu_class_init,
 240 };
 241
 242 static const TypeInfo rx62n_rx_cpu_info = {
 243     .name = TYPE_RX62N_CPU,
 244     .parent = TYPE_RX_CPU,
 245 };
 246
 247 static void rx_cpu_register_types(void)
 248 {
 249     type_register_static(&rx_cpu_info);
 250     type_register_static(&rx62n_rx_cpu_info);
 251 }
 252
 253 type_init(rx_cpu_register_types)