2 * QEMU RISC-V PMP (Physical Memory Protection)
4 * Author: Daire McNamara, daire.mcnamara@emdalo.com
5 * Ivan Griffin, ivan.griffin@emdalo.com
7 * This provides a RISC-V Physical Memory Protection implementation
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2 or later, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/osdep.h"
24 #include "qapi/error.h"
27 #include "exec/exec-all.h"
29 static void pmp_write_cfg(CPURISCVState
*env
, uint32_t addr_index
,
31 static uint8_t pmp_read_cfg(CPURISCVState
*env
, uint32_t addr_index
);
32 static void pmp_update_rule(CPURISCVState
*env
, uint32_t pmp_index
);
35 * Accessor method to extract address matching type 'a field' from cfg reg
37 static inline uint8_t pmp_get_a_field(uint8_t cfg
)
44 * Check whether a PMP is locked or not.
46 static inline int pmp_is_locked(CPURISCVState
*env
, uint32_t pmp_index
)
49 if (env
->pmp_state
.pmp
[pmp_index
].cfg_reg
& PMP_LOCK
) {
53 /* Top PMP has no 'next' to check */
54 if ((pmp_index
+ 1u) >= MAX_RISCV_PMPS
) {
62 * Count the number of active rules.
64 uint32_t pmp_get_num_rules(CPURISCVState
*env
)
66 return env
->pmp_state
.num_rules
;
70 * Accessor to get the cfg reg for a specific PMP/HART
72 static inline uint8_t pmp_read_cfg(CPURISCVState
*env
, uint32_t pmp_index
)
74 if (pmp_index
< MAX_RISCV_PMPS
) {
75 return env
->pmp_state
.pmp
[pmp_index
].cfg_reg
;
83 * Accessor to set the cfg reg for a specific PMP/HART
84 * Bounds checks and relevant lock bit.
86 static void pmp_write_cfg(CPURISCVState
*env
, uint32_t pmp_index
, uint8_t val
)
88 if (pmp_index
< MAX_RISCV_PMPS
) {
91 if (riscv_feature(env
, RISCV_FEATURE_EPMP
)) {
92 /* mseccfg.RLB is set */
93 if (MSECCFG_RLB_ISSET(env
)) {
97 /* mseccfg.MML is not set */
98 if (!MSECCFG_MML_ISSET(env
) && !pmp_is_locked(env
, pmp_index
)) {
102 /* mseccfg.MML is set */
103 if (MSECCFG_MML_ISSET(env
)) {
104 /* not adding execute bit */
105 if ((val
& PMP_LOCK
) != 0 && (val
& PMP_EXEC
) != PMP_EXEC
) {
108 /* shared region and not adding X bit */
109 if ((val
& PMP_LOCK
) != PMP_LOCK
&&
110 (val
& 0x7) != (PMP_WRITE
| PMP_EXEC
)) {
115 if (!pmp_is_locked(env
, pmp_index
)) {
121 qemu_log_mask(LOG_GUEST_ERROR
, "ignoring pmpcfg write - locked\n");
123 env
->pmp_state
.pmp
[pmp_index
].cfg_reg
= val
;
124 pmp_update_rule(env
, pmp_index
);
127 qemu_log_mask(LOG_GUEST_ERROR
,
128 "ignoring pmpcfg write - out of bounds\n");
132 static void pmp_decode_napot(target_ulong a
, target_ulong
*sa
, target_ulong
*ea
)
135 aaaa...aaa0 8-byte NAPOT range
136 aaaa...aa01 16-byte NAPOT range
137 aaaa...a011 32-byte NAPOT range
139 aa01...1111 2^XLEN-byte NAPOT range
140 a011...1111 2^(XLEN+1)-byte NAPOT range
141 0111...1111 2^(XLEN+2)-byte NAPOT range
149 void pmp_update_rule_addr(CPURISCVState
*env
, uint32_t pmp_index
)
151 uint8_t this_cfg
= env
->pmp_state
.pmp
[pmp_index
].cfg_reg
;
152 target_ulong this_addr
= env
->pmp_state
.pmp
[pmp_index
].addr_reg
;
153 target_ulong prev_addr
= 0u;
154 target_ulong sa
= 0u;
155 target_ulong ea
= 0u;
157 if (pmp_index
>= 1u) {
158 prev_addr
= env
->pmp_state
.pmp
[pmp_index
- 1].addr_reg
;
161 switch (pmp_get_a_field(this_cfg
)) {
168 sa
= prev_addr
<< 2; /* shift up from [xx:0] to [xx+2:2] */
169 ea
= (this_addr
<< 2) - 1u;
176 sa
= this_addr
<< 2; /* shift up from [xx:0] to [xx+2:2] */
180 case PMP_AMATCH_NAPOT
:
181 pmp_decode_napot(this_addr
, &sa
, &ea
);
190 env
->pmp_state
.addr
[pmp_index
].sa
= sa
;
191 env
->pmp_state
.addr
[pmp_index
].ea
= ea
;
194 void pmp_update_rule_nums(CPURISCVState
*env
)
198 env
->pmp_state
.num_rules
= 0;
199 for (i
= 0; i
< MAX_RISCV_PMPS
; i
++) {
200 const uint8_t a_field
=
201 pmp_get_a_field(env
->pmp_state
.pmp
[i
].cfg_reg
);
202 if (PMP_AMATCH_OFF
!= a_field
) {
203 env
->pmp_state
.num_rules
++;
208 /* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea'
209 * end address values.
210 * This function is called relatively infrequently whereas the check that
211 * an address is within a pmp rule is called often, so optimise that one
213 static void pmp_update_rule(CPURISCVState
*env
, uint32_t pmp_index
)
215 pmp_update_rule_addr(env
, pmp_index
);
216 pmp_update_rule_nums(env
);
219 static int pmp_is_in_range(CPURISCVState
*env
, int pmp_index
, target_ulong addr
)
223 if ((addr
>= env
->pmp_state
.addr
[pmp_index
].sa
)
224 && (addr
<= env
->pmp_state
.addr
[pmp_index
].ea
)) {
234 * Check if the address has required RWX privs when no PMP entry is matched.
236 static bool pmp_hart_has_privs_default(CPURISCVState
*env
, target_ulong addr
,
237 target_ulong size
, pmp_priv_t privs
, pmp_priv_t
*allowed_privs
,
242 if (riscv_feature(env
, RISCV_FEATURE_EPMP
)) {
243 if (MSECCFG_MMWP_ISSET(env
)) {
245 * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
246 * so we default to deny all, even for M-mode.
250 } else if (MSECCFG_MML_ISSET(env
)) {
252 * The Machine Mode Lockdown (mseccfg.MML) bit is set
253 * so we can only execute code in M-mode with an applicable
254 * rule. Other modes are disabled.
256 if (mode
== PRV_M
&& !(privs
& PMP_EXEC
)) {
258 *allowed_privs
= PMP_READ
| PMP_WRITE
;
268 if ((!riscv_feature(env
, RISCV_FEATURE_PMP
)) || (mode
== PRV_M
)) {
270 * Privileged spec v1.10 states if HW doesn't implement any PMP entry
271 * or no PMP entry matches an M-Mode access, the access succeeds.
274 *allowed_privs
= PMP_READ
| PMP_WRITE
| PMP_EXEC
;
277 * Other modes are not allowed to succeed if they don't * match a rule,
278 * but there are rules. We've checked for no rule earlier in this
294 * Check if the address has required RWX privs to complete desired operation
296 bool pmp_hart_has_privs(CPURISCVState
*env
, target_ulong addr
,
297 target_ulong size
, pmp_priv_t privs
, pmp_priv_t
*allowed_privs
,
306 /* Short cut if no rules */
307 if (0 == pmp_get_num_rules(env
)) {
308 return pmp_hart_has_privs_default(env
, addr
, size
, privs
,
309 allowed_privs
, mode
);
313 if (riscv_feature(env
, RISCV_FEATURE_MMU
)) {
315 * If size is unknown (0), assume that all bytes
316 * from addr to the end of the page will be accessed.
318 pmp_size
= -(addr
| TARGET_PAGE_MASK
);
320 pmp_size
= sizeof(target_ulong
);
326 /* 1.10 draft priv spec states there is an implicit order
328 for (i
= 0; i
< MAX_RISCV_PMPS
; i
++) {
329 s
= pmp_is_in_range(env
, i
, addr
);
330 e
= pmp_is_in_range(env
, i
, addr
+ pmp_size
- 1);
332 /* partially inside */
334 qemu_log_mask(LOG_GUEST_ERROR
,
335 "pmp violation - access is partially inside\n");
341 const uint8_t a_field
=
342 pmp_get_a_field(env
->pmp_state
.pmp
[i
].cfg_reg
);
345 * Convert the PMP permissions to match the truth table in the
348 const uint8_t epmp_operation
=
349 ((env
->pmp_state
.pmp
[i
].cfg_reg
& PMP_LOCK
) >> 4) |
350 ((env
->pmp_state
.pmp
[i
].cfg_reg
& PMP_READ
) << 2) |
351 (env
->pmp_state
.pmp
[i
].cfg_reg
& PMP_WRITE
) |
352 ((env
->pmp_state
.pmp
[i
].cfg_reg
& PMP_EXEC
) >> 2);
354 if (((s
+ e
) == 2) && (PMP_AMATCH_OFF
!= a_field
)) {
356 * If the PMP entry is not off and the address is in range,
359 if (!MSECCFG_MML_ISSET(env
)) {
361 * If mseccfg.MML Bit is not set, do pmp priv check
362 * This will always apply to regular PMP.
364 *allowed_privs
= PMP_READ
| PMP_WRITE
| PMP_EXEC
;
365 if ((mode
!= PRV_M
) || pmp_is_locked(env
, i
)) {
366 *allowed_privs
&= env
->pmp_state
.pmp
[i
].cfg_reg
;
370 * If mseccfg.MML Bit set, do the enhanced pmp priv check
373 switch (epmp_operation
) {
386 *allowed_privs
= PMP_READ
| PMP_WRITE
;
390 *allowed_privs
= PMP_EXEC
;
394 *allowed_privs
= PMP_READ
| PMP_EXEC
;
398 *allowed_privs
= PMP_READ
;
401 g_assert_not_reached();
404 switch (epmp_operation
) {
416 *allowed_privs
= PMP_EXEC
;
421 *allowed_privs
= PMP_READ
;
425 *allowed_privs
= PMP_READ
| PMP_WRITE
;
428 *allowed_privs
= PMP_READ
| PMP_EXEC
;
431 *allowed_privs
= PMP_READ
| PMP_WRITE
| PMP_EXEC
;
434 g_assert_not_reached();
439 ret
= ((privs
& *allowed_privs
) == privs
);
444 /* No rule matched */
446 return pmp_hart_has_privs_default(env
, addr
, size
, privs
,
447 allowed_privs
, mode
);
450 return ret
== 1 ? true : false;
454 * Handle a write to a pmpcfg CSR
456 void pmpcfg_csr_write(CPURISCVState
*env
, uint32_t reg_index
,
461 int pmpcfg_nums
= 2 << riscv_cpu_mxl(env
);
463 trace_pmpcfg_csr_write(env
->mhartid
, reg_index
, val
);
465 for (i
= 0; i
< pmpcfg_nums
; i
++) {
466 cfg_val
= (val
>> 8 * i
) & 0xff;
467 pmp_write_cfg(env
, (reg_index
* 4) + i
, cfg_val
);
470 /* If PMP permission of any addr has been changed, flush TLB pages. */
471 tlb_flush(env_cpu(env
));
476 * Handle a read from a pmpcfg CSR
478 target_ulong
pmpcfg_csr_read(CPURISCVState
*env
, uint32_t reg_index
)
481 target_ulong cfg_val
= 0;
482 target_ulong val
= 0;
483 int pmpcfg_nums
= 2 << riscv_cpu_mxl(env
);
485 for (i
= 0; i
< pmpcfg_nums
; i
++) {
486 val
= pmp_read_cfg(env
, (reg_index
* 4) + i
);
487 cfg_val
|= (val
<< (i
* 8));
489 trace_pmpcfg_csr_read(env
->mhartid
, reg_index
, cfg_val
);
496 * Handle a write to a pmpaddr CSR
498 void pmpaddr_csr_write(CPURISCVState
*env
, uint32_t addr_index
,
501 trace_pmpaddr_csr_write(env
->mhartid
, addr_index
, val
);
503 if (addr_index
< MAX_RISCV_PMPS
) {
505 * In TOR mode, need to check the lock bit of the next pmp
506 * (if there is a next).
508 if (addr_index
+ 1 < MAX_RISCV_PMPS
) {
509 uint8_t pmp_cfg
= env
->pmp_state
.pmp
[addr_index
+ 1].cfg_reg
;
511 if (pmp_cfg
& PMP_LOCK
&&
512 PMP_AMATCH_TOR
== pmp_get_a_field(pmp_cfg
)) {
513 qemu_log_mask(LOG_GUEST_ERROR
,
514 "ignoring pmpaddr write - pmpcfg + 1 locked\n");
519 if (!pmp_is_locked(env
, addr_index
)) {
520 env
->pmp_state
.pmp
[addr_index
].addr_reg
= val
;
521 pmp_update_rule(env
, addr_index
);
523 qemu_log_mask(LOG_GUEST_ERROR
,
524 "ignoring pmpaddr write - locked\n");
527 qemu_log_mask(LOG_GUEST_ERROR
,
528 "ignoring pmpaddr write - out of bounds\n");
534 * Handle a read from a pmpaddr CSR
536 target_ulong
pmpaddr_csr_read(CPURISCVState
*env
, uint32_t addr_index
)
538 target_ulong val
= 0;
540 if (addr_index
< MAX_RISCV_PMPS
) {
541 val
= env
->pmp_state
.pmp
[addr_index
].addr_reg
;
542 trace_pmpaddr_csr_read(env
->mhartid
, addr_index
, val
);
544 qemu_log_mask(LOG_GUEST_ERROR
,
545 "ignoring pmpaddr read - out of bounds\n");
552 * Handle a write to a mseccfg CSR
554 void mseccfg_csr_write(CPURISCVState
*env
, target_ulong val
)
558 trace_mseccfg_csr_write(env
->mhartid
, val
);
560 /* RLB cannot be enabled if it's already 0 and if any regions are locked */
561 if (!MSECCFG_RLB_ISSET(env
)) {
562 for (i
= 0; i
< MAX_RISCV_PMPS
; i
++) {
563 if (pmp_is_locked(env
, i
)) {
571 val
|= (env
->mseccfg
& (MSECCFG_MMWP
| MSECCFG_MML
));
577 * Handle a read from a mseccfg CSR
579 target_ulong
mseccfg_csr_read(CPURISCVState
*env
)
581 trace_mseccfg_csr_read(env
->mhartid
, env
->mseccfg
);
586 * Calculate the TLB size if the start address or the end address of
587 * PMP entry is presented in the TLB page.
589 static target_ulong
pmp_get_tlb_size(CPURISCVState
*env
, int pmp_index
,
590 target_ulong tlb_sa
, target_ulong tlb_ea
)
592 target_ulong pmp_sa
= env
->pmp_state
.addr
[pmp_index
].sa
;
593 target_ulong pmp_ea
= env
->pmp_state
.addr
[pmp_index
].ea
;
595 if (pmp_sa
>= tlb_sa
&& pmp_ea
<= tlb_ea
) {
596 return pmp_ea
- pmp_sa
+ 1;
599 if (pmp_sa
>= tlb_sa
&& pmp_sa
<= tlb_ea
&& pmp_ea
>= tlb_ea
) {
600 return tlb_ea
- pmp_sa
+ 1;
603 if (pmp_ea
<= tlb_ea
&& pmp_ea
>= tlb_sa
&& pmp_sa
<= tlb_sa
) {
604 return pmp_ea
- tlb_sa
+ 1;
611 * Check is there a PMP entry which range covers this page. If so,
612 * try to find the minimum granularity for the TLB size.
614 bool pmp_is_range_in_tlb(CPURISCVState
*env
, hwaddr tlb_sa
,
615 target_ulong
*tlb_size
)
619 target_ulong tlb_ea
= (tlb_sa
+ TARGET_PAGE_SIZE
- 1);
621 for (i
= 0; i
< MAX_RISCV_PMPS
; i
++) {
622 val
= pmp_get_tlb_size(env
, i
, tlb_sa
, tlb_ea
);
624 if (*tlb_size
== 0 || *tlb_size
> val
) {
630 if (*tlb_size
!= 0) {
638 * Convert PMP privilege to TLB page privilege.
640 int pmp_priv_to_page_prot(pmp_priv_t pmp_priv
)
644 if (pmp_priv
& PMP_READ
) {
647 if (pmp_priv
& PMP_WRITE
) {
650 if (pmp_priv
& PMP_EXEC
) {