4 * Copyright (c) 2013 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
25 #include "hw/core/tcg-cpu-ops.h"
26 #endif /* CONFIG_TCG */
27 #include "qemu/module.h"
28 #if !defined(CONFIG_USER_ONLY)
29 #include "hw/loader.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/hvf.h"
35 #include "qapi/visitor.h"
36 #include "hw/qdev-properties.h"
37 #include "internals.h"
39 static void aarch64_a35_initfn(Object
*obj
)
41 ARMCPU
*cpu
= ARM_CPU(obj
);
43 cpu
->dtb_compatible
= "arm,cortex-a35";
44 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
45 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
46 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
47 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
48 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
49 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
50 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
51 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
53 /* From B2.2 AArch64 identification registers. */
54 cpu
->midr
= 0x411fd040;
56 cpu
->ctr
= 0x84448004;
57 cpu
->isar
.id_pfr0
= 0x00000131;
58 cpu
->isar
.id_pfr1
= 0x00011011;
59 cpu
->isar
.id_dfr0
= 0x03010066;
61 cpu
->isar
.id_mmfr0
= 0x10201105;
62 cpu
->isar
.id_mmfr1
= 0x40000000;
63 cpu
->isar
.id_mmfr2
= 0x01260000;
64 cpu
->isar
.id_mmfr3
= 0x02102211;
65 cpu
->isar
.id_isar0
= 0x02101110;
66 cpu
->isar
.id_isar1
= 0x13112111;
67 cpu
->isar
.id_isar2
= 0x21232042;
68 cpu
->isar
.id_isar3
= 0x01112131;
69 cpu
->isar
.id_isar4
= 0x00011142;
70 cpu
->isar
.id_isar5
= 0x00011121;
71 cpu
->isar
.id_aa64pfr0
= 0x00002222;
72 cpu
->isar
.id_aa64pfr1
= 0;
73 cpu
->isar
.id_aa64dfr0
= 0x10305106;
74 cpu
->isar
.id_aa64dfr1
= 0;
75 cpu
->isar
.id_aa64isar0
= 0x00011120;
76 cpu
->isar
.id_aa64isar1
= 0;
77 cpu
->isar
.id_aa64mmfr0
= 0x00101122;
78 cpu
->isar
.id_aa64mmfr1
= 0;
79 cpu
->clidr
= 0x0a200023;
80 cpu
->dcz_blocksize
= 4;
82 /* From B2.4 AArch64 Virtual Memory control registers */
83 cpu
->reset_sctlr
= 0x00c50838;
85 /* From B2.10 AArch64 performance monitor registers */
86 cpu
->isar
.reset_pmcr_el0
= 0x410a3000;
88 /* From B2.29 Cache ID registers */
89 cpu
->ccsidr
[0] = 0x700fe01a; /* 32KB L1 dcache */
90 cpu
->ccsidr
[1] = 0x201fe00a; /* 32KB L1 icache */
91 cpu
->ccsidr
[2] = 0x703fe03a; /* 512KB L2 cache */
93 /* From B3.5 VGIC Type register */
95 cpu
->gic_vpribits
= 5;
96 cpu
->gic_vprebits
= 5;
99 /* From C6.4 Debug ID Register */
100 cpu
->isar
.dbgdidr
= 0x3516d000;
101 /* From C6.5 Debug Device ID Register */
102 cpu
->isar
.dbgdevid
= 0x00110f13;
103 /* From C6.6 Debug Device ID Register 1 */
104 cpu
->isar
.dbgdevid1
= 0x2;
106 /* From Cortex-A35 SIMD and Floating-point Support r1p0 */
107 /* From 3.2 AArch32 register summary */
108 cpu
->reset_fpsid
= 0x41034043;
110 /* From 2.2 AArch64 register summary */
111 cpu
->isar
.mvfr0
= 0x10110222;
112 cpu
->isar
.mvfr1
= 0x12111111;
113 cpu
->isar
.mvfr2
= 0x00000043;
115 /* These values are the same with A53/A57/A72. */
116 define_cortex_a72_a57_a53_cp_reginfo(cpu
);
119 void arm_cpu_sve_finalize(ARMCPU
*cpu
, Error
**errp
)
122 * If any vector lengths are explicitly enabled with sve<N> properties,
123 * then all other lengths are implicitly disabled. If sve-max-vq is
124 * specified then it is the same as explicitly enabling all lengths
125 * up to and including the specified maximum, which means all larger
126 * lengths will be implicitly disabled. If no sve<N> properties
127 * are enabled and sve-max-vq is not specified, then all lengths not
128 * explicitly disabled will be enabled. Additionally, all power-of-two
129 * vector lengths less than the maximum enabled length will be
130 * automatically enabled and all vector lengths larger than the largest
131 * disabled power-of-two vector length will be automatically disabled.
132 * Errors are generated if the user provided input that interferes with
133 * any of the above. Finally, if SVE is not disabled, then at least one
134 * vector length must be enabled.
136 uint32_t vq_map
= cpu
->sve_vq
.map
;
137 uint32_t vq_init
= cpu
->sve_vq
.init
;
138 uint32_t vq_supported
;
139 uint32_t vq_mask
= 0;
140 uint32_t tmp
, vq
, max_vq
= 0;
143 * CPU models specify a set of supported vector lengths which are
144 * enabled by default. Attempting to enable any vector length not set
145 * in the supported bitmap results in an error. When KVM is enabled we
146 * fetch the supported bitmap from the host.
149 if (kvm_arm_sve_supported()) {
150 cpu
->sve_vq
.supported
= kvm_arm_sve_get_vls(CPU(cpu
));
151 vq_supported
= cpu
->sve_vq
.supported
;
153 assert(!cpu_isar_feature(aa64_sve
, cpu
));
157 vq_supported
= cpu
->sve_vq
.supported
;
161 * Process explicit sve<N> properties.
162 * From the properties, sve_vq_map<N> implies sve_vq_init<N>.
163 * Check first for any sve<N> enabled.
166 max_vq
= 32 - clz32(vq_map
);
167 vq_mask
= MAKE_64BIT_MASK(0, max_vq
);
169 if (cpu
->sve_max_vq
&& max_vq
> cpu
->sve_max_vq
) {
170 error_setg(errp
, "cannot enable sve%d", max_vq
* 128);
171 error_append_hint(errp
, "sve%d is larger than the maximum vector "
172 "length, sve-max-vq=%d (%d bits)\n",
173 max_vq
* 128, cpu
->sve_max_vq
,
174 cpu
->sve_max_vq
* 128);
180 * For KVM we have to automatically enable all supported unitialized
181 * lengths, even when the smaller lengths are not all powers-of-two.
183 vq_map
|= vq_supported
& ~vq_init
& vq_mask
;
185 /* Propagate enabled bits down through required powers-of-two. */
186 vq_map
|= SVE_VQ_POW2_MAP
& ~vq_init
& vq_mask
;
188 } else if (cpu
->sve_max_vq
== 0) {
190 * No explicit bits enabled, and no implicit bits from sve-max-vq.
192 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
193 /* SVE is disabled and so are all vector lengths. Good. */
198 /* Disabling a supported length disables all larger lengths. */
199 tmp
= vq_init
& vq_supported
;
201 /* Disabling a power-of-two disables all larger lengths. */
202 tmp
= vq_init
& SVE_VQ_POW2_MAP
;
206 max_vq
= vq
<= ARM_MAX_VQ
? vq
- 1 : ARM_MAX_VQ
;
207 vq_mask
= MAKE_64BIT_MASK(0, max_vq
);
208 vq_map
= vq_supported
& ~vq_init
& vq_mask
;
210 if (max_vq
== 0 || vq_map
== 0) {
211 error_setg(errp
, "cannot disable sve%d", vq
* 128);
212 error_append_hint(errp
, "Disabling sve%d results in all "
213 "vector lengths being disabled.\n",
215 error_append_hint(errp
, "With SVE enabled, at least one "
216 "vector length must be enabled.\n");
220 max_vq
= 32 - clz32(vq_map
);
221 vq_mask
= MAKE_64BIT_MASK(0, max_vq
);
225 * Process the sve-max-vq property.
226 * Note that we know from the above that no bit above
227 * sve-max-vq is currently set.
229 if (cpu
->sve_max_vq
!= 0) {
230 max_vq
= cpu
->sve_max_vq
;
231 vq_mask
= MAKE_64BIT_MASK(0, max_vq
);
233 if (vq_init
& ~vq_map
& (1 << (max_vq
- 1))) {
234 error_setg(errp
, "cannot disable sve%d", max_vq
* 128);
235 error_append_hint(errp
, "The maximum vector length must be "
236 "enabled, sve-max-vq=%d (%d bits)\n",
237 max_vq
, max_vq
* 128);
241 /* Set all bits not explicitly set within sve-max-vq. */
242 vq_map
|= ~vq_init
& vq_mask
;
246 * We should know what max-vq is now. Also, as we're done
247 * manipulating sve-vq-map, we ensure any bits above max-vq
248 * are clear, just in case anybody looks.
251 assert(vq_mask
!= 0);
254 /* Ensure the set of lengths matches what is supported. */
255 tmp
= vq_map
^ (vq_supported
& vq_mask
);
257 vq
= 32 - clz32(tmp
);
258 if (vq_map
& (1 << (vq
- 1))) {
259 if (cpu
->sve_max_vq
) {
260 error_setg(errp
, "cannot set sve-max-vq=%d", cpu
->sve_max_vq
);
261 error_append_hint(errp
, "This CPU does not support "
262 "the vector length %d-bits.\n", vq
* 128);
263 error_append_hint(errp
, "It may not be possible to use "
264 "sve-max-vq with this CPU. Try "
265 "using only sve<N> properties.\n");
267 error_setg(errp
, "cannot enable sve%d", vq
* 128);
269 error_append_hint(errp
, "This CPU does not support "
270 "the vector length %d-bits.\n", vq
* 128);
272 error_append_hint(errp
, "SVE not supported by KVM "
279 error_setg(errp
, "cannot disable sve%d", vq
* 128);
280 error_append_hint(errp
, "The KVM host requires all "
281 "supported vector lengths smaller "
282 "than %d bits to also be enabled.\n",
286 /* Ensure all required powers-of-two are enabled. */
287 tmp
= SVE_VQ_POW2_MAP
& vq_mask
& ~vq_map
;
289 vq
= 32 - clz32(tmp
);
290 error_setg(errp
, "cannot disable sve%d", vq
* 128);
291 error_append_hint(errp
, "sve%d is required as it "
292 "is a power-of-two length smaller "
293 "than the maximum, sve%d\n",
294 vq
* 128, max_vq
* 128);
302 * Now that we validated all our vector lengths, the only question
303 * left to answer is if we even want SVE at all.
305 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
306 error_setg(errp
, "cannot enable sve%d", max_vq
* 128);
307 error_append_hint(errp
, "SVE must be enabled to enable vector "
309 error_append_hint(errp
, "Add sve=on to the CPU property list.\n");
313 /* From now on sve_max_vq is the actual maximum supported length. */
314 cpu
->sve_max_vq
= max_vq
;
315 cpu
->sve_vq
.map
= vq_map
;
318 static void cpu_max_get_sve_max_vq(Object
*obj
, Visitor
*v
, const char *name
,
319 void *opaque
, Error
**errp
)
321 ARMCPU
*cpu
= ARM_CPU(obj
);
324 /* All vector lengths are disabled when SVE is off. */
325 if (!cpu_isar_feature(aa64_sve
, cpu
)) {
328 value
= cpu
->sve_max_vq
;
330 visit_type_uint32(v
, name
, &value
, errp
);
333 static void cpu_max_set_sve_max_vq(Object
*obj
, Visitor
*v
, const char *name
,
334 void *opaque
, Error
**errp
)
336 ARMCPU
*cpu
= ARM_CPU(obj
);
339 if (!visit_type_uint32(v
, name
, &max_vq
, errp
)) {
343 if (kvm_enabled() && !kvm_arm_sve_supported()) {
344 error_setg(errp
, "cannot set sve-max-vq");
345 error_append_hint(errp
, "SVE not supported by KVM on this host\n");
349 if (max_vq
== 0 || max_vq
> ARM_MAX_VQ
) {
350 error_setg(errp
, "unsupported SVE vector length");
351 error_append_hint(errp
, "Valid sve-max-vq in range [1-%d]\n",
356 cpu
->sve_max_vq
= max_vq
;
360 * Note that cpu_arm_{get,set}_vq cannot use the simpler
361 * object_property_add_bool interface because they make use of the
362 * contents of "name" to determine which bit on which to operate.
364 static void cpu_arm_get_vq(Object
*obj
, Visitor
*v
, const char *name
,
365 void *opaque
, Error
**errp
)
367 ARMCPU
*cpu
= ARM_CPU(obj
);
368 ARMVQMap
*vq_map
= opaque
;
369 uint32_t vq
= atoi(&name
[3]) / 128;
370 bool sve
= vq_map
== &cpu
->sve_vq
;
373 /* All vector lengths are disabled when feature is off. */
375 ? !cpu_isar_feature(aa64_sve
, cpu
)
376 : !cpu_isar_feature(aa64_sme
, cpu
)) {
379 value
= extract32(vq_map
->map
, vq
- 1, 1);
381 visit_type_bool(v
, name
, &value
, errp
);
384 static void cpu_arm_set_vq(Object
*obj
, Visitor
*v
, const char *name
,
385 void *opaque
, Error
**errp
)
387 ARMVQMap
*vq_map
= opaque
;
388 uint32_t vq
= atoi(&name
[3]) / 128;
391 if (!visit_type_bool(v
, name
, &value
, errp
)) {
395 vq_map
->map
= deposit32(vq_map
->map
, vq
- 1, 1, value
);
396 vq_map
->init
|= 1 << (vq
- 1);
399 static bool cpu_arm_get_sve(Object
*obj
, Error
**errp
)
401 ARMCPU
*cpu
= ARM_CPU(obj
);
402 return cpu_isar_feature(aa64_sve
, cpu
);
405 static void cpu_arm_set_sve(Object
*obj
, bool value
, Error
**errp
)
407 ARMCPU
*cpu
= ARM_CPU(obj
);
410 if (value
&& kvm_enabled() && !kvm_arm_sve_supported()) {
411 error_setg(errp
, "'sve' feature not supported by KVM on this host");
415 t
= cpu
->isar
.id_aa64pfr0
;
416 t
= FIELD_DP64(t
, ID_AA64PFR0
, SVE
, value
);
417 cpu
->isar
.id_aa64pfr0
= t
;
420 void arm_cpu_sme_finalize(ARMCPU
*cpu
, Error
**errp
)
422 uint32_t vq_map
= cpu
->sme_vq
.map
;
423 uint32_t vq_init
= cpu
->sme_vq
.init
;
424 uint32_t vq_supported
= cpu
->sme_vq
.supported
;
428 if (!cpu_isar_feature(aa64_sme
, cpu
)) {
429 cpu
->isar
.id_aa64smfr0
= 0;
433 /* TODO: KVM will require limitations via SMCR_EL2. */
434 vq_map
= vq_supported
& ~vq_init
;
437 vq
= ctz32(vq_supported
) + 1;
438 error_setg(errp
, "cannot disable sme%d", vq
* 128);
439 error_append_hint(errp
, "All SME vector lengths are disabled.\n");
440 error_append_hint(errp
, "With SME enabled, at least one "
441 "vector length must be enabled.\n");
445 if (!cpu_isar_feature(aa64_sme
, cpu
)) {
446 vq
= 32 - clz32(vq_map
);
447 error_setg(errp
, "cannot enable sme%d", vq
* 128);
448 error_append_hint(errp
, "SME must be enabled to enable "
449 "vector lengths.\n");
450 error_append_hint(errp
, "Add sme=on to the CPU property list.\n");
453 /* TODO: KVM will require limitations via SMCR_EL2. */
456 cpu
->sme_vq
.map
= vq_map
;
459 static bool cpu_arm_get_sme(Object
*obj
, Error
**errp
)
461 ARMCPU
*cpu
= ARM_CPU(obj
);
462 return cpu_isar_feature(aa64_sme
, cpu
);
465 static void cpu_arm_set_sme(Object
*obj
, bool value
, Error
**errp
)
467 ARMCPU
*cpu
= ARM_CPU(obj
);
470 t
= cpu
->isar
.id_aa64pfr1
;
471 t
= FIELD_DP64(t
, ID_AA64PFR1
, SME
, value
);
472 cpu
->isar
.id_aa64pfr1
= t
;
475 static bool cpu_arm_get_sme_fa64(Object
*obj
, Error
**errp
)
477 ARMCPU
*cpu
= ARM_CPU(obj
);
478 return cpu_isar_feature(aa64_sme
, cpu
) &&
479 cpu_isar_feature(aa64_sme_fa64
, cpu
);
482 static void cpu_arm_set_sme_fa64(Object
*obj
, bool value
, Error
**errp
)
484 ARMCPU
*cpu
= ARM_CPU(obj
);
487 t
= cpu
->isar
.id_aa64smfr0
;
488 t
= FIELD_DP64(t
, ID_AA64SMFR0
, FA64
, value
);
489 cpu
->isar
.id_aa64smfr0
= t
;
492 #ifdef CONFIG_USER_ONLY
493 /* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */
494 static void cpu_arm_set_default_vec_len(Object
*obj
, Visitor
*v
,
495 const char *name
, void *opaque
,
498 uint32_t *ptr_default_vq
= opaque
;
499 int32_t default_len
, default_vq
, remainder
;
501 if (!visit_type_int32(v
, name
, &default_len
, errp
)) {
505 /* Undocumented, but the kernel allows -1 to indicate "maximum". */
506 if (default_len
== -1) {
507 *ptr_default_vq
= ARM_MAX_VQ
;
511 default_vq
= default_len
/ 16;
512 remainder
= default_len
% 16;
515 * Note that the 512 max comes from include/uapi/asm/sve_context.h
516 * and is the maximum architectural width of ZCR_ELx.LEN.
518 if (remainder
|| default_vq
< 1 || default_vq
> 512) {
519 ARMCPU
*cpu
= ARM_CPU(obj
);
521 (ptr_default_vq
== &cpu
->sve_default_vq
? "sve" : "sme");
523 error_setg(errp
, "cannot set %s-default-vector-length", which
);
525 error_append_hint(errp
, "Vector length not a multiple of 16\n");
526 } else if (default_vq
< 1) {
527 error_append_hint(errp
, "Vector length smaller than 16\n");
529 error_append_hint(errp
, "Vector length larger than %d\n",
535 *ptr_default_vq
= default_vq
;
538 static void cpu_arm_get_default_vec_len(Object
*obj
, Visitor
*v
,
539 const char *name
, void *opaque
,
542 uint32_t *ptr_default_vq
= opaque
;
543 int32_t value
= *ptr_default_vq
* 16;
545 visit_type_int32(v
, name
, &value
, errp
);
549 static void aarch64_add_sve_properties(Object
*obj
)
551 ARMCPU
*cpu
= ARM_CPU(obj
);
554 object_property_add_bool(obj
, "sve", cpu_arm_get_sve
, cpu_arm_set_sve
);
556 for (vq
= 1; vq
<= ARM_MAX_VQ
; ++vq
) {
558 sprintf(name
, "sve%d", vq
* 128);
559 object_property_add(obj
, name
, "bool", cpu_arm_get_vq
,
560 cpu_arm_set_vq
, NULL
, &cpu
->sve_vq
);
563 #ifdef CONFIG_USER_ONLY
564 /* Mirror linux /proc/sys/abi/sve_default_vector_length. */
565 object_property_add(obj
, "sve-default-vector-length", "int32",
566 cpu_arm_get_default_vec_len
,
567 cpu_arm_set_default_vec_len
, NULL
,
568 &cpu
->sve_default_vq
);
572 static void aarch64_add_sme_properties(Object
*obj
)
574 ARMCPU
*cpu
= ARM_CPU(obj
);
577 object_property_add_bool(obj
, "sme", cpu_arm_get_sme
, cpu_arm_set_sme
);
578 object_property_add_bool(obj
, "sme_fa64", cpu_arm_get_sme_fa64
,
579 cpu_arm_set_sme_fa64
);
581 for (vq
= 1; vq
<= ARM_MAX_VQ
; vq
<<= 1) {
583 sprintf(name
, "sme%d", vq
* 128);
584 object_property_add(obj
, name
, "bool", cpu_arm_get_vq
,
585 cpu_arm_set_vq
, NULL
, &cpu
->sme_vq
);
588 #ifdef CONFIG_USER_ONLY
589 /* Mirror linux /proc/sys/abi/sme_default_vector_length. */
590 object_property_add(obj
, "sme-default-vector-length", "int32",
591 cpu_arm_get_default_vec_len
,
592 cpu_arm_set_default_vec_len
, NULL
,
593 &cpu
->sme_default_vq
);
597 void arm_cpu_pauth_finalize(ARMCPU
*cpu
, Error
**errp
)
599 int arch_val
= 0, impdef_val
= 0;
602 /* Exit early if PAuth is enabled, and fall through to disable it */
603 if ((kvm_enabled() || hvf_enabled()) && cpu
->prop_pauth
) {
604 if (!cpu_isar_feature(aa64_pauth
, cpu
)) {
605 error_setg(errp
, "'pauth' feature not supported by %s on this host",
606 kvm_enabled() ? "KVM" : "hvf");
612 /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */
613 if (cpu
->prop_pauth
) {
614 if (cpu
->prop_pauth_impdef
) {
619 } else if (cpu
->prop_pauth_impdef
) {
620 error_setg(errp
, "cannot enable pauth-impdef without pauth");
621 error_append_hint(errp
, "Add pauth=on to the CPU property list.\n");
624 t
= cpu
->isar
.id_aa64isar1
;
625 t
= FIELD_DP64(t
, ID_AA64ISAR1
, APA
, arch_val
);
626 t
= FIELD_DP64(t
, ID_AA64ISAR1
, GPA
, arch_val
);
627 t
= FIELD_DP64(t
, ID_AA64ISAR1
, API
, impdef_val
);
628 t
= FIELD_DP64(t
, ID_AA64ISAR1
, GPI
, impdef_val
);
629 cpu
->isar
.id_aa64isar1
= t
;
632 static Property arm_cpu_pauth_property
=
633 DEFINE_PROP_BOOL("pauth", ARMCPU
, prop_pauth
, true);
634 static Property arm_cpu_pauth_impdef_property
=
635 DEFINE_PROP_BOOL("pauth-impdef", ARMCPU
, prop_pauth_impdef
, false);
637 static void aarch64_add_pauth_properties(Object
*obj
)
639 ARMCPU
*cpu
= ARM_CPU(obj
);
641 /* Default to PAUTH on, with the architected algorithm on TCG. */
642 qdev_property_add_static(DEVICE(obj
), &arm_cpu_pauth_property
);
643 if (kvm_enabled() || hvf_enabled()) {
645 * Mirror PAuth support from the probed sysregs back into the
646 * property for KVM or hvf. Is it just a bit backward? Yes it is!
647 * Note that prop_pauth is true whether the host CPU supports the
648 * architected QARMA5 algorithm or the IMPDEF one. We don't
649 * provide the separate pauth-impdef property for KVM or hvf,
652 cpu
->prop_pauth
= cpu_isar_feature(aa64_pauth
, cpu
);
654 qdev_property_add_static(DEVICE(obj
), &arm_cpu_pauth_impdef_property
);
658 static Property arm_cpu_lpa2_property
=
659 DEFINE_PROP_BOOL("lpa2", ARMCPU
, prop_lpa2
, true);
661 void arm_cpu_lpa2_finalize(ARMCPU
*cpu
, Error
**errp
)
666 * We only install the property for tcg -cpu max; this is the
667 * only situation in which the cpu field can be true.
669 if (!cpu
->prop_lpa2
) {
673 t
= cpu
->isar
.id_aa64mmfr0
;
674 t
= FIELD_DP64(t
, ID_AA64MMFR0
, TGRAN16
, 2); /* 16k pages w/ LPA2 */
675 t
= FIELD_DP64(t
, ID_AA64MMFR0
, TGRAN4
, 1); /* 4k pages w/ LPA2 */
676 t
= FIELD_DP64(t
, ID_AA64MMFR0
, TGRAN16_2
, 3); /* 16k stage2 w/ LPA2 */
677 t
= FIELD_DP64(t
, ID_AA64MMFR0
, TGRAN4_2
, 3); /* 4k stage2 w/ LPA2 */
678 cpu
->isar
.id_aa64mmfr0
= t
;
681 static void aarch64_a57_initfn(Object
*obj
)
683 ARMCPU
*cpu
= ARM_CPU(obj
);
685 cpu
->dtb_compatible
= "arm,cortex-a57";
686 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
687 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
688 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
689 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
690 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
691 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
692 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
693 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
694 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A57
;
695 cpu
->midr
= 0x411fd070;
696 cpu
->revidr
= 0x00000000;
697 cpu
->reset_fpsid
= 0x41034070;
698 cpu
->isar
.mvfr0
= 0x10110222;
699 cpu
->isar
.mvfr1
= 0x12111111;
700 cpu
->isar
.mvfr2
= 0x00000043;
701 cpu
->ctr
= 0x8444c004;
702 cpu
->reset_sctlr
= 0x00c50838;
703 cpu
->isar
.id_pfr0
= 0x00000131;
704 cpu
->isar
.id_pfr1
= 0x00011011;
705 cpu
->isar
.id_dfr0
= 0x03010066;
706 cpu
->id_afr0
= 0x00000000;
707 cpu
->isar
.id_mmfr0
= 0x10101105;
708 cpu
->isar
.id_mmfr1
= 0x40000000;
709 cpu
->isar
.id_mmfr2
= 0x01260000;
710 cpu
->isar
.id_mmfr3
= 0x02102211;
711 cpu
->isar
.id_isar0
= 0x02101110;
712 cpu
->isar
.id_isar1
= 0x13112111;
713 cpu
->isar
.id_isar2
= 0x21232042;
714 cpu
->isar
.id_isar3
= 0x01112131;
715 cpu
->isar
.id_isar4
= 0x00011142;
716 cpu
->isar
.id_isar5
= 0x00011121;
717 cpu
->isar
.id_isar6
= 0;
718 cpu
->isar
.id_aa64pfr0
= 0x00002222;
719 cpu
->isar
.id_aa64dfr0
= 0x10305106;
720 cpu
->isar
.id_aa64isar0
= 0x00011120;
721 cpu
->isar
.id_aa64mmfr0
= 0x00001124;
722 cpu
->isar
.dbgdidr
= 0x3516d000;
723 cpu
->isar
.dbgdevid
= 0x01110f13;
724 cpu
->isar
.dbgdevid1
= 0x2;
725 cpu
->isar
.reset_pmcr_el0
= 0x41013000;
726 cpu
->clidr
= 0x0a200023;
727 cpu
->ccsidr
[0] = 0x701fe00a; /* 32KB L1 dcache */
728 cpu
->ccsidr
[1] = 0x201fe012; /* 48KB L1 icache */
729 cpu
->ccsidr
[2] = 0x70ffe07a; /* 2048KB L2 cache */
730 cpu
->dcz_blocksize
= 4; /* 64 bytes */
731 cpu
->gic_num_lrs
= 4;
732 cpu
->gic_vpribits
= 5;
733 cpu
->gic_vprebits
= 5;
734 cpu
->gic_pribits
= 5;
735 define_cortex_a72_a57_a53_cp_reginfo(cpu
);
738 static void aarch64_a53_initfn(Object
*obj
)
740 ARMCPU
*cpu
= ARM_CPU(obj
);
742 cpu
->dtb_compatible
= "arm,cortex-a53";
743 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
744 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
745 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
746 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
747 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
748 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
749 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
750 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
751 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A53
;
752 cpu
->midr
= 0x410fd034;
753 cpu
->revidr
= 0x00000000;
754 cpu
->reset_fpsid
= 0x41034070;
755 cpu
->isar
.mvfr0
= 0x10110222;
756 cpu
->isar
.mvfr1
= 0x12111111;
757 cpu
->isar
.mvfr2
= 0x00000043;
758 cpu
->ctr
= 0x84448004; /* L1Ip = VIPT */
759 cpu
->reset_sctlr
= 0x00c50838;
760 cpu
->isar
.id_pfr0
= 0x00000131;
761 cpu
->isar
.id_pfr1
= 0x00011011;
762 cpu
->isar
.id_dfr0
= 0x03010066;
763 cpu
->id_afr0
= 0x00000000;
764 cpu
->isar
.id_mmfr0
= 0x10101105;
765 cpu
->isar
.id_mmfr1
= 0x40000000;
766 cpu
->isar
.id_mmfr2
= 0x01260000;
767 cpu
->isar
.id_mmfr3
= 0x02102211;
768 cpu
->isar
.id_isar0
= 0x02101110;
769 cpu
->isar
.id_isar1
= 0x13112111;
770 cpu
->isar
.id_isar2
= 0x21232042;
771 cpu
->isar
.id_isar3
= 0x01112131;
772 cpu
->isar
.id_isar4
= 0x00011142;
773 cpu
->isar
.id_isar5
= 0x00011121;
774 cpu
->isar
.id_isar6
= 0;
775 cpu
->isar
.id_aa64pfr0
= 0x00002222;
776 cpu
->isar
.id_aa64dfr0
= 0x10305106;
777 cpu
->isar
.id_aa64isar0
= 0x00011120;
778 cpu
->isar
.id_aa64mmfr0
= 0x00001122; /* 40 bit physical addr */
779 cpu
->isar
.dbgdidr
= 0x3516d000;
780 cpu
->isar
.dbgdevid
= 0x00110f13;
781 cpu
->isar
.dbgdevid1
= 0x1;
782 cpu
->isar
.reset_pmcr_el0
= 0x41033000;
783 cpu
->clidr
= 0x0a200023;
784 cpu
->ccsidr
[0] = 0x700fe01a; /* 32KB L1 dcache */
785 cpu
->ccsidr
[1] = 0x201fe00a; /* 32KB L1 icache */
786 cpu
->ccsidr
[2] = 0x707fe07a; /* 1024KB L2 cache */
787 cpu
->dcz_blocksize
= 4; /* 64 bytes */
788 cpu
->gic_num_lrs
= 4;
789 cpu
->gic_vpribits
= 5;
790 cpu
->gic_vprebits
= 5;
791 cpu
->gic_pribits
= 5;
792 define_cortex_a72_a57_a53_cp_reginfo(cpu
);
795 static void aarch64_a72_initfn(Object
*obj
)
797 ARMCPU
*cpu
= ARM_CPU(obj
);
799 cpu
->dtb_compatible
= "arm,cortex-a72";
800 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
801 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
802 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
803 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
804 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
805 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
806 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
807 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
808 cpu
->midr
= 0x410fd083;
809 cpu
->revidr
= 0x00000000;
810 cpu
->reset_fpsid
= 0x41034080;
811 cpu
->isar
.mvfr0
= 0x10110222;
812 cpu
->isar
.mvfr1
= 0x12111111;
813 cpu
->isar
.mvfr2
= 0x00000043;
814 cpu
->ctr
= 0x8444c004;
815 cpu
->reset_sctlr
= 0x00c50838;
816 cpu
->isar
.id_pfr0
= 0x00000131;
817 cpu
->isar
.id_pfr1
= 0x00011011;
818 cpu
->isar
.id_dfr0
= 0x03010066;
819 cpu
->id_afr0
= 0x00000000;
820 cpu
->isar
.id_mmfr0
= 0x10201105;
821 cpu
->isar
.id_mmfr1
= 0x40000000;
822 cpu
->isar
.id_mmfr2
= 0x01260000;
823 cpu
->isar
.id_mmfr3
= 0x02102211;
824 cpu
->isar
.id_isar0
= 0x02101110;
825 cpu
->isar
.id_isar1
= 0x13112111;
826 cpu
->isar
.id_isar2
= 0x21232042;
827 cpu
->isar
.id_isar3
= 0x01112131;
828 cpu
->isar
.id_isar4
= 0x00011142;
829 cpu
->isar
.id_isar5
= 0x00011121;
830 cpu
->isar
.id_aa64pfr0
= 0x00002222;
831 cpu
->isar
.id_aa64dfr0
= 0x10305106;
832 cpu
->isar
.id_aa64isar0
= 0x00011120;
833 cpu
->isar
.id_aa64mmfr0
= 0x00001124;
834 cpu
->isar
.dbgdidr
= 0x3516d000;
835 cpu
->isar
.dbgdevid
= 0x01110f13;
836 cpu
->isar
.dbgdevid1
= 0x2;
837 cpu
->isar
.reset_pmcr_el0
= 0x41023000;
838 cpu
->clidr
= 0x0a200023;
839 cpu
->ccsidr
[0] = 0x701fe00a; /* 32KB L1 dcache */
840 cpu
->ccsidr
[1] = 0x201fe012; /* 48KB L1 icache */
841 cpu
->ccsidr
[2] = 0x707fe07a; /* 1MB L2 cache */
842 cpu
->dcz_blocksize
= 4; /* 64 bytes */
843 cpu
->gic_num_lrs
= 4;
844 cpu
->gic_vpribits
= 5;
845 cpu
->gic_vprebits
= 5;
846 cpu
->gic_pribits
= 5;
847 define_cortex_a72_a57_a53_cp_reginfo(cpu
);
850 static void aarch64_a76_initfn(Object
*obj
)
852 ARMCPU
*cpu
= ARM_CPU(obj
);
854 cpu
->dtb_compatible
= "arm,cortex-a76";
855 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
856 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
857 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
858 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
859 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
860 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
861 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
862 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
864 /* Ordered by B2.4 AArch64 registers by functional group */
865 cpu
->clidr
= 0x82000023;
866 cpu
->ctr
= 0x8444C004;
867 cpu
->dcz_blocksize
= 4;
868 cpu
->isar
.id_aa64dfr0
= 0x0000000010305408ull
;
869 cpu
->isar
.id_aa64isar0
= 0x0000100010211120ull
;
870 cpu
->isar
.id_aa64isar1
= 0x0000000000100001ull
;
871 cpu
->isar
.id_aa64mmfr0
= 0x0000000000101122ull
;
872 cpu
->isar
.id_aa64mmfr1
= 0x0000000010212122ull
;
873 cpu
->isar
.id_aa64mmfr2
= 0x0000000000001011ull
;
874 cpu
->isar
.id_aa64pfr0
= 0x1100000010111112ull
; /* GIC filled in later */
875 cpu
->isar
.id_aa64pfr1
= 0x0000000000000010ull
;
876 cpu
->id_afr0
= 0x00000000;
877 cpu
->isar
.id_dfr0
= 0x04010088;
878 cpu
->isar
.id_isar0
= 0x02101110;
879 cpu
->isar
.id_isar1
= 0x13112111;
880 cpu
->isar
.id_isar2
= 0x21232042;
881 cpu
->isar
.id_isar3
= 0x01112131;
882 cpu
->isar
.id_isar4
= 0x00010142;
883 cpu
->isar
.id_isar5
= 0x01011121;
884 cpu
->isar
.id_isar6
= 0x00000010;
885 cpu
->isar
.id_mmfr0
= 0x10201105;
886 cpu
->isar
.id_mmfr1
= 0x40000000;
887 cpu
->isar
.id_mmfr2
= 0x01260000;
888 cpu
->isar
.id_mmfr3
= 0x02122211;
889 cpu
->isar
.id_mmfr4
= 0x00021110;
890 cpu
->isar
.id_pfr0
= 0x10010131;
891 cpu
->isar
.id_pfr1
= 0x00010000; /* GIC filled in later */
892 cpu
->isar
.id_pfr2
= 0x00000011;
893 cpu
->midr
= 0x414fd0b1; /* r4p1 */
896 /* From B2.18 CCSIDR_EL1 */
897 cpu
->ccsidr
[0] = 0x701fe01a; /* 64KB L1 dcache */
898 cpu
->ccsidr
[1] = 0x201fe01a; /* 64KB L1 icache */
899 cpu
->ccsidr
[2] = 0x707fe03a; /* 512KB L2 cache */
901 /* From B2.93 SCTLR_EL3 */
902 cpu
->reset_sctlr
= 0x30c50838;
904 /* From B4.23 ICH_VTR_EL2 */
905 cpu
->gic_num_lrs
= 4;
906 cpu
->gic_vpribits
= 5;
907 cpu
->gic_vprebits
= 5;
908 cpu
->gic_pribits
= 5;
910 /* From B5.1 AdvSIMD AArch64 register summary */
911 cpu
->isar
.mvfr0
= 0x10110222;
912 cpu
->isar
.mvfr1
= 0x13211111;
913 cpu
->isar
.mvfr2
= 0x00000043;
915 /* From D5.1 AArch64 PMU register summary */
916 cpu
->isar
.reset_pmcr_el0
= 0x410b3000;
919 static void aarch64_a64fx_initfn(Object
*obj
)
921 ARMCPU
*cpu
= ARM_CPU(obj
);
923 cpu
->dtb_compatible
= "arm,a64fx";
924 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
925 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
926 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
927 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
928 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
929 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
930 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
931 cpu
->midr
= 0x461f0010;
932 cpu
->revidr
= 0x00000000;
933 cpu
->ctr
= 0x86668006;
934 cpu
->reset_sctlr
= 0x30000180;
935 cpu
->isar
.id_aa64pfr0
= 0x0000000101111111; /* No RAS Extensions */
936 cpu
->isar
.id_aa64pfr1
= 0x0000000000000000;
937 cpu
->isar
.id_aa64dfr0
= 0x0000000010305408;
938 cpu
->isar
.id_aa64dfr1
= 0x0000000000000000;
939 cpu
->id_aa64afr0
= 0x0000000000000000;
940 cpu
->id_aa64afr1
= 0x0000000000000000;
941 cpu
->isar
.id_aa64mmfr0
= 0x0000000000001122;
942 cpu
->isar
.id_aa64mmfr1
= 0x0000000011212100;
943 cpu
->isar
.id_aa64mmfr2
= 0x0000000000001011;
944 cpu
->isar
.id_aa64isar0
= 0x0000000010211120;
945 cpu
->isar
.id_aa64isar1
= 0x0000000000010001;
946 cpu
->isar
.id_aa64zfr0
= 0x0000000000000000;
947 cpu
->clidr
= 0x0000000080000023;
948 cpu
->ccsidr
[0] = 0x7007e01c; /* 64KB L1 dcache */
949 cpu
->ccsidr
[1] = 0x2007e01c; /* 64KB L1 icache */
950 cpu
->ccsidr
[2] = 0x70ffe07c; /* 8MB L2 cache */
951 cpu
->dcz_blocksize
= 6; /* 256 bytes */
952 cpu
->gic_num_lrs
= 4;
953 cpu
->gic_vpribits
= 5;
954 cpu
->gic_vprebits
= 5;
955 cpu
->gic_pribits
= 5;
957 /* The A64FX supports only 128, 256 and 512 bit vector lengths */
958 aarch64_add_sve_properties(obj
);
959 cpu
->sve_vq
.supported
= (1 << 0) /* 128bit */
960 | (1 << 1) /* 256bit */
961 | (1 << 3); /* 512bit */
963 cpu
->isar
.reset_pmcr_el0
= 0x46014040;
965 /* TODO: Add A64FX specific HPC extension registers */
968 static void aarch64_neoverse_n1_initfn(Object
*obj
)
970 ARMCPU
*cpu
= ARM_CPU(obj
);
972 cpu
->dtb_compatible
= "arm,neoverse-n1";
973 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
974 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
975 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
976 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
977 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
978 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
979 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
980 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
982 /* Ordered by B2.4 AArch64 registers by functional group */
983 cpu
->clidr
= 0x82000023;
984 cpu
->ctr
= 0x8444c004;
985 cpu
->dcz_blocksize
= 4;
986 cpu
->isar
.id_aa64dfr0
= 0x0000000110305408ull
;
987 cpu
->isar
.id_aa64isar0
= 0x0000100010211120ull
;
988 cpu
->isar
.id_aa64isar1
= 0x0000000000100001ull
;
989 cpu
->isar
.id_aa64mmfr0
= 0x0000000000101125ull
;
990 cpu
->isar
.id_aa64mmfr1
= 0x0000000010212122ull
;
991 cpu
->isar
.id_aa64mmfr2
= 0x0000000000001011ull
;
992 cpu
->isar
.id_aa64pfr0
= 0x1100000010111112ull
; /* GIC filled in later */
993 cpu
->isar
.id_aa64pfr1
= 0x0000000000000020ull
;
994 cpu
->id_afr0
= 0x00000000;
995 cpu
->isar
.id_dfr0
= 0x04010088;
996 cpu
->isar
.id_isar0
= 0x02101110;
997 cpu
->isar
.id_isar1
= 0x13112111;
998 cpu
->isar
.id_isar2
= 0x21232042;
999 cpu
->isar
.id_isar3
= 0x01112131;
1000 cpu
->isar
.id_isar4
= 0x00010142;
1001 cpu
->isar
.id_isar5
= 0x01011121;
1002 cpu
->isar
.id_isar6
= 0x00000010;
1003 cpu
->isar
.id_mmfr0
= 0x10201105;
1004 cpu
->isar
.id_mmfr1
= 0x40000000;
1005 cpu
->isar
.id_mmfr2
= 0x01260000;
1006 cpu
->isar
.id_mmfr3
= 0x02122211;
1007 cpu
->isar
.id_mmfr4
= 0x00021110;
1008 cpu
->isar
.id_pfr0
= 0x10010131;
1009 cpu
->isar
.id_pfr1
= 0x00010000; /* GIC filled in later */
1010 cpu
->isar
.id_pfr2
= 0x00000011;
1011 cpu
->midr
= 0x414fd0c1; /* r4p1 */
1014 /* From B2.23 CCSIDR_EL1 */
1015 cpu
->ccsidr
[0] = 0x701fe01a; /* 64KB L1 dcache */
1016 cpu
->ccsidr
[1] = 0x201fe01a; /* 64KB L1 icache */
1017 cpu
->ccsidr
[2] = 0x70ffe03a; /* 1MB L2 cache */
1019 /* From B2.98 SCTLR_EL3 */
1020 cpu
->reset_sctlr
= 0x30c50838;
1022 /* From B4.23 ICH_VTR_EL2 */
1023 cpu
->gic_num_lrs
= 4;
1024 cpu
->gic_vpribits
= 5;
1025 cpu
->gic_vprebits
= 5;
1026 cpu
->gic_pribits
= 5;
1028 /* From B5.1 AdvSIMD AArch64 register summary */
1029 cpu
->isar
.mvfr0
= 0x10110222;
1030 cpu
->isar
.mvfr1
= 0x13211111;
1031 cpu
->isar
.mvfr2
= 0x00000043;
1033 /* From D5.1 AArch64 PMU register summary */
1034 cpu
->isar
.reset_pmcr_el0
= 0x410c3000;
1037 static void aarch64_host_initfn(Object
*obj
)
1039 #if defined(CONFIG_KVM)
1040 ARMCPU
*cpu
= ARM_CPU(obj
);
1041 kvm_arm_set_cpu_features_from_host(cpu
);
1042 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1043 aarch64_add_sve_properties(obj
);
1044 aarch64_add_pauth_properties(obj
);
1046 #elif defined(CONFIG_HVF)
1047 ARMCPU
*cpu
= ARM_CPU(obj
);
1048 hvf_arm_set_cpu_features_from_host(cpu
);
1049 aarch64_add_pauth_properties(obj
);
1051 g_assert_not_reached();
1055 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
1056 * otherwise, a CPU with as many features enabled as our emulation supports.
1057 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
1058 * this only needs to handle 64 bits.
1060 static void aarch64_max_initfn(Object
*obj
)
1062 ARMCPU
*cpu
= ARM_CPU(obj
);
1066 if (kvm_enabled() || hvf_enabled()) {
1067 /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
1068 aarch64_host_initfn(obj
);
1072 /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
1074 aarch64_a57_initfn(obj
);
1077 * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
1078 * one and try to apply errata workarounds or use impdef features we
1080 * An IMPLEMENTER field of 0 means "reserved for software use";
1081 * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
1082 * to see which features are present";
1083 * the VARIANT, PARTNUM and REVISION fields are all implementation
1084 * defined and we choose to define PARTNUM just in case guest
1085 * code needs to distinguish this QEMU CPU from other software
1086 * implementations, though this shouldn't be needed.
1088 t
= FIELD_DP64(0, MIDR_EL1
, IMPLEMENTER
, 0);
1089 t
= FIELD_DP64(t
, MIDR_EL1
, ARCHITECTURE
, 0xf);
1090 t
= FIELD_DP64(t
, MIDR_EL1
, PARTNUM
, 'Q');
1091 t
= FIELD_DP64(t
, MIDR_EL1
, VARIANT
, 0);
1092 t
= FIELD_DP64(t
, MIDR_EL1
, REVISION
, 0);
1096 * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,LoUIS}
1100 u
= FIELD_DP32(u
, CLIDR_EL1
, LOUIS
, 0);
1101 u
= FIELD_DP32(u
, CLIDR_EL1
, LOUU
, 0);
1104 t
= cpu
->isar
.id_aa64isar0
;
1105 t
= FIELD_DP64(t
, ID_AA64ISAR0
, AES
, 2); /* FEAT_PMULL */
1106 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA1
, 1); /* FEAT_SHA1 */
1107 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA2
, 2); /* FEAT_SHA512 */
1108 t
= FIELD_DP64(t
, ID_AA64ISAR0
, CRC32
, 1);
1109 t
= FIELD_DP64(t
, ID_AA64ISAR0
, ATOMIC
, 2); /* FEAT_LSE */
1110 t
= FIELD_DP64(t
, ID_AA64ISAR0
, RDM
, 1); /* FEAT_RDM */
1111 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SHA3
, 1); /* FEAT_SHA3 */
1112 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM3
, 1); /* FEAT_SM3 */
1113 t
= FIELD_DP64(t
, ID_AA64ISAR0
, SM4
, 1); /* FEAT_SM4 */
1114 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 1); /* FEAT_DotProd */
1115 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 1); /* FEAT_FHM */
1116 t
= FIELD_DP64(t
, ID_AA64ISAR0
, TS
, 2); /* FEAT_FlagM2 */
1117 t
= FIELD_DP64(t
, ID_AA64ISAR0
, TLB
, 2); /* FEAT_TLBIRANGE */
1118 t
= FIELD_DP64(t
, ID_AA64ISAR0
, RNDR
, 1); /* FEAT_RNG */
1119 cpu
->isar
.id_aa64isar0
= t
;
1121 t
= cpu
->isar
.id_aa64isar1
;
1122 t
= FIELD_DP64(t
, ID_AA64ISAR1
, DPB
, 2); /* FEAT_DPB2 */
1123 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 1); /* FEAT_JSCVT */
1124 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 1); /* FEAT_FCMA */
1125 t
= FIELD_DP64(t
, ID_AA64ISAR1
, LRCPC
, 2); /* FEAT_LRCPC2 */
1126 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 1); /* FEAT_FRINTTS */
1127 t
= FIELD_DP64(t
, ID_AA64ISAR1
, SB
, 1); /* FEAT_SB */
1128 t
= FIELD_DP64(t
, ID_AA64ISAR1
, SPECRES
, 1); /* FEAT_SPECRES */
1129 t
= FIELD_DP64(t
, ID_AA64ISAR1
, BF16
, 1); /* FEAT_BF16 */
1130 t
= FIELD_DP64(t
, ID_AA64ISAR1
, DGH
, 1); /* FEAT_DGH */
1131 t
= FIELD_DP64(t
, ID_AA64ISAR1
, I8MM
, 1); /* FEAT_I8MM */
1132 cpu
->isar
.id_aa64isar1
= t
;
1134 t
= cpu
->isar
.id_aa64pfr0
;
1135 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 1); /* FEAT_FP16 */
1136 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 1); /* FEAT_FP16 */
1137 t
= FIELD_DP64(t
, ID_AA64PFR0
, RAS
, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
1138 t
= FIELD_DP64(t
, ID_AA64PFR0
, SVE
, 1);
1139 t
= FIELD_DP64(t
, ID_AA64PFR0
, SEL2
, 1); /* FEAT_SEL2 */
1140 t
= FIELD_DP64(t
, ID_AA64PFR0
, DIT
, 1); /* FEAT_DIT */
1141 t
= FIELD_DP64(t
, ID_AA64PFR0
, CSV2
, 2); /* FEAT_CSV2_2 */
1142 t
= FIELD_DP64(t
, ID_AA64PFR0
, CSV3
, 1); /* FEAT_CSV3 */
1143 cpu
->isar
.id_aa64pfr0
= t
;
1145 t
= cpu
->isar
.id_aa64pfr1
;
1146 t
= FIELD_DP64(t
, ID_AA64PFR1
, BT
, 1); /* FEAT_BTI */
1147 t
= FIELD_DP64(t
, ID_AA64PFR1
, SSBS
, 2); /* FEAT_SSBS2 */
1149 * Begin with full support for MTE. This will be downgraded to MTE=0
1150 * during realize if the board provides no tag memory, much like
1151 * we do for EL2 with the virtualization=on property.
1153 t
= FIELD_DP64(t
, ID_AA64PFR1
, MTE
, 3); /* FEAT_MTE3 */
1154 t
= FIELD_DP64(t
, ID_AA64PFR1
, RAS_FRAC
, 0); /* FEAT_RASv1p1 + FEAT_DoubleFault */
1155 t
= FIELD_DP64(t
, ID_AA64PFR1
, SME
, 1); /* FEAT_SME */
1156 t
= FIELD_DP64(t
, ID_AA64PFR1
, CSV2_FRAC
, 0); /* FEAT_CSV2_2 */
1157 cpu
->isar
.id_aa64pfr1
= t
;
1159 t
= cpu
->isar
.id_aa64mmfr0
;
1160 t
= FIELD_DP64(t
, ID_AA64MMFR0
, PARANGE
, 6); /* FEAT_LPA: 52 bits */
1161 t
= FIELD_DP64(t
, ID_AA64MMFR0
, TGRAN16
, 1); /* 16k pages supported */
1162 t
= FIELD_DP64(t
, ID_AA64MMFR0
, TGRAN16_2
, 2); /* 16k stage2 supported */
1163 t
= FIELD_DP64(t
, ID_AA64MMFR0
, TGRAN64_2
, 2); /* 64k stage2 supported */
1164 t
= FIELD_DP64(t
, ID_AA64MMFR0
, TGRAN4_2
, 2); /* 4k stage2 supported */
1165 cpu
->isar
.id_aa64mmfr0
= t
;
1167 t
= cpu
->isar
.id_aa64mmfr1
;
1168 t
= FIELD_DP64(t
, ID_AA64MMFR1
, VMIDBITS
, 2); /* FEAT_VMID16 */
1169 t
= FIELD_DP64(t
, ID_AA64MMFR1
, VH
, 1); /* FEAT_VHE */
1170 t
= FIELD_DP64(t
, ID_AA64MMFR1
, HPDS
, 1); /* FEAT_HPDS */
1171 t
= FIELD_DP64(t
, ID_AA64MMFR1
, LO
, 1); /* FEAT_LOR */
1172 t
= FIELD_DP64(t
, ID_AA64MMFR1
, PAN
, 2); /* FEAT_PAN2 */
1173 t
= FIELD_DP64(t
, ID_AA64MMFR1
, XNX
, 1); /* FEAT_XNX */
1174 t
= FIELD_DP64(t
, ID_AA64MMFR1
, ETS
, 1); /* FEAT_ETS */
1175 t
= FIELD_DP64(t
, ID_AA64MMFR1
, HCX
, 1); /* FEAT_HCX */
1176 cpu
->isar
.id_aa64mmfr1
= t
;
1178 t
= cpu
->isar
.id_aa64mmfr2
;
1179 t
= FIELD_DP64(t
, ID_AA64MMFR2
, CNP
, 1); /* FEAT_TTCNP */
1180 t
= FIELD_DP64(t
, ID_AA64MMFR2
, UAO
, 1); /* FEAT_UAO */
1181 t
= FIELD_DP64(t
, ID_AA64MMFR2
, IESB
, 1); /* FEAT_IESB */
1182 t
= FIELD_DP64(t
, ID_AA64MMFR2
, VARANGE
, 1); /* FEAT_LVA */
1183 t
= FIELD_DP64(t
, ID_AA64MMFR2
, ST
, 1); /* FEAT_TTST */
1184 t
= FIELD_DP64(t
, ID_AA64MMFR2
, IDS
, 1); /* FEAT_IDST */
1185 t
= FIELD_DP64(t
, ID_AA64MMFR2
, FWB
, 1); /* FEAT_S2FWB */
1186 t
= FIELD_DP64(t
, ID_AA64MMFR2
, TTL
, 1); /* FEAT_TTL */
1187 t
= FIELD_DP64(t
, ID_AA64MMFR2
, BBM
, 2); /* FEAT_BBM at level 2 */
1188 cpu
->isar
.id_aa64mmfr2
= t
;
1190 t
= cpu
->isar
.id_aa64zfr0
;
1191 t
= FIELD_DP64(t
, ID_AA64ZFR0
, SVEVER
, 1);
1192 t
= FIELD_DP64(t
, ID_AA64ZFR0
, AES
, 2); /* FEAT_SVE_PMULL128 */
1193 t
= FIELD_DP64(t
, ID_AA64ZFR0
, BITPERM
, 1); /* FEAT_SVE_BitPerm */
1194 t
= FIELD_DP64(t
, ID_AA64ZFR0
, BFLOAT16
, 1); /* FEAT_BF16 */
1195 t
= FIELD_DP64(t
, ID_AA64ZFR0
, SHA3
, 1); /* FEAT_SVE_SHA3 */
1196 t
= FIELD_DP64(t
, ID_AA64ZFR0
, SM4
, 1); /* FEAT_SVE_SM4 */
1197 t
= FIELD_DP64(t
, ID_AA64ZFR0
, I8MM
, 1); /* FEAT_I8MM */
1198 t
= FIELD_DP64(t
, ID_AA64ZFR0
, F32MM
, 1); /* FEAT_F32MM */
1199 t
= FIELD_DP64(t
, ID_AA64ZFR0
, F64MM
, 1); /* FEAT_F64MM */
1200 cpu
->isar
.id_aa64zfr0
= t
;
1202 t
= cpu
->isar
.id_aa64dfr0
;
1203 t
= FIELD_DP64(t
, ID_AA64DFR0
, DEBUGVER
, 9); /* FEAT_Debugv8p4 */
1204 t
= FIELD_DP64(t
, ID_AA64DFR0
, PMUVER
, 6); /* FEAT_PMUv3p5 */
1205 cpu
->isar
.id_aa64dfr0
= t
;
1207 t
= cpu
->isar
.id_aa64smfr0
;
1208 t
= FIELD_DP64(t
, ID_AA64SMFR0
, F32F32
, 1); /* FEAT_SME */
1209 t
= FIELD_DP64(t
, ID_AA64SMFR0
, B16F32
, 1); /* FEAT_SME */
1210 t
= FIELD_DP64(t
, ID_AA64SMFR0
, F16F32
, 1); /* FEAT_SME */
1211 t
= FIELD_DP64(t
, ID_AA64SMFR0
, I8I32
, 0xf); /* FEAT_SME */
1212 t
= FIELD_DP64(t
, ID_AA64SMFR0
, F64F64
, 1); /* FEAT_SME_F64F64 */
1213 t
= FIELD_DP64(t
, ID_AA64SMFR0
, I16I64
, 0xf); /* FEAT_SME_I16I64 */
1214 t
= FIELD_DP64(t
, ID_AA64SMFR0
, FA64
, 1); /* FEAT_SME_FA64 */
1215 cpu
->isar
.id_aa64smfr0
= t
;
1217 /* Replicate the same data to the 32-bit id registers. */
1218 aa32_max_features(cpu
);
1220 #ifdef CONFIG_USER_ONLY
1222 * For usermode -cpu max we can use a larger and more efficient DCZ
1223 * blocksize since we don't have to follow what the hardware does.
1225 cpu
->ctr
= 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
1226 cpu
->dcz_blocksize
= 7; /* 512 bytes */
1229 cpu
->sve_vq
.supported
= MAKE_64BIT_MASK(0, ARM_MAX_VQ
);
1230 cpu
->sme_vq
.supported
= SVE_VQ_POW2_MAP
;
1232 aarch64_add_pauth_properties(obj
);
1233 aarch64_add_sve_properties(obj
);
1234 aarch64_add_sme_properties(obj
);
1235 object_property_add(obj
, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq
,
1236 cpu_max_set_sve_max_vq
, NULL
, NULL
);
1237 qdev_property_add_static(DEVICE(obj
), &arm_cpu_lpa2_property
);
1240 static const ARMCPUInfo aarch64_cpus
[] = {
1241 { .name
= "cortex-a35", .initfn
= aarch64_a35_initfn
},
1242 { .name
= "cortex-a57", .initfn
= aarch64_a57_initfn
},
1243 { .name
= "cortex-a53", .initfn
= aarch64_a53_initfn
},
1244 { .name
= "cortex-a72", .initfn
= aarch64_a72_initfn
},
1245 { .name
= "cortex-a76", .initfn
= aarch64_a76_initfn
},
1246 { .name
= "a64fx", .initfn
= aarch64_a64fx_initfn
},
1247 { .name
= "neoverse-n1", .initfn
= aarch64_neoverse_n1_initfn
},
1248 { .name
= "max", .initfn
= aarch64_max_initfn
},
1249 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1250 { .name
= "host", .initfn
= aarch64_host_initfn
},
1254 static bool aarch64_cpu_get_aarch64(Object
*obj
, Error
**errp
)
1256 ARMCPU
*cpu
= ARM_CPU(obj
);
1258 return arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
1261 static void aarch64_cpu_set_aarch64(Object
*obj
, bool value
, Error
**errp
)
1263 ARMCPU
*cpu
= ARM_CPU(obj
);
1265 /* At this time, this property is only allowed if KVM is enabled. This
1266 * restriction allows us to avoid fixing up functionality that assumes a
1267 * uniform execution state like do_interrupt.
1269 if (value
== false) {
1270 if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
1271 error_setg(errp
, "'aarch64' feature cannot be disabled "
1272 "unless KVM is enabled and 32-bit EL1 "
1276 unset_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
1278 set_feature(&cpu
->env
, ARM_FEATURE_AARCH64
);
1282 static void aarch64_cpu_finalizefn(Object
*obj
)
1286 static gchar
*aarch64_gdb_arch_name(CPUState
*cs
)
1288 return g_strdup("aarch64");
1291 static void aarch64_cpu_class_init(ObjectClass
*oc
, void *data
)
1293 CPUClass
*cc
= CPU_CLASS(oc
);
1295 cc
->gdb_read_register
= aarch64_cpu_gdb_read_register
;
1296 cc
->gdb_write_register
= aarch64_cpu_gdb_write_register
;
1297 cc
->gdb_num_core_regs
= 34;
1298 cc
->gdb_core_xml_file
= "aarch64-core.xml";
1299 cc
->gdb_arch_name
= aarch64_gdb_arch_name
;
1301 object_class_property_add_bool(oc
, "aarch64", aarch64_cpu_get_aarch64
,
1302 aarch64_cpu_set_aarch64
);
1303 object_class_property_set_description(oc
, "aarch64",
1304 "Set on/off to enable/disable aarch64 "
1305 "execution state ");
1308 static void aarch64_cpu_instance_init(Object
*obj
)
1310 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
1312 acc
->info
->initfn(obj
);
1313 arm_cpu_post_init(obj
);
1316 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
1318 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
1323 void aarch64_cpu_register(const ARMCPUInfo
*info
)
1325 TypeInfo type_info
= {
1326 .parent
= TYPE_AARCH64_CPU
,
1327 .instance_size
= sizeof(ARMCPU
),
1328 .instance_init
= aarch64_cpu_instance_init
,
1329 .class_size
= sizeof(ARMCPUClass
),
1330 .class_init
= info
->class_init
?: cpu_register_class_init
,
1331 .class_data
= (void *)info
,
1334 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
1335 type_register(&type_info
);
1336 g_free((void *)type_info
.name
);
1339 static const TypeInfo aarch64_cpu_type_info
= {
1340 .name
= TYPE_AARCH64_CPU
,
1341 .parent
= TYPE_ARM_CPU
,
1342 .instance_size
= sizeof(ARMCPU
),
1343 .instance_finalize
= aarch64_cpu_finalizefn
,
1345 .class_size
= sizeof(AArch64CPUClass
),
1346 .class_init
= aarch64_cpu_class_init
,
1349 static void aarch64_cpu_register_types(void)
1353 type_register_static(&aarch64_cpu_type_info
);
1355 for (i
= 0; i
< ARRAY_SIZE(aarch64_cpus
); ++i
) {
1356 aarch64_cpu_register(&aarch64_cpus
[i
]);
1360 type_init(aarch64_cpu_register_types
)