spapr: Abstract CPU core device and type specific core devices
[qemu.git] / hw / net / vmware_utils.h
blobc0dbb2ff41106a2b089c43efca330753f737605b
1 /*
2 * QEMU VMWARE paravirtual devices - auxiliary code
4 * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
6 * Developed by Daynix Computing LTD (http://www.daynix.com)
8 * Authors:
9 * Dmitry Fleytman <dmitry@daynix.com>
10 * Yan Vugenfirer <yan@daynix.com>
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
17 #ifndef VMWARE_UTILS_H
18 #define VMWARE_UTILS_H
20 #include "qemu/range.h"
21 #include "vmxnet_debug.h"
24 * Shared memory access functions with byte swap support
25 * Each function contains printout for reverse-engineering needs
28 static inline void
29 vmw_shmem_read(hwaddr addr, void *buf, int len)
31 VMW_SHPRN("SHMEM r: %" PRIx64 ", len: %d to %p", addr, len, buf);
32 cpu_physical_memory_read(addr, buf, len);
35 static inline void
36 vmw_shmem_write(hwaddr addr, void *buf, int len)
38 VMW_SHPRN("SHMEM w: %" PRIx64 ", len: %d to %p", addr, len, buf);
39 cpu_physical_memory_write(addr, buf, len);
42 static inline void
43 vmw_shmem_rw(hwaddr addr, void *buf, int len, int is_write)
45 VMW_SHPRN("SHMEM r/w: %" PRIx64 ", len: %d (to %p), is write: %d",
46 addr, len, buf, is_write);
48 cpu_physical_memory_rw(addr, buf, len, is_write);
51 static inline void
52 vmw_shmem_set(hwaddr addr, uint8_t val, int len)
54 int i;
55 VMW_SHPRN("SHMEM set: %" PRIx64 ", len: %d (value 0x%X)", addr, len, val);
57 for (i = 0; i < len; i++) {
58 cpu_physical_memory_write(addr + i, &val, 1);
62 static inline uint32_t
63 vmw_shmem_ld8(hwaddr addr)
65 uint8_t res = ldub_phys(&address_space_memory, addr);
66 VMW_SHPRN("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res);
67 return res;
70 static inline void
71 vmw_shmem_st8(hwaddr addr, uint8_t value)
73 VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value);
74 stb_phys(&address_space_memory, addr, value);
77 static inline uint32_t
78 vmw_shmem_ld16(hwaddr addr)
80 uint16_t res = lduw_le_phys(&address_space_memory, addr);
81 VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res);
82 return res;
85 static inline void
86 vmw_shmem_st16(hwaddr addr, uint16_t value)
88 VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value);
89 stw_le_phys(&address_space_memory, addr, value);
92 static inline uint32_t
93 vmw_shmem_ld32(hwaddr addr)
95 uint32_t res = ldl_le_phys(&address_space_memory, addr);
96 VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res);
97 return res;
100 static inline void
101 vmw_shmem_st32(hwaddr addr, uint32_t value)
103 VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value);
104 stl_le_phys(&address_space_memory, addr, value);
107 static inline uint64_t
108 vmw_shmem_ld64(hwaddr addr)
110 uint64_t res = ldq_le_phys(&address_space_memory, addr);
111 VMW_SHPRN("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res);
112 return res;
115 static inline void
116 vmw_shmem_st64(hwaddr addr, uint64_t value)
118 VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value);
119 stq_le_phys(&address_space_memory, addr, value);
122 /* Macros for simplification of operations on array-style registers */
125 * Whether <addr> lies inside of array-style register defined by <base>,
126 * number of elements (<cnt>) and element size (<regsize>)
129 #define VMW_IS_MULTIREG_ADDR(addr, base, cnt, regsize) \
130 range_covers_byte(base, cnt * regsize, addr)
133 * Returns index of given register (<addr>) in array-style register defined by
134 * <base> and element size (<regsize>)
137 #define VMW_MULTIREG_IDX_BY_ADDR(addr, base, regsize) \
138 (((addr) - (base)) / (regsize))
140 #endif