target-mips/exec.h

   1 #if !defined(__QEMU_MIPS_EXEC_H__)
   2 #define __QEMU_MIPS_EXEC_H__
   3
   4 //#define DEBUG_OP
   5
   6 #include "config.h"
   7 #include "mips-defs.h"
   8 #include "dyngen-exec.h"
   9 #include "cpu-defs.h"
  10
  11 register struct CPUMIPSState *env asm(AREG0);
  12
  13 #include "cpu.h"
  14 #include "exec-all.h"
  15
  16 #if !defined(CONFIG_USER_ONLY)
  17 #include "softmmu_exec.h"
  18 #endif /* !defined(CONFIG_USER_ONLY) */
  19
  20 void dump_fpu(CPUState *env);
  21 void fpu_dump_state(CPUState *env, FILE *f,
  22                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
  23                     int flags);
  24
  25 void cpu_mips_clock_init (CPUState *env);
  26 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
  27
  28 static inline int cpu_has_work(CPUState *env)
  29 {
  30     return (env->interrupt_request &
  31             (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER));
  32 }
  33
  34
  35 static inline int cpu_halted(CPUState *env)
  36 {
  37     if (!env->halted)
  38         return 0;
  39     if (cpu_has_work(env)) {
  40         env->halted = 0;
  41         return 0;
  42     }
  43     return EXCP_HALTED;
  44 }
  45
  46 static inline void compute_hflags(CPUState *env)
  47 {
  48     env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
  49                      MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
  50                      MIPS_HFLAG_UX);
  51     if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
  52         !(env->CP0_Status & (1 << CP0St_ERL)) &&
  53         !(env->hflags & MIPS_HFLAG_DM)) {
  54         env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
  55     }
  56 #if defined(TARGET_MIPS64)
  57     if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
  58         (env->CP0_Status & (1 << CP0St_PX)) ||
  59         (env->CP0_Status & (1 << CP0St_UX)))
  60         env->hflags |= MIPS_HFLAG_64;
  61     if (env->CP0_Status & (1 << CP0St_UX))
  62         env->hflags |= MIPS_HFLAG_UX;
  63 #endif
  64     if ((env->CP0_Status & (1 << CP0St_CU0)) ||
  65         !(env->hflags & MIPS_HFLAG_KSU))
  66         env->hflags |= MIPS_HFLAG_CP0;
  67     if (env->CP0_Status & (1 << CP0St_CU1))
  68         env->hflags |= MIPS_HFLAG_FPU;
  69     if (env->CP0_Status & (1 << CP0St_FR))
  70         env->hflags |= MIPS_HFLAG_F64;
  71     if (env->insn_flags & ISA_MIPS32R2) {
  72         if (env->active_fpu.fcr0 & (1 << FCR0_F64))
  73             env->hflags |= MIPS_HFLAG_COP1X;
  74     } else if (env->insn_flags & ISA_MIPS32) {
  75         if (env->hflags & MIPS_HFLAG_64)
  76             env->hflags |= MIPS_HFLAG_COP1X;
  77     } else if (env->insn_flags & ISA_MIPS4) {
  78         /* All supported MIPS IV CPUs use the XX (CU3) to enable
  79            and disable the MIPS IV extensions to the MIPS III ISA.
  80            Some other MIPS IV CPUs ignore the bit, so the check here
  81            would be too restrictive for them.  */
  82         if (env->CP0_Status & (1 << CP0St_CU3))
  83             env->hflags |= MIPS_HFLAG_COP1X;
  84     }
  85 }
  86
  87 #endif /* !defined(__QEMU_MIPS_EXEC_H__) */