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aspeed: Remove unused SoC definitions
[qemu.git] / hw / arm / aspeed_soc.c
blob3aa73d2438eff01053fa9e0f4fadf8b61d04d5a2
1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 * Jeremy Kerr <jk@ozlabs.org>
6 *
7 * Copyright 2016 IBM Corp.
8 *
9 * This code is licensed under the GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "cpu.h"
16 #include "exec/address-spaces.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19 #include "hw/char/serial.h"
20 #include "qemu/log.h"
21 #include "qemu/module.h"
22 #include "qemu/error-report.h"
23 #include "hw/i2c/aspeed_i2c.h"
24 #include "net/net.h"
25 #include "sysemu/sysemu.h"
26
27 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
28
29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
30 [ASPEED_IOMEM] = 0x1E600000,
31 [ASPEED_FMC] = 0x1E620000,
32 [ASPEED_SPI1] = 0x1E630000,
33 [ASPEED_VIC] = 0x1E6C0000,
34 [ASPEED_SDMC] = 0x1E6E0000,
35 [ASPEED_SCU] = 0x1E6E2000,
36 [ASPEED_XDMA] = 0x1E6E7000,
37 [ASPEED_ADC] = 0x1E6E9000,
38 [ASPEED_SRAM] = 0x1E720000,
39 [ASPEED_GPIO] = 0x1E780000,
40 [ASPEED_RTC] = 0x1E781000,
41 [ASPEED_TIMER1] = 0x1E782000,
42 [ASPEED_WDT] = 0x1E785000,
43 [ASPEED_PWM] = 0x1E786000,
44 [ASPEED_LPC] = 0x1E789000,
45 [ASPEED_IBT] = 0x1E789140,
46 [ASPEED_I2C] = 0x1E78A000,
47 [ASPEED_ETH1] = 0x1E660000,
48 [ASPEED_ETH2] = 0x1E680000,
49 [ASPEED_UART1] = 0x1E783000,
50 [ASPEED_UART5] = 0x1E784000,
51 [ASPEED_VUART] = 0x1E787000,
52 [ASPEED_SDRAM] = 0x40000000,
53 };
54
55 static const hwaddr aspeed_soc_ast2500_memmap[] = {
56 [ASPEED_IOMEM] = 0x1E600000,
57 [ASPEED_FMC] = 0x1E620000,
58 [ASPEED_SPI1] = 0x1E630000,
59 [ASPEED_SPI2] = 0x1E631000,
60 [ASPEED_VIC] = 0x1E6C0000,
61 [ASPEED_SDMC] = 0x1E6E0000,
62 [ASPEED_SCU] = 0x1E6E2000,
63 [ASPEED_XDMA] = 0x1E6E7000,
64 [ASPEED_ADC] = 0x1E6E9000,
65 [ASPEED_SRAM] = 0x1E720000,
66 [ASPEED_GPIO] = 0x1E780000,
67 [ASPEED_RTC] = 0x1E781000,
68 [ASPEED_TIMER1] = 0x1E782000,
69 [ASPEED_WDT] = 0x1E785000,
70 [ASPEED_PWM] = 0x1E786000,
71 [ASPEED_LPC] = 0x1E789000,
72 [ASPEED_IBT] = 0x1E789140,
73 [ASPEED_I2C] = 0x1E78A000,
74 [ASPEED_ETH1] = 0x1E660000,
75 [ASPEED_ETH2] = 0x1E680000,
76 [ASPEED_UART1] = 0x1E783000,
77 [ASPEED_UART5] = 0x1E784000,
78 [ASPEED_VUART] = 0x1E787000,
79 [ASPEED_SDRAM] = 0x80000000,
80 };
81
82 static const int aspeed_soc_ast2400_irqmap[] = {
83 [ASPEED_UART1] = 9,
84 [ASPEED_UART2] = 32,
85 [ASPEED_UART3] = 33,
86 [ASPEED_UART4] = 34,
87 [ASPEED_UART5] = 10,
88 [ASPEED_VUART] = 8,
89 [ASPEED_FMC] = 19,
90 [ASPEED_SDMC] = 0,
91 [ASPEED_SCU] = 21,
92 [ASPEED_ADC] = 31,
93 [ASPEED_GPIO] = 20,
94 [ASPEED_RTC] = 22,
95 [ASPEED_TIMER1] = 16,
96 [ASPEED_TIMER2] = 17,
97 [ASPEED_TIMER3] = 18,
98 [ASPEED_TIMER4] = 35,
99 [ASPEED_TIMER5] = 36,
100 [ASPEED_TIMER6] = 37,
101 [ASPEED_TIMER7] = 38,
102 [ASPEED_TIMER8] = 39,
103 [ASPEED_WDT] = 27,
104 [ASPEED_PWM] = 28,
105 [ASPEED_LPC] = 8,
106 [ASPEED_IBT] = 8, /* LPC */
107 [ASPEED_I2C] = 12,
108 [ASPEED_ETH1] = 2,
109 [ASPEED_ETH2] = 3,
110 [ASPEED_XDMA] = 6,
111 };
112
113 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
114
115 static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" };
116 static const char *aspeed_soc_ast2500_typenames[] = {
117 "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" };
118
119 static const AspeedSoCInfo aspeed_socs[] = {
120 {
121 .name = "ast2400-a1",
122 .cpu_type = ARM_CPU_TYPE_NAME("arm926"),
123 .silicon_rev = AST2400_A1_SILICON_REV,
124 .sram_size = 0x8000,
125 .spis_num = 1,
126 .fmc_typename = "aspeed.smc.fmc",
127 .spi_typename = aspeed_soc_ast2400_typenames,
128 .gpio_typename = "aspeed.gpio-ast2400",
129 .wdts_num = 2,
130 .irqmap = aspeed_soc_ast2400_irqmap,
131 .memmap = aspeed_soc_ast2400_memmap,
132 .num_cpus = 1,
133 }, {
134 .name = "ast2500-a1",
135 .cpu_type = ARM_CPU_TYPE_NAME("arm1176"),
136 .silicon_rev = AST2500_A1_SILICON_REV,
137 .sram_size = 0x9000,
138 .spis_num = 2,
139 .fmc_typename = "aspeed.smc.ast2500-fmc",
140 .spi_typename = aspeed_soc_ast2500_typenames,
141 .gpio_typename = "aspeed.gpio-ast2500",
142 .wdts_num = 3,
143 .irqmap = aspeed_soc_ast2500_irqmap,
144 .memmap = aspeed_soc_ast2500_memmap,
145 .num_cpus = 1,
146 },
147 };
148
149 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
150 {
151 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
152
153 return qdev_get_gpio_in(DEVICE(&s->vic), sc->info->irqmap[ctrl]);
154 }
155
156 static void aspeed_soc_init(Object *obj)
157 {
158 AspeedSoCState *s = ASPEED_SOC(obj);
159 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
160 int i;
161
162 for (i = 0; i < sc->info->num_cpus; i++) {
163 object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]),
164 sizeof(s->cpu[i]), sc->info->cpu_type,
165 &error_abort, NULL);
166 }
167
168 sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu),
169 TYPE_ASPEED_SCU);
170 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
171 sc->info->silicon_rev);
172 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
173 "hw-strap1", &error_abort);
174 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
175 "hw-strap2", &error_abort);
176 object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
177 "hw-prot-key", &error_abort);
178
179 sysbus_init_child_obj(obj, "vic", OBJECT(&s->vic), sizeof(s->vic),
180 TYPE_ASPEED_VIC);
181
182 sysbus_init_child_obj(obj, "rtc", OBJECT(&s->rtc), sizeof(s->rtc),
183 TYPE_ASPEED_RTC);
184
185 sysbus_init_child_obj(obj, "timerctrl", OBJECT(&s->timerctrl),
186 sizeof(s->timerctrl), TYPE_ASPEED_TIMER);
187 object_property_add_const_link(OBJECT(&s->timerctrl), "scu",
188 OBJECT(&s->scu), &error_abort);
189
190 sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c),
191 TYPE_ASPEED_I2C);
192
193 sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc),
194 sc->info->fmc_typename);
195 object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs",
196 &error_abort);
197
198 for (i = 0; i < sc->info->spis_num; i++) {
199 sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]),
200 sizeof(s->spi[i]), sc->info->spi_typename[i]);
201 }
202
203 sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc),
204 TYPE_ASPEED_SDMC);
205 qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
206 sc->info->silicon_rev);
207 object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
208 "ram-size", &error_abort);
209 object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
210 "max-ram-size", &error_abort);
211
212 for (i = 0; i < sc->info->wdts_num; i++) {
213 sysbus_init_child_obj(obj, "wdt[*]", OBJECT(&s->wdt[i]),
214 sizeof(s->wdt[i]), TYPE_ASPEED_WDT);
215 qdev_prop_set_uint32(DEVICE(&s->wdt[i]), "silicon-rev",
216 sc->info->silicon_rev);
217 object_property_add_const_link(OBJECT(&s->wdt[i]), "scu",
218 OBJECT(&s->scu), &error_abort);
219 }
220
221 for (i = 0; i < ASPEED_MACS_NUM; i++) {
222 sysbus_init_child_obj(obj, "ftgmac100[*]", OBJECT(&s->ftgmac100[i]),
223 sizeof(s->ftgmac100[i]), TYPE_FTGMAC100);
224 }
225
226 sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma),
227 TYPE_ASPEED_XDMA);
228
229 sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio),
230 sc->info->gpio_typename);
231 }
232
233 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
234 {
235 int i;
236 AspeedSoCState *s = ASPEED_SOC(dev);
237 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
238 Error *err = NULL, *local_err = NULL;
239
240 /* IO space */
241 create_unimplemented_device("aspeed_soc.io", sc->info->memmap[ASPEED_IOMEM],
242 ASPEED_SOC_IOMEM_SIZE);
243
244 if (s->num_cpus > sc->info->num_cpus) {
245 warn_report("%s: invalid number of CPUs %d, using default %d",
246 sc->info->name, s->num_cpus, sc->info->num_cpus);
247 s->num_cpus = sc->info->num_cpus;
248 }
249
250 /* CPU */
251 for (i = 0; i < s->num_cpus; i++) {
252 object_property_set_bool(OBJECT(&s->cpu[i]), true, "realized", &err);
253 if (err) {
254 error_propagate(errp, err);
255 return;
256 }
257 }
258
259 /* SRAM */
260 memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
261 sc->info->sram_size, &err);
262 if (err) {
263 error_propagate(errp, err);
264 return;
265 }
266 memory_region_add_subregion(get_system_memory(),
267 sc->info->memmap[ASPEED_SRAM], &s->sram);
268
269 /* SCU */
270 object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
271 if (err) {
272 error_propagate(errp, err);
273 return;
274 }
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->info->memmap[ASPEED_SCU]);
276
277 /* VIC */
278 object_property_set_bool(OBJECT(&s->vic), true, "realized", &err);
279 if (err) {
280 error_propagate(errp, err);
281 return;
282 }
283 sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->info->memmap[ASPEED_VIC]);
284 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
285 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
286 sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
287 qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
288
289 /* RTC */
290 object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
291 if (err) {
292 error_propagate(errp, err);
293 return;
294 }
295 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->info->memmap[ASPEED_RTC]);
296 sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
297 aspeed_soc_get_irq(s, ASPEED_RTC));
298
299 /* Timer */
300 object_property_set_bool(OBJECT(&s->timerctrl), true, "realized", &err);
301 if (err) {
302 error_propagate(errp, err);
303 return;
304 }
305 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
306 sc->info->memmap[ASPEED_TIMER1]);
307 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
308 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
309 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
310 }
311
312 /* UART - attach an 8250 to the IO space as our UART5 */
313 if (serial_hd(0)) {
314 qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
315 serial_mm_init(get_system_memory(), sc->info->memmap[ASPEED_UART5], 2,
316 uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
317 }
318
319 /* I2C */
320 object_property_set_bool(OBJECT(&s->i2c), true, "realized", &err);
321 if (err) {
322 error_propagate(errp, err);
323 return;
324 }
325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->info->memmap[ASPEED_I2C]);
326 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
327 aspeed_soc_get_irq(s, ASPEED_I2C));
328
329 /* FMC, The number of CS is set at the board level */
330 object_property_set_int(OBJECT(&s->fmc), sc->info->memmap[ASPEED_SDRAM],
331 "sdram-base", &err);
332 if (err) {
333 error_propagate(errp, err);
334 return;
335 }
336 object_property_set_bool(OBJECT(&s->fmc), true, "realized", &err);
337 if (err) {
338 error_propagate(errp, err);
339 return;
340 }
341 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->info->memmap[ASPEED_FMC]);
342 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
343 s->fmc.ctrl->flash_window_base);
344 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
345 aspeed_soc_get_irq(s, ASPEED_FMC));
346
347 /* SPI */
348 for (i = 0; i < sc->info->spis_num; i++) {
349 object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
350 object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
351 &local_err);
352 error_propagate(&err, local_err);
353 if (err) {
354 error_propagate(errp, err);
355 return;
356 }
357 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
358 sc->info->memmap[ASPEED_SPI1 + i]);
359 sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
360 s->spi[i].ctrl->flash_window_base);
361 }
362
363 /* SDMC - SDRAM Memory Controller */
364 object_property_set_bool(OBJECT(&s->sdmc), true, "realized", &err);
365 if (err) {
366 error_propagate(errp, err);
367 return;
368 }
369 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->info->memmap[ASPEED_SDMC]);
370
371 /* Watch dog */
372 for (i = 0; i < sc->info->wdts_num; i++) {
373 object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized", &err);
374 if (err) {
375 error_propagate(errp, err);
376 return;
377 }
378 sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
379 sc->info->memmap[ASPEED_WDT] + i * 0x20);
380 }
381
382 /* Net */
383 for (i = 0; i < nb_nics; i++) {
384 qdev_set_nic_properties(DEVICE(&s->ftgmac100[i]), &nd_table[i]);
385 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
386 &err);
387 object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "realized",
388 &local_err);
389 error_propagate(&err, local_err);
390 if (err) {
391 error_propagate(errp, err);
392 return;
393 }
394 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
395 sc->info->memmap[ASPEED_ETH1 + i]);
396 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
397 aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
398 }
399
400 /* XDMA */
401 object_property_set_bool(OBJECT(&s->xdma), true, "realized", &err);
402 if (err) {
403 error_propagate(errp, err);
404 return;
405 }
406 sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
407 sc->info->memmap[ASPEED_XDMA]);
408 sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
409 aspeed_soc_get_irq(s, ASPEED_XDMA));
410
411 /* GPIO */
412 object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
413 if (err) {
414 error_propagate(errp, err);
415 return;
416 }
417 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]);
418 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
419 aspeed_soc_get_irq(s, ASPEED_GPIO));
420 }
421 static Property aspeed_soc_properties[] = {
422 DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
423 DEFINE_PROP_END_OF_LIST(),
424 };
425
426 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
427 {
428 DeviceClass *dc = DEVICE_CLASS(oc);
429 AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
430
431 sc->info = (AspeedSoCInfo *) data;
432 dc->realize = aspeed_soc_realize;
433 /* Reason: Uses serial_hds and nd_table in realize() directly */
434 dc->user_creatable = false;
435 dc->props = aspeed_soc_properties;
436 }
437
438 static const TypeInfo aspeed_soc_type_info = {
439 .name = TYPE_ASPEED_SOC,
440 .parent = TYPE_DEVICE,
441 .instance_init = aspeed_soc_init,
442 .instance_size = sizeof(AspeedSoCState),
443 .class_size = sizeof(AspeedSoCClass),
444 .abstract = true,
445 };
446
447 static void aspeed_soc_register_types(void)
448 {
449 int i;
450
451 type_register_static(&aspeed_soc_type_info);
452 for (i = 0; i < ARRAY_SIZE(aspeed_socs); ++i) {
453 TypeInfo ti = {
454 .name = aspeed_socs[i].name,
455 .parent = TYPE_ASPEED_SOC,
456 .class_init = aspeed_soc_class_init,
457 .class_data = (void *) &aspeed_socs[i],
458 };
459 type_register(&ti);
460 }
461 }
462
463 type_init(aspeed_soc_register_types)
QEmu