2 * QEMU ESP/NCR53C9x emulation
4 * Copyright (c) 2005-2006 Fabrice Bellard
5 * Copyright (c) 2012 Herve Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/pci/pci.h"
27 #include "hw/nvram/eeprom93xx.h"
28 #include "hw/scsi/esp.h"
32 #define TYPE_AM53C974_DEVICE "am53c974"
34 #define PCI_ESP(obj) \
35 OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
46 #define DMA_CMD_MASK 0x03
47 #define DMA_CMD_DIAG 0x04
48 #define DMA_CMD_MDL 0x10
49 #define DMA_CMD_INTE_P 0x20
50 #define DMA_CMD_INTE_D 0x40
51 #define DMA_CMD_DIR 0x80
53 #define DMA_STAT_PWDN 0x01
54 #define DMA_STAT_ERROR 0x02
55 #define DMA_STAT_ABORT 0x04
56 #define DMA_STAT_DONE 0x08
57 #define DMA_STAT_SCSIINT 0x10
58 #define DMA_STAT_BCMBLT 0x20
60 #define SBAC_STATUS 0x1000
62 typedef struct PCIESPState
{
70 static void esp_pci_handle_idle(PCIESPState
*pci
, uint32_t val
)
72 trace_esp_pci_dma_idle(val
);
73 esp_dma_enable(&pci
->esp
, 0, 0);
76 static void esp_pci_handle_blast(PCIESPState
*pci
, uint32_t val
)
78 trace_esp_pci_dma_blast(val
);
79 qemu_log_mask(LOG_UNIMP
, "am53c974: cmd BLAST not implemented\n");
82 static void esp_pci_handle_abort(PCIESPState
*pci
, uint32_t val
)
84 trace_esp_pci_dma_abort(val
);
85 if (pci
->esp
.current_req
) {
86 scsi_req_cancel(pci
->esp
.current_req
);
90 static void esp_pci_handle_start(PCIESPState
*pci
, uint32_t val
)
92 trace_esp_pci_dma_start(val
);
94 pci
->dma_regs
[DMA_WBC
] = pci
->dma_regs
[DMA_STC
];
95 pci
->dma_regs
[DMA_WAC
] = pci
->dma_regs
[DMA_SPA
];
96 pci
->dma_regs
[DMA_WMAC
] = pci
->dma_regs
[DMA_SMDLA
];
98 pci
->dma_regs
[DMA_STAT
] &= ~(DMA_STAT_BCMBLT
| DMA_STAT_SCSIINT
99 | DMA_STAT_DONE
| DMA_STAT_ABORT
100 | DMA_STAT_ERROR
| DMA_STAT_PWDN
);
102 esp_dma_enable(&pci
->esp
, 0, 1);
105 static void esp_pci_dma_write(PCIESPState
*pci
, uint32_t saddr
, uint32_t val
)
107 trace_esp_pci_dma_write(saddr
, pci
->dma_regs
[saddr
], val
);
110 pci
->dma_regs
[saddr
] = val
;
111 switch (val
& DMA_CMD_MASK
) {
113 esp_pci_handle_idle(pci
, val
);
115 case 0x1: /* BLAST */
116 esp_pci_handle_blast(pci
, val
);
118 case 0x2: /* ABORT */
119 esp_pci_handle_abort(pci
, val
);
121 case 0x3: /* START */
122 esp_pci_handle_start(pci
, val
);
124 default: /* can't happen */
131 pci
->dma_regs
[saddr
] = val
;
134 if (!(pci
->sbac
& SBAC_STATUS
)) {
135 /* clear some bits on write */
136 uint32_t mask
= DMA_STAT_ERROR
| DMA_STAT_ABORT
| DMA_STAT_DONE
;
137 pci
->dma_regs
[DMA_STAT
] &= ~(val
& mask
);
141 trace_esp_pci_error_invalid_write_dma(val
, saddr
);
146 static uint32_t esp_pci_dma_read(PCIESPState
*pci
, uint32_t saddr
)
150 val
= pci
->dma_regs
[saddr
];
151 if (saddr
== DMA_STAT
) {
152 if (pci
->esp
.rregs
[ESP_RSTAT
] & STAT_INT
) {
153 val
|= DMA_STAT_SCSIINT
;
155 if (pci
->sbac
& SBAC_STATUS
) {
156 pci
->dma_regs
[DMA_STAT
] &= ~(DMA_STAT_ERROR
| DMA_STAT_ABORT
|
161 trace_esp_pci_dma_read(saddr
, val
);
165 static void esp_pci_io_write(void *opaque
, hwaddr addr
,
166 uint64_t val
, unsigned int size
)
168 PCIESPState
*pci
= opaque
;
170 if (size
< 4 || addr
& 3) {
171 /* need to upgrade request: we only support 4-bytes accesses */
172 uint32_t current
= 0, mask
;
176 current
= pci
->esp
.wregs
[addr
>> 2];
177 } else if (addr
< 0x60) {
178 current
= pci
->dma_regs
[(addr
- 0x40) >> 2];
179 } else if (addr
< 0x74) {
183 shift
= (4 - size
) * 8;
184 mask
= (~(uint32_t)0 << shift
) >> shift
;
186 shift
= ((4 - (addr
& 3)) & 3) * 8;
188 val
|= current
& ~(mask
<< shift
);
195 esp_reg_write(&pci
->esp
, addr
>> 2, val
);
196 } else if (addr
< 0x60) {
198 esp_pci_dma_write(pci
, (addr
- 0x40) >> 2, val
);
199 } else if (addr
== 0x70) {
200 /* DMA SCSI Bus and control */
201 trace_esp_pci_sbac_write(pci
->sbac
, val
);
204 trace_esp_pci_error_invalid_write((int)addr
);
208 static uint64_t esp_pci_io_read(void *opaque
, hwaddr addr
,
211 PCIESPState
*pci
= opaque
;
216 ret
= esp_reg_read(&pci
->esp
, addr
>> 2);
217 } else if (addr
< 0x60) {
219 ret
= esp_pci_dma_read(pci
, (addr
- 0x40) >> 2);
220 } else if (addr
== 0x70) {
221 /* DMA SCSI Bus and control */
222 trace_esp_pci_sbac_read(pci
->sbac
);
226 trace_esp_pci_error_invalid_read((int)addr
);
230 /* give only requested data */
231 ret
>>= (addr
& 3) * 8;
232 ret
&= ~(~(uint64_t)0 << (8 * size
));
237 static void esp_pci_dma_memory_rw(PCIESPState
*pci
, uint8_t *buf
, int len
,
241 DMADirection expected_dir
;
243 if (pci
->dma_regs
[DMA_CMD
] & DMA_CMD_DIR
) {
244 expected_dir
= DMA_DIRECTION_FROM_DEVICE
;
246 expected_dir
= DMA_DIRECTION_TO_DEVICE
;
249 if (dir
!= expected_dir
) {
250 trace_esp_pci_error_invalid_dma_direction();
254 if (pci
->dma_regs
[DMA_STAT
] & DMA_CMD_MDL
) {
255 qemu_log_mask(LOG_UNIMP
, "am53c974: MDL transfer not implemented\n");
258 addr
= pci
->dma_regs
[DMA_SPA
];
259 if (pci
->dma_regs
[DMA_WBC
] < len
) {
260 len
= pci
->dma_regs
[DMA_WBC
];
263 pci_dma_rw(&pci
->dev
, addr
, buf
, len
, dir
);
265 /* update status registers */
266 pci
->dma_regs
[DMA_WBC
] -= len
;
267 pci
->dma_regs
[DMA_WAC
] += len
;
270 static void esp_pci_dma_memory_read(void *opaque
, uint8_t *buf
, int len
)
272 PCIESPState
*pci
= opaque
;
273 esp_pci_dma_memory_rw(pci
, buf
, len
, DMA_DIRECTION_TO_DEVICE
);
276 static void esp_pci_dma_memory_write(void *opaque
, uint8_t *buf
, int len
)
278 PCIESPState
*pci
= opaque
;
279 esp_pci_dma_memory_rw(pci
, buf
, len
, DMA_DIRECTION_FROM_DEVICE
);
282 static const MemoryRegionOps esp_pci_io_ops
= {
283 .read
= esp_pci_io_read
,
284 .write
= esp_pci_io_write
,
285 .endianness
= DEVICE_LITTLE_ENDIAN
,
287 .min_access_size
= 1,
288 .max_access_size
= 4,
292 static void esp_pci_hard_reset(DeviceState
*dev
)
294 PCIESPState
*pci
= PCI_ESP(dev
);
295 esp_hard_reset(&pci
->esp
);
296 pci
->dma_regs
[DMA_CMD
] &= ~(DMA_CMD_DIR
| DMA_CMD_INTE_D
| DMA_CMD_INTE_P
297 | DMA_CMD_MDL
| DMA_CMD_DIAG
| DMA_CMD_MASK
);
298 pci
->dma_regs
[DMA_WBC
] &= ~0xffff;
299 pci
->dma_regs
[DMA_WAC
] = 0xffffffff;
300 pci
->dma_regs
[DMA_STAT
] &= ~(DMA_STAT_BCMBLT
| DMA_STAT_SCSIINT
301 | DMA_STAT_DONE
| DMA_STAT_ABORT
303 pci
->dma_regs
[DMA_WMAC
] = 0xfffffffd;
306 static const VMStateDescription vmstate_esp_pci_scsi
= {
307 .name
= "pciespscsi",
309 .minimum_version_id
= 0,
310 .minimum_version_id_old
= 0,
311 .fields
= (VMStateField
[]) {
312 VMSTATE_PCI_DEVICE(dev
, PCIESPState
),
313 VMSTATE_BUFFER_UNSAFE(dma_regs
, PCIESPState
, 0, 8 * sizeof(uint32_t)),
314 VMSTATE_STRUCT(esp
, PCIESPState
, 0, vmstate_esp
, ESPState
),
315 VMSTATE_END_OF_LIST()
319 static void esp_pci_command_complete(SCSIRequest
*req
, uint32_t status
,
322 ESPState
*s
= req
->hba_private
;
323 PCIESPState
*pci
= container_of(s
, PCIESPState
, esp
);
325 esp_command_complete(req
, status
, resid
);
326 pci
->dma_regs
[DMA_WBC
] = 0;
327 pci
->dma_regs
[DMA_STAT
] |= DMA_STAT_DONE
;
330 static const struct SCSIBusInfo esp_pci_scsi_info
= {
332 .max_target
= ESP_MAX_DEVS
,
335 .transfer_data
= esp_transfer_data
,
336 .complete
= esp_pci_command_complete
,
337 .cancel
= esp_request_cancelled
,
340 static int esp_pci_scsi_init(PCIDevice
*dev
)
342 PCIESPState
*pci
= PCI_ESP(dev
);
343 DeviceState
*d
= DEVICE(dev
);
344 ESPState
*s
= &pci
->esp
;
347 pci_conf
= pci
->dev
.config
;
349 /* Interrupt pin A */
350 pci_conf
[PCI_INTERRUPT_PIN
] = 0x01;
352 s
->dma_memory_read
= esp_pci_dma_memory_read
;
353 s
->dma_memory_write
= esp_pci_dma_memory_write
;
355 s
->chip_id
= TCHI_AM53C974
;
356 memory_region_init_io(&pci
->io
, OBJECT(pci
), &esp_pci_io_ops
, pci
,
359 pci_register_bar(&pci
->dev
, 0, PCI_BASE_ADDRESS_SPACE_IO
, &pci
->io
);
360 s
->irq
= pci
->dev
.irq
[0];
362 scsi_bus_new(&s
->bus
, d
, &esp_pci_scsi_info
, NULL
);
363 if (!d
->hotplugged
) {
364 return scsi_bus_legacy_handle_cmdline(&s
->bus
);
369 static void esp_pci_scsi_uninit(PCIDevice
*d
)
371 PCIESPState
*pci
= PCI_ESP(d
);
373 memory_region_destroy(&pci
->io
);
376 static void esp_pci_class_init(ObjectClass
*klass
, void *data
)
378 DeviceClass
*dc
= DEVICE_CLASS(klass
);
379 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
381 k
->init
= esp_pci_scsi_init
;
382 k
->exit
= esp_pci_scsi_uninit
;
383 k
->vendor_id
= PCI_VENDOR_ID_AMD
;
384 k
->device_id
= PCI_DEVICE_ID_AMD_SCSI
;
386 k
->class_id
= PCI_CLASS_STORAGE_SCSI
;
387 dc
->desc
= "AMD Am53c974 PCscsi-PCI SCSI adapter";
388 dc
->reset
= esp_pci_hard_reset
;
389 dc
->vmsd
= &vmstate_esp_pci_scsi
;
392 static const TypeInfo esp_pci_info
= {
393 .name
= TYPE_AM53C974_DEVICE
,
394 .parent
= TYPE_PCI_DEVICE
,
395 .instance_size
= sizeof(PCIESPState
),
396 .class_init
= esp_pci_class_init
,
404 #define TYPE_DC390_DEVICE "dc390"
406 OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
408 #define EE_ADAPT_SCSI_ID 64
411 #define EE_TAG_CMD_NUM 67
412 #define EE_ADAPT_OPTIONS 68
413 #define EE_BOOT_SCSI_ID 69
414 #define EE_BOOT_SCSI_LUN 70
415 #define EE_CHKSUM1 126
416 #define EE_CHKSUM2 127
418 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT 0x01
419 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
420 #define EE_ADAPT_OPTION_INT13 0x04
421 #define EE_ADAPT_OPTION_SCAM_SUPPORT 0x08
424 static uint32_t dc390_read_config(PCIDevice
*dev
, uint32_t addr
, int l
)
426 DC390State
*pci
= DC390(dev
);
429 val
= pci_default_read_config(dev
, addr
, l
);
431 if (addr
== 0x00 && l
== 1) {
432 /* First byte of address space is AND-ed with EEPROM DO line */
433 if (!eeprom93xx_read(pci
->eeprom
)) {
441 static void dc390_write_config(PCIDevice
*dev
,
442 uint32_t addr
, uint32_t val
, int l
)
444 DC390State
*pci
= DC390(dev
);
447 int eesk
= val
& 0x80 ? 1 : 0;
448 int eedi
= val
& 0x40 ? 1 : 0;
449 eeprom93xx_write(pci
->eeprom
, 1, eesk
, eedi
);
450 } else if (addr
== 0xc0) {
452 eeprom93xx_write(pci
->eeprom
, 0, 0, 0);
454 pci_default_write_config(dev
, addr
, val
, l
);
458 static int dc390_scsi_init(PCIDevice
*dev
)
460 DC390State
*pci
= DC390(dev
);
465 /* init base class */
466 ret
= esp_pci_scsi_init(dev
);
472 pci
->eeprom
= eeprom93xx_new(DEVICE(dev
), 64);
474 /* set default eeprom values */
475 contents
= (uint8_t *)eeprom93xx_data(pci
->eeprom
);
477 for (i
= 0; i
< 16; i
++) {
478 contents
[i
* 2] = 0x57;
479 contents
[i
* 2 + 1] = 0x00;
481 contents
[EE_ADAPT_SCSI_ID
] = 7;
482 contents
[EE_MODE2
] = 0x0f;
483 contents
[EE_TAG_CMD_NUM
] = 0x04;
484 contents
[EE_ADAPT_OPTIONS
] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
485 | EE_ADAPT_OPTION_BOOT_FROM_CDROM
486 | EE_ADAPT_OPTION_INT13
;
488 /* update eeprom checksum */
489 for (i
= 0; i
< EE_CHKSUM1
; i
+= 2) {
490 chksum
+= contents
[i
] + (((uint16_t)contents
[i
+ 1]) << 8);
492 chksum
= 0x1234 - chksum
;
493 contents
[EE_CHKSUM1
] = chksum
& 0xff;
494 contents
[EE_CHKSUM2
] = chksum
>> 8;
499 static void dc390_class_init(ObjectClass
*klass
, void *data
)
501 DeviceClass
*dc
= DEVICE_CLASS(klass
);
502 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
504 k
->init
= dc390_scsi_init
;
505 k
->config_read
= dc390_read_config
;
506 k
->config_write
= dc390_write_config
;
507 dc
->desc
= "Tekram DC-390 SCSI adapter";
510 static const TypeInfo dc390_info
= {
512 .parent
= TYPE_AM53C974_DEVICE
,
513 .instance_size
= sizeof(DC390State
),
514 .class_init
= dc390_class_init
,
517 static void esp_pci_register_types(void)
519 type_register_static(&esp_pci_info
);
520 type_register_static(&dc390_info
);
523 type_init(esp_pci_register_types
)