hw/scsi/esp-pci.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw/pci/pci.h"
  27 #include "hw/nvram/eeprom93xx.h"
  28 #include "hw/scsi/esp.h"
  29 #include "trace.h"
  30 #include "qemu/log.h"
  31
  32 #define TYPE_AM53C974_DEVICE "am53c974"
  33
  34 #define PCI_ESP(obj) \
  35     OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
  36
  37 #define DMA_CMD   0x0
  38 #define DMA_STC   0x1
  39 #define DMA_SPA   0x2
  40 #define DMA_WBC   0x3
  41 #define DMA_WAC   0x4
  42 #define DMA_STAT  0x5
  43 #define DMA_SMDLA 0x6
  44 #define DMA_WMAC  0x7
  45
  46 #define DMA_CMD_MASK   0x03
  47 #define DMA_CMD_DIAG   0x04
  48 #define DMA_CMD_MDL    0x10
  49 #define DMA_CMD_INTE_P 0x20
  50 #define DMA_CMD_INTE_D 0x40
  51 #define DMA_CMD_DIR    0x80
  52
  53 #define DMA_STAT_PWDN    0x01
  54 #define DMA_STAT_ERROR   0x02
  55 #define DMA_STAT_ABORT   0x04
  56 #define DMA_STAT_DONE    0x08
  57 #define DMA_STAT_SCSIINT 0x10
  58 #define DMA_STAT_BCMBLT  0x20
  59
  60 #define SBAC_STATUS 0x1000
  61
  62 typedef struct PCIESPState {
  63     PCIDevice dev;
  64     MemoryRegion io;
  65     uint32_t dma_regs[8];
  66     uint32_t sbac;
  67     ESPState esp;
  68 } PCIESPState;
  69
  70 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
  71 {
  72     trace_esp_pci_dma_idle(val);
  73     esp_dma_enable(&pci->esp, 0, 0);
  74 }
  75
  76 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
  77 {
  78     trace_esp_pci_dma_blast(val);
  79     qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
  80 }
  81
  82 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
  83 {
  84     trace_esp_pci_dma_abort(val);
  85     if (pci->esp.current_req) {
  86         scsi_req_cancel(pci->esp.current_req);
  87     }
  88 }
  89
  90 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
  91 {
  92     trace_esp_pci_dma_start(val);
  93
  94     pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
  95     pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
  96     pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
  97
  98     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
  99                                | DMA_STAT_DONE | DMA_STAT_ABORT
 100                                | DMA_STAT_ERROR | DMA_STAT_PWDN);
 101
 102     esp_dma_enable(&pci->esp, 0, 1);
 103 }
 104
 105 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
 106 {
 107     trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
 108     switch (saddr) {
 109     case DMA_CMD:
 110         pci->dma_regs[saddr] = val;
 111         switch (val & DMA_CMD_MASK) {
 112         case 0x0: /* IDLE */
 113             esp_pci_handle_idle(pci, val);
 114             break;
 115         case 0x1: /* BLAST */
 116             esp_pci_handle_blast(pci, val);
 117             break;
 118         case 0x2: /* ABORT */
 119             esp_pci_handle_abort(pci, val);
 120             break;
 121         case 0x3: /* START */
 122             esp_pci_handle_start(pci, val);
 123             break;
 124         default: /* can't happen */
 125             abort();
 126         }
 127         break;
 128     case DMA_STC:
 129     case DMA_SPA:
 130     case DMA_SMDLA:
 131         pci->dma_regs[saddr] = val;
 132         break;
 133     case DMA_STAT:
 134         if (!(pci->sbac & SBAC_STATUS)) {
 135             /* clear some bits on write */
 136             uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
 137             pci->dma_regs[DMA_STAT] &= ~(val & mask);
 138         }
 139         break;
 140     default:
 141         trace_esp_pci_error_invalid_write_dma(val, saddr);
 142         return;
 143     }
 144 }
 145
 146 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
 147 {
 148     uint32_t val;
 149
 150     val = pci->dma_regs[saddr];
 151     if (saddr == DMA_STAT) {
 152         if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
 153             val |= DMA_STAT_SCSIINT;
 154         }
 155         if (pci->sbac & SBAC_STATUS) {
 156             pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
 157                                          DMA_STAT_DONE);
 158         }
 159     }
 160
 161     trace_esp_pci_dma_read(saddr, val);
 162     return val;
 163 }
 164
 165 static void esp_pci_io_write(void *opaque, hwaddr addr,
 166                              uint64_t val, unsigned int size)
 167 {
 168     PCIESPState *pci = opaque;
 169
 170     if (size < 4 || addr & 3) {
 171         /* need to upgrade request: we only support 4-bytes accesses */
 172         uint32_t current = 0, mask;
 173         int shift;
 174
 175         if (addr < 0x40) {
 176             current = pci->esp.wregs[addr >> 2];
 177         } else if (addr < 0x60) {
 178             current = pci->dma_regs[(addr - 0x40) >> 2];
 179         } else if (addr < 0x74) {
 180             current = pci->sbac;
 181         }
 182
 183         shift = (4 - size) * 8;
 184         mask = (~(uint32_t)0 << shift) >> shift;
 185
 186         shift = ((4 - (addr & 3)) & 3) * 8;
 187         val <<= shift;
 188         val |= current & ~(mask << shift);
 189         addr &= ~3;
 190         size = 4;
 191     }
 192
 193     if (addr < 0x40) {
 194         /* SCSI core reg */
 195         esp_reg_write(&pci->esp, addr >> 2, val);
 196     } else if (addr < 0x60) {
 197         /* PCI DMA CCB */
 198         esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
 199     } else if (addr == 0x70) {
 200         /* DMA SCSI Bus and control */
 201         trace_esp_pci_sbac_write(pci->sbac, val);
 202         pci->sbac = val;
 203     } else {
 204         trace_esp_pci_error_invalid_write((int)addr);
 205     }
 206 }
 207
 208 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
 209                                 unsigned int size)
 210 {
 211     PCIESPState *pci = opaque;
 212     uint32_t ret;
 213
 214     if (addr < 0x40) {
 215         /* SCSI core reg */
 216         ret = esp_reg_read(&pci->esp, addr >> 2);
 217     } else if (addr < 0x60) {
 218         /* PCI DMA CCB */
 219         ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
 220     } else if (addr == 0x70) {
 221         /* DMA SCSI Bus and control */
 222         trace_esp_pci_sbac_read(pci->sbac);
 223         ret = pci->sbac;
 224     } else {
 225         /* Invalid region */
 226         trace_esp_pci_error_invalid_read((int)addr);
 227         ret = 0;
 228     }
 229
 230     /* give only requested data */
 231     ret >>= (addr & 3) * 8;
 232     ret &= ~(~(uint64_t)0 << (8 * size));
 233
 234     return ret;
 235 }
 236
 237 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
 238                                   DMADirection dir)
 239 {
 240     dma_addr_t addr;
 241     DMADirection expected_dir;
 242
 243     if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
 244         expected_dir = DMA_DIRECTION_FROM_DEVICE;
 245     } else {
 246         expected_dir = DMA_DIRECTION_TO_DEVICE;
 247     }
 248
 249     if (dir != expected_dir) {
 250         trace_esp_pci_error_invalid_dma_direction();
 251         return;
 252     }
 253
 254     if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
 255         qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
 256     }
 257
 258     addr = pci->dma_regs[DMA_SPA];
 259     if (pci->dma_regs[DMA_WBC] < len) {
 260         len = pci->dma_regs[DMA_WBC];
 261     }
 262
 263     pci_dma_rw(&pci->dev, addr, buf, len, dir);
 264
 265     /* update status registers */
 266     pci->dma_regs[DMA_WBC] -= len;
 267     pci->dma_regs[DMA_WAC] += len;
 268 }
 269
 270 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
 271 {
 272     PCIESPState *pci = opaque;
 273     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
 274 }
 275
 276 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
 277 {
 278     PCIESPState *pci = opaque;
 279     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
 280 }
 281
 282 static const MemoryRegionOps esp_pci_io_ops = {
 283     .read = esp_pci_io_read,
 284     .write = esp_pci_io_write,
 285     .endianness = DEVICE_LITTLE_ENDIAN,
 286     .impl = {
 287         .min_access_size = 1,
 288         .max_access_size = 4,
 289     },
 290 };
 291
 292 static void esp_pci_hard_reset(DeviceState *dev)
 293 {
 294     PCIESPState *pci = PCI_ESP(dev);
 295     esp_hard_reset(&pci->esp);
 296     pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
 297                               | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
 298     pci->dma_regs[DMA_WBC] &= ~0xffff;
 299     pci->dma_regs[DMA_WAC] = 0xffffffff;
 300     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 301                                | DMA_STAT_DONE | DMA_STAT_ABORT
 302                                | DMA_STAT_ERROR);
 303     pci->dma_regs[DMA_WMAC] = 0xfffffffd;
 304 }
 305
 306 static const VMStateDescription vmstate_esp_pci_scsi = {
 307     .name = "pciespscsi",
 308     .version_id = 0,
 309     .minimum_version_id = 0,
 310     .minimum_version_id_old = 0,
 311     .fields = (VMStateField[]) {
 312         VMSTATE_PCI_DEVICE(dev, PCIESPState),
 313         VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
 314         VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
 315         VMSTATE_END_OF_LIST()
 316     }
 317 };
 318
 319 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
 320                                      size_t resid)
 321 {
 322     ESPState *s = req->hba_private;
 323     PCIESPState *pci = container_of(s, PCIESPState, esp);
 324
 325     esp_command_complete(req, status, resid);
 326     pci->dma_regs[DMA_WBC] = 0;
 327     pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
 328 }
 329
 330 static const struct SCSIBusInfo esp_pci_scsi_info = {
 331     .tcq = false,
 332     .max_target = ESP_MAX_DEVS,
 333     .max_lun = 7,
 334
 335     .transfer_data = esp_transfer_data,
 336     .complete = esp_pci_command_complete,
 337     .cancel = esp_request_cancelled,
 338 };
 339
 340 static int esp_pci_scsi_init(PCIDevice *dev)
 341 {
 342     PCIESPState *pci = PCI_ESP(dev);
 343     DeviceState *d = DEVICE(dev);
 344     ESPState *s = &pci->esp;
 345     uint8_t *pci_conf;
 346
 347     pci_conf = pci->dev.config;
 348
 349     /* Interrupt pin A */
 350     pci_conf[PCI_INTERRUPT_PIN] = 0x01;
 351
 352     s->dma_memory_read = esp_pci_dma_memory_read;
 353     s->dma_memory_write = esp_pci_dma_memory_write;
 354     s->dma_opaque = pci;
 355     s->chip_id = TCHI_AM53C974;
 356     memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
 357                           "esp-io", 0x80);
 358
 359     pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
 360     s->irq = pci->dev.irq[0];
 361
 362     scsi_bus_new(&s->bus, d, &esp_pci_scsi_info, NULL);
 363     if (!d->hotplugged) {
 364         return scsi_bus_legacy_handle_cmdline(&s->bus);
 365     }
 366     return 0;
 367 }
 368
 369 static void esp_pci_scsi_uninit(PCIDevice *d)
 370 {
 371     PCIESPState *pci = PCI_ESP(d);
 372
 373     memory_region_destroy(&pci->io);
 374 }
 375
 376 static void esp_pci_class_init(ObjectClass *klass, void *data)
 377 {
 378     DeviceClass *dc = DEVICE_CLASS(klass);
 379     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 380
 381     k->init = esp_pci_scsi_init;
 382     k->exit = esp_pci_scsi_uninit;
 383     k->vendor_id = PCI_VENDOR_ID_AMD;
 384     k->device_id = PCI_DEVICE_ID_AMD_SCSI;
 385     k->revision = 0x10;
 386     k->class_id = PCI_CLASS_STORAGE_SCSI;
 387     dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
 388     dc->reset = esp_pci_hard_reset;
 389     dc->vmsd = &vmstate_esp_pci_scsi;
 390 }
 391
 392 static const TypeInfo esp_pci_info = {
 393     .name = TYPE_AM53C974_DEVICE,
 394     .parent = TYPE_PCI_DEVICE,
 395     .instance_size = sizeof(PCIESPState),
 396     .class_init = esp_pci_class_init,
 397 };
 398
 399 typedef struct {
 400     PCIESPState pci;
 401     eeprom_t *eeprom;
 402 } DC390State;
 403
 404 #define TYPE_DC390_DEVICE "dc390"
 405 #define DC390(obj) \
 406     OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
 407
 408 #define EE_ADAPT_SCSI_ID 64
 409 #define EE_MODE2         65
 410 #define EE_DELAY         66
 411 #define EE_TAG_CMD_NUM   67
 412 #define EE_ADAPT_OPTIONS 68
 413 #define EE_BOOT_SCSI_ID  69
 414 #define EE_BOOT_SCSI_LUN 70
 415 #define EE_CHKSUM1       126
 416 #define EE_CHKSUM2       127
 417
 418 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT   0x01
 419 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
 420 #define EE_ADAPT_OPTION_INT13           0x04
 421 #define EE_ADAPT_OPTION_SCAM_SUPPORT    0x08
 422
 423
 424 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
 425 {
 426     DC390State *pci = DC390(dev);
 427     uint32_t val;
 428
 429     val = pci_default_read_config(dev, addr, l);
 430
 431     if (addr == 0x00 && l == 1) {
 432         /* First byte of address space is AND-ed with EEPROM DO line */
 433         if (!eeprom93xx_read(pci->eeprom)) {
 434             val &= ~0xff;
 435         }
 436     }
 437
 438     return val;
 439 }
 440
 441 static void dc390_write_config(PCIDevice *dev,
 442                                uint32_t addr, uint32_t val, int l)
 443 {
 444     DC390State *pci = DC390(dev);
 445     if (addr == 0x80) {
 446         /* EEPROM write */
 447         int eesk = val & 0x80 ? 1 : 0;
 448         int eedi = val & 0x40 ? 1 : 0;
 449         eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
 450     } else if (addr == 0xc0) {
 451         /* EEPROM CS low */
 452         eeprom93xx_write(pci->eeprom, 0, 0, 0);
 453     } else {
 454         pci_default_write_config(dev, addr, val, l);
 455     }
 456 }
 457
 458 static int dc390_scsi_init(PCIDevice *dev)
 459 {
 460     DC390State *pci = DC390(dev);
 461     uint8_t *contents;
 462     uint16_t chksum = 0;
 463     int i, ret;
 464
 465     /* init base class */
 466     ret = esp_pci_scsi_init(dev);
 467     if (ret < 0) {
 468         return ret;
 469     }
 470
 471     /* EEPROM */
 472     pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
 473
 474     /* set default eeprom values */
 475     contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
 476
 477     for (i = 0; i < 16; i++) {
 478         contents[i * 2] = 0x57;
 479         contents[i * 2 + 1] = 0x00;
 480     }
 481     contents[EE_ADAPT_SCSI_ID] = 7;
 482     contents[EE_MODE2] = 0x0f;
 483     contents[EE_TAG_CMD_NUM] = 0x04;
 484     contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
 485                                | EE_ADAPT_OPTION_BOOT_FROM_CDROM
 486                                | EE_ADAPT_OPTION_INT13;
 487
 488     /* update eeprom checksum */
 489     for (i = 0; i < EE_CHKSUM1; i += 2) {
 490         chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
 491     }
 492     chksum = 0x1234 - chksum;
 493     contents[EE_CHKSUM1] = chksum & 0xff;
 494     contents[EE_CHKSUM2] = chksum >> 8;
 495
 496     return 0;
 497 }
 498
 499 static void dc390_class_init(ObjectClass *klass, void *data)
 500 {
 501     DeviceClass *dc = DEVICE_CLASS(klass);
 502     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 503
 504     k->init = dc390_scsi_init;
 505     k->config_read = dc390_read_config;
 506     k->config_write = dc390_write_config;
 507     dc->desc = "Tekram DC-390 SCSI adapter";
 508 }
 509
 510 static const TypeInfo dc390_info = {
 511     .name = "dc390",
 512     .parent = TYPE_AM53C974_DEVICE,
 513     .instance_size = sizeof(DC390State),
 514     .class_init = dc390_class_init,
 515 };
 516
 517 static void esp_pci_register_types(void)
 518 {
 519     type_register_static(&esp_pci_info);
 520     type_register_static(&dc390_info);
 521 }
 522
 523 type_init(esp_pci_register_types)