2 * QEMU model of Xilinx AXI-DMA block.
4 * Copyright (c) 2011 Edgar E. Iglesias.
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "hw/sysbus.h"
26 #include "qemu/timer.h"
27 #include "hw/ptimer.h"
29 #include "qapi/qmp/qerror.h"
30 #include "qemu/main-loop.h"
32 #include "hw/stream.h"
36 #define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
37 #define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
38 #define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
40 #define XILINX_AXI_DMA(obj) \
41 OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
43 #define XILINX_AXI_DMA_DATA_STREAM(obj) \
44 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
45 TYPE_XILINX_AXI_DMA_DATA_STREAM)
47 #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
48 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
49 TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
51 #define R_DMACR (0x00 / 4)
52 #define R_DMASR (0x04 / 4)
53 #define R_CURDESC (0x08 / 4)
54 #define R_TAILDESC (0x10 / 4)
55 #define R_MAX (0x30 / 4)
57 #define CONTROL_PAYLOAD_WORDS 5
58 #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
60 typedef struct XilinxAXIDMA XilinxAXIDMA
;
61 typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave
;
65 DMACR_TAILPTR_MODE
= 2,
72 DMASR_IOC_IRQ
= 1 << 12,
73 DMASR_DLY_IRQ
= 1 << 13,
75 DMASR_IRQ_MASK
= 7 << 12
80 uint64_t buffer_address
;
84 uint8_t app
[CONTROL_PAYLOAD_SIZE
];
88 SDESC_CTRL_EOF
= (1 << 26),
89 SDESC_CTRL_SOF
= (1 << 27),
91 SDESC_CTRL_LEN_MASK
= (1 << 23) - 1
95 SDESC_STATUS_EOF
= (1 << 26),
96 SDESC_STATUS_SOF_BIT
= 27,
97 SDESC_STATUS_SOF
= (1 << SDESC_STATUS_SOF_BIT
),
98 SDESC_STATUS_COMPLETE
= (1 << 31)
103 ptimer_state
*ptimer
;
110 unsigned int complete_cnt
;
111 uint32_t regs
[R_MAX
];
115 struct XilinxAXIDMAStreamSlave
{
118 struct XilinxAXIDMA
*dma
;
121 struct XilinxAXIDMA
{
125 StreamSlave
*tx_data_dev
;
126 StreamSlave
*tx_control_dev
;
127 XilinxAXIDMAStreamSlave rx_data_dev
;
128 XilinxAXIDMAStreamSlave rx_control_dev
;
130 struct Stream streams
[2];
132 StreamCanPushNotifyFn notify
;
137 * Helper calls to extract info from desriptors and other trivial
140 static inline int stream_desc_sof(struct SDesc
*d
)
142 return d
->control
& SDESC_CTRL_SOF
;
145 static inline int stream_desc_eof(struct SDesc
*d
)
147 return d
->control
& SDESC_CTRL_EOF
;
150 static inline int stream_resetting(struct Stream
*s
)
152 return !!(s
->regs
[R_DMACR
] & DMACR_RESET
);
155 static inline int stream_running(struct Stream
*s
)
157 return s
->regs
[R_DMACR
] & DMACR_RUNSTOP
;
160 static inline int stream_halted(struct Stream
*s
)
162 return s
->regs
[R_DMASR
] & DMASR_HALTED
;
165 static inline int stream_idle(struct Stream
*s
)
167 return !!(s
->regs
[R_DMASR
] & DMASR_IDLE
);
170 static void stream_reset(struct Stream
*s
)
172 s
->regs
[R_DMASR
] = DMASR_HALTED
; /* starts up halted. */
173 s
->regs
[R_DMACR
] = 1 << 16; /* Starts with one in compl threshold. */
176 /* Map an offset addr into a channel index. */
177 static inline int streamid_from_addr(hwaddr addr
)
187 static void stream_desc_show(struct SDesc
*d
)
189 qemu_log("buffer_addr = " PRIx64
"\n", d
->buffer_address
);
190 qemu_log("nxtdesc = " PRIx64
"\n", d
->nxtdesc
);
191 qemu_log("control = %x\n", d
->control
);
192 qemu_log("status = %x\n", d
->status
);
196 static void stream_desc_load(struct Stream
*s
, hwaddr addr
)
198 struct SDesc
*d
= &s
->desc
;
200 cpu_physical_memory_read(addr
, d
, sizeof *d
);
202 /* Convert from LE into host endianness. */
203 d
->buffer_address
= le64_to_cpu(d
->buffer_address
);
204 d
->nxtdesc
= le64_to_cpu(d
->nxtdesc
);
205 d
->control
= le32_to_cpu(d
->control
);
206 d
->status
= le32_to_cpu(d
->status
);
209 static void stream_desc_store(struct Stream
*s
, hwaddr addr
)
211 struct SDesc
*d
= &s
->desc
;
213 /* Convert from host endianness into LE. */
214 d
->buffer_address
= cpu_to_le64(d
->buffer_address
);
215 d
->nxtdesc
= cpu_to_le64(d
->nxtdesc
);
216 d
->control
= cpu_to_le32(d
->control
);
217 d
->status
= cpu_to_le32(d
->status
);
218 cpu_physical_memory_write(addr
, d
, sizeof *d
);
221 static void stream_update_irq(struct Stream
*s
)
223 unsigned int pending
, mask
, irq
;
225 pending
= s
->regs
[R_DMASR
] & DMASR_IRQ_MASK
;
226 mask
= s
->regs
[R_DMACR
] & DMASR_IRQ_MASK
;
228 irq
= pending
& mask
;
230 qemu_set_irq(s
->irq
, !!irq
);
233 static void stream_reload_complete_cnt(struct Stream
*s
)
235 unsigned int comp_th
;
236 comp_th
= (s
->regs
[R_DMACR
] >> 16) & 0xff;
237 s
->complete_cnt
= comp_th
;
240 static void timer_hit(void *opaque
)
242 struct Stream
*s
= opaque
;
244 stream_reload_complete_cnt(s
);
245 s
->regs
[R_DMASR
] |= DMASR_DLY_IRQ
;
246 stream_update_irq(s
);
249 static void stream_complete(struct Stream
*s
)
251 unsigned int comp_delay
;
253 /* Start the delayed timer. */
254 comp_delay
= s
->regs
[R_DMACR
] >> 24;
256 ptimer_stop(s
->ptimer
);
257 ptimer_set_count(s
->ptimer
, comp_delay
);
258 ptimer_run(s
->ptimer
, 1);
262 if (s
->complete_cnt
== 0) {
263 /* Raise the IOC irq. */
264 s
->regs
[R_DMASR
] |= DMASR_IOC_IRQ
;
265 stream_reload_complete_cnt(s
);
269 static void stream_process_mem2s(struct Stream
*s
, StreamSlave
*tx_data_dev
,
270 StreamSlave
*tx_control_dev
)
273 unsigned char txbuf
[16 * 1024];
276 if (!stream_running(s
) || stream_idle(s
)) {
281 stream_desc_load(s
, s
->regs
[R_CURDESC
]);
283 if (s
->desc
.status
& SDESC_STATUS_COMPLETE
) {
284 s
->regs
[R_DMASR
] |= DMASR_HALTED
;
288 if (stream_desc_sof(&s
->desc
)) {
290 stream_push(tx_control_dev
, s
->desc
.app
, sizeof(s
->desc
.app
));
293 txlen
= s
->desc
.control
& SDESC_CTRL_LEN_MASK
;
294 if ((txlen
+ s
->pos
) > sizeof txbuf
) {
295 hw_error("%s: too small internal txbuf! %d\n", __func__
,
299 cpu_physical_memory_read(s
->desc
.buffer_address
,
300 txbuf
+ s
->pos
, txlen
);
303 if (stream_desc_eof(&s
->desc
)) {
304 stream_push(tx_data_dev
, txbuf
, s
->pos
);
309 /* Update the descriptor. */
310 s
->desc
.status
= txlen
| SDESC_STATUS_COMPLETE
;
311 stream_desc_store(s
, s
->regs
[R_CURDESC
]);
314 prev_d
= s
->regs
[R_CURDESC
];
315 s
->regs
[R_CURDESC
] = s
->desc
.nxtdesc
;
316 if (prev_d
== s
->regs
[R_TAILDESC
]) {
317 s
->regs
[R_DMASR
] |= DMASR_IDLE
;
323 static size_t stream_process_s2mem(struct Stream
*s
, unsigned char *buf
,
331 if (!stream_running(s
) || stream_idle(s
)) {
336 stream_desc_load(s
, s
->regs
[R_CURDESC
]);
338 if (s
->desc
.status
& SDESC_STATUS_COMPLETE
) {
339 s
->regs
[R_DMASR
] |= DMASR_HALTED
;
343 rxlen
= s
->desc
.control
& SDESC_CTRL_LEN_MASK
;
349 cpu_physical_memory_write(s
->desc
.buffer_address
, buf
+ pos
, rxlen
);
353 /* Update the descriptor. */
356 memcpy(s
->desc
.app
, s
->app
, sizeof(s
->desc
.app
));
357 s
->desc
.status
|= SDESC_STATUS_EOF
;
360 s
->desc
.status
|= sof
<< SDESC_STATUS_SOF_BIT
;
361 s
->desc
.status
|= SDESC_STATUS_COMPLETE
;
362 stream_desc_store(s
, s
->regs
[R_CURDESC
]);
366 prev_d
= s
->regs
[R_CURDESC
];
367 s
->regs
[R_CURDESC
] = s
->desc
.nxtdesc
;
368 if (prev_d
== s
->regs
[R_TAILDESC
]) {
369 s
->regs
[R_DMASR
] |= DMASR_IDLE
;
377 static void xilinx_axidma_reset(DeviceState
*dev
)
380 XilinxAXIDMA
*s
= XILINX_AXI_DMA(dev
);
382 for (i
= 0; i
< 2; i
++) {
383 stream_reset(&s
->streams
[i
]);
388 xilinx_axidma_control_stream_push(StreamSlave
*obj
, unsigned char *buf
,
391 XilinxAXIDMAStreamSlave
*cs
= XILINX_AXI_DMA_CONTROL_STREAM(obj
);
392 struct Stream
*s
= &cs
->dma
->streams
[1];
394 if (len
!= CONTROL_PAYLOAD_SIZE
) {
395 hw_error("AXI DMA requires %d byte control stream payload\n",
396 (int)CONTROL_PAYLOAD_SIZE
);
399 memcpy(s
->app
, buf
, len
);
404 xilinx_axidma_data_stream_can_push(StreamSlave
*obj
,
405 StreamCanPushNotifyFn notify
,
408 XilinxAXIDMAStreamSlave
*ds
= XILINX_AXI_DMA_DATA_STREAM(obj
);
409 struct Stream
*s
= &ds
->dma
->streams
[1];
411 if (!stream_running(s
) || stream_idle(s
)) {
412 ds
->dma
->notify
= notify
;
413 ds
->dma
->notify_opaque
= notify_opaque
;
421 xilinx_axidma_data_stream_push(StreamSlave
*obj
, unsigned char *buf
, size_t len
)
423 XilinxAXIDMAStreamSlave
*ds
= XILINX_AXI_DMA_DATA_STREAM(obj
);
424 struct Stream
*s
= &ds
->dma
->streams
[1];
427 ret
= stream_process_s2mem(s
, buf
, len
);
428 stream_update_irq(s
);
432 static uint64_t axidma_read(void *opaque
, hwaddr addr
,
435 XilinxAXIDMA
*d
= opaque
;
440 sid
= streamid_from_addr(addr
);
441 s
= &d
->streams
[sid
];
447 /* Simulate one cycles reset delay. */
448 s
->regs
[addr
] &= ~DMACR_RESET
;
452 s
->regs
[addr
] &= 0xffff;
453 s
->regs
[addr
] |= (s
->complete_cnt
& 0xff) << 16;
454 s
->regs
[addr
] |= (ptimer_get_count(s
->ptimer
) & 0xff) << 24;
459 D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx
" v=%x\n",
460 __func__
, sid
, addr
* 4, r
));
467 static void axidma_write(void *opaque
, hwaddr addr
,
468 uint64_t value
, unsigned size
)
470 XilinxAXIDMA
*d
= opaque
;
474 sid
= streamid_from_addr(addr
);
475 s
= &d
->streams
[sid
];
481 /* Tailptr mode is always on. */
482 value
|= DMACR_TAILPTR_MODE
;
483 /* Remember our previous reset state. */
484 value
|= (s
->regs
[addr
] & DMACR_RESET
);
485 s
->regs
[addr
] = value
;
487 if (value
& DMACR_RESET
) {
491 if ((value
& 1) && !stream_resetting(s
)) {
492 /* Start processing. */
493 s
->regs
[R_DMASR
] &= ~(DMASR_HALTED
| DMASR_IDLE
);
495 stream_reload_complete_cnt(s
);
499 /* Mask away write to clear irq lines. */
500 value
&= ~(value
& DMASR_IRQ_MASK
);
501 s
->regs
[addr
] = value
;
505 s
->regs
[addr
] = value
;
506 s
->regs
[R_DMASR
] &= ~DMASR_IDLE
; /* Not idle. */
508 stream_process_mem2s(s
, d
->tx_data_dev
, d
->tx_control_dev
);
512 D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx
" v=%x\n",
513 __func__
, sid
, addr
* 4, (unsigned)value
));
514 s
->regs
[addr
] = value
;
517 if (sid
== 1 && d
->notify
) {
518 StreamCanPushNotifyFn notifytmp
= d
->notify
;
520 notifytmp(d
->notify_opaque
);
522 stream_update_irq(s
);
525 static const MemoryRegionOps axidma_ops
= {
527 .write
= axidma_write
,
528 .endianness
= DEVICE_NATIVE_ENDIAN
,
531 static void xilinx_axidma_realize(DeviceState
*dev
, Error
**errp
)
533 XilinxAXIDMA
*s
= XILINX_AXI_DMA(dev
);
534 XilinxAXIDMAStreamSlave
*ds
= XILINX_AXI_DMA_DATA_STREAM(&s
->rx_data_dev
);
535 XilinxAXIDMAStreamSlave
*cs
= XILINX_AXI_DMA_CONTROL_STREAM(
537 Error
*local_errp
= NULL
;
539 object_property_add_link(OBJECT(ds
), "dma", TYPE_XILINX_AXI_DMA
,
541 object_property_allow_set_link
,
542 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
544 object_property_add_link(OBJECT(cs
), "dma", TYPE_XILINX_AXI_DMA
,
546 object_property_allow_set_link
,
547 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
550 goto xilinx_axidma_realize_fail
;
552 object_property_set_link(OBJECT(ds
), OBJECT(s
), "dma", &local_errp
);
553 object_property_set_link(OBJECT(cs
), OBJECT(s
), "dma", &local_errp
);
555 goto xilinx_axidma_realize_fail
;
560 for (i
= 0; i
< 2; i
++) {
561 s
->streams
[i
].nr
= i
;
562 s
->streams
[i
].bh
= qemu_bh_new(timer_hit
, &s
->streams
[i
]);
563 s
->streams
[i
].ptimer
= ptimer_init(s
->streams
[i
].bh
);
564 ptimer_set_freq(s
->streams
[i
].ptimer
, s
->freqhz
);
568 xilinx_axidma_realize_fail
:
574 static void xilinx_axidma_init(Object
*obj
)
576 XilinxAXIDMA
*s
= XILINX_AXI_DMA(obj
);
577 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
579 object_property_add_link(obj
, "axistream-connected", TYPE_STREAM_SLAVE
,
580 (Object
**)&s
->tx_data_dev
,
581 qdev_prop_allow_set_link_before_realize
,
582 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
584 object_property_add_link(obj
, "axistream-control-connected",
586 (Object
**)&s
->tx_control_dev
,
587 qdev_prop_allow_set_link_before_realize
,
588 OBJ_PROP_LINK_UNREF_ON_RELEASE
,
591 object_initialize(&s
->rx_data_dev
, sizeof(s
->rx_data_dev
),
592 TYPE_XILINX_AXI_DMA_DATA_STREAM
);
593 object_initialize(&s
->rx_control_dev
, sizeof(s
->rx_control_dev
),
594 TYPE_XILINX_AXI_DMA_CONTROL_STREAM
);
595 object_property_add_child(OBJECT(s
), "axistream-connected-target",
596 (Object
*)&s
->rx_data_dev
, &error_abort
);
597 object_property_add_child(OBJECT(s
), "axistream-control-connected-target",
598 (Object
*)&s
->rx_control_dev
, &error_abort
);
600 sysbus_init_irq(sbd
, &s
->streams
[0].irq
);
601 sysbus_init_irq(sbd
, &s
->streams
[1].irq
);
603 memory_region_init_io(&s
->iomem
, obj
, &axidma_ops
, s
,
604 "xlnx.axi-dma", R_MAX
* 4 * 2);
605 sysbus_init_mmio(sbd
, &s
->iomem
);
608 static Property axidma_properties
[] = {
609 DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA
, freqhz
, 50000000),
610 DEFINE_PROP_END_OF_LIST(),
613 static void axidma_class_init(ObjectClass
*klass
, void *data
)
615 DeviceClass
*dc
= DEVICE_CLASS(klass
);
617 dc
->realize
= xilinx_axidma_realize
,
618 dc
->reset
= xilinx_axidma_reset
;
619 dc
->props
= axidma_properties
;
622 static StreamSlaveClass xilinx_axidma_data_stream_class
= {
623 .push
= xilinx_axidma_data_stream_push
,
624 .can_push
= xilinx_axidma_data_stream_can_push
,
627 static StreamSlaveClass xilinx_axidma_control_stream_class
= {
628 .push
= xilinx_axidma_control_stream_push
,
631 static void xilinx_axidma_stream_class_init(ObjectClass
*klass
, void *data
)
633 StreamSlaveClass
*ssc
= STREAM_SLAVE_CLASS(klass
);
635 ssc
->push
= ((StreamSlaveClass
*)data
)->push
;
636 ssc
->can_push
= ((StreamSlaveClass
*)data
)->can_push
;
639 static const TypeInfo axidma_info
= {
640 .name
= TYPE_XILINX_AXI_DMA
,
641 .parent
= TYPE_SYS_BUS_DEVICE
,
642 .instance_size
= sizeof(XilinxAXIDMA
),
643 .class_init
= axidma_class_init
,
644 .instance_init
= xilinx_axidma_init
,
647 static const TypeInfo xilinx_axidma_data_stream_info
= {
648 .name
= TYPE_XILINX_AXI_DMA_DATA_STREAM
,
649 .parent
= TYPE_OBJECT
,
650 .instance_size
= sizeof(struct XilinxAXIDMAStreamSlave
),
651 .class_init
= xilinx_axidma_stream_class_init
,
652 .class_data
= &xilinx_axidma_data_stream_class
,
653 .interfaces
= (InterfaceInfo
[]) {
654 { TYPE_STREAM_SLAVE
},
659 static const TypeInfo xilinx_axidma_control_stream_info
= {
660 .name
= TYPE_XILINX_AXI_DMA_CONTROL_STREAM
,
661 .parent
= TYPE_OBJECT
,
662 .instance_size
= sizeof(struct XilinxAXIDMAStreamSlave
),
663 .class_init
= xilinx_axidma_stream_class_init
,
664 .class_data
= &xilinx_axidma_control_stream_class
,
665 .interfaces
= (InterfaceInfo
[]) {
666 { TYPE_STREAM_SLAVE
},
671 static void xilinx_axidma_register_types(void)
673 type_register_static(&axidma_info
);
674 type_register_static(&xilinx_axidma_data_stream_info
);
675 type_register_static(&xilinx_axidma_control_stream_info
);
678 type_init(xilinx_axidma_register_types
)