hw/pflash_cfi01.c

   1 /*
   2  *  CFI parallel flash with Intel command set emulation
   3  *
   4  *  Copyright (c) 2006 Thorsten Zitterell
   5  *  Copyright (c) 2005 Jocelyn Mayer
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 /*
  22  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  23  * Supported commands/modes are:
  24  * - flash read
  25  * - flash write
  26  * - flash ID read
  27  * - sector erase
  28  * - CFI queries
  29  *
  30  * It does not support timings
  31  * It does not support flash interleaving
  32  * It does not implement software data protection as found in many real chips
  33  * It does not implement erase suspend/resume commands
  34  * It does not implement multiple sectors erase
  35  *
  36  * It does not implement much more ...
  37  */
  38
  39 #include "hw.h"
  40 #include "flash.h"
  41 #include "block.h"
  42 #include "qemu-timer.h"
  43 #include "exec-memory.h"
  44 #include "host-utils.h"
  45
  46 #define PFLASH_BUG(fmt, ...) \
  47 do { \
  48     printf("PFLASH: Possible BUG - " fmt, ## __VA_ARGS__); \
  49     exit(1); \
  50 } while(0)
  51
  52 /* #define PFLASH_DEBUG */
  53 #ifdef PFLASH_DEBUG
  54 #define DPRINTF(fmt, ...)                          \
  55 do {                                               \
  56     printf("PFLASH: " fmt , ## __VA_ARGS__);       \
  57 } while (0)
  58 #else
  59 #define DPRINTF(fmt, ...) do { } while (0)
  60 #endif
  61
  62 struct pflash_t {
  63     BlockDriverState *bs;
  64     target_phys_addr_t base;
  65     target_phys_addr_t sector_len;
  66     target_phys_addr_t total_len;
  67     int width;
  68     int wcycle; /* if 0, the flash is read normally */
  69     int bypass;
  70     int ro;
  71     uint8_t cmd;
  72     uint8_t status;
  73     uint16_t ident[4];
  74     uint8_t cfi_len;
  75     uint8_t cfi_table[0x52];
  76     target_phys_addr_t counter;
  77     unsigned int writeblock_size;
  78     QEMUTimer *timer;
  79     MemoryRegion mem;
  80     void *storage;
  81 };
  82
  83 static void pflash_timer (void *opaque)
  84 {
  85     pflash_t *pfl = opaque;
  86
  87     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
  88     /* Reset flash */
  89     pfl->status ^= 0x80;
  90     if (pfl->bypass) {
  91         pfl->wcycle = 2;
  92     } else {
  93         memory_region_rom_device_set_readable(&pfl->mem, true);
  94         pfl->wcycle = 0;
  95     }
  96     pfl->cmd = 0;
  97 }
  98
  99 static uint32_t pflash_read (pflash_t *pfl, target_phys_addr_t offset,
 100                              int width, int be)
 101 {
 102     target_phys_addr_t boff;
 103     uint32_t ret;
 104     uint8_t *p;
 105
 106     ret = -1;
 107     boff = offset & 0xFF; /* why this here ?? */
 108
 109     if (pfl->width == 2)
 110         boff = boff >> 1;
 111     else if (pfl->width == 4)
 112         boff = boff >> 2;
 113
 114 #if 0
 115     DPRINTF("%s: reading offset " TARGET_FMT_plx " under cmd %02x width %d\n",
 116             __func__, offset, pfl->cmd, width);
 117 #endif
 118     switch (pfl->cmd) {
 119     case 0x00:
 120         /* Flash area read */
 121         p = pfl->storage;
 122         switch (width) {
 123         case 1:
 124             ret = p[offset];
 125             DPRINTF("%s: data offset " TARGET_FMT_plx " %02x\n",
 126                     __func__, offset, ret);
 127             break;
 128         case 2:
 129             if (be) {
 130                 ret = p[offset] << 8;
 131                 ret |= p[offset + 1];
 132             } else {
 133                 ret = p[offset];
 134                 ret |= p[offset + 1] << 8;
 135             }
 136             DPRINTF("%s: data offset " TARGET_FMT_plx " %04x\n",
 137                     __func__, offset, ret);
 138             break;
 139         case 4:
 140             if (be) {
 141                 ret = p[offset] << 24;
 142                 ret |= p[offset + 1] << 16;
 143                 ret |= p[offset + 2] << 8;
 144                 ret |= p[offset + 3];
 145             } else {
 146                 ret = p[offset];
 147                 ret |= p[offset + 1] << 8;
 148                 ret |= p[offset + 2] << 16;
 149                 ret |= p[offset + 3] << 24;
 150             }
 151             DPRINTF("%s: data offset " TARGET_FMT_plx " %08x\n",
 152                     __func__, offset, ret);
 153             break;
 154         default:
 155             DPRINTF("BUG in %s\n", __func__);
 156         }
 157
 158         break;
 159     case 0x20: /* Block erase */
 160     case 0x50: /* Clear status register */
 161     case 0x60: /* Block /un)lock */
 162     case 0x70: /* Status Register */
 163     case 0xe8: /* Write block */
 164         /* Status register read */
 165         ret = pfl->status;
 166         DPRINTF("%s: status %x\n", __func__, ret);
 167         break;
 168     case 0x90:
 169         switch (boff) {
 170         case 0:
 171             ret = pfl->ident[0] << 8 | pfl->ident[1];
 172             DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret);
 173             break;
 174         case 1:
 175             ret = pfl->ident[2] << 8 | pfl->ident[3];
 176             DPRINTF("%s: Device ID Code %04x\n", __func__, ret);
 177             break;
 178         default:
 179             DPRINTF("%s: Read Device Information boff=%x\n", __func__, boff);
 180             ret = 0;
 181             break;
 182         }
 183         break;
 184     case 0x98: /* Query mode */
 185         if (boff > pfl->cfi_len)
 186             ret = 0;
 187         else
 188             ret = pfl->cfi_table[boff];
 189         break;
 190     default:
 191         /* This should never happen : reset state & treat it as a read */
 192         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 193         pfl->wcycle = 0;
 194         pfl->cmd = 0;
 195     }
 196     return ret;
 197 }
 198
 199 /* update flash content on disk */
 200 static void pflash_update(pflash_t *pfl, int offset,
 201                           int size)
 202 {
 203     int offset_end;
 204     if (pfl->bs) {
 205         offset_end = offset + size;
 206         /* round to sectors */
 207         offset = offset >> 9;
 208         offset_end = (offset_end + 511) >> 9;
 209         bdrv_write(pfl->bs, offset, pfl->storage + (offset << 9),
 210                    offset_end - offset);
 211     }
 212 }
 213
 214 static inline void pflash_data_write(pflash_t *pfl, target_phys_addr_t offset,
 215                                      uint32_t value, int width, int be)
 216 {
 217     uint8_t *p = pfl->storage;
 218
 219     DPRINTF("%s: block write offset " TARGET_FMT_plx
 220             " value %x counter " TARGET_FMT_plx "\n",
 221             __func__, offset, value, pfl->counter);
 222     switch (width) {
 223     case 1:
 224         p[offset] = value;
 225         break;
 226     case 2:
 227         if (be) {
 228             p[offset] = value >> 8;
 229             p[offset + 1] = value;
 230         } else {
 231             p[offset] = value;
 232             p[offset + 1] = value >> 8;
 233         }
 234         break;
 235     case 4:
 236         if (be) {
 237             p[offset] = value >> 24;
 238             p[offset + 1] = value >> 16;
 239             p[offset + 2] = value >> 8;
 240             p[offset + 3] = value;
 241         } else {
 242             p[offset] = value;
 243             p[offset + 1] = value >> 8;
 244             p[offset + 2] = value >> 16;
 245             p[offset + 3] = value >> 24;
 246         }
 247         break;
 248     }
 249
 250 }
 251
 252 static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
 253                          uint32_t value, int width, int be)
 254 {
 255     uint8_t *p;
 256     uint8_t cmd;
 257
 258     cmd = value;
 259
 260     DPRINTF("%s: writing offset " TARGET_FMT_plx " value %08x width %d wcycle 0x%x\n",
 261             __func__, offset, value, width, pfl->wcycle);
 262
 263     if (!pfl->wcycle) {
 264         /* Set the device in I/O access mode */
 265         memory_region_rom_device_set_readable(&pfl->mem, false);
 266     }
 267
 268     switch (pfl->wcycle) {
 269     case 0:
 270         /* read mode */
 271         switch (cmd) {
 272         case 0x00: /* ??? */
 273             goto reset_flash;
 274         case 0x10: /* Single Byte Program */
 275         case 0x40: /* Single Byte Program */
 276             DPRINTF("%s: Single Byte Program\n", __func__);
 277             break;
 278         case 0x20: /* Block erase */
 279             p = pfl->storage;
 280             offset &= ~(pfl->sector_len - 1);
 281
 282             DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes "
 283                     TARGET_FMT_plx "\n",
 284                     __func__, offset, pfl->sector_len);
 285
 286             if (!pfl->ro) {
 287                 memset(p + offset, 0xff, pfl->sector_len);
 288                 pflash_update(pfl, offset, pfl->sector_len);
 289             } else {
 290                 pfl->status |= 0x20; /* Block erase error */
 291             }
 292             pfl->status |= 0x80; /* Ready! */
 293             break;
 294         case 0x50: /* Clear status bits */
 295             DPRINTF("%s: Clear status bits\n", __func__);
 296             pfl->status = 0x0;
 297             goto reset_flash;
 298         case 0x60: /* Block (un)lock */
 299             DPRINTF("%s: Block unlock\n", __func__);
 300             break;
 301         case 0x70: /* Status Register */
 302             DPRINTF("%s: Read status register\n", __func__);
 303             pfl->cmd = cmd;
 304             return;
 305         case 0x90: /* Read Device ID */
 306             DPRINTF("%s: Read Device information\n", __func__);
 307             pfl->cmd = cmd;
 308             return;
 309         case 0x98: /* CFI query */
 310             DPRINTF("%s: CFI query\n", __func__);
 311             break;
 312         case 0xe8: /* Write to buffer */
 313             DPRINTF("%s: Write to buffer\n", __func__);
 314             pfl->status |= 0x80; /* Ready! */
 315             break;
 316         case 0xff: /* Read array mode */
 317             DPRINTF("%s: Read array mode\n", __func__);
 318             goto reset_flash;
 319         default:
 320             goto error_flash;
 321         }
 322         pfl->wcycle++;
 323         pfl->cmd = cmd;
 324         break;
 325     case 1:
 326         switch (pfl->cmd) {
 327         case 0x10: /* Single Byte Program */
 328         case 0x40: /* Single Byte Program */
 329             DPRINTF("%s: Single Byte Program\n", __func__);
 330             if (!pfl->ro) {
 331                 pflash_data_write(pfl, offset, value, width, be);
 332                 pflash_update(pfl, offset, width);
 333             } else {
 334                 pfl->status |= 0x10; /* Programming error */
 335             }
 336             pfl->status |= 0x80; /* Ready! */
 337             pfl->wcycle = 0;
 338         break;
 339         case 0x20: /* Block erase */
 340         case 0x28:
 341             if (cmd == 0xd0) { /* confirm */
 342                 pfl->wcycle = 0;
 343                 pfl->status |= 0x80;
 344             } else if (cmd == 0xff) { /* read array mode */
 345                 goto reset_flash;
 346             } else
 347                 goto error_flash;
 348
 349             break;
 350         case 0xe8:
 351             DPRINTF("%s: block write of %x bytes\n", __func__, value);
 352             pfl->counter = value;
 353             pfl->wcycle++;
 354             break;
 355         case 0x60:
 356             if (cmd == 0xd0) {
 357                 pfl->wcycle = 0;
 358                 pfl->status |= 0x80;
 359             } else if (cmd == 0x01) {
 360                 pfl->wcycle = 0;
 361                 pfl->status |= 0x80;
 362             } else if (cmd == 0xff) {
 363                 goto reset_flash;
 364             } else {
 365                 DPRINTF("%s: Unknown (un)locking command\n", __func__);
 366                 goto reset_flash;
 367             }
 368             break;
 369         case 0x98:
 370             if (cmd == 0xff) {
 371                 goto reset_flash;
 372             } else {
 373                 DPRINTF("%s: leaving query mode\n", __func__);
 374             }
 375             break;
 376         default:
 377             goto error_flash;
 378         }
 379         break;
 380     case 2:
 381         switch (pfl->cmd) {
 382         case 0xe8: /* Block write */
 383             if (!pfl->ro) {
 384                 pflash_data_write(pfl, offset, value, width, be);
 385             } else {
 386                 pfl->status |= 0x10; /* Programming error */
 387             }
 388
 389             pfl->status |= 0x80;
 390
 391             if (!pfl->counter) {
 392                 target_phys_addr_t mask = pfl->writeblock_size - 1;
 393                 mask = ~mask;
 394
 395                 DPRINTF("%s: block write finished\n", __func__);
 396                 pfl->wcycle++;
 397                 if (!pfl->ro) {
 398                     /* Flush the entire write buffer onto backing storage.  */
 399                     pflash_update(pfl, offset & mask, pfl->writeblock_size);
 400                 } else {
 401                     pfl->status |= 0x10; /* Programming error */
 402                 }
 403             }
 404
 405             pfl->counter--;
 406             break;
 407         default:
 408             goto error_flash;
 409         }
 410         break;
 411     case 3: /* Confirm mode */
 412         switch (pfl->cmd) {
 413         case 0xe8: /* Block write */
 414             if (cmd == 0xd0) {
 415                 pfl->wcycle = 0;
 416                 pfl->status |= 0x80;
 417             } else {
 418                 DPRINTF("%s: unknown command for \"write block\"\n", __func__);
 419                 PFLASH_BUG("Write block confirm");
 420                 goto reset_flash;
 421             }
 422             break;
 423         default:
 424             goto error_flash;
 425         }
 426         break;
 427     default:
 428         /* Should never happen */
 429         DPRINTF("%s: invalid write state\n",  __func__);
 430         goto reset_flash;
 431     }
 432     return;
 433
 434  error_flash:
 435     printf("%s: Unimplemented flash cmd sequence "
 436            "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)\n",
 437            __func__, offset, pfl->wcycle, pfl->cmd, value);
 438
 439  reset_flash:
 440     memory_region_rom_device_set_readable(&pfl->mem, true);
 441
 442     pfl->bypass = 0;
 443     pfl->wcycle = 0;
 444     pfl->cmd = 0;
 445     return;
 446 }
 447
 448
 449 static uint32_t pflash_readb_be(void *opaque, target_phys_addr_t addr)
 450 {
 451     return pflash_read(opaque, addr, 1, 1);
 452 }
 453
 454 static uint32_t pflash_readb_le(void *opaque, target_phys_addr_t addr)
 455 {
 456     return pflash_read(opaque, addr, 1, 0);
 457 }
 458
 459 static uint32_t pflash_readw_be(void *opaque, target_phys_addr_t addr)
 460 {
 461     pflash_t *pfl = opaque;
 462
 463     return pflash_read(pfl, addr, 2, 1);
 464 }
 465
 466 static uint32_t pflash_readw_le(void *opaque, target_phys_addr_t addr)
 467 {
 468     pflash_t *pfl = opaque;
 469
 470     return pflash_read(pfl, addr, 2, 0);
 471 }
 472
 473 static uint32_t pflash_readl_be(void *opaque, target_phys_addr_t addr)
 474 {
 475     pflash_t *pfl = opaque;
 476
 477     return pflash_read(pfl, addr, 4, 1);
 478 }
 479
 480 static uint32_t pflash_readl_le(void *opaque, target_phys_addr_t addr)
 481 {
 482     pflash_t *pfl = opaque;
 483
 484     return pflash_read(pfl, addr, 4, 0);
 485 }
 486
 487 static void pflash_writeb_be(void *opaque, target_phys_addr_t addr,
 488                              uint32_t value)
 489 {
 490     pflash_write(opaque, addr, value, 1, 1);
 491 }
 492
 493 static void pflash_writeb_le(void *opaque, target_phys_addr_t addr,
 494                              uint32_t value)
 495 {
 496     pflash_write(opaque, addr, value, 1, 0);
 497 }
 498
 499 static void pflash_writew_be(void *opaque, target_phys_addr_t addr,
 500                              uint32_t value)
 501 {
 502     pflash_t *pfl = opaque;
 503
 504     pflash_write(pfl, addr, value, 2, 1);
 505 }
 506
 507 static void pflash_writew_le(void *opaque, target_phys_addr_t addr,
 508                              uint32_t value)
 509 {
 510     pflash_t *pfl = opaque;
 511
 512     pflash_write(pfl, addr, value, 2, 0);
 513 }
 514
 515 static void pflash_writel_be(void *opaque, target_phys_addr_t addr,
 516                              uint32_t value)
 517 {
 518     pflash_t *pfl = opaque;
 519
 520     pflash_write(pfl, addr, value, 4, 1);
 521 }
 522
 523 static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
 524                              uint32_t value)
 525 {
 526     pflash_t *pfl = opaque;
 527
 528     pflash_write(pfl, addr, value, 4, 0);
 529 }
 530
 531 static const MemoryRegionOps pflash_cfi01_ops_be = {
 532     .old_mmio = {
 533         .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
 534         .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
 535     },
 536     .endianness = DEVICE_NATIVE_ENDIAN,
 537 };
 538
 539 static const MemoryRegionOps pflash_cfi01_ops_le = {
 540     .old_mmio = {
 541         .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
 542         .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
 543     },
 544     .endianness = DEVICE_NATIVE_ENDIAN,
 545 };
 546
 547 pflash_t *pflash_cfi01_register(target_phys_addr_t base,
 548                                 DeviceState *qdev, const char *name,
 549                                 target_phys_addr_t size,
 550                                 BlockDriverState *bs, uint32_t sector_len,
 551                                 int nb_blocs, int width,
 552                                 uint16_t id0, uint16_t id1,
 553                                 uint16_t id2, uint16_t id3, int be)
 554 {
 555     pflash_t *pfl;
 556     target_phys_addr_t total_len;
 557     int ret;
 558
 559     total_len = sector_len * nb_blocs;
 560
 561     /* XXX: to be fixed */
 562 #if 0
 563     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 564         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 565         return NULL;
 566 #endif
 567
 568     pfl = g_malloc0(sizeof(pflash_t));
 569
 570     memory_region_init_rom_device(
 571         &pfl->mem, be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
 572         name, size);
 573     vmstate_register_ram(&pfl->mem, qdev);
 574     pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
 575     memory_region_add_subregion(get_system_memory(), base, &pfl->mem);
 576
 577     pfl->bs = bs;
 578     if (pfl->bs) {
 579         /* read the initial flash content */
 580         ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
 581         if (ret < 0) {
 582             memory_region_del_subregion(get_system_memory(), &pfl->mem);
 583             vmstate_unregister_ram(&pfl->mem, qdev);
 584             memory_region_destroy(&pfl->mem);
 585             g_free(pfl);
 586             return NULL;
 587         }
 588         bdrv_attach_dev_nofail(pfl->bs, pfl);
 589     }
 590
 591     if (pfl->bs) {
 592         pfl->ro = bdrv_is_read_only(pfl->bs);
 593     } else {
 594         pfl->ro = 0;
 595     }
 596
 597     pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl);
 598     pfl->base = base;
 599     pfl->sector_len = sector_len;
 600     pfl->total_len = total_len;
 601     pfl->width = width;
 602     pfl->wcycle = 0;
 603     pfl->cmd = 0;
 604     pfl->status = 0;
 605     pfl->ident[0] = id0;
 606     pfl->ident[1] = id1;
 607     pfl->ident[2] = id2;
 608     pfl->ident[3] = id3;
 609     /* Hardcoded CFI table */
 610     pfl->cfi_len = 0x52;
 611     /* Standard "QRY" string */
 612     pfl->cfi_table[0x10] = 'Q';
 613     pfl->cfi_table[0x11] = 'R';
 614     pfl->cfi_table[0x12] = 'Y';
 615     /* Command set (Intel) */
 616     pfl->cfi_table[0x13] = 0x01;
 617     pfl->cfi_table[0x14] = 0x00;
 618     /* Primary extended table address (none) */
 619     pfl->cfi_table[0x15] = 0x31;
 620     pfl->cfi_table[0x16] = 0x00;
 621     /* Alternate command set (none) */
 622     pfl->cfi_table[0x17] = 0x00;
 623     pfl->cfi_table[0x18] = 0x00;
 624     /* Alternate extended table (none) */
 625     pfl->cfi_table[0x19] = 0x00;
 626     pfl->cfi_table[0x1A] = 0x00;
 627     /* Vcc min */
 628     pfl->cfi_table[0x1B] = 0x45;
 629     /* Vcc max */
 630     pfl->cfi_table[0x1C] = 0x55;
 631     /* Vpp min (no Vpp pin) */
 632     pfl->cfi_table[0x1D] = 0x00;
 633     /* Vpp max (no Vpp pin) */
 634     pfl->cfi_table[0x1E] = 0x00;
 635     /* Reserved */
 636     pfl->cfi_table[0x1F] = 0x07;
 637     /* Timeout for min size buffer write */
 638     pfl->cfi_table[0x20] = 0x07;
 639     /* Typical timeout for block erase */
 640     pfl->cfi_table[0x21] = 0x0a;
 641     /* Typical timeout for full chip erase (4096 ms) */
 642     pfl->cfi_table[0x22] = 0x00;
 643     /* Reserved */
 644     pfl->cfi_table[0x23] = 0x04;
 645     /* Max timeout for buffer write */
 646     pfl->cfi_table[0x24] = 0x04;
 647     /* Max timeout for block erase */
 648     pfl->cfi_table[0x25] = 0x04;
 649     /* Max timeout for chip erase */
 650     pfl->cfi_table[0x26] = 0x00;
 651     /* Device size */
 652     pfl->cfi_table[0x27] = ctz32(total_len); // + 1;
 653     /* Flash device interface (8 & 16 bits) */
 654     pfl->cfi_table[0x28] = 0x02;
 655     pfl->cfi_table[0x29] = 0x00;
 656     /* Max number of bytes in multi-bytes write */
 657     if (width == 1) {
 658         pfl->cfi_table[0x2A] = 0x08;
 659     } else {
 660         pfl->cfi_table[0x2A] = 0x0B;
 661     }
 662     pfl->writeblock_size = 1 << pfl->cfi_table[0x2A];
 663
 664     pfl->cfi_table[0x2B] = 0x00;
 665     /* Number of erase block regions (uniform) */
 666     pfl->cfi_table[0x2C] = 0x01;
 667     /* Erase block region 1 */
 668     pfl->cfi_table[0x2D] = nb_blocs - 1;
 669     pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8;
 670     pfl->cfi_table[0x2F] = sector_len >> 8;
 671     pfl->cfi_table[0x30] = sector_len >> 16;
 672
 673     /* Extended */
 674     pfl->cfi_table[0x31] = 'P';
 675     pfl->cfi_table[0x32] = 'R';
 676     pfl->cfi_table[0x33] = 'I';
 677
 678     pfl->cfi_table[0x34] = '1';
 679     pfl->cfi_table[0x35] = '0';
 680
 681     pfl->cfi_table[0x36] = 0x00;
 682     pfl->cfi_table[0x37] = 0x00;
 683     pfl->cfi_table[0x38] = 0x00;
 684     pfl->cfi_table[0x39] = 0x00;
 685
 686     pfl->cfi_table[0x3a] = 0x00;
 687
 688     pfl->cfi_table[0x3b] = 0x00;
 689     pfl->cfi_table[0x3c] = 0x00;
 690
 691     pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */
 692
 693     return pfl;
 694 }
 695
 696 MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)
 697 {
 698     return &fl->mem;
 699 }