hw/armv7m_nvic.c

   1 /*
   2  * ARM Nested Vectored Interrupt Controller
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  *
   9  * The ARMv7M System controller is fairly tightly tied in with the
  10  * NVIC.  Much of that is also implemented here.
  11  */
  12
  13 #include "sysbus.h"
  14 #include "qemu-timer.h"
  15 #include "arm-misc.h"
  16 #include "exec-memory.h"
  17 #include "arm_gic_internal.h"
  18
  19 typedef struct {
  20     gic_state gic;
  21     struct {
  22         uint32_t control;
  23         uint32_t reload;
  24         int64_t tick;
  25         QEMUTimer *timer;
  26     } systick;
  27     MemoryRegion sysregmem;
  28     MemoryRegion gic_iomem_alias;
  29     MemoryRegion container;
  30     uint32_t num_irq;
  31 } nvic_state;
  32
  33 #define TYPE_NVIC "armv7m_nvic"
  34 /**
  35  * NVICClass:
  36  * @parent_reset: the parent class' reset handler.
  37  *
  38  * A model of the v7M NVIC and System Controller
  39  */
  40 typedef struct NVICClass {
  41     /*< private >*/
  42     ARMGICClass parent_class;
  43     /*< public >*/
  44     int (*parent_init)(SysBusDevice *dev);
  45     void (*parent_reset)(DeviceState *dev);
  46 } NVICClass;
  47
  48 #define NVIC_CLASS(klass) \
  49     OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
  50 #define NVIC_GET_CLASS(obj) \
  51     OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
  52 #define NVIC(obj) \
  53     OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
  54
  55 static const uint8_t nvic_id[] = {
  56     0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
  57 };
  58
  59 /* qemu timers run at 1GHz.   We want something closer to 1MHz.  */
  60 #define SYSTICK_SCALE 1000ULL
  61
  62 #define SYSTICK_ENABLE    (1 << 0)
  63 #define SYSTICK_TICKINT   (1 << 1)
  64 #define SYSTICK_CLKSOURCE (1 << 2)
  65 #define SYSTICK_COUNTFLAG (1 << 16)
  66
  67 int system_clock_scale;
  68
  69 /* Conversion factor from qemu timer to SysTick frequencies.  */
  70 static inline int64_t systick_scale(nvic_state *s)
  71 {
  72     if (s->systick.control & SYSTICK_CLKSOURCE)
  73         return system_clock_scale;
  74     else
  75         return 1000;
  76 }
  77
  78 static void systick_reload(nvic_state *s, int reset)
  79 {
  80     if (reset)
  81         s->systick.tick = qemu_get_clock_ns(vm_clock);
  82     s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
  83     qemu_mod_timer(s->systick.timer, s->systick.tick);
  84 }
  85
  86 static void systick_timer_tick(void * opaque)
  87 {
  88     nvic_state *s = (nvic_state *)opaque;
  89     s->systick.control |= SYSTICK_COUNTFLAG;
  90     if (s->systick.control & SYSTICK_TICKINT) {
  91         /* Trigger the interrupt.  */
  92         armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
  93     }
  94     if (s->systick.reload == 0) {
  95         s->systick.control &= ~SYSTICK_ENABLE;
  96     } else {
  97         systick_reload(s, 0);
  98     }
  99 }
 100
 101 static void systick_reset(nvic_state *s)
 102 {
 103     s->systick.control = 0;
 104     s->systick.reload = 0;
 105     s->systick.tick = 0;
 106     qemu_del_timer(s->systick.timer);
 107 }
 108
 109 /* The external routines use the hardware vector numbering, ie. the first
 110    IRQ is #16.  The internal GIC routines use #32 as the first IRQ.  */
 111 void armv7m_nvic_set_pending(void *opaque, int irq)
 112 {
 113     nvic_state *s = (nvic_state *)opaque;
 114     if (irq >= 16)
 115         irq += 16;
 116     gic_set_pending_private(&s->gic, 0, irq);
 117 }
 118
 119 /* Make pending IRQ active.  */
 120 int armv7m_nvic_acknowledge_irq(void *opaque)
 121 {
 122     nvic_state *s = (nvic_state *)opaque;
 123     uint32_t irq;
 124
 125     irq = gic_acknowledge_irq(&s->gic, 0);
 126     if (irq == 1023)
 127         hw_error("Interrupt but no vector\n");
 128     if (irq >= 32)
 129         irq -= 16;
 130     return irq;
 131 }
 132
 133 void armv7m_nvic_complete_irq(void *opaque, int irq)
 134 {
 135     nvic_state *s = (nvic_state *)opaque;
 136     if (irq >= 16)
 137         irq += 16;
 138     gic_complete_irq(&s->gic, 0, irq);
 139 }
 140
 141 static uint32_t nvic_readl(void *opaque, uint32_t offset)
 142 {
 143     nvic_state *s = (nvic_state *)opaque;
 144     uint32_t val;
 145     int irq;
 146
 147     switch (offset) {
 148     case 4: /* Interrupt Control Type.  */
 149         return (s->num_irq / 32) - 1;
 150     case 0x10: /* SysTick Control and Status.  */
 151         val = s->systick.control;
 152         s->systick.control &= ~SYSTICK_COUNTFLAG;
 153         return val;
 154     case 0x14: /* SysTick Reload Value.  */
 155         return s->systick.reload;
 156     case 0x18: /* SysTick Current Value.  */
 157         {
 158             int64_t t;
 159             if ((s->systick.control & SYSTICK_ENABLE) == 0)
 160                 return 0;
 161             t = qemu_get_clock_ns(vm_clock);
 162             if (t >= s->systick.tick)
 163                 return 0;
 164             val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
 165             /* The interrupt in triggered when the timer reaches zero.
 166                However the counter is not reloaded until the next clock
 167                tick.  This is a hack to return zero during the first tick.  */
 168             if (val > s->systick.reload)
 169                 val = 0;
 170             return val;
 171         }
 172     case 0x1c: /* SysTick Calibration Value.  */
 173         return 10000;
 174     case 0xd00: /* CPUID Base.  */
 175         return cpu_single_env->cp15.c0_cpuid;
 176     case 0xd04: /* Interrypt Control State.  */
 177         /* VECTACTIVE */
 178         val = s->gic.running_irq[0];
 179         if (val == 1023) {
 180             val = 0;
 181         } else if (val >= 32) {
 182             val -= 16;
 183         }
 184         /* RETTOBASE */
 185         if (s->gic.running_irq[0] == 1023
 186                 || s->gic.last_active[s->gic.running_irq[0]][0] == 1023) {
 187             val |= (1 << 11);
 188         }
 189         /* VECTPENDING */
 190         if (s->gic.current_pending[0] != 1023)
 191             val |= (s->gic.current_pending[0] << 12);
 192         /* ISRPENDING */
 193         for (irq = 32; irq < s->num_irq; irq++) {
 194             if (s->gic.irq_state[irq].pending) {
 195                 val |= (1 << 22);
 196                 break;
 197             }
 198         }
 199         /* PENDSTSET */
 200         if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
 201             val |= (1 << 26);
 202         /* PENDSVSET */
 203         if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
 204             val |= (1 << 28);
 205         /* NMIPENDSET */
 206         if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
 207             val |= (1 << 31);
 208         return val;
 209     case 0xd08: /* Vector Table Offset.  */
 210         return cpu_single_env->v7m.vecbase;
 211     case 0xd0c: /* Application Interrupt/Reset Control.  */
 212         return 0xfa05000;
 213     case 0xd10: /* System Control.  */
 214         /* TODO: Implement SLEEPONEXIT.  */
 215         return 0;
 216     case 0xd14: /* Configuration Control.  */
 217         /* TODO: Implement Configuration Control bits.  */
 218         return 0;
 219     case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
 220         irq = offset - 0xd14;
 221         val = 0;
 222         val |= s->gic.priority1[irq++][0];
 223         val |= s->gic.priority1[irq++][0] << 8;
 224         val |= s->gic.priority1[irq++][0] << 16;
 225         val |= s->gic.priority1[irq][0] << 24;
 226         return val;
 227     case 0xd24: /* System Handler Status.  */
 228         val = 0;
 229         if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
 230         if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
 231         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
 232         if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
 233         if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
 234         if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
 235         if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
 236         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
 237         if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
 238         if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
 239         if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
 240         if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
 241         if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
 242         if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
 243         return val;
 244     case 0xd28: /* Configurable Fault Status.  */
 245         /* TODO: Implement Fault Status.  */
 246         hw_error("Not implemented: Configurable Fault Status.");
 247         return 0;
 248     case 0xd2c: /* Hard Fault Status.  */
 249     case 0xd30: /* Debug Fault Status.  */
 250     case 0xd34: /* Mem Manage Address.  */
 251     case 0xd38: /* Bus Fault Address.  */
 252     case 0xd3c: /* Aux Fault Status.  */
 253         /* TODO: Implement fault status registers.  */
 254         goto bad_reg;
 255     case 0xd40: /* PFR0.  */
 256         return 0x00000030;
 257     case 0xd44: /* PRF1.  */
 258         return 0x00000200;
 259     case 0xd48: /* DFR0.  */
 260         return 0x00100000;
 261     case 0xd4c: /* AFR0.  */
 262         return 0x00000000;
 263     case 0xd50: /* MMFR0.  */
 264         return 0x00000030;
 265     case 0xd54: /* MMFR1.  */
 266         return 0x00000000;
 267     case 0xd58: /* MMFR2.  */
 268         return 0x00000000;
 269     case 0xd5c: /* MMFR3.  */
 270         return 0x00000000;
 271     case 0xd60: /* ISAR0.  */
 272         return 0x01141110;
 273     case 0xd64: /* ISAR1.  */
 274         return 0x02111000;
 275     case 0xd68: /* ISAR2.  */
 276         return 0x21112231;
 277     case 0xd6c: /* ISAR3.  */
 278         return 0x01111110;
 279     case 0xd70: /* ISAR4.  */
 280         return 0x01310102;
 281     /* TODO: Implement debug registers.  */
 282     default:
 283     bad_reg:
 284         hw_error("NVIC: Bad read offset 0x%x\n", offset);
 285     }
 286 }
 287
 288 static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
 289 {
 290     nvic_state *s = (nvic_state *)opaque;
 291     uint32_t oldval;
 292     switch (offset) {
 293     case 0x10: /* SysTick Control and Status.  */
 294         oldval = s->systick.control;
 295         s->systick.control &= 0xfffffff8;
 296         s->systick.control |= value & 7;
 297         if ((oldval ^ value) & SYSTICK_ENABLE) {
 298             int64_t now = qemu_get_clock_ns(vm_clock);
 299             if (value & SYSTICK_ENABLE) {
 300                 if (s->systick.tick) {
 301                     s->systick.tick += now;
 302                     qemu_mod_timer(s->systick.timer, s->systick.tick);
 303                 } else {
 304                     systick_reload(s, 1);
 305                 }
 306             } else {
 307                 qemu_del_timer(s->systick.timer);
 308                 s->systick.tick -= now;
 309                 if (s->systick.tick < 0)
 310                   s->systick.tick = 0;
 311             }
 312         } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
 313             /* This is a hack. Force the timer to be reloaded
 314                when the reference clock is changed.  */
 315             systick_reload(s, 1);
 316         }
 317         break;
 318     case 0x14: /* SysTick Reload Value.  */
 319         s->systick.reload = value;
 320         break;
 321     case 0x18: /* SysTick Current Value.  Writes reload the timer.  */
 322         systick_reload(s, 1);
 323         s->systick.control &= ~SYSTICK_COUNTFLAG;
 324         break;
 325     case 0xd04: /* Interrupt Control State.  */
 326         if (value & (1 << 31)) {
 327             armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
 328         }
 329         if (value & (1 << 28)) {
 330             armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
 331         } else if (value & (1 << 27)) {
 332             s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
 333             gic_update(&s->gic);
 334         }
 335         if (value & (1 << 26)) {
 336             armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
 337         } else if (value & (1 << 25)) {
 338             s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
 339             gic_update(&s->gic);
 340         }
 341         break;
 342     case 0xd08: /* Vector Table Offset.  */
 343         cpu_single_env->v7m.vecbase = value & 0xffffff80;
 344         break;
 345     case 0xd0c: /* Application Interrupt/Reset Control.  */
 346         if ((value >> 16) == 0x05fa) {
 347             if (value & 2) {
 348                 hw_error("VECTCLRACTIVE not implemented");
 349             }
 350             if (value & 5) {
 351                 hw_error("System reset");
 352             }
 353         }
 354         break;
 355     case 0xd10: /* System Control.  */
 356     case 0xd14: /* Configuration Control.  */
 357         /* TODO: Implement control registers.  */
 358         goto bad_reg;
 359     case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
 360         {
 361             int irq;
 362             irq = offset - 0xd14;
 363             s->gic.priority1[irq++][0] = value & 0xff;
 364             s->gic.priority1[irq++][0] = (value >> 8) & 0xff;
 365             s->gic.priority1[irq++][0] = (value >> 16) & 0xff;
 366             s->gic.priority1[irq][0] = (value >> 24) & 0xff;
 367             gic_update(&s->gic);
 368         }
 369         break;
 370     case 0xd24: /* System Handler Control.  */
 371         /* TODO: Real hardware allows you to set/clear the active bits
 372            under some circumstances.  We don't implement this.  */
 373         s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
 374         s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
 375         s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
 376         break;
 377     case 0xd28: /* Configurable Fault Status.  */
 378     case 0xd2c: /* Hard Fault Status.  */
 379     case 0xd30: /* Debug Fault Status.  */
 380     case 0xd34: /* Mem Manage Address.  */
 381     case 0xd38: /* Bus Fault Address.  */
 382     case 0xd3c: /* Aux Fault Status.  */
 383         goto bad_reg;
 384     case 0xf00: /* Software Triggered Interrupt Register */
 385         if ((value & 0x1ff) < s->num_irq) {
 386             gic_set_pending_private(&s->gic, 0, value & 0x1ff);
 387         }
 388         break;
 389     default:
 390     bad_reg:
 391         hw_error("NVIC: Bad write offset 0x%x\n", offset);
 392     }
 393 }
 394
 395 static uint64_t nvic_sysreg_read(void *opaque, target_phys_addr_t addr,
 396                                  unsigned size)
 397 {
 398     /* At the moment we only support the ID registers for byte/word access.
 399      * This is not strictly correct as a few of the other registers also
 400      * allow byte access.
 401      */
 402     uint32_t offset = addr;
 403     if (offset >= 0xfe0) {
 404         if (offset & 3) {
 405             return 0;
 406         }
 407         return nvic_id[(offset - 0xfe0) >> 2];
 408     }
 409     if (size == 4) {
 410         return nvic_readl(opaque, offset);
 411     }
 412     hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
 413 }
 414
 415 static void nvic_sysreg_write(void *opaque, target_phys_addr_t addr,
 416                               uint64_t value, unsigned size)
 417 {
 418     uint32_t offset = addr;
 419     if (size == 4) {
 420         nvic_writel(opaque, offset, value);
 421         return;
 422     }
 423     hw_error("NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
 424 }
 425
 426 static const MemoryRegionOps nvic_sysreg_ops = {
 427     .read = nvic_sysreg_read,
 428     .write = nvic_sysreg_write,
 429     .endianness = DEVICE_NATIVE_ENDIAN,
 430 };
 431
 432 static const VMStateDescription vmstate_nvic = {
 433     .name = "armv7m_nvic",
 434     .version_id = 1,
 435     .minimum_version_id = 1,
 436     .minimum_version_id_old = 1,
 437     .fields      = (VMStateField[]) {
 438         VMSTATE_UINT32(systick.control, nvic_state),
 439         VMSTATE_UINT32(systick.reload, nvic_state),
 440         VMSTATE_INT64(systick.tick, nvic_state),
 441         VMSTATE_TIMER(systick.timer, nvic_state),
 442         VMSTATE_END_OF_LIST()
 443     }
 444 };
 445
 446 static void armv7m_nvic_reset(DeviceState *dev)
 447 {
 448     nvic_state *s = NVIC(dev);
 449     NVICClass *nc = NVIC_GET_CLASS(s);
 450     nc->parent_reset(dev);
 451     /* Common GIC reset resets to disabled; the NVIC doesn't have
 452      * per-CPU interfaces so mark our non-existent CPU interface
 453      * as enabled by default.
 454      */
 455     s->gic.cpu_enabled[0] = 1;
 456     /* The NVIC as a whole is always enabled. */
 457     s->gic.enabled = 1;
 458     systick_reset(s);
 459 }
 460
 461 static int armv7m_nvic_init(SysBusDevice *dev)
 462 {
 463     nvic_state *s = NVIC(dev);
 464     NVICClass *nc = NVIC_GET_CLASS(s);
 465
 466     /* The NVIC always has only one CPU */
 467     s->gic.num_cpu = 1;
 468     /* Tell the common code we're an NVIC */
 469     s->gic.revision = 0xffffffff;
 470     s->num_irq = s->gic.num_irq;
 471     nc->parent_init(dev);
 472     gic_init_irqs_and_distributor(&s->gic, s->num_irq);
 473     /* The NVIC and system controller register area looks like this:
 474      *  0..0xff : system control registers, including systick
 475      *  0x100..0xcff : GIC-like registers
 476      *  0xd00..0xfff : system control registers
 477      * We use overlaying to put the GIC like registers
 478      * over the top of the system control register region.
 479      */
 480     memory_region_init(&s->container, "nvic", 0x1000);
 481     /* The system register region goes at the bottom of the priority
 482      * stack as it covers the whole page.
 483      */
 484     memory_region_init_io(&s->sysregmem, &nvic_sysreg_ops, s,
 485                           "nvic_sysregs", 0x1000);
 486     memory_region_add_subregion(&s->container, 0, &s->sysregmem);
 487     /* Alias the GIC region so we can get only the section of it
 488      * we need, and layer it on top of the system register region.
 489      */
 490     memory_region_init_alias(&s->gic_iomem_alias, "nvic-gic", &s->gic.iomem,
 491                              0x100, 0xc00);
 492     memory_region_add_subregion_overlap(&s->container, 0x100,
 493                                         &s->gic_iomem_alias, 1);
 494     /* Map the whole thing into system memory at the location required
 495      * by the v7M architecture.
 496      */
 497     memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
 498     s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);
 499     return 0;
 500 }
 501
 502 static void armv7m_nvic_instance_init(Object *obj)
 503 {
 504     /* We have a different default value for the num-irq property
 505      * than our superclass. This function runs after qdev init
 506      * has set the defaults from the Property array and before
 507      * any user-specified property setting, so just modify the
 508      * value in the gic_state struct.
 509      */
 510     gic_state *s = ARM_GIC_COMMON(obj);
 511     /* The ARM v7m may have anything from 0 to 496 external interrupt
 512      * IRQ lines. We default to 64. Other boards may differ and should
 513      * set the num-irq property appropriately.
 514      */
 515     s->num_irq = 64;
 516 }
 517
 518 static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
 519 {
 520     NVICClass *nc = NVIC_CLASS(klass);
 521     DeviceClass *dc = DEVICE_CLASS(klass);
 522     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 523
 524     nc->parent_reset = dc->reset;
 525     nc->parent_init = sdc->init;
 526     sdc->init = armv7m_nvic_init;
 527     dc->vmsd  = &vmstate_nvic;
 528     dc->reset = armv7m_nvic_reset;
 529 }
 530
 531 static TypeInfo armv7m_nvic_info = {
 532     .name          = TYPE_NVIC,
 533     .parent        = TYPE_ARM_GIC_COMMON,
 534     .instance_init = armv7m_nvic_instance_init,
 535     .instance_size = sizeof(nvic_state),
 536     .class_init    = armv7m_nvic_class_init,
 537     .class_size    = sizeof(NVICClass),
 538 };
 539
 540 static void armv7m_nvic_register_types(void)
 541 {
 542     type_register_static(&armv7m_nvic_info);
 543 }
 544
 545 type_init(armv7m_nvic_register_types)