2 * MIPS32 emulation for qemu: main translation routines.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2006 Marius Groeger (FPU operations)
6 * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
32 #include "qemu-common.h"
38 //#define MIPS_DEBUG_DISAS
39 //#define MIPS_DEBUG_SIGN_EXTENSIONS
41 /* MIPS major opcodes */
42 #define MASK_OP_MAJOR(op) (op & (0x3F << 26))
45 /* indirect opcode tables */
46 OPC_SPECIAL
= (0x00 << 26),
47 OPC_REGIMM
= (0x01 << 26),
48 OPC_CP0
= (0x10 << 26),
49 OPC_CP1
= (0x11 << 26),
50 OPC_CP2
= (0x12 << 26),
51 OPC_CP3
= (0x13 << 26),
52 OPC_SPECIAL2
= (0x1C << 26),
53 OPC_SPECIAL3
= (0x1F << 26),
54 /* arithmetic with immediate */
55 OPC_ADDI
= (0x08 << 26),
56 OPC_ADDIU
= (0x09 << 26),
57 OPC_SLTI
= (0x0A << 26),
58 OPC_SLTIU
= (0x0B << 26),
59 /* logic with immediate */
60 OPC_ANDI
= (0x0C << 26),
61 OPC_ORI
= (0x0D << 26),
62 OPC_XORI
= (0x0E << 26),
63 OPC_LUI
= (0x0F << 26),
64 /* arithmetic with immediate */
65 OPC_DADDI
= (0x18 << 26),
66 OPC_DADDIU
= (0x19 << 26),
67 /* Jump and branches */
69 OPC_JAL
= (0x03 << 26),
70 OPC_BEQ
= (0x04 << 26), /* Unconditional if rs = rt = 0 (B) */
71 OPC_BEQL
= (0x14 << 26),
72 OPC_BNE
= (0x05 << 26),
73 OPC_BNEL
= (0x15 << 26),
74 OPC_BLEZ
= (0x06 << 26),
75 OPC_BLEZL
= (0x16 << 26),
76 OPC_BGTZ
= (0x07 << 26),
77 OPC_BGTZL
= (0x17 << 26),
78 OPC_JALX
= (0x1D << 26), /* MIPS 16 only */
80 OPC_LDL
= (0x1A << 26),
81 OPC_LDR
= (0x1B << 26),
82 OPC_LB
= (0x20 << 26),
83 OPC_LH
= (0x21 << 26),
84 OPC_LWL
= (0x22 << 26),
85 OPC_LW
= (0x23 << 26),
86 OPC_LBU
= (0x24 << 26),
87 OPC_LHU
= (0x25 << 26),
88 OPC_LWR
= (0x26 << 26),
89 OPC_LWU
= (0x27 << 26),
90 OPC_SB
= (0x28 << 26),
91 OPC_SH
= (0x29 << 26),
92 OPC_SWL
= (0x2A << 26),
93 OPC_SW
= (0x2B << 26),
94 OPC_SDL
= (0x2C << 26),
95 OPC_SDR
= (0x2D << 26),
96 OPC_SWR
= (0x2E << 26),
97 OPC_LL
= (0x30 << 26),
98 OPC_LLD
= (0x34 << 26),
99 OPC_LD
= (0x37 << 26),
100 OPC_SC
= (0x38 << 26),
101 OPC_SCD
= (0x3C << 26),
102 OPC_SD
= (0x3F << 26),
103 /* Floating point load/store */
104 OPC_LWC1
= (0x31 << 26),
105 OPC_LWC2
= (0x32 << 26),
106 OPC_LDC1
= (0x35 << 26),
107 OPC_LDC2
= (0x36 << 26),
108 OPC_SWC1
= (0x39 << 26),
109 OPC_SWC2
= (0x3A << 26),
110 OPC_SDC1
= (0x3D << 26),
111 OPC_SDC2
= (0x3E << 26),
112 /* MDMX ASE specific */
113 OPC_MDMX
= (0x1E << 26),
114 /* Cache and prefetch */
115 OPC_CACHE
= (0x2F << 26),
116 OPC_PREF
= (0x33 << 26),
117 /* Reserved major opcode */
118 OPC_MAJOR3B_RESERVED
= (0x3B << 26),
121 /* MIPS special opcodes */
122 #define MASK_SPECIAL(op) MASK_OP_MAJOR(op) | (op & 0x3F)
126 OPC_SLL
= 0x00 | OPC_SPECIAL
,
127 /* NOP is SLL r0, r0, 0 */
128 /* SSNOP is SLL r0, r0, 1 */
129 /* EHB is SLL r0, r0, 3 */
130 OPC_SRL
= 0x02 | OPC_SPECIAL
, /* also ROTR */
131 OPC_SRA
= 0x03 | OPC_SPECIAL
,
132 OPC_SLLV
= 0x04 | OPC_SPECIAL
,
133 OPC_SRLV
= 0x06 | OPC_SPECIAL
, /* also ROTRV */
134 OPC_SRAV
= 0x07 | OPC_SPECIAL
,
135 OPC_DSLLV
= 0x14 | OPC_SPECIAL
,
136 OPC_DSRLV
= 0x16 | OPC_SPECIAL
, /* also DROTRV */
137 OPC_DSRAV
= 0x17 | OPC_SPECIAL
,
138 OPC_DSLL
= 0x38 | OPC_SPECIAL
,
139 OPC_DSRL
= 0x3A | OPC_SPECIAL
, /* also DROTR */
140 OPC_DSRA
= 0x3B | OPC_SPECIAL
,
141 OPC_DSLL32
= 0x3C | OPC_SPECIAL
,
142 OPC_DSRL32
= 0x3E | OPC_SPECIAL
, /* also DROTR32 */
143 OPC_DSRA32
= 0x3F | OPC_SPECIAL
,
144 /* Multiplication / division */
145 OPC_MULT
= 0x18 | OPC_SPECIAL
,
146 OPC_MULTU
= 0x19 | OPC_SPECIAL
,
147 OPC_DIV
= 0x1A | OPC_SPECIAL
,
148 OPC_DIVU
= 0x1B | OPC_SPECIAL
,
149 OPC_DMULT
= 0x1C | OPC_SPECIAL
,
150 OPC_DMULTU
= 0x1D | OPC_SPECIAL
,
151 OPC_DDIV
= 0x1E | OPC_SPECIAL
,
152 OPC_DDIVU
= 0x1F | OPC_SPECIAL
,
153 /* 2 registers arithmetic / logic */
154 OPC_ADD
= 0x20 | OPC_SPECIAL
,
155 OPC_ADDU
= 0x21 | OPC_SPECIAL
,
156 OPC_SUB
= 0x22 | OPC_SPECIAL
,
157 OPC_SUBU
= 0x23 | OPC_SPECIAL
,
158 OPC_AND
= 0x24 | OPC_SPECIAL
,
159 OPC_OR
= 0x25 | OPC_SPECIAL
,
160 OPC_XOR
= 0x26 | OPC_SPECIAL
,
161 OPC_NOR
= 0x27 | OPC_SPECIAL
,
162 OPC_SLT
= 0x2A | OPC_SPECIAL
,
163 OPC_SLTU
= 0x2B | OPC_SPECIAL
,
164 OPC_DADD
= 0x2C | OPC_SPECIAL
,
165 OPC_DADDU
= 0x2D | OPC_SPECIAL
,
166 OPC_DSUB
= 0x2E | OPC_SPECIAL
,
167 OPC_DSUBU
= 0x2F | OPC_SPECIAL
,
169 OPC_JR
= 0x08 | OPC_SPECIAL
, /* Also JR.HB */
170 OPC_JALR
= 0x09 | OPC_SPECIAL
, /* Also JALR.HB */
172 OPC_TGE
= 0x30 | OPC_SPECIAL
,
173 OPC_TGEU
= 0x31 | OPC_SPECIAL
,
174 OPC_TLT
= 0x32 | OPC_SPECIAL
,
175 OPC_TLTU
= 0x33 | OPC_SPECIAL
,
176 OPC_TEQ
= 0x34 | OPC_SPECIAL
,
177 OPC_TNE
= 0x36 | OPC_SPECIAL
,
178 /* HI / LO registers load & stores */
179 OPC_MFHI
= 0x10 | OPC_SPECIAL
,
180 OPC_MTHI
= 0x11 | OPC_SPECIAL
,
181 OPC_MFLO
= 0x12 | OPC_SPECIAL
,
182 OPC_MTLO
= 0x13 | OPC_SPECIAL
,
183 /* Conditional moves */
184 OPC_MOVZ
= 0x0A | OPC_SPECIAL
,
185 OPC_MOVN
= 0x0B | OPC_SPECIAL
,
187 OPC_MOVCI
= 0x01 | OPC_SPECIAL
,
190 OPC_PMON
= 0x05 | OPC_SPECIAL
, /* unofficial */
191 OPC_SYSCALL
= 0x0C | OPC_SPECIAL
,
192 OPC_BREAK
= 0x0D | OPC_SPECIAL
,
193 OPC_SPIM
= 0x0E | OPC_SPECIAL
, /* unofficial */
194 OPC_SYNC
= 0x0F | OPC_SPECIAL
,
196 OPC_SPECIAL15_RESERVED
= 0x15 | OPC_SPECIAL
,
197 OPC_SPECIAL28_RESERVED
= 0x28 | OPC_SPECIAL
,
198 OPC_SPECIAL29_RESERVED
= 0x29 | OPC_SPECIAL
,
199 OPC_SPECIAL35_RESERVED
= 0x35 | OPC_SPECIAL
,
200 OPC_SPECIAL37_RESERVED
= 0x37 | OPC_SPECIAL
,
201 OPC_SPECIAL39_RESERVED
= 0x39 | OPC_SPECIAL
,
202 OPC_SPECIAL3D_RESERVED
= 0x3D | OPC_SPECIAL
,
205 /* Multiplication variants of the vr54xx. */
206 #define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6))
209 OPC_VR54XX_MULS
= (0x03 << 6) | OPC_MULT
,
210 OPC_VR54XX_MULSU
= (0x03 << 6) | OPC_MULTU
,
211 OPC_VR54XX_MACC
= (0x05 << 6) | OPC_MULT
,
212 OPC_VR54XX_MACCU
= (0x05 << 6) | OPC_MULTU
,
213 OPC_VR54XX_MSAC
= (0x07 << 6) | OPC_MULT
,
214 OPC_VR54XX_MSACU
= (0x07 << 6) | OPC_MULTU
,
215 OPC_VR54XX_MULHI
= (0x09 << 6) | OPC_MULT
,
216 OPC_VR54XX_MULHIU
= (0x09 << 6) | OPC_MULTU
,
217 OPC_VR54XX_MULSHI
= (0x0B << 6) | OPC_MULT
,
218 OPC_VR54XX_MULSHIU
= (0x0B << 6) | OPC_MULTU
,
219 OPC_VR54XX_MACCHI
= (0x0D << 6) | OPC_MULT
,
220 OPC_VR54XX_MACCHIU
= (0x0D << 6) | OPC_MULTU
,
221 OPC_VR54XX_MSACHI
= (0x0F << 6) | OPC_MULT
,
222 OPC_VR54XX_MSACHIU
= (0x0F << 6) | OPC_MULTU
,
225 /* REGIMM (rt field) opcodes */
226 #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16))
229 OPC_BLTZ
= (0x00 << 16) | OPC_REGIMM
,
230 OPC_BLTZL
= (0x02 << 16) | OPC_REGIMM
,
231 OPC_BGEZ
= (0x01 << 16) | OPC_REGIMM
,
232 OPC_BGEZL
= (0x03 << 16) | OPC_REGIMM
,
233 OPC_BLTZAL
= (0x10 << 16) | OPC_REGIMM
,
234 OPC_BLTZALL
= (0x12 << 16) | OPC_REGIMM
,
235 OPC_BGEZAL
= (0x11 << 16) | OPC_REGIMM
,
236 OPC_BGEZALL
= (0x13 << 16) | OPC_REGIMM
,
237 OPC_TGEI
= (0x08 << 16) | OPC_REGIMM
,
238 OPC_TGEIU
= (0x09 << 16) | OPC_REGIMM
,
239 OPC_TLTI
= (0x0A << 16) | OPC_REGIMM
,
240 OPC_TLTIU
= (0x0B << 16) | OPC_REGIMM
,
241 OPC_TEQI
= (0x0C << 16) | OPC_REGIMM
,
242 OPC_TNEI
= (0x0E << 16) | OPC_REGIMM
,
243 OPC_SYNCI
= (0x1F << 16) | OPC_REGIMM
,
246 /* Special2 opcodes */
247 #define MASK_SPECIAL2(op) MASK_OP_MAJOR(op) | (op & 0x3F)
250 /* Multiply & xxx operations */
251 OPC_MADD
= 0x00 | OPC_SPECIAL2
,
252 OPC_MADDU
= 0x01 | OPC_SPECIAL2
,
253 OPC_MUL
= 0x02 | OPC_SPECIAL2
,
254 OPC_MSUB
= 0x04 | OPC_SPECIAL2
,
255 OPC_MSUBU
= 0x05 | OPC_SPECIAL2
,
257 OPC_CLZ
= 0x20 | OPC_SPECIAL2
,
258 OPC_CLO
= 0x21 | OPC_SPECIAL2
,
259 OPC_DCLZ
= 0x24 | OPC_SPECIAL2
,
260 OPC_DCLO
= 0x25 | OPC_SPECIAL2
,
262 OPC_SDBBP
= 0x3F | OPC_SPECIAL2
,
265 /* Special3 opcodes */
266 #define MASK_SPECIAL3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
269 OPC_EXT
= 0x00 | OPC_SPECIAL3
,
270 OPC_DEXTM
= 0x01 | OPC_SPECIAL3
,
271 OPC_DEXTU
= 0x02 | OPC_SPECIAL3
,
272 OPC_DEXT
= 0x03 | OPC_SPECIAL3
,
273 OPC_INS
= 0x04 | OPC_SPECIAL3
,
274 OPC_DINSM
= 0x05 | OPC_SPECIAL3
,
275 OPC_DINSU
= 0x06 | OPC_SPECIAL3
,
276 OPC_DINS
= 0x07 | OPC_SPECIAL3
,
277 OPC_FORK
= 0x08 | OPC_SPECIAL3
,
278 OPC_YIELD
= 0x09 | OPC_SPECIAL3
,
279 OPC_BSHFL
= 0x20 | OPC_SPECIAL3
,
280 OPC_DBSHFL
= 0x24 | OPC_SPECIAL3
,
281 OPC_RDHWR
= 0x3B | OPC_SPECIAL3
,
285 #define MASK_BSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
288 OPC_WSBH
= (0x02 << 6) | OPC_BSHFL
,
289 OPC_SEB
= (0x10 << 6) | OPC_BSHFL
,
290 OPC_SEH
= (0x18 << 6) | OPC_BSHFL
,
294 #define MASK_DBSHFL(op) MASK_SPECIAL3(op) | (op & (0x1F << 6))
297 OPC_DSBH
= (0x02 << 6) | OPC_DBSHFL
,
298 OPC_DSHD
= (0x05 << 6) | OPC_DBSHFL
,
301 /* Coprocessor 0 (rs field) */
302 #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
305 OPC_MFC0
= (0x00 << 21) | OPC_CP0
,
306 OPC_DMFC0
= (0x01 << 21) | OPC_CP0
,
307 OPC_MTC0
= (0x04 << 21) | OPC_CP0
,
308 OPC_DMTC0
= (0x05 << 21) | OPC_CP0
,
309 OPC_MFTR
= (0x08 << 21) | OPC_CP0
,
310 OPC_RDPGPR
= (0x0A << 21) | OPC_CP0
,
311 OPC_MFMC0
= (0x0B << 21) | OPC_CP0
,
312 OPC_MTTR
= (0x0C << 21) | OPC_CP0
,
313 OPC_WRPGPR
= (0x0E << 21) | OPC_CP0
,
314 OPC_C0
= (0x10 << 21) | OPC_CP0
,
315 OPC_C0_FIRST
= (0x10 << 21) | OPC_CP0
,
316 OPC_C0_LAST
= (0x1F << 21) | OPC_CP0
,
320 #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF)
323 OPC_DMT
= 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
324 OPC_EMT
= 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0
,
325 OPC_DVPE
= 0x01 | (0 << 5) | OPC_MFMC0
,
326 OPC_EVPE
= 0x01 | (1 << 5) | OPC_MFMC0
,
327 OPC_DI
= (0 << 5) | (0x0C << 11) | OPC_MFMC0
,
328 OPC_EI
= (1 << 5) | (0x0C << 11) | OPC_MFMC0
,
331 /* Coprocessor 0 (with rs == C0) */
332 #define MASK_C0(op) MASK_CP0(op) | (op & 0x3F)
335 OPC_TLBR
= 0x01 | OPC_C0
,
336 OPC_TLBWI
= 0x02 | OPC_C0
,
337 OPC_TLBWR
= 0x06 | OPC_C0
,
338 OPC_TLBP
= 0x08 | OPC_C0
,
339 OPC_RFE
= 0x10 | OPC_C0
,
340 OPC_ERET
= 0x18 | OPC_C0
,
341 OPC_DERET
= 0x1F | OPC_C0
,
342 OPC_WAIT
= 0x20 | OPC_C0
,
345 /* Coprocessor 1 (rs field) */
346 #define MASK_CP1(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
349 OPC_MFC1
= (0x00 << 21) | OPC_CP1
,
350 OPC_DMFC1
= (0x01 << 21) | OPC_CP1
,
351 OPC_CFC1
= (0x02 << 21) | OPC_CP1
,
352 OPC_MFHC1
= (0x03 << 21) | OPC_CP1
,
353 OPC_MTC1
= (0x04 << 21) | OPC_CP1
,
354 OPC_DMTC1
= (0x05 << 21) | OPC_CP1
,
355 OPC_CTC1
= (0x06 << 21) | OPC_CP1
,
356 OPC_MTHC1
= (0x07 << 21) | OPC_CP1
,
357 OPC_BC1
= (0x08 << 21) | OPC_CP1
, /* bc */
358 OPC_BC1ANY2
= (0x09 << 21) | OPC_CP1
,
359 OPC_BC1ANY4
= (0x0A << 21) | OPC_CP1
,
360 OPC_S_FMT
= (0x10 << 21) | OPC_CP1
, /* 16: fmt=single fp */
361 OPC_D_FMT
= (0x11 << 21) | OPC_CP1
, /* 17: fmt=double fp */
362 OPC_E_FMT
= (0x12 << 21) | OPC_CP1
, /* 18: fmt=extended fp */
363 OPC_Q_FMT
= (0x13 << 21) | OPC_CP1
, /* 19: fmt=quad fp */
364 OPC_W_FMT
= (0x14 << 21) | OPC_CP1
, /* 20: fmt=32bit fixed */
365 OPC_L_FMT
= (0x15 << 21) | OPC_CP1
, /* 21: fmt=64bit fixed */
366 OPC_PS_FMT
= (0x16 << 21) | OPC_CP1
, /* 22: fmt=paired single fp */
369 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
370 #define MASK_BC1(op) MASK_CP1(op) | (op & (0x3 << 16))
373 OPC_BC1F
= (0x00 << 16) | OPC_BC1
,
374 OPC_BC1T
= (0x01 << 16) | OPC_BC1
,
375 OPC_BC1FL
= (0x02 << 16) | OPC_BC1
,
376 OPC_BC1TL
= (0x03 << 16) | OPC_BC1
,
380 OPC_BC1FANY2
= (0x00 << 16) | OPC_BC1ANY2
,
381 OPC_BC1TANY2
= (0x01 << 16) | OPC_BC1ANY2
,
385 OPC_BC1FANY4
= (0x00 << 16) | OPC_BC1ANY4
,
386 OPC_BC1TANY4
= (0x01 << 16) | OPC_BC1ANY4
,
389 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
392 OPC_MFC2
= (0x00 << 21) | OPC_CP2
,
393 OPC_DMFC2
= (0x01 << 21) | OPC_CP2
,
394 OPC_CFC2
= (0x02 << 21) | OPC_CP2
,
395 OPC_MFHC2
= (0x03 << 21) | OPC_CP2
,
396 OPC_MTC2
= (0x04 << 21) | OPC_CP2
,
397 OPC_DMTC2
= (0x05 << 21) | OPC_CP2
,
398 OPC_CTC2
= (0x06 << 21) | OPC_CP2
,
399 OPC_MTHC2
= (0x07 << 21) | OPC_CP2
,
400 OPC_BC2
= (0x08 << 21) | OPC_CP2
,
403 #define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
406 OPC_LWXC1
= 0x00 | OPC_CP3
,
407 OPC_LDXC1
= 0x01 | OPC_CP3
,
408 OPC_LUXC1
= 0x05 | OPC_CP3
,
409 OPC_SWXC1
= 0x08 | OPC_CP3
,
410 OPC_SDXC1
= 0x09 | OPC_CP3
,
411 OPC_SUXC1
= 0x0D | OPC_CP3
,
412 OPC_PREFX
= 0x0F | OPC_CP3
,
413 OPC_ALNV_PS
= 0x1E | OPC_CP3
,
414 OPC_MADD_S
= 0x20 | OPC_CP3
,
415 OPC_MADD_D
= 0x21 | OPC_CP3
,
416 OPC_MADD_PS
= 0x26 | OPC_CP3
,
417 OPC_MSUB_S
= 0x28 | OPC_CP3
,
418 OPC_MSUB_D
= 0x29 | OPC_CP3
,
419 OPC_MSUB_PS
= 0x2E | OPC_CP3
,
420 OPC_NMADD_S
= 0x30 | OPC_CP3
,
421 OPC_NMADD_D
= 0x31 | OPC_CP3
,
422 OPC_NMADD_PS
= 0x36 | OPC_CP3
,
423 OPC_NMSUB_S
= 0x38 | OPC_CP3
,
424 OPC_NMSUB_D
= 0x39 | OPC_CP3
,
425 OPC_NMSUB_PS
= 0x3E | OPC_CP3
,
428 /* global register indices */
429 static TCGv_ptr cpu_env
;
430 static TCGv cpu_gpr
[32], cpu_PC
;
431 static TCGv cpu_HI
[MIPS_DSP_ACC
], cpu_LO
[MIPS_DSP_ACC
], cpu_ACX
[MIPS_DSP_ACC
];
432 static TCGv cpu_dspctrl
, btarget
, bcond
;
433 static TCGv_i32 hflags
;
434 static TCGv_i32 fpu_fcr0
, fpu_fcr31
;
436 #include "gen-icount.h"
438 #define gen_helper_0i(name, arg) do { \
439 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
440 gen_helper_##name(helper_tmp); \
441 tcg_temp_free_i32(helper_tmp); \
444 #define gen_helper_1i(name, arg1, arg2) do { \
445 TCGv_i32 helper_tmp = tcg_const_i32(arg2); \
446 gen_helper_##name(arg1, helper_tmp); \
447 tcg_temp_free_i32(helper_tmp); \
450 #define gen_helper_2i(name, arg1, arg2, arg3) do { \
451 TCGv_i32 helper_tmp = tcg_const_i32(arg3); \
452 gen_helper_##name(arg1, arg2, helper_tmp); \
453 tcg_temp_free_i32(helper_tmp); \
456 #define gen_helper_3i(name, arg1, arg2, arg3, arg4) do { \
457 TCGv_i32 helper_tmp = tcg_const_i32(arg4); \
458 gen_helper_##name(arg1, arg2, arg3, helper_tmp); \
459 tcg_temp_free_i32(helper_tmp); \
462 typedef struct DisasContext
{
463 struct TranslationBlock
*tb
;
464 target_ulong pc
, saved_pc
;
466 int singlestep_enabled
;
467 /* Routine used to access memory */
469 uint32_t hflags
, saved_hflags
;
471 target_ulong btarget
;
475 BS_NONE
= 0, /* We go out of the TB without reaching a branch or an
476 * exception condition */
477 BS_STOP
= 1, /* We want to stop translation for any reason */
478 BS_BRANCH
= 2, /* We reached a branch condition */
479 BS_EXCP
= 3, /* We reached an exception condition */
482 static const char *regnames
[] =
483 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
484 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
485 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
486 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", };
488 static const char *regnames_HI
[] =
489 { "HI0", "HI1", "HI2", "HI3", };
491 static const char *regnames_LO
[] =
492 { "LO0", "LO1", "LO2", "LO3", };
494 static const char *regnames_ACX
[] =
495 { "ACX0", "ACX1", "ACX2", "ACX3", };
497 static const char *fregnames
[] =
498 { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
499 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
500 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
501 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", };
503 #ifdef MIPS_DEBUG_DISAS
504 #define MIPS_DEBUG(fmt, ...) \
505 qemu_log_mask(CPU_LOG_TB_IN_ASM, \
506 TARGET_FMT_lx ": %08x " fmt "\n", \
507 ctx->pc, ctx->opcode , ## __VA_ARGS__)
508 #define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
510 #define MIPS_DEBUG(fmt, ...) do { } while(0)
511 #define LOG_DISAS(...) do { } while (0)
514 #define MIPS_INVAL(op) \
516 MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \
517 ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \
520 /* General purpose registers moves. */
521 static inline void gen_load_gpr (TCGv t
, int reg
)
524 tcg_gen_movi_tl(t
, 0);
526 tcg_gen_mov_tl(t
, cpu_gpr
[reg
]);
529 static inline void gen_store_gpr (TCGv t
, int reg
)
532 tcg_gen_mov_tl(cpu_gpr
[reg
], t
);
535 /* Moves to/from ACX register. */
536 static inline void gen_load_ACX (TCGv t
, int reg
)
538 tcg_gen_mov_tl(t
, cpu_ACX
[reg
]);
541 static inline void gen_store_ACX (TCGv t
, int reg
)
543 tcg_gen_mov_tl(cpu_ACX
[reg
], t
);
546 /* Moves to/from shadow registers. */
547 static inline void gen_load_srsgpr (int from
, int to
)
549 TCGv t0
= tcg_temp_new();
552 tcg_gen_movi_tl(t0
, 0);
554 TCGv_i32 t2
= tcg_temp_new_i32();
555 TCGv_ptr addr
= tcg_temp_new_ptr();
557 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
558 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
559 tcg_gen_andi_i32(t2
, t2
, 0xf);
560 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
561 tcg_gen_ext_i32_ptr(addr
, t2
);
562 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
564 tcg_gen_ld_tl(t0
, addr
, sizeof(target_ulong
) * from
);
565 tcg_temp_free_ptr(addr
);
566 tcg_temp_free_i32(t2
);
568 gen_store_gpr(t0
, to
);
572 static inline void gen_store_srsgpr (int from
, int to
)
575 TCGv t0
= tcg_temp_new();
576 TCGv_i32 t2
= tcg_temp_new_i32();
577 TCGv_ptr addr
= tcg_temp_new_ptr();
579 gen_load_gpr(t0
, from
);
580 tcg_gen_ld_i32(t2
, cpu_env
, offsetof(CPUState
, CP0_SRSCtl
));
581 tcg_gen_shri_i32(t2
, t2
, CP0SRSCtl_PSS
);
582 tcg_gen_andi_i32(t2
, t2
, 0xf);
583 tcg_gen_muli_i32(t2
, t2
, sizeof(target_ulong
) * 32);
584 tcg_gen_ext_i32_ptr(addr
, t2
);
585 tcg_gen_add_ptr(addr
, cpu_env
, addr
);
587 tcg_gen_st_tl(t0
, addr
, sizeof(target_ulong
) * to
);
588 tcg_temp_free_ptr(addr
);
589 tcg_temp_free_i32(t2
);
594 /* Floating point register moves. */
595 static inline void gen_load_fpr32 (TCGv_i32 t
, int reg
)
597 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
600 static inline void gen_store_fpr32 (TCGv_i32 t
, int reg
)
602 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[FP_ENDIAN_IDX
]));
605 static inline void gen_load_fpr32h (TCGv_i32 t
, int reg
)
607 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
610 static inline void gen_store_fpr32h (TCGv_i32 t
, int reg
)
612 tcg_gen_st_i32(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].w
[!FP_ENDIAN_IDX
]));
615 static inline void gen_load_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
617 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
618 tcg_gen_ld_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
620 TCGv_i32 t0
= tcg_temp_new_i32();
621 TCGv_i32 t1
= tcg_temp_new_i32();
622 gen_load_fpr32(t0
, reg
& ~1);
623 gen_load_fpr32(t1
, reg
| 1);
624 tcg_gen_concat_i32_i64(t
, t0
, t1
);
625 tcg_temp_free_i32(t0
);
626 tcg_temp_free_i32(t1
);
630 static inline void gen_store_fpr64 (DisasContext
*ctx
, TCGv_i64 t
, int reg
)
632 if (ctx
->hflags
& MIPS_HFLAG_F64
) {
633 tcg_gen_st_i64(t
, cpu_env
, offsetof(CPUState
, active_fpu
.fpr
[reg
].d
));
635 TCGv_i64 t0
= tcg_temp_new_i64();
636 TCGv_i32 t1
= tcg_temp_new_i32();
637 tcg_gen_trunc_i64_i32(t1
, t
);
638 gen_store_fpr32(t1
, reg
& ~1);
639 tcg_gen_shri_i64(t0
, t
, 32);
640 tcg_gen_trunc_i64_i32(t1
, t0
);
641 gen_store_fpr32(t1
, reg
| 1);
642 tcg_temp_free_i32(t1
);
643 tcg_temp_free_i64(t0
);
647 static inline int get_fp_bit (int cc
)
655 #define FOP_CONDS(type, fmt, bits) \
656 static inline void gen_cmp ## type ## _ ## fmt(int n, TCGv_i##bits a, \
657 TCGv_i##bits b, int cc) \
660 case 0: gen_helper_2i(cmp ## type ## _ ## fmt ## _f, a, b, cc); break;\
661 case 1: gen_helper_2i(cmp ## type ## _ ## fmt ## _un, a, b, cc); break;\
662 case 2: gen_helper_2i(cmp ## type ## _ ## fmt ## _eq, a, b, cc); break;\
663 case 3: gen_helper_2i(cmp ## type ## _ ## fmt ## _ueq, a, b, cc); break;\
664 case 4: gen_helper_2i(cmp ## type ## _ ## fmt ## _olt, a, b, cc); break;\
665 case 5: gen_helper_2i(cmp ## type ## _ ## fmt ## _ult, a, b, cc); break;\
666 case 6: gen_helper_2i(cmp ## type ## _ ## fmt ## _ole, a, b, cc); break;\
667 case 7: gen_helper_2i(cmp ## type ## _ ## fmt ## _ule, a, b, cc); break;\
668 case 8: gen_helper_2i(cmp ## type ## _ ## fmt ## _sf, a, b, cc); break;\
669 case 9: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngle, a, b, cc); break;\
670 case 10: gen_helper_2i(cmp ## type ## _ ## fmt ## _seq, a, b, cc); break;\
671 case 11: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngl, a, b, cc); break;\
672 case 12: gen_helper_2i(cmp ## type ## _ ## fmt ## _lt, a, b, cc); break;\
673 case 13: gen_helper_2i(cmp ## type ## _ ## fmt ## _nge, a, b, cc); break;\
674 case 14: gen_helper_2i(cmp ## type ## _ ## fmt ## _le, a, b, cc); break;\
675 case 15: gen_helper_2i(cmp ## type ## _ ## fmt ## _ngt, a, b, cc); break;\
681 FOP_CONDS(abs
, d
, 64)
683 FOP_CONDS(abs
, s
, 32)
685 FOP_CONDS(abs
, ps
, 64)
689 #define OP_COND(name, cond) \
690 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, TCGv t1) \
692 int l1 = gen_new_label(); \
693 int l2 = gen_new_label(); \
695 tcg_gen_brcond_tl(cond, t0, t1, l1); \
696 tcg_gen_movi_tl(ret, 0); \
699 tcg_gen_movi_tl(ret, 1); \
702 OP_COND(eq
, TCG_COND_EQ
);
703 OP_COND(ne
, TCG_COND_NE
);
704 OP_COND(ge
, TCG_COND_GE
);
705 OP_COND(geu
, TCG_COND_GEU
);
706 OP_COND(lt
, TCG_COND_LT
);
707 OP_COND(ltu
, TCG_COND_LTU
);
710 #define OP_CONDI(name, cond) \
711 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0, target_ulong val) \
713 int l1 = gen_new_label(); \
714 int l2 = gen_new_label(); \
716 tcg_gen_brcondi_tl(cond, t0, val, l1); \
717 tcg_gen_movi_tl(ret, 0); \
720 tcg_gen_movi_tl(ret, 1); \
723 OP_CONDI(lti
, TCG_COND_LT
);
724 OP_CONDI(ltiu
, TCG_COND_LTU
);
727 #define OP_CONDZ(name, cond) \
728 static inline void glue(gen_op_, name) (TCGv ret, TCGv t0) \
730 int l1 = gen_new_label(); \
731 int l2 = gen_new_label(); \
733 tcg_gen_brcondi_tl(cond, t0, 0, l1); \
734 tcg_gen_movi_tl(ret, 0); \
737 tcg_gen_movi_tl(ret, 1); \
740 OP_CONDZ(gez
, TCG_COND_GE
);
741 OP_CONDZ(gtz
, TCG_COND_GT
);
742 OP_CONDZ(lez
, TCG_COND_LE
);
743 OP_CONDZ(ltz
, TCG_COND_LT
);
746 static inline void gen_save_pc(target_ulong pc
)
748 tcg_gen_movi_tl(cpu_PC
, pc
);
751 static inline void save_cpu_state (DisasContext
*ctx
, int do_save_pc
)
753 LOG_DISAS("hflags %08x saved %08x\n", ctx
->hflags
, ctx
->saved_hflags
);
754 if (do_save_pc
&& ctx
->pc
!= ctx
->saved_pc
) {
755 gen_save_pc(ctx
->pc
);
756 ctx
->saved_pc
= ctx
->pc
;
758 if (ctx
->hflags
!= ctx
->saved_hflags
) {
759 tcg_gen_movi_i32(hflags
, ctx
->hflags
);
760 ctx
->saved_hflags
= ctx
->hflags
;
761 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
767 tcg_gen_movi_tl(btarget
, ctx
->btarget
);
773 static inline void restore_cpu_state (CPUState
*env
, DisasContext
*ctx
)
775 ctx
->saved_hflags
= ctx
->hflags
;
776 switch (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
782 ctx
->btarget
= env
->btarget
;
788 generate_exception_err (DisasContext
*ctx
, int excp
, int err
)
790 TCGv_i32 texcp
= tcg_const_i32(excp
);
791 TCGv_i32 terr
= tcg_const_i32(err
);
792 save_cpu_state(ctx
, 1);
793 gen_helper_raise_exception_err(texcp
, terr
);
794 tcg_temp_free_i32(terr
);
795 tcg_temp_free_i32(texcp
);
799 generate_exception (DisasContext
*ctx
, int excp
)
801 save_cpu_state(ctx
, 1);
802 gen_helper_0i(raise_exception
, excp
);
805 /* Addresses computation */
806 static inline void gen_op_addr_add (DisasContext
*ctx
, TCGv ret
, TCGv arg0
, TCGv arg1
)
808 tcg_gen_add_tl(ret
, arg0
, arg1
);
810 #if defined(TARGET_MIPS64)
811 /* For compatibility with 32-bit code, data reference in user mode
812 with Status_UX = 0 should be casted to 32-bit and sign extended.
813 See the MIPS64 PRA manual, section 4.10. */
814 if (((ctx
->hflags
& MIPS_HFLAG_KSU
) == MIPS_HFLAG_UM
) &&
815 !(ctx
->hflags
& MIPS_HFLAG_UX
)) {
816 tcg_gen_ext32s_i64(ret
, ret
);
821 static inline void check_cp0_enabled(DisasContext
*ctx
)
823 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_CP0
)))
824 generate_exception_err(ctx
, EXCP_CpU
, 1);
827 static inline void check_cp1_enabled(DisasContext
*ctx
)
829 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_FPU
)))
830 generate_exception_err(ctx
, EXCP_CpU
, 1);
833 /* Verify that the processor is running with COP1X instructions enabled.
834 This is associated with the nabla symbol in the MIPS32 and MIPS64
837 static inline void check_cop1x(DisasContext
*ctx
)
839 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_COP1X
)))
840 generate_exception(ctx
, EXCP_RI
);
843 /* Verify that the processor is running with 64-bit floating-point
844 operations enabled. */
846 static inline void check_cp1_64bitmode(DisasContext
*ctx
)
848 if (unlikely(~ctx
->hflags
& (MIPS_HFLAG_F64
| MIPS_HFLAG_COP1X
)))
849 generate_exception(ctx
, EXCP_RI
);
853 * Verify if floating point register is valid; an operation is not defined
854 * if bit 0 of any register specification is set and the FR bit in the
855 * Status register equals zero, since the register numbers specify an
856 * even-odd pair of adjacent coprocessor general registers. When the FR bit
857 * in the Status register equals one, both even and odd register numbers
858 * are valid. This limitation exists only for 64 bit wide (d,l,ps) registers.
860 * Multiple 64 bit wide registers can be checked by calling
861 * gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
863 static inline void check_cp1_registers(DisasContext
*ctx
, int regs
)
865 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_F64
) && (regs
& 1)))
866 generate_exception(ctx
, EXCP_RI
);
869 /* This code generates a "reserved instruction" exception if the
870 CPU does not support the instruction set corresponding to flags. */
871 static inline void check_insn(CPUState
*env
, DisasContext
*ctx
, int flags
)
873 if (unlikely(!(env
->insn_flags
& flags
)))
874 generate_exception(ctx
, EXCP_RI
);
877 /* This code generates a "reserved instruction" exception if 64-bit
878 instructions are not enabled. */
879 static inline void check_mips_64(DisasContext
*ctx
)
881 if (unlikely(!(ctx
->hflags
& MIPS_HFLAG_64
)))
882 generate_exception(ctx
, EXCP_RI
);
885 /* load/store instructions. */
886 #define OP_LD(insn,fname) \
887 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
889 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
896 #if defined(TARGET_MIPS64)
902 #define OP_ST(insn,fname) \
903 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \
905 tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \
910 #if defined(TARGET_MIPS64)
915 #ifdef CONFIG_USER_ONLY
916 #define OP_LD_ATOMIC(insn,fname) \
917 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
919 TCGv t0 = tcg_temp_new(); \
920 tcg_gen_mov_tl(t0, arg1); \
921 tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \
922 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
923 tcg_gen_st_tl(ret, cpu_env, offsetof(CPUState, llval)); \
927 #define OP_LD_ATOMIC(insn,fname) \
928 static inline void op_ldst_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \
930 gen_helper_2i(insn, ret, arg1, ctx->mem_idx); \
933 OP_LD_ATOMIC(ll
,ld32s
);
934 #if defined(TARGET_MIPS64)
935 OP_LD_ATOMIC(lld
,ld64
);
939 #ifdef CONFIG_USER_ONLY
940 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
941 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
943 TCGv t0 = tcg_temp_new(); \
944 int l1 = gen_new_label(); \
945 int l2 = gen_new_label(); \
947 tcg_gen_andi_tl(t0, arg2, almask); \
948 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); \
949 tcg_gen_st_tl(arg2, cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
950 generate_exception(ctx, EXCP_AdES); \
952 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, lladdr)); \
953 tcg_gen_brcond_tl(TCG_COND_NE, arg2, t0, l2); \
954 tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \
955 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, llreg)); \
956 tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUState, llnewval)); \
957 gen_helper_0i(raise_exception, EXCP_SC); \
959 tcg_gen_movi_tl(t0, 0); \
960 gen_store_gpr(t0, rt); \
964 #define OP_ST_ATOMIC(insn,fname,ldname,almask) \
965 static inline void op_ldst_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) \
967 TCGv t0 = tcg_temp_new(); \
968 gen_helper_3i(insn, t0, arg1, arg2, ctx->mem_idx); \
969 gen_store_gpr(t0, rt); \
973 OP_ST_ATOMIC(sc
,st32
,ld32s
,0x3);
974 #if defined(TARGET_MIPS64)
975 OP_ST_ATOMIC(scd
,st64
,ld64
,0x7);
980 static void gen_ldst (DisasContext
*ctx
, uint32_t opc
, int rt
,
981 int base
, int16_t offset
)
983 const char *opn
= "ldst";
984 TCGv t0
= tcg_temp_new();
985 TCGv t1
= tcg_temp_new();
988 tcg_gen_movi_tl(t0
, offset
);
989 } else if (offset
== 0) {
990 gen_load_gpr(t0
, base
);
992 tcg_gen_movi_tl(t0
, offset
);
993 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
995 /* Don't do NOP if destination is zero: we must perform the actual
998 #if defined(TARGET_MIPS64)
1000 save_cpu_state(ctx
, 0);
1001 op_ldst_lwu(t0
, t0
, ctx
);
1002 gen_store_gpr(t0
, rt
);
1006 save_cpu_state(ctx
, 0);
1007 op_ldst_ld(t0
, t0
, ctx
);
1008 gen_store_gpr(t0
, rt
);
1012 save_cpu_state(ctx
, 0);
1013 op_ldst_lld(t0
, t0
, ctx
);
1014 gen_store_gpr(t0
, rt
);
1018 save_cpu_state(ctx
, 0);
1019 gen_load_gpr(t1
, rt
);
1020 op_ldst_sd(t1
, t0
, ctx
);
1024 save_cpu_state(ctx
, 1);
1025 gen_load_gpr(t1
, rt
);
1026 gen_helper_3i(ldl
, t1
, t1
, t0
, ctx
->mem_idx
);
1027 gen_store_gpr(t1
, rt
);
1031 save_cpu_state(ctx
, 1);
1032 gen_load_gpr(t1
, rt
);
1033 gen_helper_2i(sdl
, t1
, t0
, ctx
->mem_idx
);
1037 save_cpu_state(ctx
, 1);
1038 gen_load_gpr(t1
, rt
);
1039 gen_helper_3i(ldr
, t1
, t1
, t0
, ctx
->mem_idx
);
1040 gen_store_gpr(t1
, rt
);
1044 save_cpu_state(ctx
, 1);
1045 gen_load_gpr(t1
, rt
);
1046 gen_helper_2i(sdr
, t1
, t0
, ctx
->mem_idx
);
1051 save_cpu_state(ctx
, 0);
1052 op_ldst_lw(t0
, t0
, ctx
);
1053 gen_store_gpr(t0
, rt
);
1057 save_cpu_state(ctx
, 0);
1058 gen_load_gpr(t1
, rt
);
1059 op_ldst_sw(t1
, t0
, ctx
);
1063 save_cpu_state(ctx
, 0);
1064 op_ldst_lh(t0
, t0
, ctx
);
1065 gen_store_gpr(t0
, rt
);
1069 save_cpu_state(ctx
, 0);
1070 gen_load_gpr(t1
, rt
);
1071 op_ldst_sh(t1
, t0
, ctx
);
1075 save_cpu_state(ctx
, 0);
1076 op_ldst_lhu(t0
, t0
, ctx
);
1077 gen_store_gpr(t0
, rt
);
1081 save_cpu_state(ctx
, 0);
1082 op_ldst_lb(t0
, t0
, ctx
);
1083 gen_store_gpr(t0
, rt
);
1087 save_cpu_state(ctx
, 0);
1088 gen_load_gpr(t1
, rt
);
1089 op_ldst_sb(t1
, t0
, ctx
);
1093 save_cpu_state(ctx
, 0);
1094 op_ldst_lbu(t0
, t0
, ctx
);
1095 gen_store_gpr(t0
, rt
);
1099 save_cpu_state(ctx
, 1);
1100 gen_load_gpr(t1
, rt
);
1101 gen_helper_3i(lwl
, t1
, t1
, t0
, ctx
->mem_idx
);
1102 gen_store_gpr(t1
, rt
);
1106 save_cpu_state(ctx
, 1);
1107 gen_load_gpr(t1
, rt
);
1108 gen_helper_2i(swl
, t1
, t0
, ctx
->mem_idx
);
1112 save_cpu_state(ctx
, 1);
1113 gen_load_gpr(t1
, rt
);
1114 gen_helper_3i(lwr
, t1
, t1
, t0
, ctx
->mem_idx
);
1115 gen_store_gpr(t1
, rt
);
1119 save_cpu_state(ctx
, 1);
1120 gen_load_gpr(t1
, rt
);
1121 gen_helper_2i(swr
, t1
, t0
, ctx
->mem_idx
);
1125 save_cpu_state(ctx
, 1);
1126 op_ldst_ll(t0
, t0
, ctx
);
1127 gen_store_gpr(t0
, rt
);
1131 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1136 /* Store conditional */
1137 static void gen_st_cond (DisasContext
*ctx
, uint32_t opc
, int rt
,
1138 int base
, int16_t offset
)
1140 const char *opn
= "st_cond";
1143 t0
= tcg_temp_local_new();
1146 tcg_gen_movi_tl(t0
, offset
);
1147 } else if (offset
== 0) {
1148 gen_load_gpr(t0
, base
);
1150 tcg_gen_movi_tl(t0
, offset
);
1151 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
1153 /* Don't do NOP if destination is zero: we must perform the actual
1156 t1
= tcg_temp_local_new();
1157 gen_load_gpr(t1
, rt
);
1159 #if defined(TARGET_MIPS64)
1161 save_cpu_state(ctx
, 0);
1162 op_ldst_scd(t1
, t0
, rt
, ctx
);
1167 save_cpu_state(ctx
, 1);
1168 op_ldst_sc(t1
, t0
, rt
, ctx
);
1172 MIPS_DEBUG("%s %s, %d(%s)", opn
, regnames
[rt
], offset
, regnames
[base
]);
1177 /* Load and store */
1178 static void gen_flt_ldst (DisasContext
*ctx
, uint32_t opc
, int ft
,
1179 int base
, int16_t offset
)
1181 const char *opn
= "flt_ldst";
1182 TCGv t0
= tcg_temp_new();
1185 tcg_gen_movi_tl(t0
, offset
);
1186 } else if (offset
== 0) {
1187 gen_load_gpr(t0
, base
);
1189 tcg_gen_movi_tl(t0
, offset
);
1190 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
1192 /* Don't do NOP if destination is zero: we must perform the actual
1197 TCGv_i32 fp0
= tcg_temp_new_i32();
1199 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
1200 tcg_gen_trunc_tl_i32(fp0
, t0
);
1201 gen_store_fpr32(fp0
, ft
);
1202 tcg_temp_free_i32(fp0
);
1208 TCGv_i32 fp0
= tcg_temp_new_i32();
1209 TCGv t1
= tcg_temp_new();
1211 gen_load_fpr32(fp0
, ft
);
1212 tcg_gen_extu_i32_tl(t1
, fp0
);
1213 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
1215 tcg_temp_free_i32(fp0
);
1221 TCGv_i64 fp0
= tcg_temp_new_i64();
1223 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
1224 gen_store_fpr64(ctx
, fp0
, ft
);
1225 tcg_temp_free_i64(fp0
);
1231 TCGv_i64 fp0
= tcg_temp_new_i64();
1233 gen_load_fpr64(ctx
, fp0
, ft
);
1234 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
1235 tcg_temp_free_i64(fp0
);
1241 generate_exception(ctx
, EXCP_RI
);
1244 MIPS_DEBUG("%s %s, %d(%s)", opn
, fregnames
[ft
], offset
, regnames
[base
]);
1249 /* Arithmetic with immediate operand */
1250 static void gen_arith_imm (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1251 int rt
, int rs
, int16_t imm
)
1253 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1254 const char *opn
= "imm arith";
1256 if (rt
== 0 && opc
!= OPC_ADDI
&& opc
!= OPC_DADDI
) {
1257 /* If no destination, treat it as a NOP.
1258 For addi, we must generate the overflow exception when needed. */
1265 TCGv t0
= tcg_temp_local_new();
1266 TCGv t1
= tcg_temp_new();
1267 TCGv t2
= tcg_temp_new();
1268 int l1
= gen_new_label();
1270 gen_load_gpr(t1
, rs
);
1271 tcg_gen_addi_tl(t0
, t1
, uimm
);
1272 tcg_gen_ext32s_tl(t0
, t0
);
1274 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1275 tcg_gen_xori_tl(t2
, t0
, uimm
);
1276 tcg_gen_and_tl(t1
, t1
, t2
);
1278 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1280 /* operands of same sign, result different sign */
1281 generate_exception(ctx
, EXCP_OVERFLOW
);
1283 tcg_gen_ext32s_tl(t0
, t0
);
1284 gen_store_gpr(t0
, rt
);
1291 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1292 tcg_gen_ext32s_tl(cpu_gpr
[rt
], cpu_gpr
[rt
]);
1294 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1298 #if defined(TARGET_MIPS64)
1301 TCGv t0
= tcg_temp_local_new();
1302 TCGv t1
= tcg_temp_new();
1303 TCGv t2
= tcg_temp_new();
1304 int l1
= gen_new_label();
1306 gen_load_gpr(t1
, rs
);
1307 tcg_gen_addi_tl(t0
, t1
, uimm
);
1309 tcg_gen_xori_tl(t1
, t1
, ~uimm
);
1310 tcg_gen_xori_tl(t2
, t0
, uimm
);
1311 tcg_gen_and_tl(t1
, t1
, t2
);
1313 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1315 /* operands of same sign, result different sign */
1316 generate_exception(ctx
, EXCP_OVERFLOW
);
1318 gen_store_gpr(t0
, rt
);
1325 tcg_gen_addi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1327 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1333 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1336 /* Logic with immediate operand */
1337 static void gen_logic_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1340 const char *opn
= "imm logic";
1343 /* If no destination, treat it as a NOP. */
1347 uimm
= (uint16_t)imm
;
1350 if (likely(rs
!= 0))
1351 tcg_gen_andi_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1353 tcg_gen_movi_tl(cpu_gpr
[rt
], 0);
1358 tcg_gen_ori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1360 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1364 if (likely(rs
!= 0))
1365 tcg_gen_xori_tl(cpu_gpr
[rt
], cpu_gpr
[rs
], uimm
);
1367 tcg_gen_movi_tl(cpu_gpr
[rt
], uimm
);
1371 tcg_gen_movi_tl(cpu_gpr
[rt
], imm
<< 16);
1375 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1378 /* Set on less than with immediate operand */
1379 static void gen_slt_imm (CPUState
*env
, uint32_t opc
, int rt
, int rs
, int16_t imm
)
1381 target_ulong uimm
= (target_long
)imm
; /* Sign extend to 32/64 bits */
1382 const char *opn
= "imm arith";
1386 /* If no destination, treat it as a NOP. */
1390 t0
= tcg_temp_new();
1391 gen_load_gpr(t0
, rs
);
1394 gen_op_lti(cpu_gpr
[rt
], t0
, uimm
);
1398 gen_op_ltiu(cpu_gpr
[rt
], t0
, uimm
);
1402 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1406 /* Shifts with immediate operand */
1407 static void gen_shift_imm(CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1408 int rt
, int rs
, int16_t imm
)
1410 target_ulong uimm
= ((uint16_t)imm
) & 0x1f;
1411 const char *opn
= "imm shift";
1415 /* If no destination, treat it as a NOP. */
1420 t0
= tcg_temp_new();
1421 gen_load_gpr(t0
, rs
);
1424 tcg_gen_shli_tl(t0
, t0
, uimm
);
1425 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1429 tcg_gen_ext32s_tl(t0
, t0
);
1430 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1434 switch ((ctx
->opcode
>> 21) & 0x1f) {
1437 tcg_gen_ext32u_tl(t0
, t0
);
1438 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1440 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1445 /* rotr is decoded as srl on non-R2 CPUs */
1446 if (env
->insn_flags
& ISA_MIPS32R2
) {
1448 TCGv_i32 t1
= tcg_temp_new_i32();
1450 tcg_gen_trunc_tl_i32(t1
, t0
);
1451 tcg_gen_rotri_i32(t1
, t1
, uimm
);
1452 tcg_gen_ext_i32_tl(cpu_gpr
[rt
], t1
);
1453 tcg_temp_free_i32(t1
);
1458 tcg_gen_ext32u_tl(t0
, t0
);
1459 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1461 tcg_gen_ext32s_tl(cpu_gpr
[rt
], t0
);
1467 MIPS_INVAL("invalid srl flag");
1468 generate_exception(ctx
, EXCP_RI
);
1472 #if defined(TARGET_MIPS64)
1474 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
);
1478 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
);
1482 switch ((ctx
->opcode
>> 21) & 0x1f) {
1484 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1488 /* drotr is decoded as dsrl on non-R2 CPUs */
1489 if (env
->insn_flags
& ISA_MIPS32R2
) {
1491 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
);
1495 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
);
1500 MIPS_INVAL("invalid dsrl flag");
1501 generate_exception(ctx
, EXCP_RI
);
1506 tcg_gen_shli_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1510 tcg_gen_sari_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1514 switch ((ctx
->opcode
>> 21) & 0x1f) {
1516 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1520 /* drotr32 is decoded as dsrl32 on non-R2 CPUs */
1521 if (env
->insn_flags
& ISA_MIPS32R2
) {
1522 tcg_gen_rotri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1525 tcg_gen_shri_tl(cpu_gpr
[rt
], t0
, uimm
+ 32);
1530 MIPS_INVAL("invalid dsrl32 flag");
1531 generate_exception(ctx
, EXCP_RI
);
1537 MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx
, opn
, regnames
[rt
], regnames
[rs
], uimm
);
1542 static void gen_arith (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1543 int rd
, int rs
, int rt
)
1545 const char *opn
= "arith";
1547 if (rd
== 0 && opc
!= OPC_ADD
&& opc
!= OPC_SUB
1548 && opc
!= OPC_DADD
&& opc
!= OPC_DSUB
) {
1549 /* If no destination, treat it as a NOP.
1550 For add & sub, we must generate the overflow exception when needed. */
1558 TCGv t0
= tcg_temp_local_new();
1559 TCGv t1
= tcg_temp_new();
1560 TCGv t2
= tcg_temp_new();
1561 int l1
= gen_new_label();
1563 gen_load_gpr(t1
, rs
);
1564 gen_load_gpr(t2
, rt
);
1565 tcg_gen_add_tl(t0
, t1
, t2
);
1566 tcg_gen_ext32s_tl(t0
, t0
);
1567 tcg_gen_xor_tl(t1
, t1
, t2
);
1568 tcg_gen_not_tl(t1
, t1
);
1569 tcg_gen_xor_tl(t2
, t0
, t2
);
1570 tcg_gen_and_tl(t1
, t1
, t2
);
1572 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1574 /* operands of same sign, result different sign */
1575 generate_exception(ctx
, EXCP_OVERFLOW
);
1577 gen_store_gpr(t0
, rd
);
1583 if (rs
!= 0 && rt
!= 0) {
1584 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1585 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1586 } else if (rs
== 0 && rt
!= 0) {
1587 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1588 } else if (rs
!= 0 && rt
== 0) {
1589 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1591 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1597 TCGv t0
= tcg_temp_local_new();
1598 TCGv t1
= tcg_temp_new();
1599 TCGv t2
= tcg_temp_new();
1600 int l1
= gen_new_label();
1602 gen_load_gpr(t1
, rs
);
1603 gen_load_gpr(t2
, rt
);
1604 tcg_gen_sub_tl(t0
, t1
, t2
);
1605 tcg_gen_ext32s_tl(t0
, t0
);
1606 tcg_gen_xor_tl(t2
, t1
, t2
);
1607 tcg_gen_xor_tl(t1
, t0
, t1
);
1608 tcg_gen_and_tl(t1
, t1
, t2
);
1610 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1612 /* operands of different sign, first operand and result different sign */
1613 generate_exception(ctx
, EXCP_OVERFLOW
);
1615 gen_store_gpr(t0
, rd
);
1621 if (rs
!= 0 && rt
!= 0) {
1622 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1623 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1624 } else if (rs
== 0 && rt
!= 0) {
1625 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1626 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1627 } else if (rs
!= 0 && rt
== 0) {
1628 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1630 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1634 #if defined(TARGET_MIPS64)
1637 TCGv t0
= tcg_temp_local_new();
1638 TCGv t1
= tcg_temp_new();
1639 TCGv t2
= tcg_temp_new();
1640 int l1
= gen_new_label();
1642 gen_load_gpr(t1
, rs
);
1643 gen_load_gpr(t2
, rt
);
1644 tcg_gen_add_tl(t0
, t1
, t2
);
1645 tcg_gen_xor_tl(t1
, t1
, t2
);
1646 tcg_gen_not_tl(t1
, t1
);
1647 tcg_gen_xor_tl(t2
, t0
, t2
);
1648 tcg_gen_and_tl(t1
, t1
, t2
);
1650 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1652 /* operands of same sign, result different sign */
1653 generate_exception(ctx
, EXCP_OVERFLOW
);
1655 gen_store_gpr(t0
, rd
);
1661 if (rs
!= 0 && rt
!= 0) {
1662 tcg_gen_add_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1663 } else if (rs
== 0 && rt
!= 0) {
1664 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1665 } else if (rs
!= 0 && rt
== 0) {
1666 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1668 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1674 TCGv t0
= tcg_temp_local_new();
1675 TCGv t1
= tcg_temp_new();
1676 TCGv t2
= tcg_temp_new();
1677 int l1
= gen_new_label();
1679 gen_load_gpr(t1
, rs
);
1680 gen_load_gpr(t2
, rt
);
1681 tcg_gen_sub_tl(t0
, t1
, t2
);
1682 tcg_gen_xor_tl(t2
, t1
, t2
);
1683 tcg_gen_xor_tl(t1
, t0
, t1
);
1684 tcg_gen_and_tl(t1
, t1
, t2
);
1686 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
1688 /* operands of different sign, first operand and result different sign */
1689 generate_exception(ctx
, EXCP_OVERFLOW
);
1691 gen_store_gpr(t0
, rd
);
1697 if (rs
!= 0 && rt
!= 0) {
1698 tcg_gen_sub_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1699 } else if (rs
== 0 && rt
!= 0) {
1700 tcg_gen_neg_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1701 } else if (rs
!= 0 && rt
== 0) {
1702 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1704 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1710 if (likely(rs
!= 0 && rt
!= 0)) {
1711 tcg_gen_mul_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1712 tcg_gen_ext32s_tl(cpu_gpr
[rd
], cpu_gpr
[rd
]);
1714 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1719 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1722 /* Conditional move */
1723 static void gen_cond_move (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1725 const char *opn
= "cond move";
1729 /* If no destination, treat it as a NOP.
1730 For add & sub, we must generate the overflow exception when needed. */
1735 l1
= gen_new_label();
1738 if (likely(rt
!= 0))
1739 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rt
], 0, l1
);
1745 if (likely(rt
!= 0))
1746 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rt
], 0, l1
);
1751 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1753 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1756 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1760 static void gen_logic (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1762 const char *opn
= "logic";
1765 /* If no destination, treat it as a NOP. */
1772 if (likely(rs
!= 0 && rt
!= 0)) {
1773 tcg_gen_and_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1775 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1780 if (rs
!= 0 && rt
!= 0) {
1781 tcg_gen_nor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1782 } else if (rs
== 0 && rt
!= 0) {
1783 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1784 } else if (rs
!= 0 && rt
== 0) {
1785 tcg_gen_not_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1787 tcg_gen_movi_tl(cpu_gpr
[rd
], ~((target_ulong
)0));
1792 if (likely(rs
!= 0 && rt
!= 0)) {
1793 tcg_gen_or_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1794 } else if (rs
== 0 && rt
!= 0) {
1795 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1796 } else if (rs
!= 0 && rt
== 0) {
1797 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1799 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1804 if (likely(rs
!= 0 && rt
!= 0)) {
1805 tcg_gen_xor_tl(cpu_gpr
[rd
], cpu_gpr
[rs
], cpu_gpr
[rt
]);
1806 } else if (rs
== 0 && rt
!= 0) {
1807 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rt
]);
1808 } else if (rs
!= 0 && rt
== 0) {
1809 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
1811 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
1816 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1819 /* Set on lower than */
1820 static void gen_slt (CPUState
*env
, uint32_t opc
, int rd
, int rs
, int rt
)
1822 const char *opn
= "slt";
1826 /* If no destination, treat it as a NOP. */
1831 t0
= tcg_temp_new();
1832 t1
= tcg_temp_new();
1833 gen_load_gpr(t0
, rs
);
1834 gen_load_gpr(t1
, rt
);
1837 gen_op_lt(cpu_gpr
[rd
], t0
, t1
);
1841 gen_op_ltu(cpu_gpr
[rd
], t0
, t1
);
1845 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1851 static void gen_shift (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
,
1852 int rd
, int rs
, int rt
)
1854 const char *opn
= "shifts";
1858 /* If no destination, treat it as a NOP.
1859 For add & sub, we must generate the overflow exception when needed. */
1864 t0
= tcg_temp_new();
1865 t1
= tcg_temp_new();
1866 gen_load_gpr(t0
, rs
);
1867 gen_load_gpr(t1
, rt
);
1870 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1871 tcg_gen_shl_tl(t0
, t1
, t0
);
1872 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1876 tcg_gen_ext32s_tl(t1
, t1
);
1877 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1878 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1882 switch ((ctx
->opcode
>> 6) & 0x1f) {
1884 tcg_gen_ext32u_tl(t1
, t1
);
1885 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1886 tcg_gen_shr_tl(t0
, t1
, t0
);
1887 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1891 /* rotrv is decoded as srlv on non-R2 CPUs */
1892 if (env
->insn_flags
& ISA_MIPS32R2
) {
1893 TCGv_i32 t2
= tcg_temp_new_i32();
1894 TCGv_i32 t3
= tcg_temp_new_i32();
1896 tcg_gen_trunc_tl_i32(t2
, t0
);
1897 tcg_gen_trunc_tl_i32(t3
, t1
);
1898 tcg_gen_andi_i32(t2
, t2
, 0x1f);
1899 tcg_gen_rotr_i32(t2
, t3
, t2
);
1900 tcg_gen_ext_i32_tl(cpu_gpr
[rd
], t2
);
1901 tcg_temp_free_i32(t2
);
1902 tcg_temp_free_i32(t3
);
1905 tcg_gen_ext32u_tl(t1
, t1
);
1906 tcg_gen_andi_tl(t0
, t0
, 0x1f);
1907 tcg_gen_shr_tl(t0
, t1
, t0
);
1908 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
1913 MIPS_INVAL("invalid srlv flag");
1914 generate_exception(ctx
, EXCP_RI
);
1918 #if defined(TARGET_MIPS64)
1920 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1921 tcg_gen_shl_tl(cpu_gpr
[rd
], t1
, t0
);
1925 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1926 tcg_gen_sar_tl(cpu_gpr
[rd
], t1
, t0
);
1930 switch ((ctx
->opcode
>> 6) & 0x1f) {
1932 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1933 tcg_gen_shr_tl(cpu_gpr
[rd
], t1
, t0
);
1937 /* drotrv is decoded as dsrlv on non-R2 CPUs */
1938 if (env
->insn_flags
& ISA_MIPS32R2
) {
1939 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1940 tcg_gen_rotr_tl(cpu_gpr
[rd
], t1
, t0
);
1943 tcg_gen_andi_tl(t0
, t0
, 0x3f);
1944 tcg_gen_shr_tl(t0
, t1
, t0
);
1949 MIPS_INVAL("invalid dsrlv flag");
1950 generate_exception(ctx
, EXCP_RI
);
1956 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
1961 /* Arithmetic on HI/LO registers */
1962 static void gen_HILO (DisasContext
*ctx
, uint32_t opc
, int reg
)
1964 const char *opn
= "hilo";
1966 if (reg
== 0 && (opc
== OPC_MFHI
|| opc
== OPC_MFLO
)) {
1973 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_HI
[0]);
1977 tcg_gen_mov_tl(cpu_gpr
[reg
], cpu_LO
[0]);
1982 tcg_gen_mov_tl(cpu_HI
[0], cpu_gpr
[reg
]);
1984 tcg_gen_movi_tl(cpu_HI
[0], 0);
1989 tcg_gen_mov_tl(cpu_LO
[0], cpu_gpr
[reg
]);
1991 tcg_gen_movi_tl(cpu_LO
[0], 0);
1995 MIPS_DEBUG("%s %s", opn
, regnames
[reg
]);
1998 static void gen_muldiv (DisasContext
*ctx
, uint32_t opc
,
2001 const char *opn
= "mul/div";
2007 #if defined(TARGET_MIPS64)
2011 t0
= tcg_temp_local_new();
2012 t1
= tcg_temp_local_new();
2015 t0
= tcg_temp_new();
2016 t1
= tcg_temp_new();
2020 gen_load_gpr(t0
, rs
);
2021 gen_load_gpr(t1
, rt
);
2025 int l1
= gen_new_label();
2026 int l2
= gen_new_label();
2028 tcg_gen_ext32s_tl(t0
, t0
);
2029 tcg_gen_ext32s_tl(t1
, t1
);
2030 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2031 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, INT_MIN
, l2
);
2032 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1, l2
);
2034 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2035 tcg_gen_movi_tl(cpu_HI
[0], 0);
2038 tcg_gen_div_tl(cpu_LO
[0], t0
, t1
);
2039 tcg_gen_rem_tl(cpu_HI
[0], t0
, t1
);
2040 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2041 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2048 int l1
= gen_new_label();
2050 tcg_gen_ext32u_tl(t0
, t0
);
2051 tcg_gen_ext32u_tl(t1
, t1
);
2052 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2053 tcg_gen_divu_tl(cpu_LO
[0], t0
, t1
);
2054 tcg_gen_remu_tl(cpu_HI
[0], t0
, t1
);
2055 tcg_gen_ext32s_tl(cpu_LO
[0], cpu_LO
[0]);
2056 tcg_gen_ext32s_tl(cpu_HI
[0], cpu_HI
[0]);
2063 TCGv_i64 t2
= tcg_temp_new_i64();
2064 TCGv_i64 t3
= tcg_temp_new_i64();
2066 tcg_gen_ext_tl_i64(t2
, t0
);
2067 tcg_gen_ext_tl_i64(t3
, t1
);
2068 tcg_gen_mul_i64(t2
, t2
, t3
);
2069 tcg_temp_free_i64(t3
);
2070 tcg_gen_trunc_i64_tl(t0
, t2
);
2071 tcg_gen_shri_i64(t2
, t2
, 32);
2072 tcg_gen_trunc_i64_tl(t1
, t2
);
2073 tcg_temp_free_i64(t2
);
2074 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2075 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2081 TCGv_i64 t2
= tcg_temp_new_i64();
2082 TCGv_i64 t3
= tcg_temp_new_i64();
2084 tcg_gen_ext32u_tl(t0
, t0
);
2085 tcg_gen_ext32u_tl(t1
, t1
);
2086 tcg_gen_extu_tl_i64(t2
, t0
);
2087 tcg_gen_extu_tl_i64(t3
, t1
);
2088 tcg_gen_mul_i64(t2
, t2
, t3
);
2089 tcg_temp_free_i64(t3
);
2090 tcg_gen_trunc_i64_tl(t0
, t2
);
2091 tcg_gen_shri_i64(t2
, t2
, 32);
2092 tcg_gen_trunc_i64_tl(t1
, t2
);
2093 tcg_temp_free_i64(t2
);
2094 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2095 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2099 #if defined(TARGET_MIPS64)
2102 int l1
= gen_new_label();
2103 int l2
= gen_new_label();
2105 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2106 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, -1LL << 63, l2
);
2107 tcg_gen_brcondi_tl(TCG_COND_NE
, t1
, -1LL, l2
);
2108 tcg_gen_mov_tl(cpu_LO
[0], t0
);
2109 tcg_gen_movi_tl(cpu_HI
[0], 0);
2112 tcg_gen_div_i64(cpu_LO
[0], t0
, t1
);
2113 tcg_gen_rem_i64(cpu_HI
[0], t0
, t1
);
2120 int l1
= gen_new_label();
2122 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
2123 tcg_gen_divu_i64(cpu_LO
[0], t0
, t1
);
2124 tcg_gen_remu_i64(cpu_HI
[0], t0
, t1
);
2130 gen_helper_dmult(t0
, t1
);
2134 gen_helper_dmultu(t0
, t1
);
2140 TCGv_i64 t2
= tcg_temp_new_i64();
2141 TCGv_i64 t3
= tcg_temp_new_i64();
2143 tcg_gen_ext_tl_i64(t2
, t0
);
2144 tcg_gen_ext_tl_i64(t3
, t1
);
2145 tcg_gen_mul_i64(t2
, t2
, t3
);
2146 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2147 tcg_gen_add_i64(t2
, t2
, t3
);
2148 tcg_temp_free_i64(t3
);
2149 tcg_gen_trunc_i64_tl(t0
, t2
);
2150 tcg_gen_shri_i64(t2
, t2
, 32);
2151 tcg_gen_trunc_i64_tl(t1
, t2
);
2152 tcg_temp_free_i64(t2
);
2153 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2154 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2160 TCGv_i64 t2
= tcg_temp_new_i64();
2161 TCGv_i64 t3
= tcg_temp_new_i64();
2163 tcg_gen_ext32u_tl(t0
, t0
);
2164 tcg_gen_ext32u_tl(t1
, t1
);
2165 tcg_gen_extu_tl_i64(t2
, t0
);
2166 tcg_gen_extu_tl_i64(t3
, t1
);
2167 tcg_gen_mul_i64(t2
, t2
, t3
);
2168 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2169 tcg_gen_add_i64(t2
, t2
, t3
);
2170 tcg_temp_free_i64(t3
);
2171 tcg_gen_trunc_i64_tl(t0
, t2
);
2172 tcg_gen_shri_i64(t2
, t2
, 32);
2173 tcg_gen_trunc_i64_tl(t1
, t2
);
2174 tcg_temp_free_i64(t2
);
2175 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2176 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2182 TCGv_i64 t2
= tcg_temp_new_i64();
2183 TCGv_i64 t3
= tcg_temp_new_i64();
2185 tcg_gen_ext_tl_i64(t2
, t0
);
2186 tcg_gen_ext_tl_i64(t3
, t1
);
2187 tcg_gen_mul_i64(t2
, t2
, t3
);
2188 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2189 tcg_gen_sub_i64(t2
, t3
, t2
);
2190 tcg_temp_free_i64(t3
);
2191 tcg_gen_trunc_i64_tl(t0
, t2
);
2192 tcg_gen_shri_i64(t2
, t2
, 32);
2193 tcg_gen_trunc_i64_tl(t1
, t2
);
2194 tcg_temp_free_i64(t2
);
2195 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2196 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2202 TCGv_i64 t2
= tcg_temp_new_i64();
2203 TCGv_i64 t3
= tcg_temp_new_i64();
2205 tcg_gen_ext32u_tl(t0
, t0
);
2206 tcg_gen_ext32u_tl(t1
, t1
);
2207 tcg_gen_extu_tl_i64(t2
, t0
);
2208 tcg_gen_extu_tl_i64(t3
, t1
);
2209 tcg_gen_mul_i64(t2
, t2
, t3
);
2210 tcg_gen_concat_tl_i64(t3
, cpu_LO
[0], cpu_HI
[0]);
2211 tcg_gen_sub_i64(t2
, t3
, t2
);
2212 tcg_temp_free_i64(t3
);
2213 tcg_gen_trunc_i64_tl(t0
, t2
);
2214 tcg_gen_shri_i64(t2
, t2
, 32);
2215 tcg_gen_trunc_i64_tl(t1
, t2
);
2216 tcg_temp_free_i64(t2
);
2217 tcg_gen_ext32s_tl(cpu_LO
[0], t0
);
2218 tcg_gen_ext32s_tl(cpu_HI
[0], t1
);
2224 generate_exception(ctx
, EXCP_RI
);
2227 MIPS_DEBUG("%s %s %s", opn
, regnames
[rs
], regnames
[rt
]);
2233 static void gen_mul_vr54xx (DisasContext
*ctx
, uint32_t opc
,
2234 int rd
, int rs
, int rt
)
2236 const char *opn
= "mul vr54xx";
2237 TCGv t0
= tcg_temp_new();
2238 TCGv t1
= tcg_temp_new();
2240 gen_load_gpr(t0
, rs
);
2241 gen_load_gpr(t1
, rt
);
2244 case OPC_VR54XX_MULS
:
2245 gen_helper_muls(t0
, t0
, t1
);
2248 case OPC_VR54XX_MULSU
:
2249 gen_helper_mulsu(t0
, t0
, t1
);
2252 case OPC_VR54XX_MACC
:
2253 gen_helper_macc(t0
, t0
, t1
);
2256 case OPC_VR54XX_MACCU
:
2257 gen_helper_maccu(t0
, t0
, t1
);
2260 case OPC_VR54XX_MSAC
:
2261 gen_helper_msac(t0
, t0
, t1
);
2264 case OPC_VR54XX_MSACU
:
2265 gen_helper_msacu(t0
, t0
, t1
);
2268 case OPC_VR54XX_MULHI
:
2269 gen_helper_mulhi(t0
, t0
, t1
);
2272 case OPC_VR54XX_MULHIU
:
2273 gen_helper_mulhiu(t0
, t0
, t1
);
2276 case OPC_VR54XX_MULSHI
:
2277 gen_helper_mulshi(t0
, t0
, t1
);
2280 case OPC_VR54XX_MULSHIU
:
2281 gen_helper_mulshiu(t0
, t0
, t1
);
2284 case OPC_VR54XX_MACCHI
:
2285 gen_helper_macchi(t0
, t0
, t1
);
2288 case OPC_VR54XX_MACCHIU
:
2289 gen_helper_macchiu(t0
, t0
, t1
);
2292 case OPC_VR54XX_MSACHI
:
2293 gen_helper_msachi(t0
, t0
, t1
);
2296 case OPC_VR54XX_MSACHIU
:
2297 gen_helper_msachiu(t0
, t0
, t1
);
2301 MIPS_INVAL("mul vr54xx");
2302 generate_exception(ctx
, EXCP_RI
);
2305 gen_store_gpr(t0
, rd
);
2306 MIPS_DEBUG("%s %s, %s, %s", opn
, regnames
[rd
], regnames
[rs
], regnames
[rt
]);
2313 static void gen_cl (DisasContext
*ctx
, uint32_t opc
,
2316 const char *opn
= "CLx";
2324 t0
= tcg_temp_new();
2325 gen_load_gpr(t0
, rs
);
2328 gen_helper_clo(cpu_gpr
[rd
], t0
);
2332 gen_helper_clz(cpu_gpr
[rd
], t0
);
2335 #if defined(TARGET_MIPS64)
2337 gen_helper_dclo(cpu_gpr
[rd
], t0
);
2341 gen_helper_dclz(cpu_gpr
[rd
], t0
);
2346 MIPS_DEBUG("%s %s, %s", opn
, regnames
[rd
], regnames
[rs
]);
2351 static void gen_trap (DisasContext
*ctx
, uint32_t opc
,
2352 int rs
, int rt
, int16_t imm
)
2355 TCGv t0
= tcg_temp_new();
2356 TCGv t1
= tcg_temp_new();
2359 /* Load needed operands */
2367 /* Compare two registers */
2369 gen_load_gpr(t0
, rs
);
2370 gen_load_gpr(t1
, rt
);
2380 /* Compare register to immediate */
2381 if (rs
!= 0 || imm
!= 0) {
2382 gen_load_gpr(t0
, rs
);
2383 tcg_gen_movi_tl(t1
, (int32_t)imm
);
2390 case OPC_TEQ
: /* rs == rs */
2391 case OPC_TEQI
: /* r0 == 0 */
2392 case OPC_TGE
: /* rs >= rs */
2393 case OPC_TGEI
: /* r0 >= 0 */
2394 case OPC_TGEU
: /* rs >= rs unsigned */
2395 case OPC_TGEIU
: /* r0 >= 0 unsigned */
2397 generate_exception(ctx
, EXCP_TRAP
);
2399 case OPC_TLT
: /* rs < rs */
2400 case OPC_TLTI
: /* r0 < 0 */
2401 case OPC_TLTU
: /* rs < rs unsigned */
2402 case OPC_TLTIU
: /* r0 < 0 unsigned */
2403 case OPC_TNE
: /* rs != rs */
2404 case OPC_TNEI
: /* r0 != 0 */
2405 /* Never trap: treat as NOP. */
2409 int l1
= gen_new_label();
2414 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, t1
, l1
);
2418 tcg_gen_brcond_tl(TCG_COND_LT
, t0
, t1
, l1
);
2422 tcg_gen_brcond_tl(TCG_COND_LTU
, t0
, t1
, l1
);
2426 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
2430 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
2434 tcg_gen_brcond_tl(TCG_COND_EQ
, t0
, t1
, l1
);
2437 generate_exception(ctx
, EXCP_TRAP
);
2444 static inline void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
2446 TranslationBlock
*tb
;
2448 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
) &&
2449 likely(!ctx
->singlestep_enabled
)) {
2452 tcg_gen_exit_tb((long)tb
+ n
);
2455 if (ctx
->singlestep_enabled
) {
2456 save_cpu_state(ctx
, 0);
2457 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
2463 /* Branches (before delay slot) */
2464 static void gen_compute_branch (DisasContext
*ctx
, uint32_t opc
,
2465 int rs
, int rt
, int32_t offset
)
2467 target_ulong btgt
= -1;
2469 int bcond_compute
= 0;
2470 TCGv t0
= tcg_temp_new();
2471 TCGv t1
= tcg_temp_new();
2473 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
2474 #ifdef MIPS_DEBUG_DISAS
2475 LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx
"\n", ctx
->pc
);
2477 generate_exception(ctx
, EXCP_RI
);
2481 /* Load needed operands */
2487 /* Compare two registers */
2489 gen_load_gpr(t0
, rs
);
2490 gen_load_gpr(t1
, rt
);
2493 btgt
= ctx
->pc
+ 4 + offset
;
2507 /* Compare to zero */
2509 gen_load_gpr(t0
, rs
);
2512 btgt
= ctx
->pc
+ 4 + offset
;
2516 /* Jump to immediate */
2517 btgt
= ((ctx
->pc
+ 4) & (int32_t)0xF0000000) | (uint32_t)offset
;
2521 /* Jump to register */
2522 if (offset
!= 0 && offset
!= 16) {
2523 /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
2524 others are reserved. */
2525 MIPS_INVAL("jump hint");
2526 generate_exception(ctx
, EXCP_RI
);
2529 gen_load_gpr(btarget
, rs
);
2532 MIPS_INVAL("branch/jump");
2533 generate_exception(ctx
, EXCP_RI
);
2536 if (bcond_compute
== 0) {
2537 /* No condition to be computed */
2539 case OPC_BEQ
: /* rx == rx */
2540 case OPC_BEQL
: /* rx == rx likely */
2541 case OPC_BGEZ
: /* 0 >= 0 */
2542 case OPC_BGEZL
: /* 0 >= 0 likely */
2543 case OPC_BLEZ
: /* 0 <= 0 */
2544 case OPC_BLEZL
: /* 0 <= 0 likely */
2546 ctx
->hflags
|= MIPS_HFLAG_B
;
2547 MIPS_DEBUG("balways");
2549 case OPC_BGEZAL
: /* 0 >= 0 */
2550 case OPC_BGEZALL
: /* 0 >= 0 likely */
2551 /* Always take and link */
2553 ctx
->hflags
|= MIPS_HFLAG_B
;
2554 MIPS_DEBUG("balways and link");
2556 case OPC_BNE
: /* rx != rx */
2557 case OPC_BGTZ
: /* 0 > 0 */
2558 case OPC_BLTZ
: /* 0 < 0 */
2560 MIPS_DEBUG("bnever (NOP)");
2562 case OPC_BLTZAL
: /* 0 < 0 */
2563 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2564 MIPS_DEBUG("bnever and link");
2566 case OPC_BLTZALL
: /* 0 < 0 likely */
2567 tcg_gen_movi_tl(cpu_gpr
[31], ctx
->pc
+ 8);
2568 /* Skip the instruction in the delay slot */
2569 MIPS_DEBUG("bnever, link and skip");
2572 case OPC_BNEL
: /* rx != rx likely */
2573 case OPC_BGTZL
: /* 0 > 0 likely */
2574 case OPC_BLTZL
: /* 0 < 0 likely */
2575 /* Skip the instruction in the delay slot */
2576 MIPS_DEBUG("bnever and skip");
2580 ctx
->hflags
|= MIPS_HFLAG_B
;
2581 MIPS_DEBUG("j " TARGET_FMT_lx
, btgt
);
2585 ctx
->hflags
|= MIPS_HFLAG_B
;
2586 MIPS_DEBUG("jal " TARGET_FMT_lx
, btgt
);
2589 ctx
->hflags
|= MIPS_HFLAG_BR
;
2590 MIPS_DEBUG("jr %s", regnames
[rs
]);
2594 ctx
->hflags
|= MIPS_HFLAG_BR
;
2595 MIPS_DEBUG("jalr %s, %s", regnames
[rt
], regnames
[rs
]);
2598 MIPS_INVAL("branch/jump");
2599 generate_exception(ctx
, EXCP_RI
);
2605 gen_op_eq(bcond
, t0
, t1
);
2606 MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx
,
2607 regnames
[rs
], regnames
[rt
], btgt
);
2610 gen_op_eq(bcond
, t0
, t1
);
2611 MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx
,
2612 regnames
[rs
], regnames
[rt
], btgt
);
2615 gen_op_ne(bcond
, t0
, t1
);
2616 MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx
,
2617 regnames
[rs
], regnames
[rt
], btgt
);
2620 gen_op_ne(bcond
, t0
, t1
);
2621 MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx
,
2622 regnames
[rs
], regnames
[rt
], btgt
);
2625 gen_op_gez(bcond
, t0
);
2626 MIPS_DEBUG("bgez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2629 gen_op_gez(bcond
, t0
);
2630 MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2633 gen_op_gez(bcond
, t0
);
2634 MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2638 gen_op_gez(bcond
, t0
);
2640 MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2643 gen_op_gtz(bcond
, t0
);
2644 MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2647 gen_op_gtz(bcond
, t0
);
2648 MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2651 gen_op_lez(bcond
, t0
);
2652 MIPS_DEBUG("blez %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2655 gen_op_lez(bcond
, t0
);
2656 MIPS_DEBUG("blezl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2659 gen_op_ltz(bcond
, t0
);
2660 MIPS_DEBUG("bltz %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2663 gen_op_ltz(bcond
, t0
);
2664 MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2667 gen_op_ltz(bcond
, t0
);
2669 MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2671 ctx
->hflags
|= MIPS_HFLAG_BC
;
2674 gen_op_ltz(bcond
, t0
);
2676 MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx
, regnames
[rs
], btgt
);
2678 ctx
->hflags
|= MIPS_HFLAG_BL
;
2681 MIPS_INVAL("conditional branch/jump");
2682 generate_exception(ctx
, EXCP_RI
);
2686 MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx
,
2687 blink
, ctx
->hflags
, btgt
);
2689 ctx
->btarget
= btgt
;
2691 tcg_gen_movi_tl(cpu_gpr
[blink
], ctx
->pc
+ 8);
2699 /* special3 bitfield operations */
2700 static void gen_bitops (DisasContext
*ctx
, uint32_t opc
, int rt
,
2701 int rs
, int lsb
, int msb
)
2703 TCGv t0
= tcg_temp_new();
2704 TCGv t1
= tcg_temp_new();
2707 gen_load_gpr(t1
, rs
);
2712 tcg_gen_shri_tl(t0
, t1
, lsb
);
2714 tcg_gen_andi_tl(t0
, t0
, (1 << (msb
+ 1)) - 1);
2716 tcg_gen_ext32s_tl(t0
, t0
);
2719 #if defined(TARGET_MIPS64)
2721 tcg_gen_shri_tl(t0
, t1
, lsb
);
2723 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1 + 32)) - 1);
2727 tcg_gen_shri_tl(t0
, t1
, lsb
+ 32);
2728 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2731 tcg_gen_shri_tl(t0
, t1
, lsb
);
2732 tcg_gen_andi_tl(t0
, t0
, (1ULL << (msb
+ 1)) - 1);
2738 mask
= ((msb
- lsb
+ 1 < 32) ? ((1 << (msb
- lsb
+ 1)) - 1) : ~0) << lsb
;
2739 gen_load_gpr(t0
, rt
);
2740 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2741 tcg_gen_shli_tl(t1
, t1
, lsb
);
2742 tcg_gen_andi_tl(t1
, t1
, mask
);
2743 tcg_gen_or_tl(t0
, t0
, t1
);
2744 tcg_gen_ext32s_tl(t0
, t0
);
2746 #if defined(TARGET_MIPS64)
2750 mask
= ((msb
- lsb
+ 1 + 32 < 64) ? ((1ULL << (msb
- lsb
+ 1 + 32)) - 1) : ~0ULL) << lsb
;
2751 gen_load_gpr(t0
, rt
);
2752 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2753 tcg_gen_shli_tl(t1
, t1
, lsb
);
2754 tcg_gen_andi_tl(t1
, t1
, mask
);
2755 tcg_gen_or_tl(t0
, t0
, t1
);
2760 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2761 gen_load_gpr(t0
, rt
);
2762 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2763 tcg_gen_shli_tl(t1
, t1
, lsb
+ 32);
2764 tcg_gen_andi_tl(t1
, t1
, mask
);
2765 tcg_gen_or_tl(t0
, t0
, t1
);
2770 gen_load_gpr(t0
, rt
);
2771 mask
= ((1ULL << (msb
- lsb
+ 1)) - 1) << lsb
;
2772 gen_load_gpr(t0
, rt
);
2773 tcg_gen_andi_tl(t0
, t0
, ~mask
);
2774 tcg_gen_shli_tl(t1
, t1
, lsb
);
2775 tcg_gen_andi_tl(t1
, t1
, mask
);
2776 tcg_gen_or_tl(t0
, t0
, t1
);
2781 MIPS_INVAL("bitops");
2782 generate_exception(ctx
, EXCP_RI
);
2787 gen_store_gpr(t0
, rt
);
2792 static void gen_bshfl (DisasContext
*ctx
, uint32_t op2
, int rt
, int rd
)
2797 /* If no destination, treat it as a NOP. */
2802 t0
= tcg_temp_new();
2803 gen_load_gpr(t0
, rt
);
2807 TCGv t1
= tcg_temp_new();
2809 tcg_gen_shri_tl(t1
, t0
, 8);
2810 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF);
2811 tcg_gen_shli_tl(t0
, t0
, 8);
2812 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF);
2813 tcg_gen_or_tl(t0
, t0
, t1
);
2815 tcg_gen_ext32s_tl(cpu_gpr
[rd
], t0
);
2819 tcg_gen_ext8s_tl(cpu_gpr
[rd
], t0
);
2822 tcg_gen_ext16s_tl(cpu_gpr
[rd
], t0
);
2824 #if defined(TARGET_MIPS64)
2827 TCGv t1
= tcg_temp_new();
2829 tcg_gen_shri_tl(t1
, t0
, 8);
2830 tcg_gen_andi_tl(t1
, t1
, 0x00FF00FF00FF00FFULL
);
2831 tcg_gen_shli_tl(t0
, t0
, 8);
2832 tcg_gen_andi_tl(t0
, t0
, ~0x00FF00FF00FF00FFULL
);
2833 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2839 TCGv t1
= tcg_temp_new();
2841 tcg_gen_shri_tl(t1
, t0
, 16);
2842 tcg_gen_andi_tl(t1
, t1
, 0x0000FFFF0000FFFFULL
);
2843 tcg_gen_shli_tl(t0
, t0
, 16);
2844 tcg_gen_andi_tl(t0
, t0
, ~0x0000FFFF0000FFFFULL
);
2845 tcg_gen_or_tl(t0
, t0
, t1
);
2846 tcg_gen_shri_tl(t1
, t0
, 32);
2847 tcg_gen_shli_tl(t0
, t0
, 32);
2848 tcg_gen_or_tl(cpu_gpr
[rd
], t0
, t1
);
2854 MIPS_INVAL("bsfhl");
2855 generate_exception(ctx
, EXCP_RI
);
2862 #ifndef CONFIG_USER_ONLY
2863 /* CP0 (MMU and control) */
2864 static inline void gen_mfc0_load32 (TCGv arg
, target_ulong off
)
2866 TCGv_i32 t0
= tcg_temp_new_i32();
2868 tcg_gen_ld_i32(t0
, cpu_env
, off
);
2869 tcg_gen_ext_i32_tl(arg
, t0
);
2870 tcg_temp_free_i32(t0
);
2873 static inline void gen_mfc0_load64 (TCGv arg
, target_ulong off
)
2875 tcg_gen_ld_tl(arg
, cpu_env
, off
);
2876 tcg_gen_ext32s_tl(arg
, arg
);
2879 static inline void gen_mtc0_store32 (TCGv arg
, target_ulong off
)
2881 TCGv_i32 t0
= tcg_temp_new_i32();
2883 tcg_gen_trunc_tl_i32(t0
, arg
);
2884 tcg_gen_st_i32(t0
, cpu_env
, off
);
2885 tcg_temp_free_i32(t0
);
2888 static inline void gen_mtc0_store64 (TCGv arg
, target_ulong off
)
2890 tcg_gen_ext32s_tl(arg
, arg
);
2891 tcg_gen_st_tl(arg
, cpu_env
, off
);
2894 static void gen_mfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
2896 const char *rn
= "invalid";
2899 check_insn(env
, ctx
, ISA_MIPS32
);
2905 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
2909 check_insn(env
, ctx
, ASE_MT
);
2910 gen_helper_mfc0_mvpcontrol(arg
);
2914 check_insn(env
, ctx
, ASE_MT
);
2915 gen_helper_mfc0_mvpconf0(arg
);
2919 check_insn(env
, ctx
, ASE_MT
);
2920 gen_helper_mfc0_mvpconf1(arg
);
2930 gen_helper_mfc0_random(arg
);
2934 check_insn(env
, ctx
, ASE_MT
);
2935 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
2939 check_insn(env
, ctx
, ASE_MT
);
2940 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
2944 check_insn(env
, ctx
, ASE_MT
);
2945 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
2949 check_insn(env
, ctx
, ASE_MT
);
2950 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_YQMask
));
2954 check_insn(env
, ctx
, ASE_MT
);
2955 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
2959 check_insn(env
, ctx
, ASE_MT
);
2960 gen_mfc0_load64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
2961 rn
= "VPEScheFBack";
2964 check_insn(env
, ctx
, ASE_MT
);
2965 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
2975 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
2976 tcg_gen_ext32s_tl(arg
, arg
);
2980 check_insn(env
, ctx
, ASE_MT
);
2981 gen_helper_mfc0_tcstatus(arg
);
2985 check_insn(env
, ctx
, ASE_MT
);
2986 gen_helper_mfc0_tcbind(arg
);
2990 check_insn(env
, ctx
, ASE_MT
);
2991 gen_helper_mfc0_tcrestart(arg
);
2995 check_insn(env
, ctx
, ASE_MT
);
2996 gen_helper_mfc0_tchalt(arg
);
3000 check_insn(env
, ctx
, ASE_MT
);
3001 gen_helper_mfc0_tccontext(arg
);
3005 check_insn(env
, ctx
, ASE_MT
);
3006 gen_helper_mfc0_tcschedule(arg
);
3010 check_insn(env
, ctx
, ASE_MT
);
3011 gen_helper_mfc0_tcschefback(arg
);
3021 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
3022 tcg_gen_ext32s_tl(arg
, arg
);
3032 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
3033 tcg_gen_ext32s_tl(arg
, arg
);
3037 // gen_helper_mfc0_contextconfig(arg); /* SmartMIPS ASE */
3038 rn
= "ContextConfig";
3047 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
3051 check_insn(env
, ctx
, ISA_MIPS32R2
);
3052 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
3062 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
3066 check_insn(env
, ctx
, ISA_MIPS32R2
);
3067 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
3071 check_insn(env
, ctx
, ISA_MIPS32R2
);
3072 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
3076 check_insn(env
, ctx
, ISA_MIPS32R2
);
3077 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
3081 check_insn(env
, ctx
, ISA_MIPS32R2
);
3082 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
3086 check_insn(env
, ctx
, ISA_MIPS32R2
);
3087 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
3097 check_insn(env
, ctx
, ISA_MIPS32R2
);
3098 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
3108 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
3109 tcg_gen_ext32s_tl(arg
, arg
);
3119 /* Mark as an IO operation because we read the time. */
3122 gen_helper_mfc0_count(arg
);
3125 ctx
->bstate
= BS_STOP
;
3129 /* 6,7 are implementation dependent */
3137 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
3138 tcg_gen_ext32s_tl(arg
, arg
);
3148 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
3151 /* 6,7 are implementation dependent */
3159 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
3163 check_insn(env
, ctx
, ISA_MIPS32R2
);
3164 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
3168 check_insn(env
, ctx
, ISA_MIPS32R2
);
3169 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
3173 check_insn(env
, ctx
, ISA_MIPS32R2
);
3174 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3184 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
3194 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
3195 tcg_gen_ext32s_tl(arg
, arg
);
3205 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
3209 check_insn(env
, ctx
, ISA_MIPS32R2
);
3210 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
3220 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
3224 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
3228 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
3232 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
3235 /* 4,5 are reserved */
3236 /* 6,7 are implementation dependent */
3238 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
3242 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
3252 gen_helper_mfc0_lladdr(arg
);
3262 gen_helper_1i(mfc0_watchlo
, arg
, sel
);
3272 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
3282 #if defined(TARGET_MIPS64)
3283 check_insn(env
, ctx
, ISA_MIPS3
);
3284 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
3285 tcg_gen_ext32s_tl(arg
, arg
);
3294 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3297 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
3305 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3306 rn
= "'Diagnostic"; /* implementation dependent */
3311 gen_helper_mfc0_debug(arg
); /* EJTAG support */
3315 // gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
3316 rn
= "TraceControl";
3319 // gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
3320 rn
= "TraceControl2";
3323 // gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
3324 rn
= "UserTraceData";
3327 // gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
3338 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
3339 tcg_gen_ext32s_tl(arg
, arg
);
3349 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
3350 rn
= "Performance0";
3353 // gen_helper_mfc0_performance1(arg);
3354 rn
= "Performance1";
3357 // gen_helper_mfc0_performance2(arg);
3358 rn
= "Performance2";
3361 // gen_helper_mfc0_performance3(arg);
3362 rn
= "Performance3";
3365 // gen_helper_mfc0_performance4(arg);
3366 rn
= "Performance4";
3369 // gen_helper_mfc0_performance5(arg);
3370 rn
= "Performance5";
3373 // gen_helper_mfc0_performance6(arg);
3374 rn
= "Performance6";
3377 // gen_helper_mfc0_performance7(arg);
3378 rn
= "Performance7";
3385 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3391 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
3404 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
3411 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
3424 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
3431 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
3441 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
3442 tcg_gen_ext32s_tl(arg
, arg
);
3453 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
3463 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3467 LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
3468 generate_exception(ctx
, EXCP_RI
);
3471 static void gen_mtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
3473 const char *rn
= "invalid";
3476 check_insn(env
, ctx
, ISA_MIPS32
);
3485 gen_helper_mtc0_index(arg
);
3489 check_insn(env
, ctx
, ASE_MT
);
3490 gen_helper_mtc0_mvpcontrol(arg
);
3494 check_insn(env
, ctx
, ASE_MT
);
3499 check_insn(env
, ctx
, ASE_MT
);
3514 check_insn(env
, ctx
, ASE_MT
);
3515 gen_helper_mtc0_vpecontrol(arg
);
3519 check_insn(env
, ctx
, ASE_MT
);
3520 gen_helper_mtc0_vpeconf0(arg
);
3524 check_insn(env
, ctx
, ASE_MT
);
3525 gen_helper_mtc0_vpeconf1(arg
);
3529 check_insn(env
, ctx
, ASE_MT
);
3530 gen_helper_mtc0_yqmask(arg
);
3534 check_insn(env
, ctx
, ASE_MT
);
3535 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPESchedule
));
3539 check_insn(env
, ctx
, ASE_MT
);
3540 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_VPEScheFBack
));
3541 rn
= "VPEScheFBack";
3544 check_insn(env
, ctx
, ASE_MT
);
3545 gen_helper_mtc0_vpeopt(arg
);
3555 gen_helper_mtc0_entrylo0(arg
);
3559 check_insn(env
, ctx
, ASE_MT
);
3560 gen_helper_mtc0_tcstatus(arg
);
3564 check_insn(env
, ctx
, ASE_MT
);
3565 gen_helper_mtc0_tcbind(arg
);
3569 check_insn(env
, ctx
, ASE_MT
);
3570 gen_helper_mtc0_tcrestart(arg
);
3574 check_insn(env
, ctx
, ASE_MT
);
3575 gen_helper_mtc0_tchalt(arg
);
3579 check_insn(env
, ctx
, ASE_MT
);
3580 gen_helper_mtc0_tccontext(arg
);
3584 check_insn(env
, ctx
, ASE_MT
);
3585 gen_helper_mtc0_tcschedule(arg
);
3589 check_insn(env
, ctx
, ASE_MT
);
3590 gen_helper_mtc0_tcschefback(arg
);
3600 gen_helper_mtc0_entrylo1(arg
);
3610 gen_helper_mtc0_context(arg
);
3614 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
3615 rn
= "ContextConfig";
3624 gen_helper_mtc0_pagemask(arg
);
3628 check_insn(env
, ctx
, ISA_MIPS32R2
);
3629 gen_helper_mtc0_pagegrain(arg
);
3639 gen_helper_mtc0_wired(arg
);
3643 check_insn(env
, ctx
, ISA_MIPS32R2
);
3644 gen_helper_mtc0_srsconf0(arg
);
3648 check_insn(env
, ctx
, ISA_MIPS32R2
);
3649 gen_helper_mtc0_srsconf1(arg
);
3653 check_insn(env
, ctx
, ISA_MIPS32R2
);
3654 gen_helper_mtc0_srsconf2(arg
);
3658 check_insn(env
, ctx
, ISA_MIPS32R2
);
3659 gen_helper_mtc0_srsconf3(arg
);
3663 check_insn(env
, ctx
, ISA_MIPS32R2
);
3664 gen_helper_mtc0_srsconf4(arg
);
3674 check_insn(env
, ctx
, ISA_MIPS32R2
);
3675 gen_helper_mtc0_hwrena(arg
);
3689 gen_helper_mtc0_count(arg
);
3692 /* 6,7 are implementation dependent */
3700 gen_helper_mtc0_entryhi(arg
);
3710 gen_helper_mtc0_compare(arg
);
3713 /* 6,7 are implementation dependent */
3721 save_cpu_state(ctx
, 1);
3722 gen_helper_mtc0_status(arg
);
3723 /* BS_STOP isn't good enough here, hflags may have changed. */
3724 gen_save_pc(ctx
->pc
+ 4);
3725 ctx
->bstate
= BS_EXCP
;
3729 check_insn(env
, ctx
, ISA_MIPS32R2
);
3730 gen_helper_mtc0_intctl(arg
);
3731 /* Stop translation as we may have switched the execution mode */
3732 ctx
->bstate
= BS_STOP
;
3736 check_insn(env
, ctx
, ISA_MIPS32R2
);
3737 gen_helper_mtc0_srsctl(arg
);
3738 /* Stop translation as we may have switched the execution mode */
3739 ctx
->bstate
= BS_STOP
;
3743 check_insn(env
, ctx
, ISA_MIPS32R2
);
3744 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
3745 /* Stop translation as we may have switched the execution mode */
3746 ctx
->bstate
= BS_STOP
;
3756 save_cpu_state(ctx
, 1);
3757 gen_helper_mtc0_cause(arg
);
3767 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_EPC
));
3781 check_insn(env
, ctx
, ISA_MIPS32R2
);
3782 gen_helper_mtc0_ebase(arg
);
3792 gen_helper_mtc0_config0(arg
);
3794 /* Stop translation as we may have switched the execution mode */
3795 ctx
->bstate
= BS_STOP
;
3798 /* ignored, read only */
3802 gen_helper_mtc0_config2(arg
);
3804 /* Stop translation as we may have switched the execution mode */
3805 ctx
->bstate
= BS_STOP
;
3808 /* ignored, read only */
3811 /* 4,5 are reserved */
3812 /* 6,7 are implementation dependent */
3822 rn
= "Invalid config selector";
3829 gen_helper_mtc0_lladdr(arg
);
3839 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
3849 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
3859 #if defined(TARGET_MIPS64)
3860 check_insn(env
, ctx
, ISA_MIPS3
);
3861 gen_helper_mtc0_xcontext(arg
);
3870 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3873 gen_helper_mtc0_framemask(arg
);
3882 rn
= "Diagnostic"; /* implementation dependent */
3887 gen_helper_mtc0_debug(arg
); /* EJTAG support */
3888 /* BS_STOP isn't good enough here, hflags may have changed. */
3889 gen_save_pc(ctx
->pc
+ 4);
3890 ctx
->bstate
= BS_EXCP
;
3894 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
3895 rn
= "TraceControl";
3896 /* Stop translation as we may have switched the execution mode */
3897 ctx
->bstate
= BS_STOP
;
3900 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
3901 rn
= "TraceControl2";
3902 /* Stop translation as we may have switched the execution mode */
3903 ctx
->bstate
= BS_STOP
;
3906 /* Stop translation as we may have switched the execution mode */
3907 ctx
->bstate
= BS_STOP
;
3908 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
3909 rn
= "UserTraceData";
3910 /* Stop translation as we may have switched the execution mode */
3911 ctx
->bstate
= BS_STOP
;
3914 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
3915 /* Stop translation as we may have switched the execution mode */
3916 ctx
->bstate
= BS_STOP
;
3927 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_DEPC
));
3937 gen_helper_mtc0_performance0(arg
);
3938 rn
= "Performance0";
3941 // gen_helper_mtc0_performance1(arg);
3942 rn
= "Performance1";
3945 // gen_helper_mtc0_performance2(arg);
3946 rn
= "Performance2";
3949 // gen_helper_mtc0_performance3(arg);
3950 rn
= "Performance3";
3953 // gen_helper_mtc0_performance4(arg);
3954 rn
= "Performance4";
3957 // gen_helper_mtc0_performance5(arg);
3958 rn
= "Performance5";
3961 // gen_helper_mtc0_performance6(arg);
3962 rn
= "Performance6";
3965 // gen_helper_mtc0_performance7(arg);
3966 rn
= "Performance7";
3992 gen_helper_mtc0_taglo(arg
);
3999 gen_helper_mtc0_datalo(arg
);
4012 gen_helper_mtc0_taghi(arg
);
4019 gen_helper_mtc0_datahi(arg
);
4030 gen_mtc0_store64(arg
, offsetof(CPUState
, CP0_ErrorEPC
));
4041 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4047 /* Stop translation as we may have switched the execution mode */
4048 ctx
->bstate
= BS_STOP
;
4053 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4054 /* For simplicity assume that all writes can cause interrupts. */
4057 ctx
->bstate
= BS_STOP
;
4062 LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4063 generate_exception(ctx
, EXCP_RI
);
4066 #if defined(TARGET_MIPS64)
4067 static void gen_dmfc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4069 const char *rn
= "invalid";
4072 check_insn(env
, ctx
, ISA_MIPS64
);
4078 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Index
));
4082 check_insn(env
, ctx
, ASE_MT
);
4083 gen_helper_mfc0_mvpcontrol(arg
);
4087 check_insn(env
, ctx
, ASE_MT
);
4088 gen_helper_mfc0_mvpconf0(arg
);
4092 check_insn(env
, ctx
, ASE_MT
);
4093 gen_helper_mfc0_mvpconf1(arg
);
4103 gen_helper_mfc0_random(arg
);
4107 check_insn(env
, ctx
, ASE_MT
);
4108 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEControl
));
4112 check_insn(env
, ctx
, ASE_MT
);
4113 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf0
));
4117 check_insn(env
, ctx
, ASE_MT
);
4118 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEConf1
));
4122 check_insn(env
, ctx
, ASE_MT
);
4123 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_YQMask
));
4127 check_insn(env
, ctx
, ASE_MT
);
4128 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4132 check_insn(env
, ctx
, ASE_MT
);
4133 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4134 rn
= "VPEScheFBack";
4137 check_insn(env
, ctx
, ASE_MT
);
4138 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_VPEOpt
));
4148 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo0
));
4152 check_insn(env
, ctx
, ASE_MT
);
4153 gen_helper_mfc0_tcstatus(arg
);
4157 check_insn(env
, ctx
, ASE_MT
);
4158 gen_helper_mfc0_tcbind(arg
);
4162 check_insn(env
, ctx
, ASE_MT
);
4163 gen_helper_dmfc0_tcrestart(arg
);
4167 check_insn(env
, ctx
, ASE_MT
);
4168 gen_helper_dmfc0_tchalt(arg
);
4172 check_insn(env
, ctx
, ASE_MT
);
4173 gen_helper_dmfc0_tccontext(arg
);
4177 check_insn(env
, ctx
, ASE_MT
);
4178 gen_helper_dmfc0_tcschedule(arg
);
4182 check_insn(env
, ctx
, ASE_MT
);
4183 gen_helper_dmfc0_tcschefback(arg
);
4193 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryLo1
));
4203 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_Context
));
4207 // gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
4208 rn
= "ContextConfig";
4217 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageMask
));
4221 check_insn(env
, ctx
, ISA_MIPS32R2
);
4222 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PageGrain
));
4232 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Wired
));
4236 check_insn(env
, ctx
, ISA_MIPS32R2
);
4237 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf0
));
4241 check_insn(env
, ctx
, ISA_MIPS32R2
);
4242 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf1
));
4246 check_insn(env
, ctx
, ISA_MIPS32R2
);
4247 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf2
));
4251 check_insn(env
, ctx
, ISA_MIPS32R2
);
4252 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf3
));
4256 check_insn(env
, ctx
, ISA_MIPS32R2
);
4257 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSConf4
));
4267 check_insn(env
, ctx
, ISA_MIPS32R2
);
4268 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_HWREna
));
4278 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_BadVAddr
));
4288 /* Mark as an IO operation because we read the time. */
4291 gen_helper_mfc0_count(arg
);
4294 ctx
->bstate
= BS_STOP
;
4298 /* 6,7 are implementation dependent */
4306 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EntryHi
));
4316 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Compare
));
4319 /* 6,7 are implementation dependent */
4327 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Status
));
4331 check_insn(env
, ctx
, ISA_MIPS32R2
);
4332 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_IntCtl
));
4336 check_insn(env
, ctx
, ISA_MIPS32R2
);
4337 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSCtl
));
4341 check_insn(env
, ctx
, ISA_MIPS32R2
);
4342 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4352 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Cause
));
4362 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4372 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_PRid
));
4376 check_insn(env
, ctx
, ISA_MIPS32R2
);
4377 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_EBase
));
4387 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config0
));
4391 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config1
));
4395 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config2
));
4399 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config3
));
4402 /* 6,7 are implementation dependent */
4404 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config6
));
4408 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Config7
));
4418 gen_helper_dmfc0_lladdr(arg
);
4428 gen_helper_1i(dmfc0_watchlo
, arg
, sel
);
4438 gen_helper_1i(mfc0_watchhi
, arg
, sel
);
4448 check_insn(env
, ctx
, ISA_MIPS3
);
4449 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_XContext
));
4457 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4460 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Framemask
));
4468 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4469 rn
= "'Diagnostic"; /* implementation dependent */
4474 gen_helper_mfc0_debug(arg
); /* EJTAG support */
4478 // gen_helper_dmfc0_tracecontrol(arg); /* PDtrace support */
4479 rn
= "TraceControl";
4482 // gen_helper_dmfc0_tracecontrol2(arg); /* PDtrace support */
4483 rn
= "TraceControl2";
4486 // gen_helper_dmfc0_usertracedata(arg); /* PDtrace support */
4487 rn
= "UserTraceData";
4490 // gen_helper_dmfc0_tracebpc(arg); /* PDtrace support */
4501 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
4511 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_Performance0
));
4512 rn
= "Performance0";
4515 // gen_helper_dmfc0_performance1(arg);
4516 rn
= "Performance1";
4519 // gen_helper_dmfc0_performance2(arg);
4520 rn
= "Performance2";
4523 // gen_helper_dmfc0_performance3(arg);
4524 rn
= "Performance3";
4527 // gen_helper_dmfc0_performance4(arg);
4528 rn
= "Performance4";
4531 // gen_helper_dmfc0_performance5(arg);
4532 rn
= "Performance5";
4535 // gen_helper_dmfc0_performance6(arg);
4536 rn
= "Performance6";
4539 // gen_helper_dmfc0_performance7(arg);
4540 rn
= "Performance7";
4547 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4554 tcg_gen_movi_tl(arg
, 0); /* unimplemented */
4567 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagLo
));
4574 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataLo
));
4587 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_TagHi
));
4594 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DataHi
));
4604 tcg_gen_ld_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
4615 gen_mfc0_load32(arg
, offsetof(CPUState
, CP0_DESAVE
));
4625 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4629 LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
4630 generate_exception(ctx
, EXCP_RI
);
4633 static void gen_dmtc0 (CPUState
*env
, DisasContext
*ctx
, TCGv arg
, int reg
, int sel
)
4635 const char *rn
= "invalid";
4638 check_insn(env
, ctx
, ISA_MIPS64
);
4647 gen_helper_mtc0_index(arg
);
4651 check_insn(env
, ctx
, ASE_MT
);
4652 gen_helper_mtc0_mvpcontrol(arg
);
4656 check_insn(env
, ctx
, ASE_MT
);
4661 check_insn(env
, ctx
, ASE_MT
);
4676 check_insn(env
, ctx
, ASE_MT
);
4677 gen_helper_mtc0_vpecontrol(arg
);
4681 check_insn(env
, ctx
, ASE_MT
);
4682 gen_helper_mtc0_vpeconf0(arg
);
4686 check_insn(env
, ctx
, ASE_MT
);
4687 gen_helper_mtc0_vpeconf1(arg
);
4691 check_insn(env
, ctx
, ASE_MT
);
4692 gen_helper_mtc0_yqmask(arg
);
4696 check_insn(env
, ctx
, ASE_MT
);
4697 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPESchedule
));
4701 check_insn(env
, ctx
, ASE_MT
);
4702 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_VPEScheFBack
));
4703 rn
= "VPEScheFBack";
4706 check_insn(env
, ctx
, ASE_MT
);
4707 gen_helper_mtc0_vpeopt(arg
);
4717 gen_helper_mtc0_entrylo0(arg
);
4721 check_insn(env
, ctx
, ASE_MT
);
4722 gen_helper_mtc0_tcstatus(arg
);
4726 check_insn(env
, ctx
, ASE_MT
);
4727 gen_helper_mtc0_tcbind(arg
);
4731 check_insn(env
, ctx
, ASE_MT
);
4732 gen_helper_mtc0_tcrestart(arg
);
4736 check_insn(env
, ctx
, ASE_MT
);
4737 gen_helper_mtc0_tchalt(arg
);
4741 check_insn(env
, ctx
, ASE_MT
);
4742 gen_helper_mtc0_tccontext(arg
);
4746 check_insn(env
, ctx
, ASE_MT
);
4747 gen_helper_mtc0_tcschedule(arg
);
4751 check_insn(env
, ctx
, ASE_MT
);
4752 gen_helper_mtc0_tcschefback(arg
);
4762 gen_helper_mtc0_entrylo1(arg
);
4772 gen_helper_mtc0_context(arg
);
4776 // gen_helper_mtc0_contextconfig(arg); /* SmartMIPS ASE */
4777 rn
= "ContextConfig";
4786 gen_helper_mtc0_pagemask(arg
);
4790 check_insn(env
, ctx
, ISA_MIPS32R2
);
4791 gen_helper_mtc0_pagegrain(arg
);
4801 gen_helper_mtc0_wired(arg
);
4805 check_insn(env
, ctx
, ISA_MIPS32R2
);
4806 gen_helper_mtc0_srsconf0(arg
);
4810 check_insn(env
, ctx
, ISA_MIPS32R2
);
4811 gen_helper_mtc0_srsconf1(arg
);
4815 check_insn(env
, ctx
, ISA_MIPS32R2
);
4816 gen_helper_mtc0_srsconf2(arg
);
4820 check_insn(env
, ctx
, ISA_MIPS32R2
);
4821 gen_helper_mtc0_srsconf3(arg
);
4825 check_insn(env
, ctx
, ISA_MIPS32R2
);
4826 gen_helper_mtc0_srsconf4(arg
);
4836 check_insn(env
, ctx
, ISA_MIPS32R2
);
4837 gen_helper_mtc0_hwrena(arg
);
4851 gen_helper_mtc0_count(arg
);
4854 /* 6,7 are implementation dependent */
4858 /* Stop translation as we may have switched the execution mode */
4859 ctx
->bstate
= BS_STOP
;
4864 gen_helper_mtc0_entryhi(arg
);
4874 gen_helper_mtc0_compare(arg
);
4877 /* 6,7 are implementation dependent */
4881 /* Stop translation as we may have switched the execution mode */
4882 ctx
->bstate
= BS_STOP
;
4887 save_cpu_state(ctx
, 1);
4888 gen_helper_mtc0_status(arg
);
4889 /* BS_STOP isn't good enough here, hflags may have changed. */
4890 gen_save_pc(ctx
->pc
+ 4);
4891 ctx
->bstate
= BS_EXCP
;
4895 check_insn(env
, ctx
, ISA_MIPS32R2
);
4896 gen_helper_mtc0_intctl(arg
);
4897 /* Stop translation as we may have switched the execution mode */
4898 ctx
->bstate
= BS_STOP
;
4902 check_insn(env
, ctx
, ISA_MIPS32R2
);
4903 gen_helper_mtc0_srsctl(arg
);
4904 /* Stop translation as we may have switched the execution mode */
4905 ctx
->bstate
= BS_STOP
;
4909 check_insn(env
, ctx
, ISA_MIPS32R2
);
4910 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_SRSMap
));
4911 /* Stop translation as we may have switched the execution mode */
4912 ctx
->bstate
= BS_STOP
;
4922 save_cpu_state(ctx
, 1);
4923 gen_helper_mtc0_cause(arg
);
4933 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_EPC
));
4947 check_insn(env
, ctx
, ISA_MIPS32R2
);
4948 gen_helper_mtc0_ebase(arg
);
4958 gen_helper_mtc0_config0(arg
);
4960 /* Stop translation as we may have switched the execution mode */
4961 ctx
->bstate
= BS_STOP
;
4964 /* ignored, read only */
4968 gen_helper_mtc0_config2(arg
);
4970 /* Stop translation as we may have switched the execution mode */
4971 ctx
->bstate
= BS_STOP
;
4977 /* 6,7 are implementation dependent */
4979 rn
= "Invalid config selector";
4986 gen_helper_mtc0_lladdr(arg
);
4996 gen_helper_1i(mtc0_watchlo
, arg
, sel
);
5006 gen_helper_1i(mtc0_watchhi
, arg
, sel
);
5016 check_insn(env
, ctx
, ISA_MIPS3
);
5017 gen_helper_mtc0_xcontext(arg
);
5025 /* Officially reserved, but sel 0 is used for R1x000 framemask */
5028 gen_helper_mtc0_framemask(arg
);
5037 rn
= "Diagnostic"; /* implementation dependent */
5042 gen_helper_mtc0_debug(arg
); /* EJTAG support */
5043 /* BS_STOP isn't good enough here, hflags may have changed. */
5044 gen_save_pc(ctx
->pc
+ 4);
5045 ctx
->bstate
= BS_EXCP
;
5049 // gen_helper_mtc0_tracecontrol(arg); /* PDtrace support */
5050 /* Stop translation as we may have switched the execution mode */
5051 ctx
->bstate
= BS_STOP
;
5052 rn
= "TraceControl";
5055 // gen_helper_mtc0_tracecontrol2(arg); /* PDtrace support */
5056 /* Stop translation as we may have switched the execution mode */
5057 ctx
->bstate
= BS_STOP
;
5058 rn
= "TraceControl2";
5061 // gen_helper_mtc0_usertracedata(arg); /* PDtrace support */
5062 /* Stop translation as we may have switched the execution mode */
5063 ctx
->bstate
= BS_STOP
;
5064 rn
= "UserTraceData";
5067 // gen_helper_mtc0_tracebpc(arg); /* PDtrace support */
5068 /* Stop translation as we may have switched the execution mode */
5069 ctx
->bstate
= BS_STOP
;
5080 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_DEPC
));
5090 gen_helper_mtc0_performance0(arg
);
5091 rn
= "Performance0";
5094 // gen_helper_mtc0_performance1(arg);
5095 rn
= "Performance1";
5098 // gen_helper_mtc0_performance2(arg);
5099 rn
= "Performance2";
5102 // gen_helper_mtc0_performance3(arg);
5103 rn
= "Performance3";
5106 // gen_helper_mtc0_performance4(arg);
5107 rn
= "Performance4";
5110 // gen_helper_mtc0_performance5(arg);
5111 rn
= "Performance5";
5114 // gen_helper_mtc0_performance6(arg);
5115 rn
= "Performance6";
5118 // gen_helper_mtc0_performance7(arg);
5119 rn
= "Performance7";
5145 gen_helper_mtc0_taglo(arg
);
5152 gen_helper_mtc0_datalo(arg
);
5165 gen_helper_mtc0_taghi(arg
);
5172 gen_helper_mtc0_datahi(arg
);
5183 tcg_gen_st_tl(arg
, cpu_env
, offsetof(CPUState
, CP0_ErrorEPC
));
5194 gen_mtc0_store32(arg
, offsetof(CPUState
, CP0_DESAVE
));
5200 /* Stop translation as we may have switched the execution mode */
5201 ctx
->bstate
= BS_STOP
;
5206 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5207 /* For simplicity assume that all writes can cause interrupts. */
5210 ctx
->bstate
= BS_STOP
;
5215 LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn
, reg
, sel
);
5216 generate_exception(ctx
, EXCP_RI
);
5218 #endif /* TARGET_MIPS64 */
5220 static void gen_mftr(CPUState
*env
, DisasContext
*ctx
, int rt
, int rd
,
5221 int u
, int sel
, int h
)
5223 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5224 TCGv t0
= tcg_temp_local_new();
5226 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5227 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5228 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5229 tcg_gen_movi_tl(t0
, -1);
5230 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5231 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5232 tcg_gen_movi_tl(t0
, -1);
5238 gen_helper_mftc0_tcstatus(t0
);
5241 gen_helper_mftc0_tcbind(t0
);
5244 gen_helper_mftc0_tcrestart(t0
);
5247 gen_helper_mftc0_tchalt(t0
);
5250 gen_helper_mftc0_tccontext(t0
);
5253 gen_helper_mftc0_tcschedule(t0
);
5256 gen_helper_mftc0_tcschefback(t0
);
5259 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5266 gen_helper_mftc0_entryhi(t0
);
5269 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5275 gen_helper_mftc0_status(t0
);
5278 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5284 gen_helper_mftc0_debug(t0
);
5287 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5292 gen_mfc0(env
, ctx
, t0
, rt
, sel
);
5294 } else switch (sel
) {
5295 /* GPR registers. */
5297 gen_helper_1i(mftgpr
, t0
, rt
);
5299 /* Auxiliary CPU registers */
5303 gen_helper_1i(mftlo
, t0
, 0);
5306 gen_helper_1i(mfthi
, t0
, 0);
5309 gen_helper_1i(mftacx
, t0
, 0);
5312 gen_helper_1i(mftlo
, t0
, 1);
5315 gen_helper_1i(mfthi
, t0
, 1);
5318 gen_helper_1i(mftacx
, t0
, 1);
5321 gen_helper_1i(mftlo
, t0
, 2);
5324 gen_helper_1i(mfthi
, t0
, 2);
5327 gen_helper_1i(mftacx
, t0
, 2);
5330 gen_helper_1i(mftlo
, t0
, 3);
5333 gen_helper_1i(mfthi
, t0
, 3);
5336 gen_helper_1i(mftacx
, t0
, 3);
5339 gen_helper_mftdsp(t0
);
5345 /* Floating point (COP1). */
5347 /* XXX: For now we support only a single FPU context. */
5349 TCGv_i32 fp0
= tcg_temp_new_i32();
5351 gen_load_fpr32(fp0
, rt
);
5352 tcg_gen_ext_i32_tl(t0
, fp0
);
5353 tcg_temp_free_i32(fp0
);
5355 TCGv_i32 fp0
= tcg_temp_new_i32();
5357 gen_load_fpr32h(fp0
, rt
);
5358 tcg_gen_ext_i32_tl(t0
, fp0
);
5359 tcg_temp_free_i32(fp0
);
5363 /* XXX: For now we support only a single FPU context. */
5364 gen_helper_1i(cfc1
, t0
, rt
);
5366 /* COP2: Not implemented. */
5373 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5374 gen_store_gpr(t0
, rd
);
5380 LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt
, u
, sel
, h
);
5381 generate_exception(ctx
, EXCP_RI
);
5384 static void gen_mttr(CPUState
*env
, DisasContext
*ctx
, int rd
, int rt
,
5385 int u
, int sel
, int h
)
5387 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
5388 TCGv t0
= tcg_temp_local_new();
5390 gen_load_gpr(t0
, rt
);
5391 if ((env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) == 0 &&
5392 ((env
->tcs
[other_tc
].CP0_TCBind
& (0xf << CP0TCBd_CurVPE
)) !=
5393 (env
->active_tc
.CP0_TCBind
& (0xf << CP0TCBd_CurVPE
))))
5395 else if ((env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
)) >
5396 (env
->mvp
->CP0_MVPConf0
& (0xff << CP0MVPC0_PTC
)))
5403 gen_helper_mttc0_tcstatus(t0
);
5406 gen_helper_mttc0_tcbind(t0
);
5409 gen_helper_mttc0_tcrestart(t0
);
5412 gen_helper_mttc0_tchalt(t0
);
5415 gen_helper_mttc0_tccontext(t0
);
5418 gen_helper_mttc0_tcschedule(t0
);
5421 gen_helper_mttc0_tcschefback(t0
);
5424 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5431 gen_helper_mttc0_entryhi(t0
);
5434 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5440 gen_helper_mttc0_status(t0
);
5443 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5449 gen_helper_mttc0_debug(t0
);
5452 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5457 gen_mtc0(env
, ctx
, t0
, rd
, sel
);
5459 } else switch (sel
) {
5460 /* GPR registers. */
5462 gen_helper_1i(mttgpr
, t0
, rd
);
5464 /* Auxiliary CPU registers */
5468 gen_helper_1i(mttlo
, t0
, 0);
5471 gen_helper_1i(mtthi
, t0
, 0);
5474 gen_helper_1i(mttacx
, t0
, 0);
5477 gen_helper_1i(mttlo
, t0
, 1);
5480 gen_helper_1i(mtthi
, t0
, 1);
5483 gen_helper_1i(mttacx
, t0
, 1);
5486 gen_helper_1i(mttlo
, t0
, 2);
5489 gen_helper_1i(mtthi
, t0
, 2);
5492 gen_helper_1i(mttacx
, t0
, 2);
5495 gen_helper_1i(mttlo
, t0
, 3);
5498 gen_helper_1i(mtthi
, t0
, 3);
5501 gen_helper_1i(mttacx
, t0
, 3);
5504 gen_helper_mttdsp(t0
);
5510 /* Floating point (COP1). */
5512 /* XXX: For now we support only a single FPU context. */
5514 TCGv_i32 fp0
= tcg_temp_new_i32();
5516 tcg_gen_trunc_tl_i32(fp0
, t0
);
5517 gen_store_fpr32(fp0
, rd
);
5518 tcg_temp_free_i32(fp0
);
5520 TCGv_i32 fp0
= tcg_temp_new_i32();
5522 tcg_gen_trunc_tl_i32(fp0
, t0
);
5523 gen_store_fpr32h(fp0
, rd
);
5524 tcg_temp_free_i32(fp0
);
5528 /* XXX: For now we support only a single FPU context. */
5529 gen_helper_1i(ctc1
, t0
, rd
);
5531 /* COP2: Not implemented. */
5538 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5544 LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd
, u
, sel
, h
);
5545 generate_exception(ctx
, EXCP_RI
);
5548 static void gen_cp0 (CPUState
*env
, DisasContext
*ctx
, uint32_t opc
, int rt
, int rd
)
5550 const char *opn
= "ldst";
5558 gen_mfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5563 TCGv t0
= tcg_temp_new();
5565 gen_load_gpr(t0
, rt
);
5566 gen_mtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5571 #if defined(TARGET_MIPS64)
5573 check_insn(env
, ctx
, ISA_MIPS3
);
5578 gen_dmfc0(env
, ctx
, cpu_gpr
[rt
], rd
, ctx
->opcode
& 0x7);
5582 check_insn(env
, ctx
, ISA_MIPS3
);
5584 TCGv t0
= tcg_temp_new();
5586 gen_load_gpr(t0
, rt
);
5587 gen_dmtc0(env
, ctx
, t0
, rd
, ctx
->opcode
& 0x7);
5594 check_insn(env
, ctx
, ASE_MT
);
5599 gen_mftr(env
, ctx
, rt
, rd
, (ctx
->opcode
>> 5) & 1,
5600 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5604 check_insn(env
, ctx
, ASE_MT
);
5605 gen_mttr(env
, ctx
, rd
, rt
, (ctx
->opcode
>> 5) & 1,
5606 ctx
->opcode
& 0x7, (ctx
->opcode
>> 4) & 1);
5611 if (!env
->tlb
->helper_tlbwi
)
5617 if (!env
->tlb
->helper_tlbwr
)
5623 if (!env
->tlb
->helper_tlbp
)
5629 if (!env
->tlb
->helper_tlbr
)
5635 check_insn(env
, ctx
, ISA_MIPS2
);
5637 ctx
->bstate
= BS_EXCP
;
5641 check_insn(env
, ctx
, ISA_MIPS32
);
5642 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
5644 generate_exception(ctx
, EXCP_RI
);
5647 ctx
->bstate
= BS_EXCP
;
5652 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
5653 /* If we get an exception, we want to restart at next instruction */
5655 save_cpu_state(ctx
, 1);
5658 ctx
->bstate
= BS_EXCP
;
5663 generate_exception(ctx
, EXCP_RI
);
5666 MIPS_DEBUG("%s %s %d", opn
, regnames
[rt
], rd
);
5668 #endif /* !CONFIG_USER_ONLY */
5670 /* CP1 Branches (before delay slot) */
5671 static void gen_compute_branch1 (CPUState
*env
, DisasContext
*ctx
, uint32_t op
,
5672 int32_t cc
, int32_t offset
)
5674 target_ulong btarget
;
5675 const char *opn
= "cp1 cond branch";
5676 TCGv_i32 t0
= tcg_temp_new_i32();
5679 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
5681 btarget
= ctx
->pc
+ 4 + offset
;
5685 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5686 tcg_gen_not_i32(t0
, t0
);
5687 tcg_gen_andi_i32(t0
, t0
, 1);
5688 tcg_gen_extu_i32_tl(bcond
, t0
);
5692 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5693 tcg_gen_not_i32(t0
, t0
);
5694 tcg_gen_andi_i32(t0
, t0
, 1);
5695 tcg_gen_extu_i32_tl(bcond
, t0
);
5699 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5700 tcg_gen_andi_i32(t0
, t0
, 1);
5701 tcg_gen_extu_i32_tl(bcond
, t0
);
5705 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5706 tcg_gen_andi_i32(t0
, t0
, 1);
5707 tcg_gen_extu_i32_tl(bcond
, t0
);
5710 ctx
->hflags
|= MIPS_HFLAG_BL
;
5714 TCGv_i32 t1
= tcg_temp_new_i32();
5715 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5716 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5717 tcg_gen_or_i32(t0
, t0
, t1
);
5718 tcg_temp_free_i32(t1
);
5719 tcg_gen_not_i32(t0
, t0
);
5720 tcg_gen_andi_i32(t0
, t0
, 1);
5721 tcg_gen_extu_i32_tl(bcond
, t0
);
5727 TCGv_i32 t1
= tcg_temp_new_i32();
5728 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5729 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5730 tcg_gen_or_i32(t0
, t0
, t1
);
5731 tcg_temp_free_i32(t1
);
5732 tcg_gen_andi_i32(t0
, t0
, 1);
5733 tcg_gen_extu_i32_tl(bcond
, t0
);
5739 TCGv_i32 t1
= tcg_temp_new_i32();
5740 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5741 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5742 tcg_gen_or_i32(t0
, t0
, t1
);
5743 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5744 tcg_gen_or_i32(t0
, t0
, t1
);
5745 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5746 tcg_gen_or_i32(t0
, t0
, t1
);
5747 tcg_temp_free_i32(t1
);
5748 tcg_gen_not_i32(t0
, t0
);
5749 tcg_gen_andi_i32(t0
, t0
, 1);
5750 tcg_gen_extu_i32_tl(bcond
, t0
);
5756 TCGv_i32 t1
= tcg_temp_new_i32();
5757 tcg_gen_shri_i32(t0
, fpu_fcr31
, get_fp_bit(cc
));
5758 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+1));
5759 tcg_gen_or_i32(t0
, t0
, t1
);
5760 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+2));
5761 tcg_gen_or_i32(t0
, t0
, t1
);
5762 tcg_gen_shri_i32(t1
, fpu_fcr31
, get_fp_bit(cc
+3));
5763 tcg_gen_or_i32(t0
, t0
, t1
);
5764 tcg_temp_free_i32(t1
);
5765 tcg_gen_andi_i32(t0
, t0
, 1);
5766 tcg_gen_extu_i32_tl(bcond
, t0
);
5770 ctx
->hflags
|= MIPS_HFLAG_BC
;
5774 generate_exception (ctx
, EXCP_RI
);
5777 MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx
, opn
,
5778 ctx
->hflags
, btarget
);
5779 ctx
->btarget
= btarget
;
5782 tcg_temp_free_i32(t0
);
5785 /* Coprocessor 1 (FPU) */
5787 #define FOP(func, fmt) (((fmt) << 21) | (func))
5789 static void gen_cp1 (DisasContext
*ctx
, uint32_t opc
, int rt
, int fs
)
5791 const char *opn
= "cp1 move";
5792 TCGv t0
= tcg_temp_new();
5797 TCGv_i32 fp0
= tcg_temp_new_i32();
5799 gen_load_fpr32(fp0
, fs
);
5800 tcg_gen_ext_i32_tl(t0
, fp0
);
5801 tcg_temp_free_i32(fp0
);
5803 gen_store_gpr(t0
, rt
);
5807 gen_load_gpr(t0
, rt
);
5809 TCGv_i32 fp0
= tcg_temp_new_i32();
5811 tcg_gen_trunc_tl_i32(fp0
, t0
);
5812 gen_store_fpr32(fp0
, fs
);
5813 tcg_temp_free_i32(fp0
);
5818 gen_helper_1i(cfc1
, t0
, fs
);
5819 gen_store_gpr(t0
, rt
);
5823 gen_load_gpr(t0
, rt
);
5824 gen_helper_1i(ctc1
, t0
, fs
);
5827 #if defined(TARGET_MIPS64)
5829 gen_load_fpr64(ctx
, t0
, fs
);
5830 gen_store_gpr(t0
, rt
);
5834 gen_load_gpr(t0
, rt
);
5835 gen_store_fpr64(ctx
, t0
, fs
);
5841 TCGv_i32 fp0
= tcg_temp_new_i32();
5843 gen_load_fpr32h(fp0
, fs
);
5844 tcg_gen_ext_i32_tl(t0
, fp0
);
5845 tcg_temp_free_i32(fp0
);
5847 gen_store_gpr(t0
, rt
);
5851 gen_load_gpr(t0
, rt
);
5853 TCGv_i32 fp0
= tcg_temp_new_i32();
5855 tcg_gen_trunc_tl_i32(fp0
, t0
);
5856 gen_store_fpr32h(fp0
, fs
);
5857 tcg_temp_free_i32(fp0
);
5863 generate_exception (ctx
, EXCP_RI
);
5866 MIPS_DEBUG("%s %s %s", opn
, regnames
[rt
], fregnames
[fs
]);
5872 static void gen_movci (DisasContext
*ctx
, int rd
, int rs
, int cc
, int tf
)
5888 l1
= gen_new_label();
5889 t0
= tcg_temp_new_i32();
5890 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5891 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5892 tcg_temp_free_i32(t0
);
5894 tcg_gen_movi_tl(cpu_gpr
[rd
], 0);
5896 tcg_gen_mov_tl(cpu_gpr
[rd
], cpu_gpr
[rs
]);
5901 static inline void gen_movcf_s (int fs
, int fd
, int cc
, int tf
)
5904 TCGv_i32 t0
= tcg_temp_new_i32();
5905 int l1
= gen_new_label();
5912 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5913 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5914 gen_load_fpr32(t0
, fs
);
5915 gen_store_fpr32(t0
, fd
);
5917 tcg_temp_free_i32(t0
);
5920 static inline void gen_movcf_d (DisasContext
*ctx
, int fs
, int fd
, int cc
, int tf
)
5923 TCGv_i32 t0
= tcg_temp_new_i32();
5925 int l1
= gen_new_label();
5932 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5933 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5934 tcg_temp_free_i32(t0
);
5935 fp0
= tcg_temp_new_i64();
5936 gen_load_fpr64(ctx
, fp0
, fs
);
5937 gen_store_fpr64(ctx
, fp0
, fd
);
5938 tcg_temp_free_i64(fp0
);
5942 static inline void gen_movcf_ps (int fs
, int fd
, int cc
, int tf
)
5945 TCGv_i32 t0
= tcg_temp_new_i32();
5946 int l1
= gen_new_label();
5947 int l2
= gen_new_label();
5954 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
));
5955 tcg_gen_brcondi_i32(cond
, t0
, 0, l1
);
5956 gen_load_fpr32(t0
, fs
);
5957 gen_store_fpr32(t0
, fd
);
5960 tcg_gen_andi_i32(t0
, fpu_fcr31
, 1 << get_fp_bit(cc
+1));
5961 tcg_gen_brcondi_i32(cond
, t0
, 0, l2
);
5962 gen_load_fpr32h(t0
, fs
);
5963 gen_store_fpr32h(t0
, fd
);
5964 tcg_temp_free_i32(t0
);
5969 static void gen_farith (DisasContext
*ctx
, uint32_t op1
,
5970 int ft
, int fs
, int fd
, int cc
)
5972 const char *opn
= "farith";
5973 const char *condnames
[] = {
5991 const char *condnames_abs
[] = {
6009 enum { BINOP
, CMPOP
, OTHEROP
} optype
= OTHEROP
;
6010 uint32_t func
= ctx
->opcode
& 0x3f;
6012 switch (ctx
->opcode
& FOP(0x3f, 0x1f)) {
6015 TCGv_i32 fp0
= tcg_temp_new_i32();
6016 TCGv_i32 fp1
= tcg_temp_new_i32();
6018 gen_load_fpr32(fp0
, fs
);
6019 gen_load_fpr32(fp1
, ft
);
6020 gen_helper_float_add_s(fp0
, fp0
, fp1
);
6021 tcg_temp_free_i32(fp1
);
6022 gen_store_fpr32(fp0
, fd
);
6023 tcg_temp_free_i32(fp0
);
6030 TCGv_i32 fp0
= tcg_temp_new_i32();
6031 TCGv_i32 fp1
= tcg_temp_new_i32();
6033 gen_load_fpr32(fp0
, fs
);
6034 gen_load_fpr32(fp1
, ft
);
6035 gen_helper_float_sub_s(fp0
, fp0
, fp1
);
6036 tcg_temp_free_i32(fp1
);
6037 gen_store_fpr32(fp0
, fd
);
6038 tcg_temp_free_i32(fp0
);
6045 TCGv_i32 fp0
= tcg_temp_new_i32();
6046 TCGv_i32 fp1
= tcg_temp_new_i32();
6048 gen_load_fpr32(fp0
, fs
);
6049 gen_load_fpr32(fp1
, ft
);
6050 gen_helper_float_mul_s(fp0
, fp0
, fp1
);
6051 tcg_temp_free_i32(fp1
);
6052 gen_store_fpr32(fp0
, fd
);
6053 tcg_temp_free_i32(fp0
);
6060 TCGv_i32 fp0
= tcg_temp_new_i32();
6061 TCGv_i32 fp1
= tcg_temp_new_i32();
6063 gen_load_fpr32(fp0
, fs
);
6064 gen_load_fpr32(fp1
, ft
);
6065 gen_helper_float_div_s(fp0
, fp0
, fp1
);
6066 tcg_temp_free_i32(fp1
);
6067 gen_store_fpr32(fp0
, fd
);
6068 tcg_temp_free_i32(fp0
);
6075 TCGv_i32 fp0
= tcg_temp_new_i32();
6077 gen_load_fpr32(fp0
, fs
);
6078 gen_helper_float_sqrt_s(fp0
, fp0
);
6079 gen_store_fpr32(fp0
, fd
);
6080 tcg_temp_free_i32(fp0
);
6086 TCGv_i32 fp0
= tcg_temp_new_i32();
6088 gen_load_fpr32(fp0
, fs
);
6089 gen_helper_float_abs_s(fp0
, fp0
);
6090 gen_store_fpr32(fp0
, fd
);
6091 tcg_temp_free_i32(fp0
);
6097 TCGv_i32 fp0
= tcg_temp_new_i32();
6099 gen_load_fpr32(fp0
, fs
);
6100 gen_store_fpr32(fp0
, fd
);
6101 tcg_temp_free_i32(fp0
);
6107 TCGv_i32 fp0
= tcg_temp_new_i32();
6109 gen_load_fpr32(fp0
, fs
);
6110 gen_helper_float_chs_s(fp0
, fp0
);
6111 gen_store_fpr32(fp0
, fd
);
6112 tcg_temp_free_i32(fp0
);
6117 check_cp1_64bitmode(ctx
);
6119 TCGv_i32 fp32
= tcg_temp_new_i32();
6120 TCGv_i64 fp64
= tcg_temp_new_i64();
6122 gen_load_fpr32(fp32
, fs
);
6123 gen_helper_float_roundl_s(fp64
, fp32
);
6124 tcg_temp_free_i32(fp32
);
6125 gen_store_fpr64(ctx
, fp64
, fd
);
6126 tcg_temp_free_i64(fp64
);
6131 check_cp1_64bitmode(ctx
);
6133 TCGv_i32 fp32
= tcg_temp_new_i32();
6134 TCGv_i64 fp64
= tcg_temp_new_i64();
6136 gen_load_fpr32(fp32
, fs
);
6137 gen_helper_float_truncl_s(fp64
, fp32
);
6138 tcg_temp_free_i32(fp32
);
6139 gen_store_fpr64(ctx
, fp64
, fd
);
6140 tcg_temp_free_i64(fp64
);
6145 check_cp1_64bitmode(ctx
);
6147 TCGv_i32 fp32
= tcg_temp_new_i32();
6148 TCGv_i64 fp64
= tcg_temp_new_i64();
6150 gen_load_fpr32(fp32
, fs
);
6151 gen_helper_float_ceill_s(fp64
, fp32
);
6152 tcg_temp_free_i32(fp32
);
6153 gen_store_fpr64(ctx
, fp64
, fd
);
6154 tcg_temp_free_i64(fp64
);
6159 check_cp1_64bitmode(ctx
);
6161 TCGv_i32 fp32
= tcg_temp_new_i32();
6162 TCGv_i64 fp64
= tcg_temp_new_i64();
6164 gen_load_fpr32(fp32
, fs
);
6165 gen_helper_float_floorl_s(fp64
, fp32
);
6166 tcg_temp_free_i32(fp32
);
6167 gen_store_fpr64(ctx
, fp64
, fd
);
6168 tcg_temp_free_i64(fp64
);
6174 TCGv_i32 fp0
= tcg_temp_new_i32();
6176 gen_load_fpr32(fp0
, fs
);
6177 gen_helper_float_roundw_s(fp0
, fp0
);
6178 gen_store_fpr32(fp0
, fd
);
6179 tcg_temp_free_i32(fp0
);
6185 TCGv_i32 fp0
= tcg_temp_new_i32();
6187 gen_load_fpr32(fp0
, fs
);
6188 gen_helper_float_truncw_s(fp0
, fp0
);
6189 gen_store_fpr32(fp0
, fd
);
6190 tcg_temp_free_i32(fp0
);
6196 TCGv_i32 fp0
= tcg_temp_new_i32();
6198 gen_load_fpr32(fp0
, fs
);
6199 gen_helper_float_ceilw_s(fp0
, fp0
);
6200 gen_store_fpr32(fp0
, fd
);
6201 tcg_temp_free_i32(fp0
);
6207 TCGv_i32 fp0
= tcg_temp_new_i32();
6209 gen_load_fpr32(fp0
, fs
);
6210 gen_helper_float_floorw_s(fp0
, fp0
);
6211 gen_store_fpr32(fp0
, fd
);
6212 tcg_temp_free_i32(fp0
);
6217 gen_movcf_s(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6222 int l1
= gen_new_label();
6226 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6228 fp0
= tcg_temp_new_i32();
6229 gen_load_fpr32(fp0
, fs
);
6230 gen_store_fpr32(fp0
, fd
);
6231 tcg_temp_free_i32(fp0
);
6238 int l1
= gen_new_label();
6242 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6243 fp0
= tcg_temp_new_i32();
6244 gen_load_fpr32(fp0
, fs
);
6245 gen_store_fpr32(fp0
, fd
);
6246 tcg_temp_free_i32(fp0
);
6255 TCGv_i32 fp0
= tcg_temp_new_i32();
6257 gen_load_fpr32(fp0
, fs
);
6258 gen_helper_float_recip_s(fp0
, fp0
);
6259 gen_store_fpr32(fp0
, fd
);
6260 tcg_temp_free_i32(fp0
);
6267 TCGv_i32 fp0
= tcg_temp_new_i32();
6269 gen_load_fpr32(fp0
, fs
);
6270 gen_helper_float_rsqrt_s(fp0
, fp0
);
6271 gen_store_fpr32(fp0
, fd
);
6272 tcg_temp_free_i32(fp0
);
6277 check_cp1_64bitmode(ctx
);
6279 TCGv_i32 fp0
= tcg_temp_new_i32();
6280 TCGv_i32 fp1
= tcg_temp_new_i32();
6282 gen_load_fpr32(fp0
, fs
);
6283 gen_load_fpr32(fp1
, fd
);
6284 gen_helper_float_recip2_s(fp0
, fp0
, fp1
);
6285 tcg_temp_free_i32(fp1
);
6286 gen_store_fpr32(fp0
, fd
);
6287 tcg_temp_free_i32(fp0
);
6292 check_cp1_64bitmode(ctx
);
6294 TCGv_i32 fp0
= tcg_temp_new_i32();
6296 gen_load_fpr32(fp0
, fs
);
6297 gen_helper_float_recip1_s(fp0
, fp0
);
6298 gen_store_fpr32(fp0
, fd
);
6299 tcg_temp_free_i32(fp0
);
6304 check_cp1_64bitmode(ctx
);
6306 TCGv_i32 fp0
= tcg_temp_new_i32();
6308 gen_load_fpr32(fp0
, fs
);
6309 gen_helper_float_rsqrt1_s(fp0
, fp0
);
6310 gen_store_fpr32(fp0
, fd
);
6311 tcg_temp_free_i32(fp0
);
6316 check_cp1_64bitmode(ctx
);
6318 TCGv_i32 fp0
= tcg_temp_new_i32();
6319 TCGv_i32 fp1
= tcg_temp_new_i32();
6321 gen_load_fpr32(fp0
, fs
);
6322 gen_load_fpr32(fp1
, ft
);
6323 gen_helper_float_rsqrt2_s(fp0
, fp0
, fp1
);
6324 tcg_temp_free_i32(fp1
);
6325 gen_store_fpr32(fp0
, fd
);
6326 tcg_temp_free_i32(fp0
);
6331 check_cp1_registers(ctx
, fd
);
6333 TCGv_i32 fp32
= tcg_temp_new_i32();
6334 TCGv_i64 fp64
= tcg_temp_new_i64();
6336 gen_load_fpr32(fp32
, fs
);
6337 gen_helper_float_cvtd_s(fp64
, fp32
);
6338 tcg_temp_free_i32(fp32
);
6339 gen_store_fpr64(ctx
, fp64
, fd
);
6340 tcg_temp_free_i64(fp64
);
6346 TCGv_i32 fp0
= tcg_temp_new_i32();
6348 gen_load_fpr32(fp0
, fs
);
6349 gen_helper_float_cvtw_s(fp0
, fp0
);
6350 gen_store_fpr32(fp0
, fd
);
6351 tcg_temp_free_i32(fp0
);
6356 check_cp1_64bitmode(ctx
);
6358 TCGv_i32 fp32
= tcg_temp_new_i32();
6359 TCGv_i64 fp64
= tcg_temp_new_i64();
6361 gen_load_fpr32(fp32
, fs
);
6362 gen_helper_float_cvtl_s(fp64
, fp32
);
6363 tcg_temp_free_i32(fp32
);
6364 gen_store_fpr64(ctx
, fp64
, fd
);
6365 tcg_temp_free_i64(fp64
);
6370 check_cp1_64bitmode(ctx
);
6372 TCGv_i64 fp64
= tcg_temp_new_i64();
6373 TCGv_i32 fp32_0
= tcg_temp_new_i32();
6374 TCGv_i32 fp32_1
= tcg_temp_new_i32();
6376 gen_load_fpr32(fp32_0
, fs
);
6377 gen_load_fpr32(fp32_1
, ft
);
6378 tcg_gen_concat_i32_i64(fp64
, fp32_0
, fp32_1
);
6379 tcg_temp_free_i32(fp32_1
);
6380 tcg_temp_free_i32(fp32_0
);
6381 gen_store_fpr64(ctx
, fp64
, fd
);
6382 tcg_temp_free_i64(fp64
);
6403 TCGv_i32 fp0
= tcg_temp_new_i32();
6404 TCGv_i32 fp1
= tcg_temp_new_i32();
6406 gen_load_fpr32(fp0
, fs
);
6407 gen_load_fpr32(fp1
, ft
);
6408 if (ctx
->opcode
& (1 << 6)) {
6410 gen_cmpabs_s(func
-48, fp0
, fp1
, cc
);
6411 opn
= condnames_abs
[func
-48];
6413 gen_cmp_s(func
-48, fp0
, fp1
, cc
);
6414 opn
= condnames
[func
-48];
6416 tcg_temp_free_i32(fp0
);
6417 tcg_temp_free_i32(fp1
);
6421 check_cp1_registers(ctx
, fs
| ft
| fd
);
6423 TCGv_i64 fp0
= tcg_temp_new_i64();
6424 TCGv_i64 fp1
= tcg_temp_new_i64();
6426 gen_load_fpr64(ctx
, fp0
, fs
);
6427 gen_load_fpr64(ctx
, fp1
, ft
);
6428 gen_helper_float_add_d(fp0
, fp0
, fp1
);
6429 tcg_temp_free_i64(fp1
);
6430 gen_store_fpr64(ctx
, fp0
, fd
);
6431 tcg_temp_free_i64(fp0
);
6437 check_cp1_registers(ctx
, fs
| ft
| fd
);
6439 TCGv_i64 fp0
= tcg_temp_new_i64();
6440 TCGv_i64 fp1
= tcg_temp_new_i64();
6442 gen_load_fpr64(ctx
, fp0
, fs
);
6443 gen_load_fpr64(ctx
, fp1
, ft
);
6444 gen_helper_float_sub_d(fp0
, fp0
, fp1
);
6445 tcg_temp_free_i64(fp1
);
6446 gen_store_fpr64(ctx
, fp0
, fd
);
6447 tcg_temp_free_i64(fp0
);
6453 check_cp1_registers(ctx
, fs
| ft
| fd
);
6455 TCGv_i64 fp0
= tcg_temp_new_i64();
6456 TCGv_i64 fp1
= tcg_temp_new_i64();
6458 gen_load_fpr64(ctx
, fp0
, fs
);
6459 gen_load_fpr64(ctx
, fp1
, ft
);
6460 gen_helper_float_mul_d(fp0
, fp0
, fp1
);
6461 tcg_temp_free_i64(fp1
);
6462 gen_store_fpr64(ctx
, fp0
, fd
);
6463 tcg_temp_free_i64(fp0
);
6469 check_cp1_registers(ctx
, fs
| ft
| fd
);
6471 TCGv_i64 fp0
= tcg_temp_new_i64();
6472 TCGv_i64 fp1
= tcg_temp_new_i64();
6474 gen_load_fpr64(ctx
, fp0
, fs
);
6475 gen_load_fpr64(ctx
, fp1
, ft
);
6476 gen_helper_float_div_d(fp0
, fp0
, fp1
);
6477 tcg_temp_free_i64(fp1
);
6478 gen_store_fpr64(ctx
, fp0
, fd
);
6479 tcg_temp_free_i64(fp0
);
6485 check_cp1_registers(ctx
, fs
| fd
);
6487 TCGv_i64 fp0
= tcg_temp_new_i64();
6489 gen_load_fpr64(ctx
, fp0
, fs
);
6490 gen_helper_float_sqrt_d(fp0
, fp0
);
6491 gen_store_fpr64(ctx
, fp0
, fd
);
6492 tcg_temp_free_i64(fp0
);
6497 check_cp1_registers(ctx
, fs
| fd
);
6499 TCGv_i64 fp0
= tcg_temp_new_i64();
6501 gen_load_fpr64(ctx
, fp0
, fs
);
6502 gen_helper_float_abs_d(fp0
, fp0
);
6503 gen_store_fpr64(ctx
, fp0
, fd
);
6504 tcg_temp_free_i64(fp0
);
6509 check_cp1_registers(ctx
, fs
| fd
);
6511 TCGv_i64 fp0
= tcg_temp_new_i64();
6513 gen_load_fpr64(ctx
, fp0
, fs
);
6514 gen_store_fpr64(ctx
, fp0
, fd
);
6515 tcg_temp_free_i64(fp0
);
6520 check_cp1_registers(ctx
, fs
| fd
);
6522 TCGv_i64 fp0
= tcg_temp_new_i64();
6524 gen_load_fpr64(ctx
, fp0
, fs
);
6525 gen_helper_float_chs_d(fp0
, fp0
);
6526 gen_store_fpr64(ctx
, fp0
, fd
);
6527 tcg_temp_free_i64(fp0
);
6532 check_cp1_64bitmode(ctx
);
6534 TCGv_i64 fp0
= tcg_temp_new_i64();
6536 gen_load_fpr64(ctx
, fp0
, fs
);
6537 gen_helper_float_roundl_d(fp0
, fp0
);
6538 gen_store_fpr64(ctx
, fp0
, fd
);
6539 tcg_temp_free_i64(fp0
);
6544 check_cp1_64bitmode(ctx
);
6546 TCGv_i64 fp0
= tcg_temp_new_i64();
6548 gen_load_fpr64(ctx
, fp0
, fs
);
6549 gen_helper_float_truncl_d(fp0
, fp0
);
6550 gen_store_fpr64(ctx
, fp0
, fd
);
6551 tcg_temp_free_i64(fp0
);
6556 check_cp1_64bitmode(ctx
);
6558 TCGv_i64 fp0
= tcg_temp_new_i64();
6560 gen_load_fpr64(ctx
, fp0
, fs
);
6561 gen_helper_float_ceill_d(fp0
, fp0
);
6562 gen_store_fpr64(ctx
, fp0
, fd
);
6563 tcg_temp_free_i64(fp0
);
6568 check_cp1_64bitmode(ctx
);
6570 TCGv_i64 fp0
= tcg_temp_new_i64();
6572 gen_load_fpr64(ctx
, fp0
, fs
);
6573 gen_helper_float_floorl_d(fp0
, fp0
);
6574 gen_store_fpr64(ctx
, fp0
, fd
);
6575 tcg_temp_free_i64(fp0
);
6580 check_cp1_registers(ctx
, fs
);
6582 TCGv_i32 fp32
= tcg_temp_new_i32();
6583 TCGv_i64 fp64
= tcg_temp_new_i64();
6585 gen_load_fpr64(ctx
, fp64
, fs
);
6586 gen_helper_float_roundw_d(fp32
, fp64
);
6587 tcg_temp_free_i64(fp64
);
6588 gen_store_fpr32(fp32
, fd
);
6589 tcg_temp_free_i32(fp32
);
6594 check_cp1_registers(ctx
, fs
);
6596 TCGv_i32 fp32
= tcg_temp_new_i32();
6597 TCGv_i64 fp64
= tcg_temp_new_i64();
6599 gen_load_fpr64(ctx
, fp64
, fs
);
6600 gen_helper_float_truncw_d(fp32
, fp64
);
6601 tcg_temp_free_i64(fp64
);
6602 gen_store_fpr32(fp32
, fd
);
6603 tcg_temp_free_i32(fp32
);
6608 check_cp1_registers(ctx
, fs
);
6610 TCGv_i32 fp32
= tcg_temp_new_i32();
6611 TCGv_i64 fp64
= tcg_temp_new_i64();
6613 gen_load_fpr64(ctx
, fp64
, fs
);
6614 gen_helper_float_ceilw_d(fp32
, fp64
);
6615 tcg_temp_free_i64(fp64
);
6616 gen_store_fpr32(fp32
, fd
);
6617 tcg_temp_free_i32(fp32
);
6622 check_cp1_registers(ctx
, fs
);
6624 TCGv_i32 fp32
= tcg_temp_new_i32();
6625 TCGv_i64 fp64
= tcg_temp_new_i64();
6627 gen_load_fpr64(ctx
, fp64
, fs
);
6628 gen_helper_float_floorw_d(fp32
, fp64
);
6629 tcg_temp_free_i64(fp64
);
6630 gen_store_fpr32(fp32
, fd
);
6631 tcg_temp_free_i32(fp32
);
6636 gen_movcf_d(ctx
, fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6641 int l1
= gen_new_label();
6645 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6647 fp0
= tcg_temp_new_i64();
6648 gen_load_fpr64(ctx
, fp0
, fs
);
6649 gen_store_fpr64(ctx
, fp0
, fd
);
6650 tcg_temp_free_i64(fp0
);
6657 int l1
= gen_new_label();
6661 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6662 fp0
= tcg_temp_new_i64();
6663 gen_load_fpr64(ctx
, fp0
, fs
);
6664 gen_store_fpr64(ctx
, fp0
, fd
);
6665 tcg_temp_free_i64(fp0
);
6672 check_cp1_64bitmode(ctx
);
6674 TCGv_i64 fp0
= tcg_temp_new_i64();
6676 gen_load_fpr64(ctx
, fp0
, fs
);
6677 gen_helper_float_recip_d(fp0
, fp0
);
6678 gen_store_fpr64(ctx
, fp0
, fd
);
6679 tcg_temp_free_i64(fp0
);
6684 check_cp1_64bitmode(ctx
);
6686 TCGv_i64 fp0
= tcg_temp_new_i64();
6688 gen_load_fpr64(ctx
, fp0
, fs
);
6689 gen_helper_float_rsqrt_d(fp0
, fp0
);
6690 gen_store_fpr64(ctx
, fp0
, fd
);
6691 tcg_temp_free_i64(fp0
);
6696 check_cp1_64bitmode(ctx
);
6698 TCGv_i64 fp0
= tcg_temp_new_i64();
6699 TCGv_i64 fp1
= tcg_temp_new_i64();
6701 gen_load_fpr64(ctx
, fp0
, fs
);
6702 gen_load_fpr64(ctx
, fp1
, ft
);
6703 gen_helper_float_recip2_d(fp0
, fp0
, fp1
);
6704 tcg_temp_free_i64(fp1
);
6705 gen_store_fpr64(ctx
, fp0
, fd
);
6706 tcg_temp_free_i64(fp0
);
6711 check_cp1_64bitmode(ctx
);
6713 TCGv_i64 fp0
= tcg_temp_new_i64();
6715 gen_load_fpr64(ctx
, fp0
, fs
);
6716 gen_helper_float_recip1_d(fp0
, fp0
);
6717 gen_store_fpr64(ctx
, fp0
, fd
);
6718 tcg_temp_free_i64(fp0
);
6723 check_cp1_64bitmode(ctx
);
6725 TCGv_i64 fp0
= tcg_temp_new_i64();
6727 gen_load_fpr64(ctx
, fp0
, fs
);
6728 gen_helper_float_rsqrt1_d(fp0
, fp0
);
6729 gen_store_fpr64(ctx
, fp0
, fd
);
6730 tcg_temp_free_i64(fp0
);
6735 check_cp1_64bitmode(ctx
);
6737 TCGv_i64 fp0
= tcg_temp_new_i64();
6738 TCGv_i64 fp1
= tcg_temp_new_i64();
6740 gen_load_fpr64(ctx
, fp0
, fs
);
6741 gen_load_fpr64(ctx
, fp1
, ft
);
6742 gen_helper_float_rsqrt2_d(fp0
, fp0
, fp1
);
6743 tcg_temp_free_i64(fp1
);
6744 gen_store_fpr64(ctx
, fp0
, fd
);
6745 tcg_temp_free_i64(fp0
);
6766 TCGv_i64 fp0
= tcg_temp_new_i64();
6767 TCGv_i64 fp1
= tcg_temp_new_i64();
6769 gen_load_fpr64(ctx
, fp0
, fs
);
6770 gen_load_fpr64(ctx
, fp1
, ft
);
6771 if (ctx
->opcode
& (1 << 6)) {
6773 check_cp1_registers(ctx
, fs
| ft
);
6774 gen_cmpabs_d(func
-48, fp0
, fp1
, cc
);
6775 opn
= condnames_abs
[func
-48];
6777 check_cp1_registers(ctx
, fs
| ft
);
6778 gen_cmp_d(func
-48, fp0
, fp1
, cc
);
6779 opn
= condnames
[func
-48];
6781 tcg_temp_free_i64(fp0
);
6782 tcg_temp_free_i64(fp1
);
6786 check_cp1_registers(ctx
, fs
);
6788 TCGv_i32 fp32
= tcg_temp_new_i32();
6789 TCGv_i64 fp64
= tcg_temp_new_i64();
6791 gen_load_fpr64(ctx
, fp64
, fs
);
6792 gen_helper_float_cvts_d(fp32
, fp64
);
6793 tcg_temp_free_i64(fp64
);
6794 gen_store_fpr32(fp32
, fd
);
6795 tcg_temp_free_i32(fp32
);
6800 check_cp1_registers(ctx
, fs
);
6802 TCGv_i32 fp32
= tcg_temp_new_i32();
6803 TCGv_i64 fp64
= tcg_temp_new_i64();
6805 gen_load_fpr64(ctx
, fp64
, fs
);
6806 gen_helper_float_cvtw_d(fp32
, fp64
);
6807 tcg_temp_free_i64(fp64
);
6808 gen_store_fpr32(fp32
, fd
);
6809 tcg_temp_free_i32(fp32
);
6814 check_cp1_64bitmode(ctx
);
6816 TCGv_i64 fp0
= tcg_temp_new_i64();
6818 gen_load_fpr64(ctx
, fp0
, fs
);
6819 gen_helper_float_cvtl_d(fp0
, fp0
);
6820 gen_store_fpr64(ctx
, fp0
, fd
);
6821 tcg_temp_free_i64(fp0
);
6827 TCGv_i32 fp0
= tcg_temp_new_i32();
6829 gen_load_fpr32(fp0
, fs
);
6830 gen_helper_float_cvts_w(fp0
, fp0
);
6831 gen_store_fpr32(fp0
, fd
);
6832 tcg_temp_free_i32(fp0
);
6837 check_cp1_registers(ctx
, fd
);
6839 TCGv_i32 fp32
= tcg_temp_new_i32();
6840 TCGv_i64 fp64
= tcg_temp_new_i64();
6842 gen_load_fpr32(fp32
, fs
);
6843 gen_helper_float_cvtd_w(fp64
, fp32
);
6844 tcg_temp_free_i32(fp32
);
6845 gen_store_fpr64(ctx
, fp64
, fd
);
6846 tcg_temp_free_i64(fp64
);
6851 check_cp1_64bitmode(ctx
);
6853 TCGv_i32 fp32
= tcg_temp_new_i32();
6854 TCGv_i64 fp64
= tcg_temp_new_i64();
6856 gen_load_fpr64(ctx
, fp64
, fs
);
6857 gen_helper_float_cvts_l(fp32
, fp64
);
6858 tcg_temp_free_i64(fp64
);
6859 gen_store_fpr32(fp32
, fd
);
6860 tcg_temp_free_i32(fp32
);
6865 check_cp1_64bitmode(ctx
);
6867 TCGv_i64 fp0
= tcg_temp_new_i64();
6869 gen_load_fpr64(ctx
, fp0
, fs
);
6870 gen_helper_float_cvtd_l(fp0
, fp0
);
6871 gen_store_fpr64(ctx
, fp0
, fd
);
6872 tcg_temp_free_i64(fp0
);
6877 check_cp1_64bitmode(ctx
);
6879 TCGv_i64 fp0
= tcg_temp_new_i64();
6881 gen_load_fpr64(ctx
, fp0
, fs
);
6882 gen_helper_float_cvtps_pw(fp0
, fp0
);
6883 gen_store_fpr64(ctx
, fp0
, fd
);
6884 tcg_temp_free_i64(fp0
);
6889 check_cp1_64bitmode(ctx
);
6891 TCGv_i64 fp0
= tcg_temp_new_i64();
6892 TCGv_i64 fp1
= tcg_temp_new_i64();
6894 gen_load_fpr64(ctx
, fp0
, fs
);
6895 gen_load_fpr64(ctx
, fp1
, ft
);
6896 gen_helper_float_add_ps(fp0
, fp0
, fp1
);
6897 tcg_temp_free_i64(fp1
);
6898 gen_store_fpr64(ctx
, fp0
, fd
);
6899 tcg_temp_free_i64(fp0
);
6904 check_cp1_64bitmode(ctx
);
6906 TCGv_i64 fp0
= tcg_temp_new_i64();
6907 TCGv_i64 fp1
= tcg_temp_new_i64();
6909 gen_load_fpr64(ctx
, fp0
, fs
);
6910 gen_load_fpr64(ctx
, fp1
, ft
);
6911 gen_helper_float_sub_ps(fp0
, fp0
, fp1
);
6912 tcg_temp_free_i64(fp1
);
6913 gen_store_fpr64(ctx
, fp0
, fd
);
6914 tcg_temp_free_i64(fp0
);
6919 check_cp1_64bitmode(ctx
);
6921 TCGv_i64 fp0
= tcg_temp_new_i64();
6922 TCGv_i64 fp1
= tcg_temp_new_i64();
6924 gen_load_fpr64(ctx
, fp0
, fs
);
6925 gen_load_fpr64(ctx
, fp1
, ft
);
6926 gen_helper_float_mul_ps(fp0
, fp0
, fp1
);
6927 tcg_temp_free_i64(fp1
);
6928 gen_store_fpr64(ctx
, fp0
, fd
);
6929 tcg_temp_free_i64(fp0
);
6934 check_cp1_64bitmode(ctx
);
6936 TCGv_i64 fp0
= tcg_temp_new_i64();
6938 gen_load_fpr64(ctx
, fp0
, fs
);
6939 gen_helper_float_abs_ps(fp0
, fp0
);
6940 gen_store_fpr64(ctx
, fp0
, fd
);
6941 tcg_temp_free_i64(fp0
);
6946 check_cp1_64bitmode(ctx
);
6948 TCGv_i64 fp0
= tcg_temp_new_i64();
6950 gen_load_fpr64(ctx
, fp0
, fs
);
6951 gen_store_fpr64(ctx
, fp0
, fd
);
6952 tcg_temp_free_i64(fp0
);
6957 check_cp1_64bitmode(ctx
);
6959 TCGv_i64 fp0
= tcg_temp_new_i64();
6961 gen_load_fpr64(ctx
, fp0
, fs
);
6962 gen_helper_float_chs_ps(fp0
, fp0
);
6963 gen_store_fpr64(ctx
, fp0
, fd
);
6964 tcg_temp_free_i64(fp0
);
6969 check_cp1_64bitmode(ctx
);
6970 gen_movcf_ps(fs
, fd
, (ft
>> 2) & 0x7, ft
& 0x1);
6974 check_cp1_64bitmode(ctx
);
6976 int l1
= gen_new_label();
6980 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[ft
], 0, l1
);
6981 fp0
= tcg_temp_new_i64();
6982 gen_load_fpr64(ctx
, fp0
, fs
);
6983 gen_store_fpr64(ctx
, fp0
, fd
);
6984 tcg_temp_free_i64(fp0
);
6990 check_cp1_64bitmode(ctx
);
6992 int l1
= gen_new_label();
6996 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[ft
], 0, l1
);
6997 fp0
= tcg_temp_new_i64();
6998 gen_load_fpr64(ctx
, fp0
, fs
);
6999 gen_store_fpr64(ctx
, fp0
, fd
);
7000 tcg_temp_free_i64(fp0
);
7007 check_cp1_64bitmode(ctx
);
7009 TCGv_i64 fp0
= tcg_temp_new_i64();
7010 TCGv_i64 fp1
= tcg_temp_new_i64();
7012 gen_load_fpr64(ctx
, fp0
, ft
);
7013 gen_load_fpr64(ctx
, fp1
, fs
);
7014 gen_helper_float_addr_ps(fp0
, fp0
, fp1
);
7015 tcg_temp_free_i64(fp1
);
7016 gen_store_fpr64(ctx
, fp0
, fd
);
7017 tcg_temp_free_i64(fp0
);
7022 check_cp1_64bitmode(ctx
);
7024 TCGv_i64 fp0
= tcg_temp_new_i64();
7025 TCGv_i64 fp1
= tcg_temp_new_i64();
7027 gen_load_fpr64(ctx
, fp0
, ft
);
7028 gen_load_fpr64(ctx
, fp1
, fs
);
7029 gen_helper_float_mulr_ps(fp0
, fp0
, fp1
);
7030 tcg_temp_free_i64(fp1
);
7031 gen_store_fpr64(ctx
, fp0
, fd
);
7032 tcg_temp_free_i64(fp0
);
7037 check_cp1_64bitmode(ctx
);
7039 TCGv_i64 fp0
= tcg_temp_new_i64();
7040 TCGv_i64 fp1
= tcg_temp_new_i64();
7042 gen_load_fpr64(ctx
, fp0
, fs
);
7043 gen_load_fpr64(ctx
, fp1
, fd
);
7044 gen_helper_float_recip2_ps(fp0
, fp0
, fp1
);
7045 tcg_temp_free_i64(fp1
);
7046 gen_store_fpr64(ctx
, fp0
, fd
);
7047 tcg_temp_free_i64(fp0
);
7052 check_cp1_64bitmode(ctx
);
7054 TCGv_i64 fp0
= tcg_temp_new_i64();
7056 gen_load_fpr64(ctx
, fp0
, fs
);
7057 gen_helper_float_recip1_ps(fp0
, fp0
);
7058 gen_store_fpr64(ctx
, fp0
, fd
);
7059 tcg_temp_free_i64(fp0
);
7064 check_cp1_64bitmode(ctx
);
7066 TCGv_i64 fp0
= tcg_temp_new_i64();
7068 gen_load_fpr64(ctx
, fp0
, fs
);
7069 gen_helper_float_rsqrt1_ps(fp0
, fp0
);
7070 gen_store_fpr64(ctx
, fp0
, fd
);
7071 tcg_temp_free_i64(fp0
);
7076 check_cp1_64bitmode(ctx
);
7078 TCGv_i64 fp0
= tcg_temp_new_i64();
7079 TCGv_i64 fp1
= tcg_temp_new_i64();
7081 gen_load_fpr64(ctx
, fp0
, fs
);
7082 gen_load_fpr64(ctx
, fp1
, ft
);
7083 gen_helper_float_rsqrt2_ps(fp0
, fp0
, fp1
);
7084 tcg_temp_free_i64(fp1
);
7085 gen_store_fpr64(ctx
, fp0
, fd
);
7086 tcg_temp_free_i64(fp0
);
7091 check_cp1_64bitmode(ctx
);
7093 TCGv_i32 fp0
= tcg_temp_new_i32();
7095 gen_load_fpr32h(fp0
, fs
);
7096 gen_helper_float_cvts_pu(fp0
, fp0
);
7097 gen_store_fpr32(fp0
, fd
);
7098 tcg_temp_free_i32(fp0
);
7103 check_cp1_64bitmode(ctx
);
7105 TCGv_i64 fp0
= tcg_temp_new_i64();
7107 gen_load_fpr64(ctx
, fp0
, fs
);
7108 gen_helper_float_cvtpw_ps(fp0
, fp0
);
7109 gen_store_fpr64(ctx
, fp0
, fd
);
7110 tcg_temp_free_i64(fp0
);
7115 check_cp1_64bitmode(ctx
);
7117 TCGv_i32 fp0
= tcg_temp_new_i32();
7119 gen_load_fpr32(fp0
, fs
);
7120 gen_helper_float_cvts_pl(fp0
, fp0
);
7121 gen_store_fpr32(fp0
, fd
);
7122 tcg_temp_free_i32(fp0
);
7127 check_cp1_64bitmode(ctx
);
7129 TCGv_i32 fp0
= tcg_temp_new_i32();
7130 TCGv_i32 fp1
= tcg_temp_new_i32();
7132 gen_load_fpr32(fp0
, fs
);
7133 gen_load_fpr32(fp1
, ft
);
7134 gen_store_fpr32h(fp0
, fd
);
7135 gen_store_fpr32(fp1
, fd
);
7136 tcg_temp_free_i32(fp0
);
7137 tcg_temp_free_i32(fp1
);
7142 check_cp1_64bitmode(ctx
);
7144 TCGv_i32 fp0
= tcg_temp_new_i32();
7145 TCGv_i32 fp1
= tcg_temp_new_i32();
7147 gen_load_fpr32(fp0
, fs
);
7148 gen_load_fpr32h(fp1
, ft
);
7149 gen_store_fpr32(fp1
, fd
);
7150 gen_store_fpr32h(fp0
, fd
);
7151 tcg_temp_free_i32(fp0
);
7152 tcg_temp_free_i32(fp1
);
7157 check_cp1_64bitmode(ctx
);
7159 TCGv_i32 fp0
= tcg_temp_new_i32();
7160 TCGv_i32 fp1
= tcg_temp_new_i32();
7162 gen_load_fpr32h(fp0
, fs
);
7163 gen_load_fpr32(fp1
, ft
);
7164 gen_store_fpr32(fp1
, fd
);
7165 gen_store_fpr32h(fp0
, fd
);
7166 tcg_temp_free_i32(fp0
);
7167 tcg_temp_free_i32(fp1
);
7172 check_cp1_64bitmode(ctx
);
7174 TCGv_i32 fp0
= tcg_temp_new_i32();
7175 TCGv_i32 fp1
= tcg_temp_new_i32();
7177 gen_load_fpr32h(fp0
, fs
);
7178 gen_load_fpr32h(fp1
, ft
);
7179 gen_store_fpr32(fp1
, fd
);
7180 gen_store_fpr32h(fp0
, fd
);
7181 tcg_temp_free_i32(fp0
);
7182 tcg_temp_free_i32(fp1
);
7202 check_cp1_64bitmode(ctx
);
7204 TCGv_i64 fp0
= tcg_temp_new_i64();
7205 TCGv_i64 fp1
= tcg_temp_new_i64();
7207 gen_load_fpr64(ctx
, fp0
, fs
);
7208 gen_load_fpr64(ctx
, fp1
, ft
);
7209 if (ctx
->opcode
& (1 << 6)) {
7210 gen_cmpabs_ps(func
-48, fp0
, fp1
, cc
);
7211 opn
= condnames_abs
[func
-48];
7213 gen_cmp_ps(func
-48, fp0
, fp1
, cc
);
7214 opn
= condnames
[func
-48];
7216 tcg_temp_free_i64(fp0
);
7217 tcg_temp_free_i64(fp1
);
7222 generate_exception (ctx
, EXCP_RI
);
7227 MIPS_DEBUG("%s %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fs
], fregnames
[ft
]);
7230 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fs
], fregnames
[ft
]);
7233 MIPS_DEBUG("%s %s,%s", opn
, fregnames
[fd
], fregnames
[fs
]);
7238 /* Coprocessor 3 (FPU) */
7239 static void gen_flt3_ldst (DisasContext
*ctx
, uint32_t opc
,
7240 int fd
, int fs
, int base
, int index
)
7242 const char *opn
= "extended float load/store";
7244 TCGv t0
= tcg_temp_new();
7247 gen_load_gpr(t0
, index
);
7248 } else if (index
== 0) {
7249 gen_load_gpr(t0
, base
);
7251 gen_load_gpr(t0
, index
);
7252 gen_op_addr_add(ctx
, t0
, cpu_gpr
[base
], t0
);
7254 /* Don't do NOP if destination is zero: we must perform the actual
7256 save_cpu_state(ctx
, 0);
7261 TCGv_i32 fp0
= tcg_temp_new_i32();
7263 tcg_gen_qemu_ld32s(t0
, t0
, ctx
->mem_idx
);
7264 tcg_gen_trunc_tl_i32(fp0
, t0
);
7265 gen_store_fpr32(fp0
, fd
);
7266 tcg_temp_free_i32(fp0
);
7272 check_cp1_registers(ctx
, fd
);
7274 TCGv_i64 fp0
= tcg_temp_new_i64();
7276 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7277 gen_store_fpr64(ctx
, fp0
, fd
);
7278 tcg_temp_free_i64(fp0
);
7283 check_cp1_64bitmode(ctx
);
7284 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7286 TCGv_i64 fp0
= tcg_temp_new_i64();
7288 tcg_gen_qemu_ld64(fp0
, t0
, ctx
->mem_idx
);
7289 gen_store_fpr64(ctx
, fp0
, fd
);
7290 tcg_temp_free_i64(fp0
);
7297 TCGv_i32 fp0
= tcg_temp_new_i32();
7298 TCGv t1
= tcg_temp_new();
7300 gen_load_fpr32(fp0
, fs
);
7301 tcg_gen_extu_i32_tl(t1
, fp0
);
7302 tcg_gen_qemu_st32(t1
, t0
, ctx
->mem_idx
);
7303 tcg_temp_free_i32(fp0
);
7311 check_cp1_registers(ctx
, fs
);
7313 TCGv_i64 fp0
= tcg_temp_new_i64();
7315 gen_load_fpr64(ctx
, fp0
, fs
);
7316 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7317 tcg_temp_free_i64(fp0
);
7323 check_cp1_64bitmode(ctx
);
7324 tcg_gen_andi_tl(t0
, t0
, ~0x7);
7326 TCGv_i64 fp0
= tcg_temp_new_i64();
7328 gen_load_fpr64(ctx
, fp0
, fs
);
7329 tcg_gen_qemu_st64(fp0
, t0
, ctx
->mem_idx
);
7330 tcg_temp_free_i64(fp0
);
7337 MIPS_DEBUG("%s %s, %s(%s)", opn
, fregnames
[store
? fs
: fd
],
7338 regnames
[index
], regnames
[base
]);
7341 static void gen_flt3_arith (DisasContext
*ctx
, uint32_t opc
,
7342 int fd
, int fr
, int fs
, int ft
)
7344 const char *opn
= "flt3_arith";
7348 check_cp1_64bitmode(ctx
);
7350 TCGv t0
= tcg_temp_local_new();
7351 TCGv_i32 fp
= tcg_temp_new_i32();
7352 TCGv_i32 fph
= tcg_temp_new_i32();
7353 int l1
= gen_new_label();
7354 int l2
= gen_new_label();
7356 gen_load_gpr(t0
, fr
);
7357 tcg_gen_andi_tl(t0
, t0
, 0x7);
7359 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 0, l1
);
7360 gen_load_fpr32(fp
, fs
);
7361 gen_load_fpr32h(fph
, fs
);
7362 gen_store_fpr32(fp
, fd
);
7363 gen_store_fpr32h(fph
, fd
);
7366 tcg_gen_brcondi_tl(TCG_COND_NE
, t0
, 4, l2
);
7368 #ifdef TARGET_WORDS_BIGENDIAN
7369 gen_load_fpr32(fp
, fs
);
7370 gen_load_fpr32h(fph
, ft
);
7371 gen_store_fpr32h(fp
, fd
);
7372 gen_store_fpr32(fph
, fd
);
7374 gen_load_fpr32h(fph
, fs
);
7375 gen_load_fpr32(fp
, ft
);
7376 gen_store_fpr32(fph
, fd
);
7377 gen_store_fpr32h(fp
, fd
);
7380 tcg_temp_free_i32(fp
);
7381 tcg_temp_free_i32(fph
);
7388 TCGv_i32 fp0
= tcg_temp_new_i32();
7389 TCGv_i32 fp1
= tcg_temp_new_i32();
7390 TCGv_i32 fp2
= tcg_temp_new_i32();
7392 gen_load_fpr32(fp0
, fs
);
7393 gen_load_fpr32(fp1
, ft
);
7394 gen_load_fpr32(fp2
, fr
);
7395 gen_helper_float_muladd_s(fp2
, fp0
, fp1
, fp2
);
7396 tcg_temp_free_i32(fp0
);
7397 tcg_temp_free_i32(fp1
);
7398 gen_store_fpr32(fp2
, fd
);
7399 tcg_temp_free_i32(fp2
);
7405 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7407 TCGv_i64 fp0
= tcg_temp_new_i64();
7408 TCGv_i64 fp1
= tcg_temp_new_i64();
7409 TCGv_i64 fp2
= tcg_temp_new_i64();
7411 gen_load_fpr64(ctx
, fp0
, fs
);
7412 gen_load_fpr64(ctx
, fp1
, ft
);
7413 gen_load_fpr64(ctx
, fp2
, fr
);
7414 gen_helper_float_muladd_d(fp2
, fp0
, fp1
, fp2
);
7415 tcg_temp_free_i64(fp0
);
7416 tcg_temp_free_i64(fp1
);
7417 gen_store_fpr64(ctx
, fp2
, fd
);
7418 tcg_temp_free_i64(fp2
);
7423 check_cp1_64bitmode(ctx
);
7425 TCGv_i64 fp0
= tcg_temp_new_i64();
7426 TCGv_i64 fp1
= tcg_temp_new_i64();
7427 TCGv_i64 fp2
= tcg_temp_new_i64();
7429 gen_load_fpr64(ctx
, fp0
, fs
);
7430 gen_load_fpr64(ctx
, fp1
, ft
);
7431 gen_load_fpr64(ctx
, fp2
, fr
);
7432 gen_helper_float_muladd_ps(fp2
, fp0
, fp1
, fp2
);
7433 tcg_temp_free_i64(fp0
);
7434 tcg_temp_free_i64(fp1
);
7435 gen_store_fpr64(ctx
, fp2
, fd
);
7436 tcg_temp_free_i64(fp2
);
7443 TCGv_i32 fp0
= tcg_temp_new_i32();
7444 TCGv_i32 fp1
= tcg_temp_new_i32();
7445 TCGv_i32 fp2
= tcg_temp_new_i32();
7447 gen_load_fpr32(fp0
, fs
);
7448 gen_load_fpr32(fp1
, ft
);
7449 gen_load_fpr32(fp2
, fr
);
7450 gen_helper_float_mulsub_s(fp2
, fp0
, fp1
, fp2
);
7451 tcg_temp_free_i32(fp0
);
7452 tcg_temp_free_i32(fp1
);
7453 gen_store_fpr32(fp2
, fd
);
7454 tcg_temp_free_i32(fp2
);
7460 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7462 TCGv_i64 fp0
= tcg_temp_new_i64();
7463 TCGv_i64 fp1
= tcg_temp_new_i64();
7464 TCGv_i64 fp2
= tcg_temp_new_i64();
7466 gen_load_fpr64(ctx
, fp0
, fs
);
7467 gen_load_fpr64(ctx
, fp1
, ft
);
7468 gen_load_fpr64(ctx
, fp2
, fr
);
7469 gen_helper_float_mulsub_d(fp2
, fp0
, fp1
, fp2
);
7470 tcg_temp_free_i64(fp0
);
7471 tcg_temp_free_i64(fp1
);
7472 gen_store_fpr64(ctx
, fp2
, fd
);
7473 tcg_temp_free_i64(fp2
);
7478 check_cp1_64bitmode(ctx
);
7480 TCGv_i64 fp0
= tcg_temp_new_i64();
7481 TCGv_i64 fp1
= tcg_temp_new_i64();
7482 TCGv_i64 fp2
= tcg_temp_new_i64();
7484 gen_load_fpr64(ctx
, fp0
, fs
);
7485 gen_load_fpr64(ctx
, fp1
, ft
);
7486 gen_load_fpr64(ctx
, fp2
, fr
);
7487 gen_helper_float_mulsub_ps(fp2
, fp0
, fp1
, fp2
);
7488 tcg_temp_free_i64(fp0
);
7489 tcg_temp_free_i64(fp1
);
7490 gen_store_fpr64(ctx
, fp2
, fd
);
7491 tcg_temp_free_i64(fp2
);
7498 TCGv_i32 fp0
= tcg_temp_new_i32();
7499 TCGv_i32 fp1
= tcg_temp_new_i32();
7500 TCGv_i32 fp2
= tcg_temp_new_i32();
7502 gen_load_fpr32(fp0
, fs
);
7503 gen_load_fpr32(fp1
, ft
);
7504 gen_load_fpr32(fp2
, fr
);
7505 gen_helper_float_nmuladd_s(fp2
, fp0
, fp1
, fp2
);
7506 tcg_temp_free_i32(fp0
);
7507 tcg_temp_free_i32(fp1
);
7508 gen_store_fpr32(fp2
, fd
);
7509 tcg_temp_free_i32(fp2
);
7515 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7517 TCGv_i64 fp0
= tcg_temp_new_i64();
7518 TCGv_i64 fp1
= tcg_temp_new_i64();
7519 TCGv_i64 fp2
= tcg_temp_new_i64();
7521 gen_load_fpr64(ctx
, fp0
, fs
);
7522 gen_load_fpr64(ctx
, fp1
, ft
);
7523 gen_load_fpr64(ctx
, fp2
, fr
);
7524 gen_helper_float_nmuladd_d(fp2
, fp0
, fp1
, fp2
);
7525 tcg_temp_free_i64(fp0
);
7526 tcg_temp_free_i64(fp1
);
7527 gen_store_fpr64(ctx
, fp2
, fd
);
7528 tcg_temp_free_i64(fp2
);
7533 check_cp1_64bitmode(ctx
);
7535 TCGv_i64 fp0
= tcg_temp_new_i64();
7536 TCGv_i64 fp1
= tcg_temp_new_i64();
7537 TCGv_i64 fp2
= tcg_temp_new_i64();
7539 gen_load_fpr64(ctx
, fp0
, fs
);
7540 gen_load_fpr64(ctx
, fp1
, ft
);
7541 gen_load_fpr64(ctx
, fp2
, fr
);
7542 gen_helper_float_nmuladd_ps(fp2
, fp0
, fp1
, fp2
);
7543 tcg_temp_free_i64(fp0
);
7544 tcg_temp_free_i64(fp1
);
7545 gen_store_fpr64(ctx
, fp2
, fd
);
7546 tcg_temp_free_i64(fp2
);
7553 TCGv_i32 fp0
= tcg_temp_new_i32();
7554 TCGv_i32 fp1
= tcg_temp_new_i32();
7555 TCGv_i32 fp2
= tcg_temp_new_i32();
7557 gen_load_fpr32(fp0
, fs
);
7558 gen_load_fpr32(fp1
, ft
);
7559 gen_load_fpr32(fp2
, fr
);
7560 gen_helper_float_nmulsub_s(fp2
, fp0
, fp1
, fp2
);
7561 tcg_temp_free_i32(fp0
);
7562 tcg_temp_free_i32(fp1
);
7563 gen_store_fpr32(fp2
, fd
);
7564 tcg_temp_free_i32(fp2
);
7570 check_cp1_registers(ctx
, fd
| fs
| ft
| fr
);
7572 TCGv_i64 fp0
= tcg_temp_new_i64();
7573 TCGv_i64 fp1
= tcg_temp_new_i64();
7574 TCGv_i64 fp2
= tcg_temp_new_i64();
7576 gen_load_fpr64(ctx
, fp0
, fs
);
7577 gen_load_fpr64(ctx
, fp1
, ft
);
7578 gen_load_fpr64(ctx
, fp2
, fr
);
7579 gen_helper_float_nmulsub_d(fp2
, fp0
, fp1
, fp2
);
7580 tcg_temp_free_i64(fp0
);
7581 tcg_temp_free_i64(fp1
);
7582 gen_store_fpr64(ctx
, fp2
, fd
);
7583 tcg_temp_free_i64(fp2
);
7588 check_cp1_64bitmode(ctx
);
7590 TCGv_i64 fp0
= tcg_temp_new_i64();
7591 TCGv_i64 fp1
= tcg_temp_new_i64();
7592 TCGv_i64 fp2
= tcg_temp_new_i64();
7594 gen_load_fpr64(ctx
, fp0
, fs
);
7595 gen_load_fpr64(ctx
, fp1
, ft
);
7596 gen_load_fpr64(ctx
, fp2
, fr
);
7597 gen_helper_float_nmulsub_ps(fp2
, fp0
, fp1
, fp2
);
7598 tcg_temp_free_i64(fp0
);
7599 tcg_temp_free_i64(fp1
);
7600 gen_store_fpr64(ctx
, fp2
, fd
);
7601 tcg_temp_free_i64(fp2
);
7607 generate_exception (ctx
, EXCP_RI
);
7610 MIPS_DEBUG("%s %s, %s, %s, %s", opn
, fregnames
[fd
], fregnames
[fr
],
7611 fregnames
[fs
], fregnames
[ft
]);
7614 /* ISA extensions (ASEs) */
7615 /* MIPS16 extension to MIPS32 */
7616 /* SmartMIPS extension to MIPS32 */
7618 #if defined(TARGET_MIPS64)
7620 /* MDMX extension to MIPS64 */
7624 static void decode_opc (CPUState
*env
, DisasContext
*ctx
)
7628 uint32_t op
, op1
, op2
;
7631 /* make sure instructions are on a word boundary */
7632 if (ctx
->pc
& 0x3) {
7633 env
->CP0_BadVAddr
= ctx
->pc
;
7634 generate_exception(ctx
, EXCP_AdEL
);
7638 /* Handle blikely not taken case */
7639 if ((ctx
->hflags
& MIPS_HFLAG_BMASK
) == MIPS_HFLAG_BL
) {
7640 int l1
= gen_new_label();
7642 MIPS_DEBUG("blikely condition (" TARGET_FMT_lx
")", ctx
->pc
+ 4);
7643 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
7644 tcg_gen_movi_i32(hflags
, ctx
->hflags
& ~MIPS_HFLAG_BMASK
);
7645 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
7649 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
)))
7650 tcg_gen_debug_insn_start(ctx
->pc
);
7652 op
= MASK_OP_MAJOR(ctx
->opcode
);
7653 rs
= (ctx
->opcode
>> 21) & 0x1f;
7654 rt
= (ctx
->opcode
>> 16) & 0x1f;
7655 rd
= (ctx
->opcode
>> 11) & 0x1f;
7656 sa
= (ctx
->opcode
>> 6) & 0x1f;
7657 imm
= (int16_t)ctx
->opcode
;
7660 op1
= MASK_SPECIAL(ctx
->opcode
);
7662 case OPC_SLL
: /* Shift with immediate */
7665 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7667 case OPC_MOVN
: /* Conditional move */
7669 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7670 gen_cond_move(env
, op1
, rd
, rs
, rt
);
7672 case OPC_ADD
... OPC_SUBU
:
7673 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7675 case OPC_SLLV
: /* Shifts */
7678 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
7680 case OPC_SLT
: /* Set on less than */
7682 gen_slt(env
, op1
, rd
, rs
, rt
);
7684 case OPC_AND
: /* Logic*/
7688 gen_logic(env
, op1
, rd
, rs
, rt
);
7690 case OPC_MULT
... OPC_DIVU
:
7692 check_insn(env
, ctx
, INSN_VR54XX
);
7693 op1
= MASK_MUL_VR54XX(ctx
->opcode
);
7694 gen_mul_vr54xx(ctx
, op1
, rd
, rs
, rt
);
7696 gen_muldiv(ctx
, op1
, rs
, rt
);
7698 case OPC_JR
... OPC_JALR
:
7699 gen_compute_branch(ctx
, op1
, rs
, rd
, sa
);
7701 case OPC_TGE
... OPC_TEQ
: /* Traps */
7703 gen_trap(ctx
, op1
, rs
, rt
, -1);
7705 case OPC_MFHI
: /* Move from HI/LO */
7707 gen_HILO(ctx
, op1
, rd
);
7710 case OPC_MTLO
: /* Move to HI/LO */
7711 gen_HILO(ctx
, op1
, rs
);
7713 case OPC_PMON
: /* Pmon entry point, also R4010 selsl */
7714 #ifdef MIPS_STRICT_STANDARD
7715 MIPS_INVAL("PMON / selsl");
7716 generate_exception(ctx
, EXCP_RI
);
7718 gen_helper_0i(pmon
, sa
);
7722 generate_exception(ctx
, EXCP_SYSCALL
);
7723 ctx
->bstate
= BS_STOP
;
7726 generate_exception(ctx
, EXCP_BREAK
);
7729 #ifdef MIPS_STRICT_STANDARD
7731 generate_exception(ctx
, EXCP_RI
);
7733 /* Implemented as RI exception for now. */
7734 MIPS_INVAL("spim (unofficial)");
7735 generate_exception(ctx
, EXCP_RI
);
7743 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
7744 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
7745 check_cp1_enabled(ctx
);
7746 gen_movci(ctx
, rd
, rs
, (ctx
->opcode
>> 18) & 0x7,
7747 (ctx
->opcode
>> 16) & 1);
7749 generate_exception_err(ctx
, EXCP_CpU
, 1);
7753 #if defined(TARGET_MIPS64)
7754 /* MIPS64 specific opcodes */
7761 check_insn(env
, ctx
, ISA_MIPS3
);
7763 gen_shift_imm(env
, ctx
, op1
, rd
, rt
, sa
);
7765 case OPC_DADD
... OPC_DSUBU
:
7766 check_insn(env
, ctx
, ISA_MIPS3
);
7768 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7773 check_insn(env
, ctx
, ISA_MIPS3
);
7775 gen_shift(env
, ctx
, op1
, rd
, rs
, rt
);
7777 case OPC_DMULT
... OPC_DDIVU
:
7778 check_insn(env
, ctx
, ISA_MIPS3
);
7780 gen_muldiv(ctx
, op1
, rs
, rt
);
7783 default: /* Invalid */
7784 MIPS_INVAL("special");
7785 generate_exception(ctx
, EXCP_RI
);
7790 op1
= MASK_SPECIAL2(ctx
->opcode
);
7792 case OPC_MADD
... OPC_MADDU
: /* Multiply and add/sub */
7793 case OPC_MSUB
... OPC_MSUBU
:
7794 check_insn(env
, ctx
, ISA_MIPS32
);
7795 gen_muldiv(ctx
, op1
, rs
, rt
);
7798 gen_arith(env
, ctx
, op1
, rd
, rs
, rt
);
7802 check_insn(env
, ctx
, ISA_MIPS32
);
7803 gen_cl(ctx
, op1
, rd
, rs
);
7806 /* XXX: not clear which exception should be raised
7807 * when in debug mode...
7809 check_insn(env
, ctx
, ISA_MIPS32
);
7810 if (!(ctx
->hflags
& MIPS_HFLAG_DM
)) {
7811 generate_exception(ctx
, EXCP_DBp
);
7813 generate_exception(ctx
, EXCP_DBp
);
7817 #if defined(TARGET_MIPS64)
7820 check_insn(env
, ctx
, ISA_MIPS64
);
7822 gen_cl(ctx
, op1
, rd
, rs
);
7825 default: /* Invalid */
7826 MIPS_INVAL("special2");
7827 generate_exception(ctx
, EXCP_RI
);
7832 op1
= MASK_SPECIAL3(ctx
->opcode
);
7836 check_insn(env
, ctx
, ISA_MIPS32R2
);
7837 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7840 check_insn(env
, ctx
, ISA_MIPS32R2
);
7841 op2
= MASK_BSHFL(ctx
->opcode
);
7842 gen_bshfl(ctx
, op2
, rt
, rd
);
7845 check_insn(env
, ctx
, ISA_MIPS32R2
);
7847 TCGv t0
= tcg_temp_new();
7851 save_cpu_state(ctx
, 1);
7852 gen_helper_rdhwr_cpunum(t0
);
7853 gen_store_gpr(t0
, rt
);
7856 save_cpu_state(ctx
, 1);
7857 gen_helper_rdhwr_synci_step(t0
);
7858 gen_store_gpr(t0
, rt
);
7861 save_cpu_state(ctx
, 1);
7862 gen_helper_rdhwr_cc(t0
);
7863 gen_store_gpr(t0
, rt
);
7866 save_cpu_state(ctx
, 1);
7867 gen_helper_rdhwr_ccres(t0
);
7868 gen_store_gpr(t0
, rt
);
7871 #if defined(CONFIG_USER_ONLY)
7872 tcg_gen_ld_tl(t0
, cpu_env
, offsetof(CPUState
, tls_value
));
7873 gen_store_gpr(t0
, rt
);
7876 /* XXX: Some CPUs implement this in hardware.
7877 Not supported yet. */
7879 default: /* Invalid */
7880 MIPS_INVAL("rdhwr");
7881 generate_exception(ctx
, EXCP_RI
);
7888 check_insn(env
, ctx
, ASE_MT
);
7890 TCGv t0
= tcg_temp_new();
7891 TCGv t1
= tcg_temp_new();
7893 gen_load_gpr(t0
, rt
);
7894 gen_load_gpr(t1
, rs
);
7895 gen_helper_fork(t0
, t1
);
7901 check_insn(env
, ctx
, ASE_MT
);
7903 TCGv t0
= tcg_temp_new();
7905 save_cpu_state(ctx
, 1);
7906 gen_load_gpr(t0
, rs
);
7907 gen_helper_yield(t0
, t0
);
7908 gen_store_gpr(t0
, rd
);
7912 #if defined(TARGET_MIPS64)
7913 case OPC_DEXTM
... OPC_DEXT
:
7914 case OPC_DINSM
... OPC_DINS
:
7915 check_insn(env
, ctx
, ISA_MIPS64R2
);
7917 gen_bitops(ctx
, op1
, rt
, rs
, sa
, rd
);
7920 check_insn(env
, ctx
, ISA_MIPS64R2
);
7922 op2
= MASK_DBSHFL(ctx
->opcode
);
7923 gen_bshfl(ctx
, op2
, rt
, rd
);
7926 default: /* Invalid */
7927 MIPS_INVAL("special3");
7928 generate_exception(ctx
, EXCP_RI
);
7933 op1
= MASK_REGIMM(ctx
->opcode
);
7935 case OPC_BLTZ
... OPC_BGEZL
: /* REGIMM branches */
7936 case OPC_BLTZAL
... OPC_BGEZALL
:
7937 gen_compute_branch(ctx
, op1
, rs
, -1, imm
<< 2);
7939 case OPC_TGEI
... OPC_TEQI
: /* REGIMM traps */
7941 gen_trap(ctx
, op1
, rs
, -1, imm
);
7944 check_insn(env
, ctx
, ISA_MIPS32R2
);
7947 default: /* Invalid */
7948 MIPS_INVAL("regimm");
7949 generate_exception(ctx
, EXCP_RI
);
7954 check_cp0_enabled(ctx
);
7955 op1
= MASK_CP0(ctx
->opcode
);
7961 #if defined(TARGET_MIPS64)
7965 #ifndef CONFIG_USER_ONLY
7966 gen_cp0(env
, ctx
, op1
, rt
, rd
);
7967 #endif /* !CONFIG_USER_ONLY */
7969 case OPC_C0_FIRST
... OPC_C0_LAST
:
7970 #ifndef CONFIG_USER_ONLY
7971 gen_cp0(env
, ctx
, MASK_C0(ctx
->opcode
), rt
, rd
);
7972 #endif /* !CONFIG_USER_ONLY */
7975 #ifndef CONFIG_USER_ONLY
7977 TCGv t0
= tcg_temp_new();
7979 op2
= MASK_MFMC0(ctx
->opcode
);
7982 check_insn(env
, ctx
, ASE_MT
);
7983 gen_helper_dmt(t0
, t0
);
7984 gen_store_gpr(t0
, rt
);
7987 check_insn(env
, ctx
, ASE_MT
);
7988 gen_helper_emt(t0
, t0
);
7989 gen_store_gpr(t0
, rt
);
7992 check_insn(env
, ctx
, ASE_MT
);
7993 gen_helper_dvpe(t0
, t0
);
7994 gen_store_gpr(t0
, rt
);
7997 check_insn(env
, ctx
, ASE_MT
);
7998 gen_helper_evpe(t0
, t0
);
7999 gen_store_gpr(t0
, rt
);
8002 check_insn(env
, ctx
, ISA_MIPS32R2
);
8003 save_cpu_state(ctx
, 1);
8005 gen_store_gpr(t0
, rt
);
8006 /* Stop translation as we may have switched the execution mode */
8007 ctx
->bstate
= BS_STOP
;
8010 check_insn(env
, ctx
, ISA_MIPS32R2
);
8011 save_cpu_state(ctx
, 1);
8013 gen_store_gpr(t0
, rt
);
8014 /* Stop translation as we may have switched the execution mode */
8015 ctx
->bstate
= BS_STOP
;
8017 default: /* Invalid */
8018 MIPS_INVAL("mfmc0");
8019 generate_exception(ctx
, EXCP_RI
);
8024 #endif /* !CONFIG_USER_ONLY */
8027 check_insn(env
, ctx
, ISA_MIPS32R2
);
8028 gen_load_srsgpr(rt
, rd
);
8031 check_insn(env
, ctx
, ISA_MIPS32R2
);
8032 gen_store_srsgpr(rt
, rd
);
8036 generate_exception(ctx
, EXCP_RI
);
8040 case OPC_ADDI
: /* Arithmetic with immediate opcode */
8042 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8044 case OPC_SLTI
: /* Set on less than with immediate opcode */
8046 gen_slt_imm(env
, op
, rt
, rs
, imm
);
8048 case OPC_ANDI
: /* Arithmetic with immediate opcode */
8052 gen_logic_imm(env
, op
, rt
, rs
, imm
);
8054 case OPC_J
... OPC_JAL
: /* Jump */
8055 offset
= (int32_t)(ctx
->opcode
& 0x3FFFFFF) << 2;
8056 gen_compute_branch(ctx
, op
, rs
, rt
, offset
);
8058 case OPC_BEQ
... OPC_BGTZ
: /* Branch */
8059 case OPC_BEQL
... OPC_BGTZL
:
8060 gen_compute_branch(ctx
, op
, rs
, rt
, imm
<< 2);
8062 case OPC_LB
... OPC_LWR
: /* Load and stores */
8063 case OPC_SB
... OPC_SW
:
8066 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8069 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
8072 check_insn(env
, ctx
, ISA_MIPS3
| ISA_MIPS32
);
8076 check_insn(env
, ctx
, ISA_MIPS4
| ISA_MIPS32
);
8080 /* Floating point (COP1). */
8085 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8086 check_cp1_enabled(ctx
);
8087 gen_flt_ldst(ctx
, op
, rt
, rs
, imm
);
8089 generate_exception_err(ctx
, EXCP_CpU
, 1);
8094 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8095 check_cp1_enabled(ctx
);
8096 op1
= MASK_CP1(ctx
->opcode
);
8100 check_insn(env
, ctx
, ISA_MIPS32R2
);
8105 gen_cp1(ctx
, op1
, rt
, rd
);
8107 #if defined(TARGET_MIPS64)
8110 check_insn(env
, ctx
, ISA_MIPS3
);
8111 gen_cp1(ctx
, op1
, rt
, rd
);
8117 check_insn(env
, ctx
, ASE_MIPS3D
);
8120 gen_compute_branch1(env
, ctx
, MASK_BC1(ctx
->opcode
),
8121 (rt
>> 2) & 0x7, imm
<< 2);
8128 gen_farith(ctx
, MASK_CP1_FUNC(ctx
->opcode
), rt
, rd
, sa
,
8133 generate_exception (ctx
, EXCP_RI
);
8137 generate_exception_err(ctx
, EXCP_CpU
, 1);
8147 /* COP2: Not implemented. */
8148 generate_exception_err(ctx
, EXCP_CpU
, 2);
8152 if (env
->CP0_Config1
& (1 << CP0C1_FP
)) {
8153 check_cp1_enabled(ctx
);
8154 op1
= MASK_CP3(ctx
->opcode
);
8162 gen_flt3_ldst(ctx
, op1
, sa
, rd
, rs
, rt
);
8180 gen_flt3_arith(ctx
, op1
, sa
, rs
, rd
, rt
);
8184 generate_exception (ctx
, EXCP_RI
);
8188 generate_exception_err(ctx
, EXCP_CpU
, 1);
8192 #if defined(TARGET_MIPS64)
8193 /* MIPS64 opcodes */
8195 case OPC_LDL
... OPC_LDR
:
8196 case OPC_SDL
... OPC_SDR
:
8200 check_insn(env
, ctx
, ISA_MIPS3
);
8202 gen_ldst(ctx
, op
, rt
, rs
, imm
);
8205 check_insn(env
, ctx
, ISA_MIPS3
);
8207 gen_st_cond(ctx
, op
, rt
, rs
, imm
);
8211 check_insn(env
, ctx
, ISA_MIPS3
);
8213 gen_arith_imm(env
, ctx
, op
, rt
, rs
, imm
);
8217 check_insn(env
, ctx
, ASE_MIPS16
);
8218 /* MIPS16: Not implemented. */
8220 check_insn(env
, ctx
, ASE_MDMX
);
8221 /* MDMX: Not implemented. */
8222 default: /* Invalid */
8223 MIPS_INVAL("major opcode");
8224 generate_exception(ctx
, EXCP_RI
);
8227 if (ctx
->hflags
& MIPS_HFLAG_BMASK
) {
8228 int hflags
= ctx
->hflags
& MIPS_HFLAG_BMASK
;
8229 /* Branches completion */
8230 ctx
->hflags
&= ~MIPS_HFLAG_BMASK
;
8231 ctx
->bstate
= BS_BRANCH
;
8232 save_cpu_state(ctx
, 0);
8233 /* FIXME: Need to clear can_do_io. */
8236 /* unconditional branch */
8237 MIPS_DEBUG("unconditional branch");
8238 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8241 /* blikely taken case */
8242 MIPS_DEBUG("blikely branch taken");
8243 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8246 /* Conditional branch */
8247 MIPS_DEBUG("conditional branch");
8249 int l1
= gen_new_label();
8251 tcg_gen_brcondi_tl(TCG_COND_NE
, bcond
, 0, l1
);
8252 gen_goto_tb(ctx
, 1, ctx
->pc
+ 4);
8254 gen_goto_tb(ctx
, 0, ctx
->btarget
);
8258 /* unconditional branch to register */
8259 MIPS_DEBUG("branch to register");
8260 tcg_gen_mov_tl(cpu_PC
, btarget
);
8261 if (ctx
->singlestep_enabled
) {
8262 save_cpu_state(ctx
, 0);
8263 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8268 MIPS_DEBUG("unknown branch");
8275 gen_intermediate_code_internal (CPUState
*env
, TranslationBlock
*tb
,
8279 target_ulong pc_start
;
8280 uint16_t *gen_opc_end
;
8287 qemu_log("search pc %d\n", search_pc
);
8290 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
8293 ctx
.singlestep_enabled
= env
->singlestep_enabled
;
8295 ctx
.bstate
= BS_NONE
;
8296 /* Restore delay slot state from the tb context. */
8297 ctx
.hflags
= (uint32_t)tb
->flags
; /* FIXME: maybe use 64 bits here? */
8298 restore_cpu_state(env
, &ctx
);
8299 #ifdef CONFIG_USER_ONLY
8300 ctx
.mem_idx
= MIPS_HFLAG_UM
;
8302 ctx
.mem_idx
= ctx
.hflags
& MIPS_HFLAG_KSU
;
8305 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8307 max_insns
= CF_COUNT_MASK
;
8309 qemu_log_mask(CPU_LOG_TB_CPU
, "------------------------------------------------\n");
8310 /* FIXME: This may print out stale hflags from env... */
8311 log_cpu_state_mask(CPU_LOG_TB_CPU
, env
, 0);
8313 LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb
, ctx
.mem_idx
, ctx
.hflags
);
8315 while (ctx
.bstate
== BS_NONE
) {
8316 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
8317 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8318 if (bp
->pc
== ctx
.pc
) {
8319 save_cpu_state(&ctx
, 1);
8320 ctx
.bstate
= BS_BRANCH
;
8321 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8322 /* Include the breakpoint location or the tb won't
8323 * be flushed when it must be. */
8325 goto done_generating
;
8331 j
= gen_opc_ptr
- gen_opc_buf
;
8335 gen_opc_instr_start
[lj
++] = 0;
8337 gen_opc_pc
[lj
] = ctx
.pc
;
8338 gen_opc_hflags
[lj
] = ctx
.hflags
& MIPS_HFLAG_BMASK
;
8339 gen_opc_instr_start
[lj
] = 1;
8340 gen_opc_icount
[lj
] = num_insns
;
8342 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8344 ctx
.opcode
= ldl_code(ctx
.pc
);
8345 decode_opc(env
, &ctx
);
8349 /* Execute a branch and its delay slot as a single instruction.
8350 This is what GDB expects and is consistent with what the
8351 hardware does (e.g. if a delay slot instruction faults, the
8352 reported PC is the PC of the branch). */
8353 if (env
->singlestep_enabled
&& (ctx
.hflags
& MIPS_HFLAG_BMASK
) == 0)
8356 if ((ctx
.pc
& (TARGET_PAGE_SIZE
- 1)) == 0)
8359 if (gen_opc_ptr
>= gen_opc_end
)
8362 if (num_insns
>= max_insns
)
8368 if (tb
->cflags
& CF_LAST_IO
)
8370 if (env
->singlestep_enabled
&& ctx
.bstate
!= BS_BRANCH
) {
8371 save_cpu_state(&ctx
, ctx
.bstate
== BS_NONE
);
8372 gen_helper_0i(raise_exception
, EXCP_DEBUG
);
8374 switch (ctx
.bstate
) {
8376 gen_helper_interrupt_restart();
8377 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8380 save_cpu_state(&ctx
, 0);
8381 gen_goto_tb(&ctx
, 0, ctx
.pc
);
8384 gen_helper_interrupt_restart();
8393 gen_icount_end(tb
, num_insns
);
8394 *gen_opc_ptr
= INDEX_op_end
;
8396 j
= gen_opc_ptr
- gen_opc_buf
;
8399 gen_opc_instr_start
[lj
++] = 0;
8401 tb
->size
= ctx
.pc
- pc_start
;
8402 tb
->icount
= num_insns
;
8406 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8407 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8408 log_target_disas(pc_start
, ctx
.pc
- pc_start
, 0);
8411 qemu_log_mask(CPU_LOG_TB_CPU
, "---------------- %d %08x\n", ctx
.bstate
, ctx
.hflags
);
8415 void gen_intermediate_code (CPUState
*env
, struct TranslationBlock
*tb
)
8417 gen_intermediate_code_internal(env
, tb
, 0);
8420 void gen_intermediate_code_pc (CPUState
*env
, struct TranslationBlock
*tb
)
8422 gen_intermediate_code_internal(env
, tb
, 1);
8425 static void fpu_dump_state(CPUState
*env
, FILE *f
,
8426 int (*fpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8430 int is_fpu64
= !!(env
->hflags
& MIPS_HFLAG_F64
);
8432 #define printfpr(fp) \
8435 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu: %13g\n", \
8436 (fp)->w[FP_ENDIAN_IDX], (fp)->d, (fp)->fd, \
8437 (fp)->fs[FP_ENDIAN_IDX], (fp)->fs[!FP_ENDIAN_IDX]); \
8440 tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \
8441 tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \
8442 fpu_fprintf(f, "w:%08x d:%016lx fd:%13g fs:%13g psu:%13g\n", \
8443 tmp.w[FP_ENDIAN_IDX], tmp.d, tmp.fd, \
8444 tmp.fs[FP_ENDIAN_IDX], tmp.fs[!FP_ENDIAN_IDX]); \
8449 fpu_fprintf(f
, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n",
8450 env
->active_fpu
.fcr0
, env
->active_fpu
.fcr31
, is_fpu64
, env
->active_fpu
.fp_status
,
8451 get_float_exception_flags(&env
->active_fpu
.fp_status
));
8452 for (i
= 0; i
< 32; (is_fpu64
) ? i
++ : (i
+= 2)) {
8453 fpu_fprintf(f
, "%3s: ", fregnames
[i
]);
8454 printfpr(&env
->active_fpu
.fpr
[i
]);
8460 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8461 /* Debug help: The architecture requires 32bit code to maintain proper
8462 sign-extended values on 64bit machines. */
8464 #define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
8467 cpu_mips_check_sign_extensions (CPUState
*env
, FILE *f
,
8468 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8473 if (!SIGN_EXT_P(env
->active_tc
.PC
))
8474 cpu_fprintf(f
, "BROKEN: pc=0x" TARGET_FMT_lx
"\n", env
->active_tc
.PC
);
8475 if (!SIGN_EXT_P(env
->active_tc
.HI
[0]))
8476 cpu_fprintf(f
, "BROKEN: HI=0x" TARGET_FMT_lx
"\n", env
->active_tc
.HI
[0]);
8477 if (!SIGN_EXT_P(env
->active_tc
.LO
[0]))
8478 cpu_fprintf(f
, "BROKEN: LO=0x" TARGET_FMT_lx
"\n", env
->active_tc
.LO
[0]);
8479 if (!SIGN_EXT_P(env
->btarget
))
8480 cpu_fprintf(f
, "BROKEN: btarget=0x" TARGET_FMT_lx
"\n", env
->btarget
);
8482 for (i
= 0; i
< 32; i
++) {
8483 if (!SIGN_EXT_P(env
->active_tc
.gpr
[i
]))
8484 cpu_fprintf(f
, "BROKEN: %s=0x" TARGET_FMT_lx
"\n", regnames
[i
], env
->active_tc
.gpr
[i
]);
8487 if (!SIGN_EXT_P(env
->CP0_EPC
))
8488 cpu_fprintf(f
, "BROKEN: EPC=0x" TARGET_FMT_lx
"\n", env
->CP0_EPC
);
8489 if (!SIGN_EXT_P(env
->lladdr
))
8490 cpu_fprintf(f
, "BROKEN: LLAddr=0x" TARGET_FMT_lx
"\n", env
->lladdr
);
8494 void cpu_dump_state (CPUState
*env
, FILE *f
,
8495 int (*cpu_fprintf
)(FILE *f
, const char *fmt
, ...),
8500 cpu_fprintf(f
, "pc=0x" TARGET_FMT_lx
" HI=0x" TARGET_FMT_lx
" LO=0x" TARGET_FMT_lx
" ds %04x " TARGET_FMT_lx
" %d\n",
8501 env
->active_tc
.PC
, env
->active_tc
.HI
[0], env
->active_tc
.LO
[0],
8502 env
->hflags
, env
->btarget
, env
->bcond
);
8503 for (i
= 0; i
< 32; i
++) {
8505 cpu_fprintf(f
, "GPR%02d:", i
);
8506 cpu_fprintf(f
, " %s " TARGET_FMT_lx
, regnames
[i
], env
->active_tc
.gpr
[i
]);
8508 cpu_fprintf(f
, "\n");
8511 cpu_fprintf(f
, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" TARGET_FMT_lx
"\n",
8512 env
->CP0_Status
, env
->CP0_Cause
, env
->CP0_EPC
);
8513 cpu_fprintf(f
, " Config0 0x%08x Config1 0x%08x LLAddr 0x" TARGET_FMT_lx
"\n",
8514 env
->CP0_Config0
, env
->CP0_Config1
, env
->lladdr
);
8515 if (env
->hflags
& MIPS_HFLAG_FPU
)
8516 fpu_dump_state(env
, f
, cpu_fprintf
, flags
);
8517 #if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
8518 cpu_mips_check_sign_extensions(env
, f
, cpu_fprintf
, flags
);
8522 static void mips_tcg_init(void)
8527 /* Initialize various static tables. */
8531 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
8532 TCGV_UNUSED(cpu_gpr
[0]);
8533 for (i
= 1; i
< 32; i
++)
8534 cpu_gpr
[i
] = tcg_global_mem_new(TCG_AREG0
,
8535 offsetof(CPUState
, active_tc
.gpr
[i
]),
8537 cpu_PC
= tcg_global_mem_new(TCG_AREG0
,
8538 offsetof(CPUState
, active_tc
.PC
), "PC");
8539 for (i
= 0; i
< MIPS_DSP_ACC
; i
++) {
8540 cpu_HI
[i
] = tcg_global_mem_new(TCG_AREG0
,
8541 offsetof(CPUState
, active_tc
.HI
[i
]),
8543 cpu_LO
[i
] = tcg_global_mem_new(TCG_AREG0
,
8544 offsetof(CPUState
, active_tc
.LO
[i
]),
8546 cpu_ACX
[i
] = tcg_global_mem_new(TCG_AREG0
,
8547 offsetof(CPUState
, active_tc
.ACX
[i
]),
8550 cpu_dspctrl
= tcg_global_mem_new(TCG_AREG0
,
8551 offsetof(CPUState
, active_tc
.DSPControl
),
8553 bcond
= tcg_global_mem_new(TCG_AREG0
,
8554 offsetof(CPUState
, bcond
), "bcond");
8555 btarget
= tcg_global_mem_new(TCG_AREG0
,
8556 offsetof(CPUState
, btarget
), "btarget");
8557 hflags
= tcg_global_mem_new_i32(TCG_AREG0
,
8558 offsetof(CPUState
, hflags
), "hflags");
8560 fpu_fcr0
= tcg_global_mem_new_i32(TCG_AREG0
,
8561 offsetof(CPUState
, active_fpu
.fcr0
),
8563 fpu_fcr31
= tcg_global_mem_new_i32(TCG_AREG0
,
8564 offsetof(CPUState
, active_fpu
.fcr31
),
8567 /* register helpers */
8568 #define GEN_HELPER 2
8574 #include "translate_init.c"
8576 CPUMIPSState
*cpu_mips_init (const char *cpu_model
)
8579 const mips_def_t
*def
;
8581 def
= cpu_mips_find_by_name(cpu_model
);
8584 env
= qemu_mallocz(sizeof(CPUMIPSState
));
8585 env
->cpu_model
= def
;
8586 env
->cpu_model_str
= cpu_model
;
8589 #ifndef CONFIG_USER_ONLY
8596 qemu_init_vcpu(env
);
8600 void cpu_reset (CPUMIPSState
*env
)
8602 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
8603 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
8604 log_cpu_state(env
, 0);
8607 memset(env
, 0, offsetof(CPUMIPSState
, breakpoints
));
8610 /* Reset registers to their default values */
8611 env
->CP0_PRid
= env
->cpu_model
->CP0_PRid
;
8612 env
->CP0_Config0
= env
->cpu_model
->CP0_Config0
;
8613 #ifdef TARGET_WORDS_BIGENDIAN
8614 env
->CP0_Config0
|= (1 << CP0C0_BE
);
8616 env
->CP0_Config1
= env
->cpu_model
->CP0_Config1
;
8617 env
->CP0_Config2
= env
->cpu_model
->CP0_Config2
;
8618 env
->CP0_Config3
= env
->cpu_model
->CP0_Config3
;
8619 env
->CP0_Config6
= env
->cpu_model
->CP0_Config6
;
8620 env
->CP0_Config7
= env
->cpu_model
->CP0_Config7
;
8621 env
->CP0_LLAddr_rw_bitmask
= env
->cpu_model
->CP0_LLAddr_rw_bitmask
8622 << env
->cpu_model
->CP0_LLAddr_shift
;
8623 env
->CP0_LLAddr_shift
= env
->cpu_model
->CP0_LLAddr_shift
;
8624 env
->SYNCI_Step
= env
->cpu_model
->SYNCI_Step
;
8625 env
->CCRes
= env
->cpu_model
->CCRes
;
8626 env
->CP0_Status_rw_bitmask
= env
->cpu_model
->CP0_Status_rw_bitmask
;
8627 env
->CP0_TCStatus_rw_bitmask
= env
->cpu_model
->CP0_TCStatus_rw_bitmask
;
8628 env
->CP0_SRSCtl
= env
->cpu_model
->CP0_SRSCtl
;
8629 env
->current_tc
= 0;
8630 env
->SEGBITS
= env
->cpu_model
->SEGBITS
;
8631 env
->SEGMask
= (target_ulong
)((1ULL << env
->cpu_model
->SEGBITS
) - 1);
8632 #if defined(TARGET_MIPS64)
8633 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
8634 env
->SEGMask
|= 3ULL << 62;
8637 env
->PABITS
= env
->cpu_model
->PABITS
;
8638 env
->PAMask
= (target_ulong
)((1ULL << env
->cpu_model
->PABITS
) - 1);
8639 env
->CP0_SRSConf0_rw_bitmask
= env
->cpu_model
->CP0_SRSConf0_rw_bitmask
;
8640 env
->CP0_SRSConf0
= env
->cpu_model
->CP0_SRSConf0
;
8641 env
->CP0_SRSConf1_rw_bitmask
= env
->cpu_model
->CP0_SRSConf1_rw_bitmask
;
8642 env
->CP0_SRSConf1
= env
->cpu_model
->CP0_SRSConf1
;
8643 env
->CP0_SRSConf2_rw_bitmask
= env
->cpu_model
->CP0_SRSConf2_rw_bitmask
;
8644 env
->CP0_SRSConf2
= env
->cpu_model
->CP0_SRSConf2
;
8645 env
->CP0_SRSConf3_rw_bitmask
= env
->cpu_model
->CP0_SRSConf3_rw_bitmask
;
8646 env
->CP0_SRSConf3
= env
->cpu_model
->CP0_SRSConf3
;
8647 env
->CP0_SRSConf4_rw_bitmask
= env
->cpu_model
->CP0_SRSConf4_rw_bitmask
;
8648 env
->CP0_SRSConf4
= env
->cpu_model
->CP0_SRSConf4
;
8649 env
->insn_flags
= env
->cpu_model
->insn_flags
;
8651 #if defined(CONFIG_USER_ONLY)
8652 env
->hflags
= MIPS_HFLAG_UM
;
8653 /* Enable access to the SYNCI_Step register. */
8654 env
->CP0_HWREna
|= (1 << 1);
8656 if (env
->hflags
& MIPS_HFLAG_BMASK
) {
8657 /* If the exception was raised from a delay slot,
8658 come back to the jump. */
8659 env
->CP0_ErrorEPC
= env
->active_tc
.PC
- 4;
8661 env
->CP0_ErrorEPC
= env
->active_tc
.PC
;
8663 env
->active_tc
.PC
= (int32_t)0xBFC00000;
8664 env
->CP0_Random
= env
->tlb
->nb_tlb
- 1;
8665 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
8667 /* SMP not implemented */
8668 env
->CP0_EBase
= 0x80000000;
8669 env
->CP0_Status
= (1 << CP0St_BEV
) | (1 << CP0St_ERL
);
8670 /* vectored interrupts not implemented, timer on int 7,
8671 no performance counters. */
8672 env
->CP0_IntCtl
= 0xe0000000;
8676 for (i
= 0; i
< 7; i
++) {
8677 env
->CP0_WatchLo
[i
] = 0;
8678 env
->CP0_WatchHi
[i
] = 0x80000000;
8680 env
->CP0_WatchLo
[7] = 0;
8681 env
->CP0_WatchHi
[7] = 0;
8683 /* Count register increments in debug mode, EJTAG version 1 */
8684 env
->CP0_Debug
= (1 << CP0DB_CNT
) | (0x1 << CP0DB_VER
);
8685 env
->hflags
= MIPS_HFLAG_CP0
;
8687 #if defined(TARGET_MIPS64)
8688 if (env
->cpu_model
->insn_flags
& ISA_MIPS3
) {
8689 env
->hflags
|= MIPS_HFLAG_64
;
8692 env
->exception_index
= EXCP_NONE
;
8695 void gen_pc_load(CPUState
*env
, TranslationBlock
*tb
,
8696 unsigned long searched_pc
, int pc_pos
, void *puc
)
8698 env
->active_tc
.PC
= gen_opc_pc
[pc_pos
];
8699 env
->hflags
&= ~MIPS_HFLAG_BMASK
;
8700 env
->hflags
|= gen_opc_hflags
[pc_pos
];