hw/ppc_oldworld.c

   1 /*
   2  * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "ppc.h"
  27 #include "ppc_mac.h"
  28 #include "mac_dbdma.h"
  29 #include "nvram.h"
  30 #include "pc.h"
  31 #include "sysemu.h"
  32 #include "net.h"
  33 #include "isa.h"
  34 #include "pci.h"
  35 #include "usb-ohci.h"
  36 #include "boards.h"
  37 #include "fw_cfg.h"
  38 #include "escc.h"
  39 #include "ide.h"
  40 #include "loader.h"
  41 #include "elf.h"
  42
  43 #define MAX_IDE_BUS 2
  44 #define VGA_BIOS_SIZE 65536
  45 #define CFG_ADDR 0xf0000510
  46
  47 /* temporary frame buffer OSI calls for the video.x driver. The right
  48    solution is to modify the driver to use VGA PCI I/Os */
  49 /* XXX: to be removed. This is no way related to emulation */
  50 static int vga_osi_call (CPUState *env)
  51 {
  52     static int vga_vbl_enabled;
  53     int linesize;
  54
  55 #if 0
  56     printf("osi_call R5=%016" PRIx64 "\n", ppc_dump_gpr(env, 5));
  57 #endif
  58
  59     /* same handler as PearPC, coming from the original MOL video
  60        driver. */
  61     switch(env->gpr[5]) {
  62     case 4:
  63         break;
  64     case 28: /* set_vmode */
  65         if (env->gpr[6] != 1 || env->gpr[7] != 0)
  66             env->gpr[3] = 1;
  67         else
  68             env->gpr[3] = 0;
  69         break;
  70     case 29: /* get_vmode_info */
  71         if (env->gpr[6] != 0) {
  72             if (env->gpr[6] != 1 || env->gpr[7] != 0) {
  73                 env->gpr[3] = 1;
  74                 break;
  75             }
  76         }
  77         env->gpr[3] = 0;
  78         env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
  79         env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
  80         env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
  81         env->gpr[7] = 85 << 16; /* refresh rate */
  82         env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
  83         linesize = ((graphic_depth + 7) >> 3) * graphic_width;
  84         linesize = (linesize + 3) & ~3;
  85         env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
  86         break;
  87     case 31: /* set_video power */
  88         env->gpr[3] = 0;
  89         break;
  90     case 39: /* video_ctrl */
  91         if (env->gpr[6] == 0 || env->gpr[6] == 1)
  92             vga_vbl_enabled = env->gpr[6];
  93         env->gpr[3] = 0;
  94         break;
  95     case 47:
  96         break;
  97     case 59: /* set_color */
  98         /* R6 = index, R7 = RGB */
  99         env->gpr[3] = 0;
 100         break;
 101     case 64: /* get color */
 102         /* R6 = index */
 103         env->gpr[3] = 0;
 104         break;
 105     case 116: /* set hwcursor */
 106         /* R6 = x, R7 = y, R8 = visible, R9 = data */
 107         break;
 108     default:
 109         fprintf(stderr, "unsupported OSI call R5=%016" PRIx64 "\n",
 110                 ppc_dump_gpr(env, 5));
 111         break;
 112     }
 113
 114     return 1; /* osi_call handled */
 115 }
 116
 117 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 118 {
 119     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 120     return 0;
 121 }
 122
 123 static void ppc_heathrow_init (ram_addr_t ram_size,
 124                                const char *boot_device,
 125                                const char *kernel_filename,
 126                                const char *kernel_cmdline,
 127                                const char *initrd_filename,
 128                                const char *cpu_model)
 129 {
 130     CPUState *env = NULL, *envs[MAX_CPUS];
 131     char *filename;
 132     qemu_irq *pic, **heathrow_irqs;
 133     int linux_boot, i;
 134     ram_addr_t ram_offset, bios_offset, vga_bios_offset;
 135     uint32_t kernel_base, initrd_base;
 136     int32_t kernel_size, initrd_size;
 137     PCIBus *pci_bus;
 138     MacIONVRAMState *nvr;
 139     int vga_bios_size, bios_size;
 140     int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index;
 141     int escc_mem_index, ide_mem_index[2];
 142     uint16_t ppc_boot_device;
 143     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 144     void *fw_cfg;
 145     void *dbdma;
 146     uint8_t *vga_bios_ptr;
 147
 148     linux_boot = (kernel_filename != NULL);
 149
 150     /* init CPUs */
 151     if (cpu_model == NULL)
 152         cpu_model = "G3";
 153     for (i = 0; i < smp_cpus; i++) {
 154         env = cpu_init(cpu_model);
 155         if (!env) {
 156             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 157             exit(1);
 158         }
 159         /* Set time-base frequency to 16.6 Mhz */
 160         cpu_ppc_tb_init(env,  16600000UL);
 161         env->osi_call = vga_osi_call;
 162         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 163         envs[i] = env;
 164     }
 165
 166     /* allocate RAM */
 167     if (ram_size > (2047 << 20)) {
 168         fprintf(stderr,
 169                 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
 170                 ((unsigned int)ram_size / (1 << 20)));
 171         exit(1);
 172     }
 173
 174     ram_offset = qemu_ram_alloc(ram_size);
 175     cpu_register_physical_memory(0, ram_size, ram_offset);
 176
 177     /* allocate and load BIOS */
 178     bios_offset = qemu_ram_alloc(BIOS_SIZE);
 179     if (bios_name == NULL)
 180         bios_name = PROM_FILENAME;
 181     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 182     cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM);
 183
 184     /* Load OpenBIOS (ELF) */
 185     if (filename) {
 186         bios_size = load_elf(filename, 0, NULL, NULL, NULL,
 187                                1, ELF_MACHINE, 0);
 188         qemu_free(filename);
 189     } else {
 190         bios_size = -1;
 191     }
 192     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 193         hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name);
 194         exit(1);
 195     }
 196
 197     /* allocate and load VGA BIOS */
 198     vga_bios_offset = qemu_ram_alloc(VGA_BIOS_SIZE);
 199     vga_bios_ptr = qemu_get_ram_ptr(vga_bios_offset);
 200     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, VGABIOS_FILENAME);
 201     if (filename) {
 202         vga_bios_size = load_image(filename, vga_bios_ptr + 8);
 203         qemu_free(filename);
 204     } else {
 205         vga_bios_size = -1;
 206     }
 207     if (vga_bios_size < 0) {
 208         /* if no bios is present, we can still work */
 209         fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n",
 210                 VGABIOS_FILENAME);
 211         vga_bios_size = 0;
 212     } else {
 213         /* set a specific header (XXX: find real Apple format for NDRV
 214            drivers) */
 215         vga_bios_ptr[0] = 'N';
 216         vga_bios_ptr[1] = 'D';
 217         vga_bios_ptr[2] = 'R';
 218         vga_bios_ptr[3] = 'V';
 219         cpu_to_be32w((uint32_t *)(vga_bios_ptr + 4), vga_bios_size);
 220         vga_bios_size += 8;
 221
 222         /* Round to page boundary */
 223         vga_bios_size = (vga_bios_size + TARGET_PAGE_SIZE - 1) &
 224             TARGET_PAGE_MASK;
 225     }
 226
 227     if (linux_boot) {
 228         uint64_t lowaddr = 0;
 229         int bswap_needed;
 230
 231 #ifdef BSWAP_NEEDED
 232         bswap_needed = 1;
 233 #else
 234         bswap_needed = 0;
 235 #endif
 236         kernel_base = KERNEL_LOAD_ADDR;
 237         /* Now we can load the kernel. The first step tries to load the kernel
 238            supposing PhysAddr = 0x00000000. If that was wrong the kernel is
 239            loaded again, the new PhysAddr being computed from lowaddr. */
 240         kernel_size = load_elf(kernel_filename, kernel_base, NULL, &lowaddr, NULL,
 241                                1, ELF_MACHINE, 0);
 242         if (kernel_size > 0 && lowaddr != KERNEL_LOAD_ADDR) {
 243             kernel_size = load_elf(kernel_filename, (2 * kernel_base) - lowaddr,
 244                                    NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 245         }
 246         if (kernel_size < 0)
 247             kernel_size = load_aout(kernel_filename, kernel_base,
 248                                     ram_size - kernel_base, bswap_needed,
 249                                     TARGET_PAGE_SIZE);
 250         if (kernel_size < 0)
 251             kernel_size = load_image_targphys(kernel_filename,
 252                                               kernel_base,
 253                                               ram_size - kernel_base);
 254         if (kernel_size < 0) {
 255             hw_error("qemu: could not load kernel '%s'\n",
 256                       kernel_filename);
 257             exit(1);
 258         }
 259         /* load initrd */
 260         if (initrd_filename) {
 261             initrd_base = INITRD_LOAD_ADDR;
 262             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 263                                               ram_size - initrd_base);
 264             if (initrd_size < 0) {
 265                 hw_error("qemu: could not load initial ram disk '%s'\n",
 266                          initrd_filename);
 267                 exit(1);
 268             }
 269         } else {
 270             initrd_base = 0;
 271             initrd_size = 0;
 272         }
 273         ppc_boot_device = 'm';
 274     } else {
 275         kernel_base = 0;
 276         kernel_size = 0;
 277         initrd_base = 0;
 278         initrd_size = 0;
 279         ppc_boot_device = '\0';
 280         for (i = 0; boot_device[i] != '\0'; i++) {
 281             /* TOFIX: for now, the second IDE channel is not properly
 282              *        used by OHW. The Mac floppy disk are not emulated.
 283              *        For now, OHW cannot boot from the network.
 284              */
 285 #if 0
 286             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 287                 ppc_boot_device = boot_device[i];
 288                 break;
 289             }
 290 #else
 291             if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
 292                 ppc_boot_device = boot_device[i];
 293                 break;
 294             }
 295 #endif
 296         }
 297         if (ppc_boot_device == '\0') {
 298             fprintf(stderr, "No valid boot device for G3 Beige machine\n");
 299             exit(1);
 300         }
 301     }
 302
 303     isa_mem_base = 0x80000000;
 304
 305     /* Register 2 MB of ISA IO space */
 306     isa_mmio_init(0xfe000000, 0x00200000);
 307
 308     /* XXX: we register only 1 output pin for heathrow PIC */
 309     heathrow_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
 310     heathrow_irqs[0] =
 311         qemu_mallocz(smp_cpus * sizeof(qemu_irq) * 1);
 312     /* Connect the heathrow PIC outputs to the 6xx bus */
 313     for (i = 0; i < smp_cpus; i++) {
 314         switch (PPC_INPUT(env)) {
 315         case PPC_FLAGS_INPUT_6xx:
 316             heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
 317             heathrow_irqs[i][0] =
 318                 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
 319             break;
 320         default:
 321             hw_error("Bus model not supported on OldWorld Mac machine\n");
 322         }
 323     }
 324
 325     /* init basic PC hardware */
 326     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 327         hw_error("Only 6xx bus is supported on heathrow machine\n");
 328     }
 329     pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
 330     pci_bus = pci_grackle_init(0xfec00000, pic);
 331     pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size);
 332
 333     escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
 334                                serial_hds[1], ESCC_CLOCK, 4);
 335
 336     for(i = 0; i < nb_nics; i++)
 337         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 338
 339
 340     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 341         fprintf(stderr, "qemu: too many IDE bus\n");
 342         exit(1);
 343     }
 344
 345     /* First IDE channel is a MAC IDE on the MacIO bus */
 346     hd[0] = drive_get(IF_IDE, 0, 0);
 347     hd[1] = drive_get(IF_IDE, 0, 1);
 348     dbdma = DBDMA_init(&dbdma_mem_index);
 349     ide_mem_index[0] = -1;
 350     ide_mem_index[1] = pmac_ide_init(hd, pic[0x0D], dbdma, 0x16, pic[0x02]);
 351
 352     /* Second IDE channel is a CMD646 on the PCI bus */
 353     hd[0] = drive_get(IF_IDE, 1, 0);
 354     hd[1] = drive_get(IF_IDE, 1, 1);
 355     hd[3] = hd[2] = NULL;
 356     pci_cmd646_ide_init(pci_bus, hd, 0);
 357
 358     /* cuda also initialize ADB */
 359     cuda_init(&cuda_mem_index, pic[0x12]);
 360
 361     adb_kbd_init(&adb_bus);
 362     adb_mouse_init(&adb_bus);
 363
 364     nvr = macio_nvram_init(&nvram_mem_index, 0x2000, 4);
 365     pmac_format_nvram_partition(nvr, 0x2000);
 366
 367     macio_init(pci_bus, PCI_DEVICE_ID_APPLE_343S1201, 1, pic_mem_index,
 368                dbdma_mem_index, cuda_mem_index, nvr, 2, ide_mem_index,
 369                escc_mem_index);
 370
 371     if (usb_enabled) {
 372         usb_ohci_init_pci(pci_bus, -1);
 373     }
 374
 375     if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
 376         graphic_depth = 15;
 377
 378     /* No PCI init: the BIOS will do it */
 379
 380     fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
 381     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 382     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 383     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
 384     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
 385     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 386     if (kernel_cmdline) {
 387         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 388         pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 389     } else {
 390         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 391     }
 392     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
 393     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 394     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
 395
 396     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
 397     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
 398     fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
 399
 400     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 401 }
 402
 403 static QEMUMachine heathrow_machine = {
 404     .name = "g3beige",
 405     .desc = "Heathrow based PowerMAC",
 406     .init = ppc_heathrow_init,
 407     .max_cpus = MAX_CPUS,
 408     .is_default = 1,
 409 };
 410
 411 static void heathrow_machine_init(void)
 412 {
 413     qemu_register_machine(&heathrow_machine);
 414 }
 415
 416 machine_init(heathrow_machine_init);