hw/gpio/imx_gpio.c

   1 /*
   2  * i.MX processors GPIO emulation.
   3  *
   4  * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "hw/gpio/imx_gpio.h"
  22 #include "qemu/log.h"
  23
  24 #ifndef DEBUG_IMX_GPIO
  25 #define DEBUG_IMX_GPIO 0
  26 #endif
  27
  28 typedef enum IMXGPIOLevel {
  29     IMX_GPIO_LEVEL_LOW = 0,
  30     IMX_GPIO_LEVEL_HIGH = 1,
  31 } IMXGPIOLevel;
  32
  33 #define DPRINTF(fmt, args...) \
  34     do { \
  35         if (DEBUG_IMX_GPIO) { \
  36             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \
  37                                              __func__, ##args); \
  38         } \
  39     } while (0)
  40
  41 static const char *imx_gpio_reg_name(uint32_t reg)
  42 {
  43     switch (reg) {
  44     case DR_ADDR:
  45         return "DR";
  46     case GDIR_ADDR:
  47         return "GDIR";
  48     case PSR_ADDR:
  49         return "PSR";
  50     case ICR1_ADDR:
  51         return "ICR1";
  52     case ICR2_ADDR:
  53         return "ICR2";
  54     case IMR_ADDR:
  55         return "IMR";
  56     case ISR_ADDR:
  57         return "ISR";
  58     case EDGE_SEL_ADDR:
  59         return "EDGE_SEL";
  60     default:
  61         return "[?]";
  62     }
  63 }
  64
  65 static void imx_gpio_update_int(IMXGPIOState *s)
  66 {
  67     if (s->has_upper_pin_irq) {
  68         qemu_set_irq(s->irq[0], (s->isr & s->imr & 0x0000FFFF) ? 1 : 0);
  69         qemu_set_irq(s->irq[1], (s->isr & s->imr & 0xFFFF0000) ? 1 : 0);
  70     } else {
  71         qemu_set_irq(s->irq[0], (s->isr & s->imr) ? 1 : 0);
  72     }
  73 }
  74
  75 static void imx_gpio_set_int_line(IMXGPIOState *s, int line, IMXGPIOLevel level)
  76 {
  77     /* if this signal isn't configured as an input signal, nothing to do */
  78     if (!extract32(s->gdir, line, 1)) {
  79         return;
  80     }
  81
  82     /* When set, EDGE_SEL overrides the ICR config */
  83     if (extract32(s->edge_sel, line, 1)) {
  84         /* we detect interrupt on rising and falling edge */
  85         if (extract32(s->psr, line, 1) != level) {
  86             /* level changed */
  87             s->isr = deposit32(s->isr, line, 1, 1);
  88         }
  89     } else if (extract64(s->icr, 2*line + 1, 1)) {
  90         /* interrupt is edge sensitive */
  91         if (extract32(s->psr, line, 1) != level) {
  92             /* level changed */
  93             if (extract64(s->icr, 2*line, 1) != level) {
  94                 s->isr = deposit32(s->isr, line, 1, 1);
  95             }
  96         }
  97     } else {
  98         /* interrupt is level sensitive */
  99         if (extract64(s->icr, 2*line, 1) == level) {
 100             s->isr = deposit32(s->isr, line, 1, 1);
 101         }
 102     }
 103 }
 104
 105 static void imx_gpio_set(void *opaque, int line, int level)
 106 {
 107     IMXGPIOState *s = IMX_GPIO(opaque);
 108     IMXGPIOLevel imx_level = level ? IMX_GPIO_LEVEL_HIGH : IMX_GPIO_LEVEL_LOW;
 109
 110     imx_gpio_set_int_line(s, line, imx_level);
 111
 112     /* this is an input signal, so set PSR */
 113     s->psr = deposit32(s->psr, line, 1, imx_level);
 114
 115     imx_gpio_update_int(s);
 116 }
 117
 118 static void imx_gpio_set_all_int_lines(IMXGPIOState *s)
 119 {
 120     int i;
 121
 122     for (i = 0; i < IMX_GPIO_PIN_COUNT; i++) {
 123         IMXGPIOLevel imx_level = extract32(s->psr, i, 1);
 124         imx_gpio_set_int_line(s, i, imx_level);
 125     }
 126
 127     imx_gpio_update_int(s);
 128 }
 129
 130 static inline void imx_gpio_set_all_output_lines(IMXGPIOState *s)
 131 {
 132     int i;
 133
 134     for (i = 0; i < IMX_GPIO_PIN_COUNT; i++) {
 135         /*
 136          * if the line is set as output, then forward the line
 137          * level to its user.
 138          */
 139         if (extract32(s->gdir, i, 1) && s->output[i]) {
 140             qemu_set_irq(s->output[i], extract32(s->dr, i, 1));
 141         }
 142     }
 143 }
 144
 145 static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size)
 146 {
 147     IMXGPIOState *s = IMX_GPIO(opaque);
 148     uint32_t reg_value = 0;
 149
 150     switch (offset) {
 151     case DR_ADDR:
 152         /*
 153          * depending on the "line" configuration, the bit values
 154          * are coming either from DR or PSR
 155          */
 156         reg_value = (s->dr & s->gdir) | (s->psr & ~s->gdir);
 157         break;
 158
 159     case GDIR_ADDR:
 160         reg_value = s->gdir;
 161         break;
 162
 163     case PSR_ADDR:
 164         reg_value = s->psr & ~s->gdir;
 165         break;
 166
 167     case ICR1_ADDR:
 168         reg_value = extract64(s->icr, 0, 32);
 169         break;
 170
 171     case ICR2_ADDR:
 172         reg_value = extract64(s->icr, 32, 32);
 173         break;
 174
 175     case IMR_ADDR:
 176         reg_value = s->imr;
 177         break;
 178
 179     case ISR_ADDR:
 180         reg_value = s->isr;
 181         break;
 182
 183     case EDGE_SEL_ADDR:
 184         if (s->has_edge_sel) {
 185             reg_value = s->edge_sel;
 186         } else {
 187             qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
 188                           "present on this version of GPIO device\n",
 189                           TYPE_IMX_GPIO, __func__);
 190         }
 191         break;
 192
 193     default:
 194         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 195                       HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
 196         break;
 197     }
 198
 199     DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value);
 200
 201     return reg_value;
 202 }
 203
 204 static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value,
 205                            unsigned size)
 206 {
 207     IMXGPIOState *s = IMX_GPIO(opaque);
 208
 209     DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset),
 210             (uint32_t)value);
 211
 212     switch (offset) {
 213     case DR_ADDR:
 214         s->dr = value;
 215         imx_gpio_set_all_output_lines(s);
 216         break;
 217
 218     case GDIR_ADDR:
 219         s->gdir = value;
 220         imx_gpio_set_all_output_lines(s);
 221         imx_gpio_set_all_int_lines(s);
 222         break;
 223
 224     case ICR1_ADDR:
 225         s->icr = deposit64(s->icr, 0, 32, value);
 226         imx_gpio_set_all_int_lines(s);
 227         break;
 228
 229     case ICR2_ADDR:
 230         s->icr = deposit64(s->icr, 32, 32, value);
 231         imx_gpio_set_all_int_lines(s);
 232         break;
 233
 234     case IMR_ADDR:
 235         s->imr = value;
 236         imx_gpio_update_int(s);
 237         break;
 238
 239     case ISR_ADDR:
 240         s->isr |= ~value;
 241         imx_gpio_set_all_int_lines(s);
 242         break;
 243
 244     case EDGE_SEL_ADDR:
 245         if (s->has_edge_sel) {
 246             s->edge_sel = value;
 247             imx_gpio_set_all_int_lines(s);
 248         } else {
 249             qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not "
 250                           "present on this version of GPIO device\n",
 251                           TYPE_IMX_GPIO, __func__);
 252         }
 253         break;
 254
 255     default:
 256         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
 257                       HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset);
 258         break;
 259     }
 260
 261     return;
 262 }
 263
 264 static const MemoryRegionOps imx_gpio_ops = {
 265     .read = imx_gpio_read,
 266     .write = imx_gpio_write,
 267     .valid.min_access_size = 4,
 268     .valid.max_access_size = 4,
 269     .endianness = DEVICE_NATIVE_ENDIAN,
 270 };
 271
 272 static const VMStateDescription vmstate_imx_gpio = {
 273     .name = TYPE_IMX_GPIO,
 274     .version_id = 1,
 275     .minimum_version_id = 1,
 276     .minimum_version_id_old = 1,
 277     .fields = (VMStateField[]) {
 278         VMSTATE_UINT32(dr, IMXGPIOState),
 279         VMSTATE_UINT32(gdir, IMXGPIOState),
 280         VMSTATE_UINT32(psr, IMXGPIOState),
 281         VMSTATE_UINT64(icr, IMXGPIOState),
 282         VMSTATE_UINT32(imr, IMXGPIOState),
 283         VMSTATE_UINT32(isr, IMXGPIOState),
 284         VMSTATE_BOOL(has_edge_sel, IMXGPIOState),
 285         VMSTATE_UINT32(edge_sel, IMXGPIOState),
 286         VMSTATE_END_OF_LIST()
 287     }
 288 };
 289
 290 static Property imx_gpio_properties[] = {
 291     DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true),
 292     DEFINE_PROP_BOOL("has-upper-pin-irq", IMXGPIOState, has_upper_pin_irq,
 293                      false),
 294     DEFINE_PROP_END_OF_LIST(),
 295 };
 296
 297 static void imx_gpio_reset(DeviceState *dev)
 298 {
 299     IMXGPIOState *s = IMX_GPIO(dev);
 300
 301     s->dr       = 0;
 302     s->gdir     = 0;
 303     s->psr      = 0;
 304     s->icr      = 0;
 305     s->imr      = 0;
 306     s->isr      = 0;
 307     s->edge_sel = 0;
 308
 309     imx_gpio_set_all_output_lines(s);
 310     imx_gpio_update_int(s);
 311 }
 312
 313 static void imx_gpio_realize(DeviceState *dev, Error **errp)
 314 {
 315     IMXGPIOState *s = IMX_GPIO(dev);
 316
 317     memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpio_ops, s,
 318                           TYPE_IMX_GPIO, IMX_GPIO_MEM_SIZE);
 319
 320     qdev_init_gpio_in(DEVICE(s), imx_gpio_set, IMX_GPIO_PIN_COUNT);
 321     qdev_init_gpio_out(DEVICE(s), s->output, IMX_GPIO_PIN_COUNT);
 322
 323     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[0]);
 324     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[1]);
 325     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
 326 }
 327
 328 static void imx_gpio_class_init(ObjectClass *klass, void *data)
 329 {
 330     DeviceClass *dc = DEVICE_CLASS(klass);
 331
 332     dc->realize = imx_gpio_realize;
 333     dc->reset = imx_gpio_reset;
 334     dc->props = imx_gpio_properties;
 335     dc->vmsd = &vmstate_imx_gpio;
 336     dc->desc = "i.MX GPIO controller";
 337 }
 338
 339 static const TypeInfo imx_gpio_info = {
 340     .name = TYPE_IMX_GPIO,
 341     .parent = TYPE_SYS_BUS_DEVICE,
 342     .instance_size = sizeof(IMXGPIOState),
 343     .class_init = imx_gpio_class_init,
 344 };
 345
 346 static void imx_gpio_register_types(void)
 347 {
 348     type_register_static(&imx_gpio_info);
 349 }
 350
 351 type_init(imx_gpio_register_types)