4 * Copyright (c) 2019 Yoshinori Sato
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/bswap.h"
21 #include "qemu/qemu-print.h"
23 #include "exec/exec-all.h"
24 #include "tcg/tcg-op.h"
25 #include "exec/cpu_ldst.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28 #include "exec/translator.h"
31 typedef struct DisasContext
{
32 DisasContextBase base
;
38 typedef struct DisasCompare
{
44 const char *rx_crname(uint8_t cr
)
46 static const char *cr_names
[] = {
47 "psw", "pc", "usp", "fpsw", "", "", "", "",
48 "bpsw", "bpc", "isp", "fintv", "intb", "", "", ""
50 if (cr
>= ARRAY_SIZE(cr_names
)) {
56 /* Target-specific values for dc->base.is_jmp. */
57 #define DISAS_JUMP DISAS_TARGET_0
58 #define DISAS_UPDATE DISAS_TARGET_1
59 #define DISAS_EXIT DISAS_TARGET_2
61 /* global register indexes */
62 static TCGv cpu_regs
[16];
63 static TCGv cpu_psw_o
, cpu_psw_s
, cpu_psw_z
, cpu_psw_c
;
64 static TCGv cpu_psw_i
, cpu_psw_pm
, cpu_psw_u
, cpu_psw_ipl
;
65 static TCGv cpu_usp
, cpu_fpsw
, cpu_bpsw
, cpu_bpc
, cpu_isp
;
66 static TCGv cpu_fintv
, cpu_intb
, cpu_pc
;
67 static TCGv_i64 cpu_acc
;
69 #define cpu_sp cpu_regs[0]
71 #include "exec/gen-icount.h"
74 static uint32_t decode_load_bytes(DisasContext
*ctx
, uint32_t insn
,
78 uint8_t b
= cpu_ldub_code(ctx
->env
, ctx
->base
.pc_next
++);
79 insn
|= b
<< (32 - i
* 8);
84 static uint32_t li(DisasContext
*ctx
, int sz
)
87 CPURXState
*env
= ctx
->env
;
88 addr
= ctx
->base
.pc_next
;
90 tcg_debug_assert(sz
< 4);
93 ctx
->base
.pc_next
+= 1;
94 return cpu_ldsb_code(env
, addr
);
96 ctx
->base
.pc_next
+= 2;
97 return cpu_ldsw_code(env
, addr
);
99 ctx
->base
.pc_next
+= 3;
100 tmp
= cpu_ldsb_code(env
, addr
+ 2) << 16;
101 tmp
|= cpu_lduw_code(env
, addr
) & 0xffff;
104 ctx
->base
.pc_next
+= 4;
105 return cpu_ldl_code(env
, addr
);
110 static int bdsp_s(DisasContext
*ctx
, int d
)
126 /* Include the auto-generated decoder. */
127 #include "decode-insns.c.inc"
129 void rx_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
131 RXCPU
*cpu
= RX_CPU(cs
);
132 CPURXState
*env
= &cpu
->env
;
136 psw
= rx_cpu_pack_psw(env
);
137 qemu_fprintf(f
, "pc=0x%08x psw=0x%08x\n",
139 for (i
= 0; i
< 16; i
+= 4) {
140 qemu_fprintf(f
, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
141 i
, env
->regs
[i
], i
+ 1, env
->regs
[i
+ 1],
142 i
+ 2, env
->regs
[i
+ 2], i
+ 3, env
->regs
[i
+ 3]);
146 static void gen_goto_tb(DisasContext
*dc
, int n
, target_ulong dest
)
148 if (translator_use_goto_tb(&dc
->base
, dest
)) {
150 tcg_gen_movi_i32(cpu_pc
, dest
);
151 tcg_gen_exit_tb(dc
->base
.tb
, n
);
153 tcg_gen_movi_i32(cpu_pc
, dest
);
154 tcg_gen_lookup_and_goto_ptr();
156 dc
->base
.is_jmp
= DISAS_NORETURN
;
159 /* generic load wrapper */
160 static inline void rx_gen_ld(unsigned int size
, TCGv reg
, TCGv mem
)
162 tcg_gen_qemu_ld_i32(reg
, mem
, 0, size
| MO_SIGN
| MO_TE
);
165 /* unsigned load wrapper */
166 static inline void rx_gen_ldu(unsigned int size
, TCGv reg
, TCGv mem
)
168 tcg_gen_qemu_ld_i32(reg
, mem
, 0, size
| MO_TE
);
171 /* generic store wrapper */
172 static inline void rx_gen_st(unsigned int size
, TCGv reg
, TCGv mem
)
174 tcg_gen_qemu_st_i32(reg
, mem
, 0, size
| MO_TE
);
178 static inline void rx_gen_regindex(DisasContext
*ctx
, TCGv mem
,
179 int size
, int ri
, int rb
)
181 tcg_gen_shli_i32(mem
, cpu_regs
[ri
], size
);
182 tcg_gen_add_i32(mem
, mem
, cpu_regs
[rb
]);
186 static inline TCGv
rx_index_addr(DisasContext
*ctx
, TCGv mem
,
187 int ld
, int size
, int reg
)
191 tcg_debug_assert(ld
< 3);
194 return cpu_regs
[reg
];
196 dsp
= cpu_ldub_code(ctx
->env
, ctx
->base
.pc_next
) << size
;
197 tcg_gen_addi_i32(mem
, cpu_regs
[reg
], dsp
);
198 ctx
->base
.pc_next
+= 1;
201 dsp
= cpu_lduw_code(ctx
->env
, ctx
->base
.pc_next
) << size
;
202 tcg_gen_addi_i32(mem
, cpu_regs
[reg
], dsp
);
203 ctx
->base
.pc_next
+= 2;
209 static inline MemOp
mi_to_mop(unsigned mi
)
211 static const MemOp mop
[5] = { MO_SB
, MO_SW
, MO_UL
, MO_UW
, MO_UB
};
212 tcg_debug_assert(mi
< 5);
216 /* load source operand */
217 static inline TCGv
rx_load_source(DisasContext
*ctx
, TCGv mem
,
218 int ld
, int mi
, int rs
)
224 addr
= rx_index_addr(ctx
, mem
, ld
, mop
& MO_SIZE
, rs
);
225 tcg_gen_qemu_ld_i32(mem
, addr
, 0, mop
| MO_TE
);
232 /* Processor mode check */
233 static int is_privileged(DisasContext
*ctx
, int is_exception
)
235 if (FIELD_EX32(ctx
->tb_flags
, PSW
, PM
)) {
237 gen_helper_raise_privilege_violation(cpu_env
);
245 /* generate QEMU condition */
246 static void psw_cond(DisasCompare
*dc
, uint32_t cond
)
248 tcg_debug_assert(cond
< 16);
251 dc
->cond
= TCG_COND_EQ
;
252 dc
->value
= cpu_psw_z
;
255 dc
->cond
= TCG_COND_NE
;
256 dc
->value
= cpu_psw_z
;
259 dc
->cond
= TCG_COND_NE
;
260 dc
->value
= cpu_psw_c
;
263 dc
->cond
= TCG_COND_EQ
;
264 dc
->value
= cpu_psw_c
;
266 case 4: /* gtu (C& ~Z) == 1 */
267 case 5: /* leu (C& ~Z) == 0 */
268 tcg_gen_setcondi_i32(TCG_COND_NE
, dc
->temp
, cpu_psw_z
, 0);
269 tcg_gen_and_i32(dc
->temp
, dc
->temp
, cpu_psw_c
);
270 dc
->cond
= (cond
== 4) ? TCG_COND_NE
: TCG_COND_EQ
;
271 dc
->value
= dc
->temp
;
273 case 6: /* pz (S == 0) */
274 dc
->cond
= TCG_COND_GE
;
275 dc
->value
= cpu_psw_s
;
277 case 7: /* n (S == 1) */
278 dc
->cond
= TCG_COND_LT
;
279 dc
->value
= cpu_psw_s
;
281 case 8: /* ge (S^O)==0 */
282 case 9: /* lt (S^O)==1 */
283 tcg_gen_xor_i32(dc
->temp
, cpu_psw_o
, cpu_psw_s
);
284 dc
->cond
= (cond
== 8) ? TCG_COND_GE
: TCG_COND_LT
;
285 dc
->value
= dc
->temp
;
287 case 10: /* gt ((S^O)|Z)==0 */
288 case 11: /* le ((S^O)|Z)==1 */
289 tcg_gen_xor_i32(dc
->temp
, cpu_psw_o
, cpu_psw_s
);
290 tcg_gen_sari_i32(dc
->temp
, dc
->temp
, 31);
291 tcg_gen_andc_i32(dc
->temp
, cpu_psw_z
, dc
->temp
);
292 dc
->cond
= (cond
== 10) ? TCG_COND_NE
: TCG_COND_EQ
;
293 dc
->value
= dc
->temp
;
296 dc
->cond
= TCG_COND_LT
;
297 dc
->value
= cpu_psw_o
;
300 dc
->cond
= TCG_COND_GE
;
301 dc
->value
= cpu_psw_o
;
303 case 14: /* always true */
304 dc
->cond
= TCG_COND_ALWAYS
;
305 dc
->value
= dc
->temp
;
307 case 15: /* always false */
308 dc
->cond
= TCG_COND_NEVER
;
309 dc
->value
= dc
->temp
;
314 static void move_from_cr(DisasContext
*ctx
, TCGv ret
, int cr
, uint32_t pc
)
318 gen_helper_pack_psw(ret
, cpu_env
);
321 tcg_gen_movi_i32(ret
, pc
);
324 if (FIELD_EX32(ctx
->tb_flags
, PSW
, U
)) {
325 tcg_gen_mov_i32(ret
, cpu_sp
);
327 tcg_gen_mov_i32(ret
, cpu_usp
);
331 tcg_gen_mov_i32(ret
, cpu_fpsw
);
334 tcg_gen_mov_i32(ret
, cpu_bpsw
);
337 tcg_gen_mov_i32(ret
, cpu_bpc
);
340 if (FIELD_EX32(ctx
->tb_flags
, PSW
, U
)) {
341 tcg_gen_mov_i32(ret
, cpu_isp
);
343 tcg_gen_mov_i32(ret
, cpu_sp
);
347 tcg_gen_mov_i32(ret
, cpu_fintv
);
350 tcg_gen_mov_i32(ret
, cpu_intb
);
353 qemu_log_mask(LOG_GUEST_ERROR
, "Unimplement control register %d", cr
);
354 /* Unimplement registers return 0 */
355 tcg_gen_movi_i32(ret
, 0);
360 static void move_to_cr(DisasContext
*ctx
, TCGv val
, int cr
)
362 if (cr
>= 8 && !is_privileged(ctx
, 0)) {
363 /* Some control registers can only be written in privileged mode. */
364 qemu_log_mask(LOG_GUEST_ERROR
,
365 "disallow control register write %s", rx_crname(cr
));
370 gen_helper_set_psw(cpu_env
, val
);
371 if (is_privileged(ctx
, 0)) {
372 /* PSW.{I,U} may be updated here. exit TB. */
373 ctx
->base
.is_jmp
= DISAS_UPDATE
;
376 /* case 1: to PC not supported */
378 if (FIELD_EX32(ctx
->tb_flags
, PSW
, U
)) {
379 tcg_gen_mov_i32(cpu_sp
, val
);
381 tcg_gen_mov_i32(cpu_usp
, val
);
385 gen_helper_set_fpsw(cpu_env
, val
);
388 tcg_gen_mov_i32(cpu_bpsw
, val
);
391 tcg_gen_mov_i32(cpu_bpc
, val
);
394 if (FIELD_EX32(ctx
->tb_flags
, PSW
, U
)) {
395 tcg_gen_mov_i32(cpu_isp
, val
);
397 tcg_gen_mov_i32(cpu_sp
, val
);
401 tcg_gen_mov_i32(cpu_fintv
, val
);
404 tcg_gen_mov_i32(cpu_intb
, val
);
407 qemu_log_mask(LOG_GUEST_ERROR
,
408 "Unimplement control register %d", cr
);
413 static void push(TCGv val
)
415 tcg_gen_subi_i32(cpu_sp
, cpu_sp
, 4);
416 rx_gen_st(MO_32
, val
, cpu_sp
);
419 static void pop(TCGv ret
)
421 rx_gen_ld(MO_32
, ret
, cpu_sp
);
422 tcg_gen_addi_i32(cpu_sp
, cpu_sp
, 4);
425 /* mov.<bwl> rs,dsp5[rd] */
426 static bool trans_MOV_rm(DisasContext
*ctx
, arg_MOV_rm
*a
)
429 mem
= tcg_temp_new();
430 tcg_gen_addi_i32(mem
, cpu_regs
[a
->rd
], a
->dsp
<< a
->sz
);
431 rx_gen_st(a
->sz
, cpu_regs
[a
->rs
], mem
);
436 /* mov.<bwl> dsp5[rs],rd */
437 static bool trans_MOV_mr(DisasContext
*ctx
, arg_MOV_mr
*a
)
440 mem
= tcg_temp_new();
441 tcg_gen_addi_i32(mem
, cpu_regs
[a
->rs
], a
->dsp
<< a
->sz
);
442 rx_gen_ld(a
->sz
, cpu_regs
[a
->rd
], mem
);
447 /* mov.l #uimm4,rd */
448 /* mov.l #uimm8,rd */
450 static bool trans_MOV_ir(DisasContext
*ctx
, arg_MOV_ir
*a
)
452 tcg_gen_movi_i32(cpu_regs
[a
->rd
], a
->imm
);
456 /* mov.<bwl> #uimm8,dsp[rd] */
457 /* mov.<bwl> #imm, dsp[rd] */
458 static bool trans_MOV_im(DisasContext
*ctx
, arg_MOV_im
*a
)
461 imm
= tcg_const_i32(a
->imm
);
462 mem
= tcg_temp_new();
463 tcg_gen_addi_i32(mem
, cpu_regs
[a
->rd
], a
->dsp
<< a
->sz
);
464 rx_gen_st(a
->sz
, imm
, mem
);
470 /* mov.<bwl> [ri,rb],rd */
471 static bool trans_MOV_ar(DisasContext
*ctx
, arg_MOV_ar
*a
)
474 mem
= tcg_temp_new();
475 rx_gen_regindex(ctx
, mem
, a
->sz
, a
->ri
, a
->rb
);
476 rx_gen_ld(a
->sz
, cpu_regs
[a
->rd
], mem
);
481 /* mov.<bwl> rd,[ri,rb] */
482 static bool trans_MOV_ra(DisasContext
*ctx
, arg_MOV_ra
*a
)
485 mem
= tcg_temp_new();
486 rx_gen_regindex(ctx
, mem
, a
->sz
, a
->ri
, a
->rb
);
487 rx_gen_st(a
->sz
, cpu_regs
[a
->rs
], mem
);
492 /* mov.<bwl> dsp[rs],dsp[rd] */
493 /* mov.<bwl> rs,dsp[rd] */
494 /* mov.<bwl> dsp[rs],rd */
495 /* mov.<bwl> rs,rd */
496 static bool trans_MOV_mm(DisasContext
*ctx
, arg_MOV_mm
*a
)
498 static void (* const mov
[])(TCGv ret
, TCGv arg
) = {
499 tcg_gen_ext8s_i32
, tcg_gen_ext16s_i32
, tcg_gen_mov_i32
,
502 if (a
->lds
== 3 && a
->ldd
== 3) {
503 /* mov.<bwl> rs,rd */
504 mov
[a
->sz
](cpu_regs
[a
->rd
], cpu_regs
[a
->rs
]);
508 mem
= tcg_temp_new();
510 /* mov.<bwl> rs,dsp[rd] */
511 addr
= rx_index_addr(ctx
, mem
, a
->ldd
, a
->sz
, a
->rs
);
512 rx_gen_st(a
->sz
, cpu_regs
[a
->rd
], addr
);
513 } else if (a
->ldd
== 3) {
514 /* mov.<bwl> dsp[rs],rd */
515 addr
= rx_index_addr(ctx
, mem
, a
->lds
, a
->sz
, a
->rs
);
516 rx_gen_ld(a
->sz
, cpu_regs
[a
->rd
], addr
);
518 /* mov.<bwl> dsp[rs],dsp[rd] */
519 tmp
= tcg_temp_new();
520 addr
= rx_index_addr(ctx
, mem
, a
->lds
, a
->sz
, a
->rs
);
521 rx_gen_ld(a
->sz
, tmp
, addr
);
522 addr
= rx_index_addr(ctx
, mem
, a
->ldd
, a
->sz
, a
->rd
);
523 rx_gen_st(a
->sz
, tmp
, addr
);
530 /* mov.<bwl> rs,[rd+] */
531 /* mov.<bwl> rs,[-rd] */
532 static bool trans_MOV_rp(DisasContext
*ctx
, arg_MOV_rp
*a
)
535 val
= tcg_temp_new();
536 tcg_gen_mov_i32(val
, cpu_regs
[a
->rs
]);
538 tcg_gen_subi_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 1 << a
->sz
);
540 rx_gen_st(a
->sz
, val
, cpu_regs
[a
->rd
]);
542 tcg_gen_addi_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 1 << a
->sz
);
548 /* mov.<bwl> [rd+],rs */
549 /* mov.<bwl> [-rd],rs */
550 static bool trans_MOV_pr(DisasContext
*ctx
, arg_MOV_pr
*a
)
553 val
= tcg_temp_new();
555 tcg_gen_subi_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 1 << a
->sz
);
557 rx_gen_ld(a
->sz
, val
, cpu_regs
[a
->rd
]);
559 tcg_gen_addi_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 1 << a
->sz
);
561 tcg_gen_mov_i32(cpu_regs
[a
->rs
], val
);
566 /* movu.<bw> dsp5[rs],rd */
567 /* movu.<bw> dsp[rs],rd */
568 static bool trans_MOVU_mr(DisasContext
*ctx
, arg_MOVU_mr
*a
)
571 mem
= tcg_temp_new();
572 tcg_gen_addi_i32(mem
, cpu_regs
[a
->rs
], a
->dsp
<< a
->sz
);
573 rx_gen_ldu(a
->sz
, cpu_regs
[a
->rd
], mem
);
578 /* movu.<bw> rs,rd */
579 static bool trans_MOVU_rr(DisasContext
*ctx
, arg_MOVU_rr
*a
)
581 static void (* const ext
[])(TCGv ret
, TCGv arg
) = {
582 tcg_gen_ext8u_i32
, tcg_gen_ext16u_i32
,
584 ext
[a
->sz
](cpu_regs
[a
->rd
], cpu_regs
[a
->rs
]);
588 /* movu.<bw> [ri,rb],rd */
589 static bool trans_MOVU_ar(DisasContext
*ctx
, arg_MOVU_ar
*a
)
592 mem
= tcg_temp_new();
593 rx_gen_regindex(ctx
, mem
, a
->sz
, a
->ri
, a
->rb
);
594 rx_gen_ldu(a
->sz
, cpu_regs
[a
->rd
], mem
);
599 /* movu.<bw> [rd+],rs */
600 /* mov.<bw> [-rd],rs */
601 static bool trans_MOVU_pr(DisasContext
*ctx
, arg_MOVU_pr
*a
)
604 val
= tcg_temp_new();
606 tcg_gen_subi_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 1 << a
->sz
);
608 rx_gen_ldu(a
->sz
, val
, cpu_regs
[a
->rd
]);
610 tcg_gen_addi_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 1 << a
->sz
);
612 tcg_gen_mov_i32(cpu_regs
[a
->rs
], val
);
619 static bool trans_POP(DisasContext
*ctx
, arg_POP
*a
)
621 /* mov.l [r0+], rd */
627 trans_MOV_pr(ctx
, &mov_a
);
632 static bool trans_POPC(DisasContext
*ctx
, arg_POPC
*a
)
635 val
= tcg_temp_new();
637 move_to_cr(ctx
, val
, a
->cr
);
643 static bool trans_POPM(DisasContext
*ctx
, arg_POPM
*a
)
646 if (a
->rd
== 0 || a
->rd
>= a
->rd2
) {
647 qemu_log_mask(LOG_GUEST_ERROR
,
648 "Invalid register ranges r%d-r%d", a
->rd
, a
->rd2
);
651 while (r
<= a
->rd2
&& r
< 16) {
659 static bool trans_PUSH_r(DisasContext
*ctx
, arg_PUSH_r
*a
)
662 val
= tcg_temp_new();
663 tcg_gen_mov_i32(val
, cpu_regs
[a
->rs
]);
664 tcg_gen_subi_i32(cpu_sp
, cpu_sp
, 4);
665 rx_gen_st(a
->sz
, val
, cpu_sp
);
670 /* push.<bwl> dsp[rs] */
671 static bool trans_PUSH_m(DisasContext
*ctx
, arg_PUSH_m
*a
)
674 mem
= tcg_temp_new();
675 val
= tcg_temp_new();
676 addr
= rx_index_addr(ctx
, mem
, a
->ld
, a
->sz
, a
->rs
);
677 rx_gen_ld(a
->sz
, val
, addr
);
678 tcg_gen_subi_i32(cpu_sp
, cpu_sp
, 4);
679 rx_gen_st(a
->sz
, val
, cpu_sp
);
686 static bool trans_PUSHC(DisasContext
*ctx
, arg_PUSHC
*a
)
689 val
= tcg_temp_new();
690 move_from_cr(ctx
, val
, a
->cr
, ctx
->pc
);
697 static bool trans_PUSHM(DisasContext
*ctx
, arg_PUSHM
*a
)
701 if (a
->rs
== 0 || a
->rs
>= a
->rs2
) {
702 qemu_log_mask(LOG_GUEST_ERROR
,
703 "Invalid register ranges r%d-r%d", a
->rs
, a
->rs2
);
706 while (r
>= a
->rs
&& r
>= 0) {
713 static bool trans_XCHG_rr(DisasContext
*ctx
, arg_XCHG_rr
*a
)
716 tmp
= tcg_temp_new();
717 tcg_gen_mov_i32(tmp
, cpu_regs
[a
->rs
]);
718 tcg_gen_mov_i32(cpu_regs
[a
->rs
], cpu_regs
[a
->rd
]);
719 tcg_gen_mov_i32(cpu_regs
[a
->rd
], tmp
);
724 /* xchg dsp[rs].<mi>,rd */
725 static bool trans_XCHG_mr(DisasContext
*ctx
, arg_XCHG_mr
*a
)
728 mem
= tcg_temp_new();
730 case 0: /* dsp[rs].b */
731 case 1: /* dsp[rs].w */
732 case 2: /* dsp[rs].l */
733 addr
= rx_index_addr(ctx
, mem
, a
->ld
, a
->mi
, a
->rs
);
735 case 3: /* dsp[rs].uw */
736 case 4: /* dsp[rs].ub */
737 addr
= rx_index_addr(ctx
, mem
, a
->ld
, 4 - a
->mi
, a
->rs
);
740 g_assert_not_reached();
742 tcg_gen_atomic_xchg_i32(cpu_regs
[a
->rd
], addr
, cpu_regs
[a
->rd
],
743 0, mi_to_mop(a
->mi
));
748 static inline void stcond(TCGCond cond
, int rd
, int imm
)
752 z
= tcg_const_i32(0);
753 _imm
= tcg_const_i32(imm
);
754 tcg_gen_movcond_i32(cond
, cpu_regs
[rd
], cpu_psw_z
, z
,
761 static bool trans_STZ(DisasContext
*ctx
, arg_STZ
*a
)
763 stcond(TCG_COND_EQ
, a
->rd
, a
->imm
);
768 static bool trans_STNZ(DisasContext
*ctx
, arg_STNZ
*a
)
770 stcond(TCG_COND_NE
, a
->rd
, a
->imm
);
775 /* sccnd.<bwl> dsp:[rd] */
776 static bool trans_SCCnd(DisasContext
*ctx
, arg_SCCnd
*a
)
780 dc
.temp
= tcg_temp_new();
781 psw_cond(&dc
, a
->cd
);
783 val
= tcg_temp_new();
784 mem
= tcg_temp_new();
785 tcg_gen_setcondi_i32(dc
.cond
, val
, dc
.value
, 0);
786 addr
= rx_index_addr(ctx
, mem
, a
->sz
, a
->ld
, a
->rd
);
787 rx_gen_st(a
->sz
, val
, addr
);
791 tcg_gen_setcondi_i32(dc
.cond
, cpu_regs
[a
->rd
], dc
.value
, 0);
793 tcg_temp_free(dc
.temp
);
798 static bool trans_RTSD_i(DisasContext
*ctx
, arg_RTSD_i
*a
)
800 tcg_gen_addi_i32(cpu_sp
, cpu_sp
, a
->imm
<< 2);
802 ctx
->base
.is_jmp
= DISAS_JUMP
;
806 /* rtsd #imm, rd-rd2 */
807 static bool trans_RTSD_irr(DisasContext
*ctx
, arg_RTSD_irr
*a
)
812 if (a
->rd2
>= a
->rd
) {
813 adj
= a
->imm
- (a
->rd2
- a
->rd
+ 1);
815 adj
= a
->imm
- (15 - a
->rd
+ 1);
818 tcg_gen_addi_i32(cpu_sp
, cpu_sp
, adj
<< 2);
820 while (dst
<= a
->rd2
&& dst
< 16) {
821 pop(cpu_regs
[dst
++]);
824 ctx
->base
.is_jmp
= DISAS_JUMP
;
828 typedef void (*op2fn
)(TCGv ret
, TCGv arg1
);
829 typedef void (*op3fn
)(TCGv ret
, TCGv arg1
, TCGv arg2
);
831 static inline void rx_gen_op_rr(op2fn opr
, int dst
, int src
)
833 opr(cpu_regs
[dst
], cpu_regs
[src
]);
836 static inline void rx_gen_op_rrr(op3fn opr
, int dst
, int src
, int src2
)
838 opr(cpu_regs
[dst
], cpu_regs
[src
], cpu_regs
[src2
]);
841 static inline void rx_gen_op_irr(op3fn opr
, int dst
, int src
, uint32_t src2
)
843 TCGv imm
= tcg_const_i32(src2
);
844 opr(cpu_regs
[dst
], cpu_regs
[src
], imm
);
848 static inline void rx_gen_op_mr(op3fn opr
, DisasContext
*ctx
,
849 int dst
, int src
, int ld
, int mi
)
852 mem
= tcg_temp_new();
853 val
= rx_load_source(ctx
, mem
, ld
, mi
, src
);
854 opr(cpu_regs
[dst
], cpu_regs
[dst
], val
);
858 static void rx_and(TCGv ret
, TCGv arg1
, TCGv arg2
)
860 tcg_gen_and_i32(cpu_psw_s
, arg1
, arg2
);
861 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_s
);
862 tcg_gen_mov_i32(ret
, cpu_psw_s
);
865 /* and #uimm:4, rd */
867 static bool trans_AND_ir(DisasContext
*ctx
, arg_AND_ir
*a
)
869 rx_gen_op_irr(rx_and
, a
->rd
, a
->rd
, a
->imm
);
873 /* and dsp[rs], rd */
875 static bool trans_AND_mr(DisasContext
*ctx
, arg_AND_mr
*a
)
877 rx_gen_op_mr(rx_and
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
882 static bool trans_AND_rrr(DisasContext
*ctx
, arg_AND_rrr
*a
)
884 rx_gen_op_rrr(rx_and
, a
->rd
, a
->rs
, a
->rs2
);
888 static void rx_or(TCGv ret
, TCGv arg1
, TCGv arg2
)
890 tcg_gen_or_i32(cpu_psw_s
, arg1
, arg2
);
891 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_s
);
892 tcg_gen_mov_i32(ret
, cpu_psw_s
);
897 static bool trans_OR_ir(DisasContext
*ctx
, arg_OR_ir
*a
)
899 rx_gen_op_irr(rx_or
, a
->rd
, a
->rd
, a
->imm
);
905 static bool trans_OR_mr(DisasContext
*ctx
, arg_OR_mr
*a
)
907 rx_gen_op_mr(rx_or
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
912 static bool trans_OR_rrr(DisasContext
*ctx
, arg_OR_rrr
*a
)
914 rx_gen_op_rrr(rx_or
, a
->rd
, a
->rs
, a
->rs2
);
918 static void rx_xor(TCGv ret
, TCGv arg1
, TCGv arg2
)
920 tcg_gen_xor_i32(cpu_psw_s
, arg1
, arg2
);
921 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_s
);
922 tcg_gen_mov_i32(ret
, cpu_psw_s
);
926 static bool trans_XOR_ir(DisasContext
*ctx
, arg_XOR_ir
*a
)
928 rx_gen_op_irr(rx_xor
, a
->rd
, a
->rd
, a
->imm
);
932 /* xor dsp[rs], rd */
934 static bool trans_XOR_mr(DisasContext
*ctx
, arg_XOR_mr
*a
)
936 rx_gen_op_mr(rx_xor
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
940 static void rx_tst(TCGv ret
, TCGv arg1
, TCGv arg2
)
942 tcg_gen_and_i32(cpu_psw_s
, arg1
, arg2
);
943 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_s
);
947 static bool trans_TST_ir(DisasContext
*ctx
, arg_TST_ir
*a
)
949 rx_gen_op_irr(rx_tst
, a
->rd
, a
->rd
, a
->imm
);
953 /* tst dsp[rs], rd */
955 static bool trans_TST_mr(DisasContext
*ctx
, arg_TST_mr
*a
)
957 rx_gen_op_mr(rx_tst
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
961 static void rx_not(TCGv ret
, TCGv arg1
)
963 tcg_gen_not_i32(ret
, arg1
);
964 tcg_gen_mov_i32(cpu_psw_z
, ret
);
965 tcg_gen_mov_i32(cpu_psw_s
, ret
);
970 static bool trans_NOT_rr(DisasContext
*ctx
, arg_NOT_rr
*a
)
972 rx_gen_op_rr(rx_not
, a
->rd
, a
->rs
);
976 static void rx_neg(TCGv ret
, TCGv arg1
)
978 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_psw_o
, arg1
, 0x80000000);
979 tcg_gen_neg_i32(ret
, arg1
);
980 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_psw_c
, ret
, 0);
981 tcg_gen_mov_i32(cpu_psw_z
, ret
);
982 tcg_gen_mov_i32(cpu_psw_s
, ret
);
988 static bool trans_NEG_rr(DisasContext
*ctx
, arg_NEG_rr
*a
)
990 rx_gen_op_rr(rx_neg
, a
->rd
, a
->rs
);
994 /* ret = arg1 + arg2 + psw_c */
995 static void rx_adc(TCGv ret
, TCGv arg1
, TCGv arg2
)
998 z
= tcg_const_i32(0);
999 tcg_gen_add2_i32(cpu_psw_s
, cpu_psw_c
, arg1
, z
, cpu_psw_c
, z
);
1000 tcg_gen_add2_i32(cpu_psw_s
, cpu_psw_c
, cpu_psw_s
, cpu_psw_c
, arg2
, z
);
1001 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_s
);
1002 tcg_gen_xor_i32(cpu_psw_o
, cpu_psw_s
, arg1
);
1003 tcg_gen_xor_i32(z
, arg1
, arg2
);
1004 tcg_gen_andc_i32(cpu_psw_o
, cpu_psw_o
, z
);
1005 tcg_gen_mov_i32(ret
, cpu_psw_s
);
1010 static bool trans_ADC_ir(DisasContext
*ctx
, arg_ADC_ir
*a
)
1012 rx_gen_op_irr(rx_adc
, a
->rd
, a
->rd
, a
->imm
);
1017 static bool trans_ADC_rr(DisasContext
*ctx
, arg_ADC_rr
*a
)
1019 rx_gen_op_rrr(rx_adc
, a
->rd
, a
->rd
, a
->rs
);
1023 /* adc dsp[rs], rd */
1024 static bool trans_ADC_mr(DisasContext
*ctx
, arg_ADC_mr
*a
)
1030 rx_gen_op_mr(rx_adc
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1034 /* ret = arg1 + arg2 */
1035 static void rx_add(TCGv ret
, TCGv arg1
, TCGv arg2
)
1038 z
= tcg_const_i32(0);
1039 tcg_gen_add2_i32(cpu_psw_s
, cpu_psw_c
, arg1
, z
, arg2
, z
);
1040 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_s
);
1041 tcg_gen_xor_i32(cpu_psw_o
, cpu_psw_s
, arg1
);
1042 tcg_gen_xor_i32(z
, arg1
, arg2
);
1043 tcg_gen_andc_i32(cpu_psw_o
, cpu_psw_o
, z
);
1044 tcg_gen_mov_i32(ret
, cpu_psw_s
);
1048 /* add #uimm4, rd */
1049 /* add #imm, rs, rd */
1050 static bool trans_ADD_irr(DisasContext
*ctx
, arg_ADD_irr
*a
)
1052 rx_gen_op_irr(rx_add
, a
->rd
, a
->rs2
, a
->imm
);
1057 /* add dsp[rs], rd */
1058 static bool trans_ADD_mr(DisasContext
*ctx
, arg_ADD_mr
*a
)
1060 rx_gen_op_mr(rx_add
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1064 /* add rs, rs2, rd */
1065 static bool trans_ADD_rrr(DisasContext
*ctx
, arg_ADD_rrr
*a
)
1067 rx_gen_op_rrr(rx_add
, a
->rd
, a
->rs
, a
->rs2
);
1071 /* ret = arg1 - arg2 */
1072 static void rx_sub(TCGv ret
, TCGv arg1
, TCGv arg2
)
1075 tcg_gen_sub_i32(cpu_psw_s
, arg1
, arg2
);
1076 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_s
);
1077 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_psw_c
, arg1
, arg2
);
1078 tcg_gen_xor_i32(cpu_psw_o
, cpu_psw_s
, arg1
);
1079 temp
= tcg_temp_new_i32();
1080 tcg_gen_xor_i32(temp
, arg1
, arg2
);
1081 tcg_gen_and_i32(cpu_psw_o
, cpu_psw_o
, temp
);
1082 tcg_temp_free_i32(temp
);
1083 /* CMP not required return */
1085 tcg_gen_mov_i32(ret
, cpu_psw_s
);
1088 static void rx_cmp(TCGv dummy
, TCGv arg1
, TCGv arg2
)
1090 rx_sub(NULL
, arg1
, arg2
);
1092 /* ret = arg1 - arg2 - !psw_c */
1093 /* -> ret = arg1 + ~arg2 + psw_c */
1094 static void rx_sbb(TCGv ret
, TCGv arg1
, TCGv arg2
)
1097 temp
= tcg_temp_new();
1098 tcg_gen_not_i32(temp
, arg2
);
1099 rx_adc(ret
, arg1
, temp
);
1100 tcg_temp_free(temp
);
1103 /* cmp #imm4, rs2 */
1104 /* cmp #imm8, rs2 */
1106 static bool trans_CMP_ir(DisasContext
*ctx
, arg_CMP_ir
*a
)
1108 rx_gen_op_irr(rx_cmp
, 0, a
->rs2
, a
->imm
);
1113 /* cmp dsp[rs], rs2 */
1114 static bool trans_CMP_mr(DisasContext
*ctx
, arg_CMP_mr
*a
)
1116 rx_gen_op_mr(rx_cmp
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1121 static bool trans_SUB_ir(DisasContext
*ctx
, arg_SUB_ir
*a
)
1123 rx_gen_op_irr(rx_sub
, a
->rd
, a
->rd
, a
->imm
);
1128 /* sub dsp[rs], rd */
1129 static bool trans_SUB_mr(DisasContext
*ctx
, arg_SUB_mr
*a
)
1131 rx_gen_op_mr(rx_sub
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1135 /* sub rs2, rs, rd */
1136 static bool trans_SUB_rrr(DisasContext
*ctx
, arg_SUB_rrr
*a
)
1138 rx_gen_op_rrr(rx_sub
, a
->rd
, a
->rs2
, a
->rs
);
1143 static bool trans_SBB_rr(DisasContext
*ctx
, arg_SBB_rr
*a
)
1145 rx_gen_op_rrr(rx_sbb
, a
->rd
, a
->rd
, a
->rs
);
1149 /* sbb dsp[rs], rd */
1150 static bool trans_SBB_mr(DisasContext
*ctx
, arg_SBB_mr
*a
)
1156 rx_gen_op_mr(rx_sbb
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1160 static void rx_abs(TCGv ret
, TCGv arg1
)
1164 neg
= tcg_temp_new();
1165 zero
= tcg_const_i32(0);
1166 tcg_gen_neg_i32(neg
, arg1
);
1167 tcg_gen_movcond_i32(TCG_COND_LT
, ret
, arg1
, zero
, neg
, arg1
);
1169 tcg_temp_free(zero
);
1174 static bool trans_ABS_rr(DisasContext
*ctx
, arg_ABS_rr
*a
)
1176 rx_gen_op_rr(rx_abs
, a
->rd
, a
->rs
);
1181 static bool trans_MAX_ir(DisasContext
*ctx
, arg_MAX_ir
*a
)
1183 rx_gen_op_irr(tcg_gen_smax_i32
, a
->rd
, a
->rd
, a
->imm
);
1188 /* max dsp[rs], rd */
1189 static bool trans_MAX_mr(DisasContext
*ctx
, arg_MAX_mr
*a
)
1191 rx_gen_op_mr(tcg_gen_smax_i32
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1196 static bool trans_MIN_ir(DisasContext
*ctx
, arg_MIN_ir
*a
)
1198 rx_gen_op_irr(tcg_gen_smin_i32
, a
->rd
, a
->rd
, a
->imm
);
1203 /* min dsp[rs], rd */
1204 static bool trans_MIN_mr(DisasContext
*ctx
, arg_MIN_mr
*a
)
1206 rx_gen_op_mr(tcg_gen_smin_i32
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1210 /* mul #uimm4, rd */
1212 static bool trans_MUL_ir(DisasContext
*ctx
, arg_MUL_ir
*a
)
1214 rx_gen_op_irr(tcg_gen_mul_i32
, a
->rd
, a
->rd
, a
->imm
);
1219 /* mul dsp[rs], rd */
1220 static bool trans_MUL_mr(DisasContext
*ctx
, arg_MUL_mr
*a
)
1222 rx_gen_op_mr(tcg_gen_mul_i32
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1226 /* mul rs, rs2, rd */
1227 static bool trans_MUL_rrr(DisasContext
*ctx
, arg_MUL_rrr
*a
)
1229 rx_gen_op_rrr(tcg_gen_mul_i32
, a
->rd
, a
->rs
, a
->rs2
);
1234 static bool trans_EMUL_ir(DisasContext
*ctx
, arg_EMUL_ir
*a
)
1236 TCGv imm
= tcg_const_i32(a
->imm
);
1238 qemu_log_mask(LOG_GUEST_ERROR
, "rd too large %d", a
->rd
);
1240 tcg_gen_muls2_i32(cpu_regs
[a
->rd
], cpu_regs
[(a
->rd
+ 1) & 15],
1241 cpu_regs
[a
->rd
], imm
);
1247 /* emul dsp[rs], rd */
1248 static bool trans_EMUL_mr(DisasContext
*ctx
, arg_EMUL_mr
*a
)
1252 qemu_log_mask(LOG_GUEST_ERROR
, "rd too large %d", a
->rd
);
1254 mem
= tcg_temp_new();
1255 val
= rx_load_source(ctx
, mem
, a
->ld
, a
->mi
, a
->rs
);
1256 tcg_gen_muls2_i32(cpu_regs
[a
->rd
], cpu_regs
[(a
->rd
+ 1) & 15],
1257 cpu_regs
[a
->rd
], val
);
1262 /* emulu #imm, rd */
1263 static bool trans_EMULU_ir(DisasContext
*ctx
, arg_EMULU_ir
*a
)
1265 TCGv imm
= tcg_const_i32(a
->imm
);
1267 qemu_log_mask(LOG_GUEST_ERROR
, "rd too large %d", a
->rd
);
1269 tcg_gen_mulu2_i32(cpu_regs
[a
->rd
], cpu_regs
[(a
->rd
+ 1) & 15],
1270 cpu_regs
[a
->rd
], imm
);
1276 /* emulu dsp[rs], rd */
1277 static bool trans_EMULU_mr(DisasContext
*ctx
, arg_EMULU_mr
*a
)
1281 qemu_log_mask(LOG_GUEST_ERROR
, "rd too large %d", a
->rd
);
1283 mem
= tcg_temp_new();
1284 val
= rx_load_source(ctx
, mem
, a
->ld
, a
->mi
, a
->rs
);
1285 tcg_gen_mulu2_i32(cpu_regs
[a
->rd
], cpu_regs
[(a
->rd
+ 1) & 15],
1286 cpu_regs
[a
->rd
], val
);
1291 static void rx_div(TCGv ret
, TCGv arg1
, TCGv arg2
)
1293 gen_helper_div(ret
, cpu_env
, arg1
, arg2
);
1296 static void rx_divu(TCGv ret
, TCGv arg1
, TCGv arg2
)
1298 gen_helper_divu(ret
, cpu_env
, arg1
, arg2
);
1302 static bool trans_DIV_ir(DisasContext
*ctx
, arg_DIV_ir
*a
)
1304 rx_gen_op_irr(rx_div
, a
->rd
, a
->rd
, a
->imm
);
1309 /* div dsp[rs], rd */
1310 static bool trans_DIV_mr(DisasContext
*ctx
, arg_DIV_mr
*a
)
1312 rx_gen_op_mr(rx_div
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1317 static bool trans_DIVU_ir(DisasContext
*ctx
, arg_DIVU_ir
*a
)
1319 rx_gen_op_irr(rx_divu
, a
->rd
, a
->rd
, a
->imm
);
1324 /* divu dsp[rs], rd */
1325 static bool trans_DIVU_mr(DisasContext
*ctx
, arg_DIVU_mr
*a
)
1327 rx_gen_op_mr(rx_divu
, ctx
, a
->rd
, a
->rs
, a
->ld
, a
->mi
);
1332 /* shll #imm:5, rd */
1333 /* shll #imm:5, rs2, rd */
1334 static bool trans_SHLL_irr(DisasContext
*ctx
, arg_SHLL_irr
*a
)
1337 tmp
= tcg_temp_new();
1339 tcg_gen_sari_i32(cpu_psw_c
, cpu_regs
[a
->rs2
], 32 - a
->imm
);
1340 tcg_gen_shli_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rs2
], a
->imm
);
1341 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_psw_o
, cpu_psw_c
, 0);
1342 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_psw_c
, 0xffffffff);
1343 tcg_gen_or_i32(cpu_psw_o
, cpu_psw_o
, tmp
);
1344 tcg_gen_setcondi_i32(TCG_COND_NE
, cpu_psw_c
, cpu_psw_c
, 0);
1346 tcg_gen_mov_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rs2
]);
1347 tcg_gen_movi_i32(cpu_psw_c
, 0);
1348 tcg_gen_movi_i32(cpu_psw_o
, 0);
1350 tcg_gen_mov_i32(cpu_psw_z
, cpu_regs
[a
->rd
]);
1351 tcg_gen_mov_i32(cpu_psw_s
, cpu_regs
[a
->rd
]);
1356 static bool trans_SHLL_rr(DisasContext
*ctx
, arg_SHLL_rr
*a
)
1358 TCGLabel
*noshift
, *done
;
1361 noshift
= gen_new_label();
1362 done
= gen_new_label();
1363 /* if (cpu_regs[a->rs]) { */
1364 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_regs
[a
->rs
], 0, noshift
);
1365 count
= tcg_const_i32(32);
1366 tmp
= tcg_temp_new();
1367 tcg_gen_andi_i32(tmp
, cpu_regs
[a
->rs
], 31);
1368 tcg_gen_sub_i32(count
, count
, tmp
);
1369 tcg_gen_sar_i32(cpu_psw_c
, cpu_regs
[a
->rd
], count
);
1370 tcg_gen_shl_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], tmp
);
1371 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_psw_o
, cpu_psw_c
, 0);
1372 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_psw_c
, 0xffffffff);
1373 tcg_gen_or_i32(cpu_psw_o
, cpu_psw_o
, tmp
);
1374 tcg_gen_setcondi_i32(TCG_COND_NE
, cpu_psw_c
, cpu_psw_c
, 0);
1377 gen_set_label(noshift
);
1378 tcg_gen_movi_i32(cpu_psw_c
, 0);
1379 tcg_gen_movi_i32(cpu_psw_o
, 0);
1381 gen_set_label(done
);
1382 tcg_gen_mov_i32(cpu_psw_z
, cpu_regs
[a
->rd
]);
1383 tcg_gen_mov_i32(cpu_psw_s
, cpu_regs
[a
->rd
]);
1384 tcg_temp_free(count
);
1389 static inline void shiftr_imm(uint32_t rd
, uint32_t rs
, uint32_t imm
,
1392 static void (* const gen_sXri
[])(TCGv ret
, TCGv arg1
, int arg2
) = {
1393 tcg_gen_shri_i32
, tcg_gen_sari_i32
,
1395 tcg_debug_assert(alith
< 2);
1397 gen_sXri
[alith
](cpu_regs
[rd
], cpu_regs
[rs
], imm
- 1);
1398 tcg_gen_andi_i32(cpu_psw_c
, cpu_regs
[rd
], 0x00000001);
1399 gen_sXri
[alith
](cpu_regs
[rd
], cpu_regs
[rd
], 1);
1401 tcg_gen_mov_i32(cpu_regs
[rd
], cpu_regs
[rs
]);
1402 tcg_gen_movi_i32(cpu_psw_c
, 0);
1404 tcg_gen_movi_i32(cpu_psw_o
, 0);
1405 tcg_gen_mov_i32(cpu_psw_z
, cpu_regs
[rd
]);
1406 tcg_gen_mov_i32(cpu_psw_s
, cpu_regs
[rd
]);
1409 static inline void shiftr_reg(uint32_t rd
, uint32_t rs
, unsigned int alith
)
1411 TCGLabel
*noshift
, *done
;
1413 static void (* const gen_sXri
[])(TCGv ret
, TCGv arg1
, int arg2
) = {
1414 tcg_gen_shri_i32
, tcg_gen_sari_i32
,
1416 static void (* const gen_sXr
[])(TCGv ret
, TCGv arg1
, TCGv arg2
) = {
1417 tcg_gen_shr_i32
, tcg_gen_sar_i32
,
1419 tcg_debug_assert(alith
< 2);
1420 noshift
= gen_new_label();
1421 done
= gen_new_label();
1422 count
= tcg_temp_new();
1423 /* if (cpu_regs[rs]) { */
1424 tcg_gen_brcondi_i32(TCG_COND_EQ
, cpu_regs
[rs
], 0, noshift
);
1425 tcg_gen_andi_i32(count
, cpu_regs
[rs
], 31);
1426 tcg_gen_subi_i32(count
, count
, 1);
1427 gen_sXr
[alith
](cpu_regs
[rd
], cpu_regs
[rd
], count
);
1428 tcg_gen_andi_i32(cpu_psw_c
, cpu_regs
[rd
], 0x00000001);
1429 gen_sXri
[alith
](cpu_regs
[rd
], cpu_regs
[rd
], 1);
1432 gen_set_label(noshift
);
1433 tcg_gen_movi_i32(cpu_psw_c
, 0);
1435 gen_set_label(done
);
1436 tcg_gen_movi_i32(cpu_psw_o
, 0);
1437 tcg_gen_mov_i32(cpu_psw_z
, cpu_regs
[rd
]);
1438 tcg_gen_mov_i32(cpu_psw_s
, cpu_regs
[rd
]);
1439 tcg_temp_free(count
);
1442 /* shar #imm:5, rd */
1443 /* shar #imm:5, rs2, rd */
1444 static bool trans_SHAR_irr(DisasContext
*ctx
, arg_SHAR_irr
*a
)
1446 shiftr_imm(a
->rd
, a
->rs2
, a
->imm
, 1);
1451 static bool trans_SHAR_rr(DisasContext
*ctx
, arg_SHAR_rr
*a
)
1453 shiftr_reg(a
->rd
, a
->rs
, 1);
1457 /* shlr #imm:5, rd */
1458 /* shlr #imm:5, rs2, rd */
1459 static bool trans_SHLR_irr(DisasContext
*ctx
, arg_SHLR_irr
*a
)
1461 shiftr_imm(a
->rd
, a
->rs2
, a
->imm
, 0);
1466 static bool trans_SHLR_rr(DisasContext
*ctx
, arg_SHLR_rr
*a
)
1468 shiftr_reg(a
->rd
, a
->rs
, 0);
1473 static bool trans_ROLC(DisasContext
*ctx
, arg_ROLC
*a
)
1476 tmp
= tcg_temp_new();
1477 tcg_gen_shri_i32(tmp
, cpu_regs
[a
->rd
], 31);
1478 tcg_gen_shli_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 1);
1479 tcg_gen_or_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], cpu_psw_c
);
1480 tcg_gen_mov_i32(cpu_psw_c
, tmp
);
1481 tcg_gen_mov_i32(cpu_psw_z
, cpu_regs
[a
->rd
]);
1482 tcg_gen_mov_i32(cpu_psw_s
, cpu_regs
[a
->rd
]);
1488 static bool trans_RORC(DisasContext
*ctx
, arg_RORC
*a
)
1491 tmp
= tcg_temp_new();
1492 tcg_gen_andi_i32(tmp
, cpu_regs
[a
->rd
], 0x00000001);
1493 tcg_gen_shri_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 1);
1494 tcg_gen_shli_i32(cpu_psw_c
, cpu_psw_c
, 31);
1495 tcg_gen_or_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], cpu_psw_c
);
1496 tcg_gen_mov_i32(cpu_psw_c
, tmp
);
1497 tcg_gen_mov_i32(cpu_psw_z
, cpu_regs
[a
->rd
]);
1498 tcg_gen_mov_i32(cpu_psw_s
, cpu_regs
[a
->rd
]);
1502 enum {ROTR
= 0, ROTL
= 1};
1503 enum {ROT_IMM
= 0, ROT_REG
= 1};
1504 static inline void rx_rot(int ir
, int dir
, int rd
, int src
)
1508 if (ir
== ROT_IMM
) {
1509 tcg_gen_rotli_i32(cpu_regs
[rd
], cpu_regs
[rd
], src
);
1511 tcg_gen_rotl_i32(cpu_regs
[rd
], cpu_regs
[rd
], cpu_regs
[src
]);
1513 tcg_gen_andi_i32(cpu_psw_c
, cpu_regs
[rd
], 0x00000001);
1516 if (ir
== ROT_IMM
) {
1517 tcg_gen_rotri_i32(cpu_regs
[rd
], cpu_regs
[rd
], src
);
1519 tcg_gen_rotr_i32(cpu_regs
[rd
], cpu_regs
[rd
], cpu_regs
[src
]);
1521 tcg_gen_shri_i32(cpu_psw_c
, cpu_regs
[rd
], 31);
1524 tcg_gen_mov_i32(cpu_psw_z
, cpu_regs
[rd
]);
1525 tcg_gen_mov_i32(cpu_psw_s
, cpu_regs
[rd
]);
1529 static bool trans_ROTL_ir(DisasContext
*ctx
, arg_ROTL_ir
*a
)
1531 rx_rot(ROT_IMM
, ROTL
, a
->rd
, a
->imm
);
1536 static bool trans_ROTL_rr(DisasContext
*ctx
, arg_ROTL_rr
*a
)
1538 rx_rot(ROT_REG
, ROTL
, a
->rd
, a
->rs
);
1543 static bool trans_ROTR_ir(DisasContext
*ctx
, arg_ROTR_ir
*a
)
1545 rx_rot(ROT_IMM
, ROTR
, a
->rd
, a
->imm
);
1550 static bool trans_ROTR_rr(DisasContext
*ctx
, arg_ROTR_rr
*a
)
1552 rx_rot(ROT_REG
, ROTR
, a
->rd
, a
->rs
);
1557 static bool trans_REVL(DisasContext
*ctx
, arg_REVL
*a
)
1559 tcg_gen_bswap32_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rs
]);
1564 static bool trans_REVW(DisasContext
*ctx
, arg_REVW
*a
)
1567 tmp
= tcg_temp_new();
1568 tcg_gen_andi_i32(tmp
, cpu_regs
[a
->rs
], 0x00ff00ff);
1569 tcg_gen_shli_i32(tmp
, tmp
, 8);
1570 tcg_gen_shri_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rs
], 8);
1571 tcg_gen_andi_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], 0x00ff00ff);
1572 tcg_gen_or_i32(cpu_regs
[a
->rd
], cpu_regs
[a
->rd
], tmp
);
1577 /* conditional branch helper */
1578 static void rx_bcnd_main(DisasContext
*ctx
, int cd
, int dst
)
1585 dc
.temp
= tcg_temp_new();
1587 t
= gen_new_label();
1588 done
= gen_new_label();
1589 tcg_gen_brcondi_i32(dc
.cond
, dc
.value
, 0, t
);
1590 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
1593 gen_goto_tb(ctx
, 1, ctx
->pc
+ dst
);
1594 gen_set_label(done
);
1595 tcg_temp_free(dc
.temp
);
1598 /* always true case */
1599 gen_goto_tb(ctx
, 0, ctx
->pc
+ dst
);
1602 /* always false case */
1608 /* beq dsp:3 / bne dsp:3 */
1609 /* beq dsp:8 / bne dsp:8 */
1610 /* bc dsp:8 / bnc dsp:8 */
1611 /* bgtu dsp:8 / bleu dsp:8 */
1612 /* bpz dsp:8 / bn dsp:8 */
1613 /* bge dsp:8 / blt dsp:8 */
1614 /* bgt dsp:8 / ble dsp:8 */
1615 /* bo dsp:8 / bno dsp:8 */
1616 /* beq dsp:16 / bne dsp:16 */
1617 static bool trans_BCnd(DisasContext
*ctx
, arg_BCnd
*a
)
1619 rx_bcnd_main(ctx
, a
->cd
, a
->dsp
);
1627 static bool trans_BRA(DisasContext
*ctx
, arg_BRA
*a
)
1629 rx_bcnd_main(ctx
, 14, a
->dsp
);
1634 static bool trans_BRA_l(DisasContext
*ctx
, arg_BRA_l
*a
)
1636 tcg_gen_addi_i32(cpu_pc
, cpu_regs
[a
->rd
], ctx
->pc
);
1637 ctx
->base
.is_jmp
= DISAS_JUMP
;
1641 static inline void rx_save_pc(DisasContext
*ctx
)
1643 TCGv pc
= tcg_const_i32(ctx
->base
.pc_next
);
1649 static bool trans_JMP(DisasContext
*ctx
, arg_JMP
*a
)
1651 tcg_gen_mov_i32(cpu_pc
, cpu_regs
[a
->rs
]);
1652 ctx
->base
.is_jmp
= DISAS_JUMP
;
1657 static bool trans_JSR(DisasContext
*ctx
, arg_JSR
*a
)
1660 tcg_gen_mov_i32(cpu_pc
, cpu_regs
[a
->rs
]);
1661 ctx
->base
.is_jmp
= DISAS_JUMP
;
1667 static bool trans_BSR(DisasContext
*ctx
, arg_BSR
*a
)
1670 rx_bcnd_main(ctx
, 14, a
->dsp
);
1675 static bool trans_BSR_l(DisasContext
*ctx
, arg_BSR_l
*a
)
1678 tcg_gen_addi_i32(cpu_pc
, cpu_regs
[a
->rd
], ctx
->pc
);
1679 ctx
->base
.is_jmp
= DISAS_JUMP
;
1684 static bool trans_RTS(DisasContext
*ctx
, arg_RTS
*a
)
1687 ctx
->base
.is_jmp
= DISAS_JUMP
;
1692 static bool trans_NOP(DisasContext
*ctx
, arg_NOP
*a
)
1698 static bool trans_SCMPU(DisasContext
*ctx
, arg_SCMPU
*a
)
1700 gen_helper_scmpu(cpu_env
);
1705 static bool trans_SMOVU(DisasContext
*ctx
, arg_SMOVU
*a
)
1707 gen_helper_smovu(cpu_env
);
1712 static bool trans_SMOVF(DisasContext
*ctx
, arg_SMOVF
*a
)
1714 gen_helper_smovf(cpu_env
);
1719 static bool trans_SMOVB(DisasContext
*ctx
, arg_SMOVB
*a
)
1721 gen_helper_smovb(cpu_env
);
1725 #define STRING(op) \
1727 TCGv size = tcg_const_i32(a->sz); \
1728 gen_helper_##op(cpu_env, size); \
1729 tcg_temp_free(size); \
1733 static bool trans_SUNTIL(DisasContext
*ctx
, arg_SUNTIL
*a
)
1740 static bool trans_SWHILE(DisasContext
*ctx
, arg_SWHILE
*a
)
1746 static bool trans_SSTR(DisasContext
*ctx
, arg_SSTR
*a
)
1753 static bool trans_RMPA(DisasContext
*ctx
, arg_RMPA
*a
)
1759 static void rx_mul64hi(TCGv_i64 ret
, int rs
, int rs2
)
1761 TCGv_i64 tmp0
, tmp1
;
1762 tmp0
= tcg_temp_new_i64();
1763 tmp1
= tcg_temp_new_i64();
1764 tcg_gen_ext_i32_i64(tmp0
, cpu_regs
[rs
]);
1765 tcg_gen_sari_i64(tmp0
, tmp0
, 16);
1766 tcg_gen_ext_i32_i64(tmp1
, cpu_regs
[rs2
]);
1767 tcg_gen_sari_i64(tmp1
, tmp1
, 16);
1768 tcg_gen_mul_i64(ret
, tmp0
, tmp1
);
1769 tcg_gen_shli_i64(ret
, ret
, 16);
1770 tcg_temp_free_i64(tmp0
);
1771 tcg_temp_free_i64(tmp1
);
1774 static void rx_mul64lo(TCGv_i64 ret
, int rs
, int rs2
)
1776 TCGv_i64 tmp0
, tmp1
;
1777 tmp0
= tcg_temp_new_i64();
1778 tmp1
= tcg_temp_new_i64();
1779 tcg_gen_ext_i32_i64(tmp0
, cpu_regs
[rs
]);
1780 tcg_gen_ext16s_i64(tmp0
, tmp0
);
1781 tcg_gen_ext_i32_i64(tmp1
, cpu_regs
[rs2
]);
1782 tcg_gen_ext16s_i64(tmp1
, tmp1
);
1783 tcg_gen_mul_i64(ret
, tmp0
, tmp1
);
1784 tcg_gen_shli_i64(ret
, ret
, 16);
1785 tcg_temp_free_i64(tmp0
);
1786 tcg_temp_free_i64(tmp1
);
1790 static bool trans_MULHI(DisasContext
*ctx
, arg_MULHI
*a
)
1792 rx_mul64hi(cpu_acc
, a
->rs
, a
->rs2
);
1797 static bool trans_MULLO(DisasContext
*ctx
, arg_MULLO
*a
)
1799 rx_mul64lo(cpu_acc
, a
->rs
, a
->rs2
);
1804 static bool trans_MACHI(DisasContext
*ctx
, arg_MACHI
*a
)
1807 tmp
= tcg_temp_new_i64();
1808 rx_mul64hi(tmp
, a
->rs
, a
->rs2
);
1809 tcg_gen_add_i64(cpu_acc
, cpu_acc
, tmp
);
1810 tcg_temp_free_i64(tmp
);
1815 static bool trans_MACLO(DisasContext
*ctx
, arg_MACLO
*a
)
1818 tmp
= tcg_temp_new_i64();
1819 rx_mul64lo(tmp
, a
->rs
, a
->rs2
);
1820 tcg_gen_add_i64(cpu_acc
, cpu_acc
, tmp
);
1821 tcg_temp_free_i64(tmp
);
1826 static bool trans_MVFACHI(DisasContext
*ctx
, arg_MVFACHI
*a
)
1828 tcg_gen_extrh_i64_i32(cpu_regs
[a
->rd
], cpu_acc
);
1833 static bool trans_MVFACMI(DisasContext
*ctx
, arg_MVFACMI
*a
)
1836 rd64
= tcg_temp_new_i64();
1837 tcg_gen_extract_i64(rd64
, cpu_acc
, 16, 32);
1838 tcg_gen_extrl_i64_i32(cpu_regs
[a
->rd
], rd64
);
1839 tcg_temp_free_i64(rd64
);
1844 static bool trans_MVTACHI(DisasContext
*ctx
, arg_MVTACHI
*a
)
1847 rs64
= tcg_temp_new_i64();
1848 tcg_gen_extu_i32_i64(rs64
, cpu_regs
[a
->rs
]);
1849 tcg_gen_deposit_i64(cpu_acc
, cpu_acc
, rs64
, 32, 32);
1850 tcg_temp_free_i64(rs64
);
1855 static bool trans_MVTACLO(DisasContext
*ctx
, arg_MVTACLO
*a
)
1858 rs64
= tcg_temp_new_i64();
1859 tcg_gen_extu_i32_i64(rs64
, cpu_regs
[a
->rs
]);
1860 tcg_gen_deposit_i64(cpu_acc
, cpu_acc
, rs64
, 0, 32);
1861 tcg_temp_free_i64(rs64
);
1866 static bool trans_RACW(DisasContext
*ctx
, arg_RACW
*a
)
1868 TCGv imm
= tcg_const_i32(a
->imm
+ 1);
1869 gen_helper_racw(cpu_env
, imm
);
1875 static bool trans_SAT(DisasContext
*ctx
, arg_SAT
*a
)
1878 tmp
= tcg_temp_new();
1879 z
= tcg_const_i32(0);
1880 /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
1881 tcg_gen_sari_i32(tmp
, cpu_psw_s
, 31);
1882 /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
1883 tcg_gen_xori_i32(tmp
, tmp
, 0x80000000);
1884 tcg_gen_movcond_i32(TCG_COND_LT
, cpu_regs
[a
->rd
],
1885 cpu_psw_o
, z
, tmp
, cpu_regs
[a
->rd
]);
1892 static bool trans_SATR(DisasContext
*ctx
, arg_SATR
*a
)
1894 gen_helper_satr(cpu_env
);
1898 #define cat3(a, b, c) a##b##c
1899 #define FOP(name, op) \
1900 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
1901 cat3(arg_, name, _ir) * a) \
1903 TCGv imm = tcg_const_i32(li(ctx, 0)); \
1904 gen_helper_##op(cpu_regs[a->rd], cpu_env, \
1905 cpu_regs[a->rd], imm); \
1906 tcg_temp_free(imm); \
1909 static bool cat3(trans_, name, _mr)(DisasContext *ctx, \
1910 cat3(arg_, name, _mr) * a) \
1913 mem = tcg_temp_new(); \
1914 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1915 gen_helper_##op(cpu_regs[a->rd], cpu_env, \
1916 cpu_regs[a->rd], val); \
1917 tcg_temp_free(mem); \
1921 #define FCONVOP(name, op) \
1922 static bool trans_##name(DisasContext *ctx, arg_##name * a) \
1925 mem = tcg_temp_new(); \
1926 val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
1927 gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \
1928 tcg_temp_free(mem); \
1938 static bool trans_FCMP_ir(DisasContext
*ctx
, arg_FCMP_ir
* a
)
1940 TCGv imm
= tcg_const_i32(li(ctx
, 0));
1941 gen_helper_fcmp(cpu_env
, cpu_regs
[a
->rd
], imm
);
1946 /* fcmp dsp[rs], rd */
1948 static bool trans_FCMP_mr(DisasContext
*ctx
, arg_FCMP_mr
*a
)
1951 mem
= tcg_temp_new();
1952 val
= rx_load_source(ctx
, mem
, a
->ld
, MO_32
, a
->rs
);
1953 gen_helper_fcmp(cpu_env
, cpu_regs
[a
->rd
], val
);
1959 FCONVOP(ROUND
, round
)
1962 /* itof dsp[rs], rd */
1963 static bool trans_ITOF(DisasContext
*ctx
, arg_ITOF
* a
)
1966 mem
= tcg_temp_new();
1967 val
= rx_load_source(ctx
, mem
, a
->ld
, a
->mi
, a
->rs
);
1968 gen_helper_itof(cpu_regs
[a
->rd
], cpu_env
, val
);
1973 static void rx_bsetm(TCGv mem
, TCGv mask
)
1976 val
= tcg_temp_new();
1977 rx_gen_ld(MO_8
, val
, mem
);
1978 tcg_gen_or_i32(val
, val
, mask
);
1979 rx_gen_st(MO_8
, val
, mem
);
1983 static void rx_bclrm(TCGv mem
, TCGv mask
)
1986 val
= tcg_temp_new();
1987 rx_gen_ld(MO_8
, val
, mem
);
1988 tcg_gen_andc_i32(val
, val
, mask
);
1989 rx_gen_st(MO_8
, val
, mem
);
1993 static void rx_btstm(TCGv mem
, TCGv mask
)
1996 val
= tcg_temp_new();
1997 rx_gen_ld(MO_8
, val
, mem
);
1998 tcg_gen_and_i32(val
, val
, mask
);
1999 tcg_gen_setcondi_i32(TCG_COND_NE
, cpu_psw_c
, val
, 0);
2000 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_c
);
2004 static void rx_bnotm(TCGv mem
, TCGv mask
)
2007 val
= tcg_temp_new();
2008 rx_gen_ld(MO_8
, val
, mem
);
2009 tcg_gen_xor_i32(val
, val
, mask
);
2010 rx_gen_st(MO_8
, val
, mem
);
2014 static void rx_bsetr(TCGv reg
, TCGv mask
)
2016 tcg_gen_or_i32(reg
, reg
, mask
);
2019 static void rx_bclrr(TCGv reg
, TCGv mask
)
2021 tcg_gen_andc_i32(reg
, reg
, mask
);
2024 static inline void rx_btstr(TCGv reg
, TCGv mask
)
2027 t0
= tcg_temp_new();
2028 tcg_gen_and_i32(t0
, reg
, mask
);
2029 tcg_gen_setcondi_i32(TCG_COND_NE
, cpu_psw_c
, t0
, 0);
2030 tcg_gen_mov_i32(cpu_psw_z
, cpu_psw_c
);
2034 static inline void rx_bnotr(TCGv reg
, TCGv mask
)
2036 tcg_gen_xor_i32(reg
, reg
, mask
);
2039 #define BITOP(name, op) \
2040 static bool cat3(trans_, name, _im)(DisasContext *ctx, \
2041 cat3(arg_, name, _im) * a) \
2043 TCGv mask, mem, addr; \
2044 mem = tcg_temp_new(); \
2045 mask = tcg_const_i32(1 << a->imm); \
2046 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
2047 cat3(rx_, op, m)(addr, mask); \
2048 tcg_temp_free(mask); \
2049 tcg_temp_free(mem); \
2052 static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
2053 cat3(arg_, name, _ir) * a) \
2056 mask = tcg_const_i32(1 << a->imm); \
2057 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
2058 tcg_temp_free(mask); \
2061 static bool cat3(trans_, name, _rr)(DisasContext *ctx, \
2062 cat3(arg_, name, _rr) * a) \
2065 mask = tcg_const_i32(1); \
2066 b = tcg_temp_new(); \
2067 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
2068 tcg_gen_shl_i32(mask, mask, b); \
2069 cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
2070 tcg_temp_free(mask); \
2074 static bool cat3(trans_, name, _rm)(DisasContext *ctx, \
2075 cat3(arg_, name, _rm) * a) \
2077 TCGv mask, mem, addr, b; \
2078 mask = tcg_const_i32(1); \
2079 b = tcg_temp_new(); \
2080 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
2081 tcg_gen_shl_i32(mask, mask, b); \
2082 mem = tcg_temp_new(); \
2083 addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
2084 cat3(rx_, op, m)(addr, mask); \
2085 tcg_temp_free(mem); \
2086 tcg_temp_free(mask); \
2096 static inline void bmcnd_op(TCGv val
, TCGCond cond
, int pos
)
2100 dc
.temp
= tcg_temp_new();
2101 bit
= tcg_temp_new();
2102 psw_cond(&dc
, cond
);
2103 tcg_gen_andi_i32(val
, val
, ~(1 << pos
));
2104 tcg_gen_setcondi_i32(dc
.cond
, bit
, dc
.value
, 0);
2105 tcg_gen_deposit_i32(val
, val
, bit
, pos
, 1);
2107 tcg_temp_free(dc
.temp
);
2110 /* bmcnd #imm, dsp[rd] */
2111 static bool trans_BMCnd_im(DisasContext
*ctx
, arg_BMCnd_im
*a
)
2113 TCGv val
, mem
, addr
;
2114 val
= tcg_temp_new();
2115 mem
= tcg_temp_new();
2116 addr
= rx_index_addr(ctx
, mem
, a
->ld
, MO_8
, a
->rd
);
2117 rx_gen_ld(MO_8
, val
, addr
);
2118 bmcnd_op(val
, a
->cd
, a
->imm
);
2119 rx_gen_st(MO_8
, val
, addr
);
2125 /* bmcond #imm, rd */
2126 static bool trans_BMCnd_ir(DisasContext
*ctx
, arg_BMCnd_ir
*a
)
2128 bmcnd_op(cpu_regs
[a
->rd
], a
->cd
, a
->imm
);
2141 static inline void clrsetpsw(DisasContext
*ctx
, int cb
, int val
)
2146 tcg_gen_movi_i32(cpu_psw_c
, val
);
2149 tcg_gen_movi_i32(cpu_psw_z
, val
== 0);
2152 tcg_gen_movi_i32(cpu_psw_s
, val
? -1 : 0);
2155 tcg_gen_movi_i32(cpu_psw_o
, val
<< 31);
2158 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid distination %d", cb
);
2161 } else if (is_privileged(ctx
, 0)) {
2164 tcg_gen_movi_i32(cpu_psw_i
, val
);
2165 ctx
->base
.is_jmp
= DISAS_UPDATE
;
2168 if (FIELD_EX32(ctx
->tb_flags
, PSW
, U
) != val
) {
2169 ctx
->tb_flags
= FIELD_DP32(ctx
->tb_flags
, PSW
, U
, val
);
2170 tcg_gen_movi_i32(cpu_psw_u
, val
);
2171 tcg_gen_mov_i32(val
? cpu_isp
: cpu_usp
, cpu_sp
);
2172 tcg_gen_mov_i32(cpu_sp
, val
? cpu_usp
: cpu_isp
);
2176 qemu_log_mask(LOG_GUEST_ERROR
, "Invalid distination %d", cb
);
2183 static bool trans_CLRPSW(DisasContext
*ctx
, arg_CLRPSW
*a
)
2185 clrsetpsw(ctx
, a
->cb
, 0);
2190 static bool trans_SETPSW(DisasContext
*ctx
, arg_SETPSW
*a
)
2192 clrsetpsw(ctx
, a
->cb
, 1);
2197 static bool trans_MVTIPL(DisasContext
*ctx
, arg_MVTIPL
*a
)
2199 if (is_privileged(ctx
, 1)) {
2200 tcg_gen_movi_i32(cpu_psw_ipl
, a
->imm
);
2201 ctx
->base
.is_jmp
= DISAS_UPDATE
;
2207 static bool trans_MVTC_i(DisasContext
*ctx
, arg_MVTC_i
*a
)
2211 imm
= tcg_const_i32(a
->imm
);
2212 move_to_cr(ctx
, imm
, a
->cr
);
2218 static bool trans_MVTC_r(DisasContext
*ctx
, arg_MVTC_r
*a
)
2220 move_to_cr(ctx
, cpu_regs
[a
->rs
], a
->cr
);
2225 static bool trans_MVFC(DisasContext
*ctx
, arg_MVFC
*a
)
2227 move_from_cr(ctx
, cpu_regs
[a
->rd
], a
->cr
, ctx
->pc
);
2232 static bool trans_RTFI(DisasContext
*ctx
, arg_RTFI
*a
)
2235 if (is_privileged(ctx
, 1)) {
2236 psw
= tcg_temp_new();
2237 tcg_gen_mov_i32(cpu_pc
, cpu_bpc
);
2238 tcg_gen_mov_i32(psw
, cpu_bpsw
);
2239 gen_helper_set_psw_rte(cpu_env
, psw
);
2240 ctx
->base
.is_jmp
= DISAS_EXIT
;
2247 static bool trans_RTE(DisasContext
*ctx
, arg_RTE
*a
)
2250 if (is_privileged(ctx
, 1)) {
2251 psw
= tcg_temp_new();
2254 gen_helper_set_psw_rte(cpu_env
, psw
);
2255 ctx
->base
.is_jmp
= DISAS_EXIT
;
2262 static bool trans_BRK(DisasContext
*ctx
, arg_BRK
*a
)
2264 tcg_gen_movi_i32(cpu_pc
, ctx
->base
.pc_next
);
2265 gen_helper_rxbrk(cpu_env
);
2266 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2271 static bool trans_INT(DisasContext
*ctx
, arg_INT
*a
)
2275 tcg_debug_assert(a
->imm
< 0x100);
2276 vec
= tcg_const_i32(a
->imm
);
2277 tcg_gen_movi_i32(cpu_pc
, ctx
->base
.pc_next
);
2278 gen_helper_rxint(cpu_env
, vec
);
2280 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2285 static bool trans_WAIT(DisasContext
*ctx
, arg_WAIT
*a
)
2287 if (is_privileged(ctx
, 1)) {
2288 tcg_gen_movi_i32(cpu_pc
, ctx
->base
.pc_next
);
2289 gen_helper_wait(cpu_env
);
2294 static void rx_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
2296 CPURXState
*env
= cs
->env_ptr
;
2297 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
2299 ctx
->tb_flags
= ctx
->base
.tb
->flags
;
2302 static void rx_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cs
)
2306 static void rx_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
2308 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
2310 tcg_gen_insn_start(ctx
->base
.pc_next
);
2313 static void rx_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
2315 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
2318 ctx
->pc
= ctx
->base
.pc_next
;
2319 insn
= decode_load(ctx
);
2320 if (!decode(ctx
, insn
)) {
2321 gen_helper_raise_illegal_instruction(cpu_env
);
2325 static void rx_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
2327 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
2329 switch (ctx
->base
.is_jmp
) {
2331 case DISAS_TOO_MANY
:
2332 gen_goto_tb(ctx
, 0, dcbase
->pc_next
);
2335 tcg_gen_lookup_and_goto_ptr();
2338 tcg_gen_movi_i32(cpu_pc
, ctx
->base
.pc_next
);
2341 tcg_gen_exit_tb(NULL
, 0);
2343 case DISAS_NORETURN
:
2346 g_assert_not_reached();
2350 static void rx_tr_disas_log(const DisasContextBase
*dcbase
,
2351 CPUState
*cs
, FILE *logfile
)
2353 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
2354 target_disas(logfile
, cs
, dcbase
->pc_first
, dcbase
->tb
->size
);
2357 static const TranslatorOps rx_tr_ops
= {
2358 .init_disas_context
= rx_tr_init_disas_context
,
2359 .tb_start
= rx_tr_tb_start
,
2360 .insn_start
= rx_tr_insn_start
,
2361 .translate_insn
= rx_tr_translate_insn
,
2362 .tb_stop
= rx_tr_tb_stop
,
2363 .disas_log
= rx_tr_disas_log
,
2366 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
2370 translator_loop(&rx_tr_ops
, &dc
.base
, cs
, tb
, max_insns
);
2373 void restore_state_to_opc(CPURXState
*env
, TranslationBlock
*tb
,
2379 #define ALLOC_REGISTER(sym, name) \
2380 cpu_##sym = tcg_global_mem_new_i32(cpu_env, \
2381 offsetof(CPURXState, sym), name)
2383 void rx_translate_init(void)
2385 static const char * const regnames
[NUM_REGS
] = {
2386 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
2387 "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"
2391 for (i
= 0; i
< NUM_REGS
; i
++) {
2392 cpu_regs
[i
] = tcg_global_mem_new_i32(cpu_env
,
2393 offsetof(CPURXState
, regs
[i
]),
2396 ALLOC_REGISTER(pc
, "PC");
2397 ALLOC_REGISTER(psw_o
, "PSW(O)");
2398 ALLOC_REGISTER(psw_s
, "PSW(S)");
2399 ALLOC_REGISTER(psw_z
, "PSW(Z)");
2400 ALLOC_REGISTER(psw_c
, "PSW(C)");
2401 ALLOC_REGISTER(psw_u
, "PSW(U)");
2402 ALLOC_REGISTER(psw_i
, "PSW(I)");
2403 ALLOC_REGISTER(psw_pm
, "PSW(PM)");
2404 ALLOC_REGISTER(psw_ipl
, "PSW(IPL)");
2405 ALLOC_REGISTER(usp
, "USP");
2406 ALLOC_REGISTER(fpsw
, "FPSW");
2407 ALLOC_REGISTER(bpsw
, "BPSW");
2408 ALLOC_REGISTER(bpc
, "BPC");
2409 ALLOC_REGISTER(isp
, "ISP");
2410 ALLOC_REGISTER(fintv
, "FINTV");
2411 ALLOC_REGISTER(intb
, "INTB");
2412 cpu_acc
= tcg_global_mem_new_i64(cpu_env
,
2413 offsetof(CPURXState
, acc
), "ACC");