2 * QEMU ARM CPU -- internal functions and types
4 * Copyright (c) 2014 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
28 #include "hw/registerfields.h"
29 #include "tcg/tcg-gvec-desc.h"
32 /* register banks for CPU modes */
42 static inline bool excp_is_internal(int excp
)
44 /* Return true if this exception number represents a QEMU-internal
45 * exception that will not be passed to the guest.
47 return excp
== EXCP_INTERRUPT
50 || excp
== EXCP_HALTED
51 || excp
== EXCP_EXCEPTION_EXIT
52 || excp
== EXCP_KERNEL_TRAP
53 || excp
== EXCP_SEMIHOST
;
56 /* Scale factor for generic timers, ie number of ns per tick.
57 * This gives a 62.5MHz timer.
59 #define GTIMER_SCALE 16
61 /* Bit definitions for the v7M CONTROL register */
62 FIELD(V7M_CONTROL
, NPRIV
, 0, 1)
63 FIELD(V7M_CONTROL
, SPSEL
, 1, 1)
64 FIELD(V7M_CONTROL
, FPCA
, 2, 1)
65 FIELD(V7M_CONTROL
, SFPA
, 3, 1)
67 /* Bit definitions for v7M exception return payload */
68 FIELD(V7M_EXCRET
, ES
, 0, 1)
69 FIELD(V7M_EXCRET
, RES0
, 1, 1)
70 FIELD(V7M_EXCRET
, SPSEL
, 2, 1)
71 FIELD(V7M_EXCRET
, MODE
, 3, 1)
72 FIELD(V7M_EXCRET
, FTYPE
, 4, 1)
73 FIELD(V7M_EXCRET
, DCRS
, 5, 1)
74 FIELD(V7M_EXCRET
, S
, 6, 1)
75 FIELD(V7M_EXCRET
, RES1
, 7, 25) /* including the must-be-1 prefix */
77 /* Minimum value which is a magic number for exception return */
78 #define EXC_RETURN_MIN_MAGIC 0xff000000
79 /* Minimum number which is a magic number for function or exception return
80 * when using v8M security extension
82 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
84 /* We use a few fake FSR values for internal purposes in M profile.
85 * M profile cores don't have A/R format FSRs, but currently our
86 * get_phys_addr() code assumes A/R profile and reports failures via
87 * an A/R format FSR value. We then translate that into the proper
88 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
89 * Mostly the FSR values we use for this are those defined for v7PMSA,
90 * since we share some of that codepath. A few kinds of fault are
91 * only for M profile and have no A/R equivalent, though, so we have
92 * to pick a value from the reserved range (which we never otherwise
93 * generate) to use for these.
94 * These values will never be visible to the guest.
96 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
97 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
100 * raise_exception: Raise the specified exception.
101 * Raise a guest exception with the specified value, syndrome register
102 * and target exception level. This should be called from helper functions,
103 * and never returns because we will longjump back up to the CPU main loop.
105 void QEMU_NORETURN
raise_exception(CPUARMState
*env
, uint32_t excp
,
106 uint32_t syndrome
, uint32_t target_el
);
109 * Similarly, but also use unwinding to restore cpu state.
111 void QEMU_NORETURN
raise_exception_ra(CPUARMState
*env
, uint32_t excp
,
112 uint32_t syndrome
, uint32_t target_el
,
116 * For AArch64, map a given EL to an index in the banked_spsr array.
117 * Note that this mapping and the AArch32 mapping defined in bank_number()
118 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
119 * mandated mapping between each other.
121 static inline unsigned int aarch64_banked_spsr_index(unsigned int el
)
123 static const unsigned int map
[4] = {
124 [1] = BANK_SVC
, /* EL1. */
125 [2] = BANK_HYP
, /* EL2. */
126 [3] = BANK_MON
, /* EL3. */
128 assert(el
>= 1 && el
<= 3);
132 /* Map CPU modes onto saved register banks. */
133 static inline int bank_number(int mode
)
136 case ARM_CPU_MODE_USR
:
137 case ARM_CPU_MODE_SYS
:
139 case ARM_CPU_MODE_SVC
:
141 case ARM_CPU_MODE_ABT
:
143 case ARM_CPU_MODE_UND
:
145 case ARM_CPU_MODE_IRQ
:
147 case ARM_CPU_MODE_FIQ
:
149 case ARM_CPU_MODE_HYP
:
151 case ARM_CPU_MODE_MON
:
154 g_assert_not_reached();
158 * r14_bank_number: Map CPU mode onto register bank for r14
160 * Given an AArch32 CPU mode, return the index into the saved register
161 * banks to use for the R14 (LR) in that mode. This is the same as
162 * bank_number(), except for the special case of Hyp mode, where
163 * R14 is shared with USR and SYS, unlike its R13 and SPSR.
164 * This should be used as the index into env->banked_r14[], and
165 * bank_number() used for the index into env->banked_r13[] and
166 * env->banked_spsr[].
168 static inline int r14_bank_number(int mode
)
170 return (mode
== ARM_CPU_MODE_HYP
) ? BANK_USRSYS
: bank_number(mode
);
173 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
);
174 void arm_translate_init(void);
177 void arm_cpu_synchronize_from_tb(CPUState
*cs
, const TranslationBlock
*tb
);
178 #endif /* CONFIG_TCG */
181 * aarch64_sve_zcr_get_valid_len:
183 * @start_len: maximum len to consider
185 * Return the maximum supported sve vector length <= @start_len.
186 * Note that both @start_len and the return value are in units
187 * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128.
189 uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU
*cpu
, uint32_t start_len
);
191 enum arm_fprounding
{
200 int arm_rmode_to_sf(int rmode
);
202 static inline void aarch64_save_sp(CPUARMState
*env
, int el
)
204 if (env
->pstate
& PSTATE_SP
) {
205 env
->sp_el
[el
] = env
->xregs
[31];
207 env
->sp_el
[0] = env
->xregs
[31];
211 static inline void aarch64_restore_sp(CPUARMState
*env
, int el
)
213 if (env
->pstate
& PSTATE_SP
) {
214 env
->xregs
[31] = env
->sp_el
[el
];
216 env
->xregs
[31] = env
->sp_el
[0];
220 static inline void update_spsel(CPUARMState
*env
, uint32_t imm
)
222 unsigned int cur_el
= arm_current_el(env
);
223 /* Update PSTATE SPSel bit; this requires us to update the
224 * working stack pointer in xregs[31].
226 if (!((imm
^ env
->pstate
) & PSTATE_SP
)) {
229 aarch64_save_sp(env
, cur_el
);
230 env
->pstate
= deposit32(env
->pstate
, 0, 1, imm
);
232 /* We rely on illegal updates to SPsel from EL0 to get trapped
233 * at translation time.
235 assert(cur_el
>= 1 && cur_el
<= 3);
236 aarch64_restore_sp(env
, cur_el
);
243 * Returns the implementation defined bit-width of physical addresses.
244 * The ARMv8 reference manuals refer to this as PAMax().
246 static inline unsigned int arm_pamax(ARMCPU
*cpu
)
248 static const unsigned int pamax_map
[] = {
256 unsigned int parange
=
257 FIELD_EX64(cpu
->isar
.id_aa64mmfr0
, ID_AA64MMFR0
, PARANGE
);
259 /* id_aa64mmfr0 is a read-only register so values outside of the
260 * supported mappings can be considered an implementation error. */
261 assert(parange
< ARRAY_SIZE(pamax_map
));
262 return pamax_map
[parange
];
265 /* Return true if extended addresses are enabled.
266 * This is always the case if our translation regime is 64 bit,
267 * but depends on TTBCR.EAE for 32 bit.
269 static inline bool extended_addresses_enabled(CPUARMState
*env
)
271 TCR
*tcr
= &env
->cp15
.tcr_el
[arm_is_secure(env
) ? 3 : 1];
272 return arm_el_is_aa64(env
, 1) ||
273 (arm_feature(env
, ARM_FEATURE_LPAE
) && (tcr
->raw_tcr
& TTBCR_EAE
));
276 /* Update a QEMU watchpoint based on the information the guest has set in the
277 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
279 void hw_watchpoint_update(ARMCPU
*cpu
, int n
);
280 /* Update the QEMU watchpoints for every guest watchpoint. This does a
281 * complete delete-and-reinstate of the QEMU watchpoint list and so is
282 * suitable for use after migration or on reset.
284 void hw_watchpoint_update_all(ARMCPU
*cpu
);
285 /* Update a QEMU breakpoint based on the information the guest has set in the
286 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
288 void hw_breakpoint_update(ARMCPU
*cpu
, int n
);
289 /* Update the QEMU breakpoints for every guest breakpoint. This does a
290 * complete delete-and-reinstate of the QEMU breakpoint list and so is
291 * suitable for use after migration or on reset.
293 void hw_breakpoint_update_all(ARMCPU
*cpu
);
295 /* Callback function for checking if a breakpoint should trigger. */
296 bool arm_debug_check_breakpoint(CPUState
*cs
);
298 /* Callback function for checking if a watchpoint should trigger. */
299 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
);
301 /* Adjust addresses (in BE32 mode) before testing against watchpoint
304 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
);
306 /* Callback function for when a watchpoint or breakpoint triggers. */
307 void arm_debug_excp_handler(CPUState
*cs
);
309 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
310 static inline bool arm_is_psci_call(ARMCPU
*cpu
, int excp_type
)
314 static inline void arm_handle_psci_call(ARMCPU
*cpu
)
316 g_assert_not_reached();
319 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
320 bool arm_is_psci_call(ARMCPU
*cpu
, int excp_type
);
321 /* Actually handle a PSCI call */
322 void arm_handle_psci_call(ARMCPU
*cpu
);
326 * arm_clear_exclusive: clear the exclusive monitor
328 * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
330 static inline void arm_clear_exclusive(CPUARMState
*env
)
332 env
->exclusive_addr
= -1;
336 * ARMFaultType: type of an ARM MMU fault
337 * This corresponds to the v8A pseudocode's Fault enumeration,
338 * with extensions for QEMU internal conditions.
340 typedef enum ARMFaultType
{
347 ARMFault_Translation
,
348 ARMFault_AddressSize
,
349 ARMFault_SyncExternal
,
350 ARMFault_SyncExternalOnWalk
,
352 ARMFault_SyncParityOnWalk
,
353 ARMFault_AsyncParity
,
354 ARMFault_AsyncExternal
,
356 ARMFault_TLBConflict
,
359 ARMFault_ICacheMaint
,
360 ARMFault_QEMU_NSCExec
, /* v8M: NS executing in S&NSC memory */
361 ARMFault_QEMU_SFault
, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */
365 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
366 * @type: Type of fault
367 * @level: Table walk level (for translation, access flag and permission faults)
368 * @domain: Domain of the fault address (for non-LPAE CPUs only)
369 * @s2addr: Address that caused a fault at stage 2
370 * @stage2: True if we faulted at stage 2
371 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
372 * @s1ns: True if we faulted on a non-secure IPA while in secure state
373 * @ea: True if we should set the EA (external abort type) bit in syndrome
375 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo
;
376 struct ARMMMUFaultInfo
{
388 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC
389 * Compare pseudocode EncodeSDFSC(), though unlike that function
390 * we set up a whole FSR-format code including domain field and
391 * putting the high bit of the FSC into bit 10.
393 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo
*fi
)
400 case ARMFault_AccessFlag
:
401 fsc
= fi
->level
== 1 ? 0x3 : 0x6;
403 case ARMFault_Alignment
:
406 case ARMFault_Permission
:
407 fsc
= fi
->level
== 1 ? 0xd : 0xf;
409 case ARMFault_Domain
:
410 fsc
= fi
->level
== 1 ? 0x9 : 0xb;
412 case ARMFault_Translation
:
413 fsc
= fi
->level
== 1 ? 0x5 : 0x7;
415 case ARMFault_SyncExternal
:
416 fsc
= 0x8 | (fi
->ea
<< 12);
418 case ARMFault_SyncExternalOnWalk
:
419 fsc
= fi
->level
== 1 ? 0xc : 0xe;
420 fsc
|= (fi
->ea
<< 12);
422 case ARMFault_SyncParity
:
425 case ARMFault_SyncParityOnWalk
:
426 fsc
= fi
->level
== 1 ? 0x40c : 0x40e;
428 case ARMFault_AsyncParity
:
431 case ARMFault_AsyncExternal
:
432 fsc
= 0x406 | (fi
->ea
<< 12);
437 case ARMFault_TLBConflict
:
440 case ARMFault_Lockdown
:
443 case ARMFault_Exclusive
:
446 case ARMFault_ICacheMaint
:
449 case ARMFault_Background
:
452 case ARMFault_QEMU_NSCExec
:
453 fsc
= M_FAKE_FSR_NSC_EXEC
;
455 case ARMFault_QEMU_SFault
:
456 fsc
= M_FAKE_FSR_SFAULT
;
459 /* Other faults can't occur in a context that requires a
460 * short-format status code.
462 g_assert_not_reached();
465 fsc
|= (fi
->domain
<< 4);
470 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC
471 * Compare pseudocode EncodeLDFSC(), though unlike that function
472 * we fill in also the LPAE bit 9 of a DFSR format.
474 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo
*fi
)
481 case ARMFault_AddressSize
:
484 case ARMFault_AccessFlag
:
485 fsc
= (fi
->level
& 3) | (0x2 << 2);
487 case ARMFault_Permission
:
488 fsc
= (fi
->level
& 3) | (0x3 << 2);
490 case ARMFault_Translation
:
491 fsc
= (fi
->level
& 3) | (0x1 << 2);
493 case ARMFault_SyncExternal
:
494 fsc
= 0x10 | (fi
->ea
<< 12);
496 case ARMFault_SyncExternalOnWalk
:
497 fsc
= (fi
->level
& 3) | (0x5 << 2) | (fi
->ea
<< 12);
499 case ARMFault_SyncParity
:
502 case ARMFault_SyncParityOnWalk
:
503 fsc
= (fi
->level
& 3) | (0x7 << 2);
505 case ARMFault_AsyncParity
:
508 case ARMFault_AsyncExternal
:
509 fsc
= 0x11 | (fi
->ea
<< 12);
511 case ARMFault_Alignment
:
517 case ARMFault_TLBConflict
:
520 case ARMFault_Lockdown
:
523 case ARMFault_Exclusive
:
527 /* Other faults can't occur in a context that requires a
528 * long-format status code.
530 g_assert_not_reached();
537 static inline bool arm_extabort_type(MemTxResult result
)
539 /* The EA bit in syndromes and fault status registers is an
540 * IMPDEF classification of external aborts. ARM implementations
541 * usually use this to indicate AXI bus Decode error (0) or
542 * Slave error (1); in QEMU we follow that.
544 return result
!= MEMTX_DECODE_ERROR
;
547 #ifdef CONFIG_USER_ONLY
548 void arm_cpu_record_sigsegv(CPUState
*cpu
, vaddr addr
,
549 MMUAccessType access_type
,
550 bool maperr
, uintptr_t ra
);
551 void arm_cpu_record_sigbus(CPUState
*cpu
, vaddr addr
,
552 MMUAccessType access_type
, uintptr_t ra
);
554 bool arm_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
555 MMUAccessType access_type
, int mmu_idx
,
556 bool probe
, uintptr_t retaddr
);
559 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx
)
561 return mmu_idx
& ARM_MMU_IDX_COREIDX_MASK
;
564 static inline ARMMMUIdx
core_to_arm_mmu_idx(CPUARMState
*env
, int mmu_idx
)
566 if (arm_feature(env
, ARM_FEATURE_M
)) {
567 return mmu_idx
| ARM_MMU_IDX_M
;
569 return mmu_idx
| ARM_MMU_IDX_A
;
573 static inline ARMMMUIdx
core_to_aa64_mmu_idx(int mmu_idx
)
575 /* AArch64 is always a-profile. */
576 return mmu_idx
| ARM_MMU_IDX_A
;
579 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx
);
582 * Return the MMU index for a v7M CPU with all relevant information
583 * manually specified.
585 ARMMMUIdx
arm_v7m_mmu_idx_all(CPUARMState
*env
,
586 bool secstate
, bool priv
, bool negpri
);
589 * Return the MMU index for a v7M CPU in the specified security and
592 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState
*env
,
593 bool secstate
, bool priv
);
595 /* Return the MMU index for a v7M CPU in the specified security state */
596 ARMMMUIdx
arm_v7m_mmu_idx_for_secstate(CPUARMState
*env
, bool secstate
);
598 /* Return true if the stage 1 translation regime is using LPAE format page
600 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
602 /* Raise a data fault alignment exception for the specified virtual address */
603 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
604 MMUAccessType access_type
,
605 int mmu_idx
, uintptr_t retaddr
) QEMU_NORETURN
;
607 /* arm_cpu_do_transaction_failed: handle a memory system error response
608 * (eg "no device/memory present at address") by raising an external abort
611 void arm_cpu_do_transaction_failed(CPUState
*cs
, hwaddr physaddr
,
612 vaddr addr
, unsigned size
,
613 MMUAccessType access_type
,
614 int mmu_idx
, MemTxAttrs attrs
,
615 MemTxResult response
, uintptr_t retaddr
);
617 /* Call any registered EL change hooks */
618 static inline void arm_call_pre_el_change_hook(ARMCPU
*cpu
)
620 ARMELChangeHook
*hook
, *next
;
621 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
622 hook
->hook(cpu
, hook
->opaque
);
625 static inline void arm_call_el_change_hook(ARMCPU
*cpu
)
627 ARMELChangeHook
*hook
, *next
;
628 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
629 hook
->hook(cpu
, hook
->opaque
);
633 /* Return true if this address translation regime has two ranges. */
634 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx
)
637 case ARMMMUIdx_Stage1_E0
:
638 case ARMMMUIdx_Stage1_E1
:
639 case ARMMMUIdx_Stage1_E1_PAN
:
640 case ARMMMUIdx_Stage1_SE0
:
641 case ARMMMUIdx_Stage1_SE1
:
642 case ARMMMUIdx_Stage1_SE1_PAN
:
643 case ARMMMUIdx_E10_0
:
644 case ARMMMUIdx_E10_1
:
645 case ARMMMUIdx_E10_1_PAN
:
646 case ARMMMUIdx_E20_0
:
647 case ARMMMUIdx_E20_2
:
648 case ARMMMUIdx_E20_2_PAN
:
649 case ARMMMUIdx_SE10_0
:
650 case ARMMMUIdx_SE10_1
:
651 case ARMMMUIdx_SE10_1_PAN
:
652 case ARMMMUIdx_SE20_0
:
653 case ARMMMUIdx_SE20_2
:
654 case ARMMMUIdx_SE20_2_PAN
:
661 /* Return true if this address translation regime is secure */
662 static inline bool regime_is_secure(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
665 case ARMMMUIdx_E10_0
:
666 case ARMMMUIdx_E10_1
:
667 case ARMMMUIdx_E10_1_PAN
:
668 case ARMMMUIdx_E20_0
:
669 case ARMMMUIdx_E20_2
:
670 case ARMMMUIdx_E20_2_PAN
:
671 case ARMMMUIdx_Stage1_E0
:
672 case ARMMMUIdx_Stage1_E1
:
673 case ARMMMUIdx_Stage1_E1_PAN
:
675 case ARMMMUIdx_Stage2
:
676 case ARMMMUIdx_MPrivNegPri
:
677 case ARMMMUIdx_MUserNegPri
:
678 case ARMMMUIdx_MPriv
:
679 case ARMMMUIdx_MUser
:
682 case ARMMMUIdx_SE10_0
:
683 case ARMMMUIdx_SE10_1
:
684 case ARMMMUIdx_SE10_1_PAN
:
685 case ARMMMUIdx_SE20_0
:
686 case ARMMMUIdx_SE20_2
:
687 case ARMMMUIdx_SE20_2_PAN
:
688 case ARMMMUIdx_Stage1_SE0
:
689 case ARMMMUIdx_Stage1_SE1
:
690 case ARMMMUIdx_Stage1_SE1_PAN
:
692 case ARMMMUIdx_Stage2_S
:
693 case ARMMMUIdx_MSPrivNegPri
:
694 case ARMMMUIdx_MSUserNegPri
:
695 case ARMMMUIdx_MSPriv
:
696 case ARMMMUIdx_MSUser
:
699 g_assert_not_reached();
703 static inline bool regime_is_pan(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
706 case ARMMMUIdx_Stage1_E1_PAN
:
707 case ARMMMUIdx_Stage1_SE1_PAN
:
708 case ARMMMUIdx_E10_1_PAN
:
709 case ARMMMUIdx_E20_2_PAN
:
710 case ARMMMUIdx_SE10_1_PAN
:
711 case ARMMMUIdx_SE20_2_PAN
:
718 /* Return the exception level which controls this address translation regime */
719 static inline uint32_t regime_el(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
722 case ARMMMUIdx_SE20_0
:
723 case ARMMMUIdx_SE20_2
:
724 case ARMMMUIdx_SE20_2_PAN
:
725 case ARMMMUIdx_E20_0
:
726 case ARMMMUIdx_E20_2
:
727 case ARMMMUIdx_E20_2_PAN
:
728 case ARMMMUIdx_Stage2
:
729 case ARMMMUIdx_Stage2_S
:
735 case ARMMMUIdx_SE10_0
:
736 case ARMMMUIdx_Stage1_SE0
:
737 return arm_el_is_aa64(env
, 3) ? 1 : 3;
738 case ARMMMUIdx_SE10_1
:
739 case ARMMMUIdx_SE10_1_PAN
:
740 case ARMMMUIdx_Stage1_E0
:
741 case ARMMMUIdx_Stage1_E1
:
742 case ARMMMUIdx_Stage1_E1_PAN
:
743 case ARMMMUIdx_Stage1_SE1
:
744 case ARMMMUIdx_Stage1_SE1_PAN
:
745 case ARMMMUIdx_E10_0
:
746 case ARMMMUIdx_E10_1
:
747 case ARMMMUIdx_E10_1_PAN
:
748 case ARMMMUIdx_MPrivNegPri
:
749 case ARMMMUIdx_MUserNegPri
:
750 case ARMMMUIdx_MPriv
:
751 case ARMMMUIdx_MUser
:
752 case ARMMMUIdx_MSPrivNegPri
:
753 case ARMMMUIdx_MSUserNegPri
:
754 case ARMMMUIdx_MSPriv
:
755 case ARMMMUIdx_MSUser
:
758 g_assert_not_reached();
762 /* Return the TCR controlling this translation regime */
763 static inline TCR
*regime_tcr(CPUARMState
*env
, ARMMMUIdx mmu_idx
)
765 if (mmu_idx
== ARMMMUIdx_Stage2
) {
766 return &env
->cp15
.vtcr_el2
;
768 if (mmu_idx
== ARMMMUIdx_Stage2_S
) {
770 * Note: Secure stage 2 nominally shares fields from VTCR_EL2, but
771 * those are not currently used by QEMU, so just return VSTCR_EL2.
773 return &env
->cp15
.vstcr_el2
;
775 return &env
->cp15
.tcr_el
[regime_el(env
, mmu_idx
)];
778 /* Return the FSR value for a debug exception (watchpoint, hardware
779 * breakpoint or BKPT insn) targeting the specified exception level.
781 static inline uint32_t arm_debug_exception_fsr(CPUARMState
*env
)
783 ARMMMUFaultInfo fi
= { .type
= ARMFault_Debug
};
784 int target_el
= arm_debug_target_el(env
);
785 bool using_lpae
= false;
787 if (target_el
== 2 || arm_el_is_aa64(env
, target_el
)) {
790 if (arm_feature(env
, ARM_FEATURE_LPAE
) &&
791 (env
->cp15
.tcr_el
[target_el
].raw_tcr
& TTBCR_EAE
)) {
797 return arm_fi_to_lfsc(&fi
);
799 return arm_fi_to_sfsc(&fi
);
804 * arm_num_brps: Return number of implemented breakpoints.
805 * Note that the ID register BRPS field is "number of bps - 1",
806 * and we return the actual number of breakpoints.
808 static inline int arm_num_brps(ARMCPU
*cpu
)
810 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
811 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, BRPS
) + 1;
813 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, BRPS
) + 1;
818 * arm_num_wrps: Return number of implemented watchpoints.
819 * Note that the ID register WRPS field is "number of wps - 1",
820 * and we return the actual number of watchpoints.
822 static inline int arm_num_wrps(ARMCPU
*cpu
)
824 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
825 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, WRPS
) + 1;
827 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, WRPS
) + 1;
832 * arm_num_ctx_cmps: Return number of implemented context comparators.
833 * Note that the ID register CTX_CMPS field is "number of cmps - 1",
834 * and we return the actual number of comparators.
836 static inline int arm_num_ctx_cmps(ARMCPU
*cpu
)
838 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
839 return FIELD_EX64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, CTX_CMPS
) + 1;
841 return FIELD_EX32(cpu
->isar
.dbgdidr
, DBGDIDR
, CTX_CMPS
) + 1;
846 * v7m_using_psp: Return true if using process stack pointer
847 * Return true if the CPU is currently using the process stack
848 * pointer, or false if it is using the main stack pointer.
850 static inline bool v7m_using_psp(CPUARMState
*env
)
852 /* Handler mode always uses the main stack; for thread mode
853 * the CONTROL.SPSEL bit determines the answer.
854 * Note that in v7M it is not possible to be in Handler mode with
855 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
857 return !arm_v7m_is_handler_mode(env
) &&
858 env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_SPSEL_MASK
;
862 * v7m_sp_limit: Return SP limit for current CPU state
863 * Return the SP limit value for the current CPU security state
866 static inline uint32_t v7m_sp_limit(CPUARMState
*env
)
868 if (v7m_using_psp(env
)) {
869 return env
->v7m
.psplim
[env
->v7m
.secure
];
871 return env
->v7m
.msplim
[env
->v7m
.secure
];
877 * Return true if the v7M CPACR permits access to the FPU for the specified
878 * security state and privilege level.
880 static inline bool v7m_cpacr_pass(CPUARMState
*env
,
881 bool is_secure
, bool is_priv
)
883 switch (extract32(env
->v7m
.cpacr
[is_secure
], 20, 2)) {
885 case 2: /* UNPREDICTABLE: we treat like 0 */
892 g_assert_not_reached();
897 * aarch32_mode_name(): Return name of the AArch32 CPU mode
898 * @psr: Program Status Register indicating CPU mode
900 * Returns, for debug logging purposes, a printable representation
901 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
902 * the low bits of the specified PSR.
904 static inline const char *aarch32_mode_name(uint32_t psr
)
906 static const char cpu_mode_names
[16][4] = {
907 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
908 "???", "???", "hyp", "und", "???", "???", "???", "sys"
911 return cpu_mode_names
[psr
& 0xf];
915 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request
917 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following
918 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit.
919 * Must be called with the iothread lock held.
921 void arm_cpu_update_virq(ARMCPU
*cpu
);
924 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request
926 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following
927 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit.
928 * Must be called with the iothread lock held.
930 void arm_cpu_update_vfiq(ARMCPU
*cpu
);
934 * @env: The cpu environment
935 * @el: The EL to use.
937 * Return the full ARMMMUIdx for the translation regime for EL.
939 ARMMMUIdx
arm_mmu_idx_el(CPUARMState
*env
, int el
);
943 * @env: The cpu environment
945 * Return the full ARMMMUIdx for the current translation regime.
947 ARMMMUIdx
arm_mmu_idx(CPUARMState
*env
);
950 * arm_stage1_mmu_idx:
951 * @env: The cpu environment
953 * Return the ARMMMUIdx for the stage1 traversal for the current regime.
955 #ifdef CONFIG_USER_ONLY
956 static inline ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
)
958 return ARMMMUIdx_Stage1_E0
;
961 ARMMMUIdx
arm_stage1_mmu_idx(CPUARMState
*env
);
965 * arm_mmu_idx_is_stage1_of_2:
966 * @mmu_idx: The ARMMMUIdx to test
968 * Return true if @mmu_idx is a NOTLB mmu_idx that is the
969 * first stage of a two stage regime.
971 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx
)
974 case ARMMMUIdx_Stage1_E0
:
975 case ARMMMUIdx_Stage1_E1
:
976 case ARMMMUIdx_Stage1_E1_PAN
:
977 case ARMMMUIdx_Stage1_SE0
:
978 case ARMMMUIdx_Stage1_SE1
:
979 case ARMMMUIdx_Stage1_SE1_PAN
:
986 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features
,
987 const ARMISARegisters
*id
)
989 uint32_t valid
= CPSR_M
| CPSR_AIF
| CPSR_IL
| CPSR_NZCV
;
991 if ((features
>> ARM_FEATURE_V4T
) & 1) {
994 if ((features
>> ARM_FEATURE_V5
) & 1) {
995 valid
|= CPSR_Q
; /* V5TE in reality*/
997 if ((features
>> ARM_FEATURE_V6
) & 1) {
998 valid
|= CPSR_E
| CPSR_GE
;
1000 if ((features
>> ARM_FEATURE_THUMB2
) & 1) {
1003 if (isar_feature_aa32_jazelle(id
)) {
1006 if (isar_feature_aa32_pan(id
)) {
1009 if (isar_feature_aa32_dit(id
)) {
1012 if (isar_feature_aa32_ssbs(id
)) {
1019 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters
*id
)
1023 valid
= PSTATE_M
| PSTATE_DAIF
| PSTATE_IL
| PSTATE_SS
| PSTATE_NZCV
;
1024 if (isar_feature_aa64_bti(id
)) {
1025 valid
|= PSTATE_BTYPE
;
1027 if (isar_feature_aa64_pan(id
)) {
1028 valid
|= PSTATE_PAN
;
1030 if (isar_feature_aa64_uao(id
)) {
1031 valid
|= PSTATE_UAO
;
1033 if (isar_feature_aa64_dit(id
)) {
1034 valid
|= PSTATE_DIT
;
1036 if (isar_feature_aa64_ssbs(id
)) {
1037 valid
|= PSTATE_SSBS
;
1039 if (isar_feature_aa64_mte(id
)) {
1040 valid
|= PSTATE_TCO
;
1047 * Parameters of a given virtual address, as extracted from the
1048 * translation control register (TCR) for a given regime.
1050 typedef struct ARMVAParameters
{
1052 unsigned select
: 1;
1060 ARMVAParameters
aa64_va_parameters(CPUARMState
*env
, uint64_t va
,
1061 ARMMMUIdx mmu_idx
, bool data
);
1063 static inline int exception_target_el(CPUARMState
*env
)
1065 int target_el
= MAX(1, arm_current_el(env
));
1068 * No such thing as secure EL1 if EL3 is aarch32,
1069 * so update the target EL to EL3 in this case.
1071 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
1078 /* Determine if allocation tags are available. */
1079 static inline bool allocation_tag_access_enabled(CPUARMState
*env
, int el
,
1083 && arm_feature(env
, ARM_FEATURE_EL3
)
1084 && !(env
->cp15
.scr_el3
& SCR_ATA
)) {
1087 if (el
< 2 && arm_feature(env
, ARM_FEATURE_EL2
)) {
1088 uint64_t hcr
= arm_hcr_el2_eff(env
);
1089 if (!(hcr
& HCR_ATA
) && (!(hcr
& HCR_E2H
) || !(hcr
& HCR_TGE
))) {
1093 sctlr
&= (el
== 0 ? SCTLR_ATA0
: SCTLR_ATA
);
1097 #ifndef CONFIG_USER_ONLY
1099 /* Security attributes for an address, as returned by v8m_security_lookup. */
1100 typedef struct V8M_SAttributes
{
1101 bool subpage
; /* true if these attrs don't cover the whole TARGET_PAGE */
1110 void v8m_security_lookup(CPUARMState
*env
, uint32_t address
,
1111 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1112 V8M_SAttributes
*sattrs
);
1114 bool pmsav8_mpu_lookup(CPUARMState
*env
, uint32_t address
,
1115 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1116 hwaddr
*phys_ptr
, MemTxAttrs
*txattrs
,
1117 int *prot
, bool *is_subpage
,
1118 ARMMMUFaultInfo
*fi
, uint32_t *mregion
);
1120 /* Cacheability and shareability attributes for a memory access */
1121 typedef struct ARMCacheAttrs
{
1122 unsigned int attrs
:8; /* as in the MAIR register encoding */
1123 unsigned int shareability
:2; /* as in the SH field of the VMSAv8-64 PTEs */
1126 bool get_phys_addr(CPUARMState
*env
, target_ulong address
,
1127 MMUAccessType access_type
, ARMMMUIdx mmu_idx
,
1128 hwaddr
*phys_ptr
, MemTxAttrs
*attrs
, int *prot
,
1129 target_ulong
*page_size
,
1130 ARMMMUFaultInfo
*fi
, ARMCacheAttrs
*cacheattrs
)
1131 __attribute__((nonnull
));
1133 void arm_log_exception(int idx
);
1135 #endif /* !CONFIG_USER_ONLY */
1138 * The log2 of the words in the tag block, for GMID_EL1.BS.
1139 * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
1141 #define GMID_EL1_BS 6
1143 /* We associate one allocation tag per 16 bytes, the minimum. */
1144 #define LOG2_TAG_GRANULE 4
1145 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
1148 * SVE predicates are 1/8 the size of SVE vectors, and cannot use
1149 * the same simd_desc() encoding due to restrictions on size.
1150 * Use these instead.
1152 FIELD(PREDDESC
, OPRSZ
, 0, 6)
1153 FIELD(PREDDESC
, ESZ
, 6, 2)
1154 FIELD(PREDDESC
, DATA
, 8, 24)
1157 * The SVE simd_data field, for memory ops, contains either
1158 * rd (5 bits) or a shift count (2 bits).
1160 #define SVE_MTEDESC_SHIFT 5
1162 /* Bits within a descriptor passed to the helper_mte_check* functions. */
1163 FIELD(MTEDESC
, MIDX
, 0, 4)
1164 FIELD(MTEDESC
, TBI
, 4, 2)
1165 FIELD(MTEDESC
, TCMA
, 6, 2)
1166 FIELD(MTEDESC
, WRITE
, 8, 1)
1167 FIELD(MTEDESC
, SIZEM1
, 9, SIMD_DATA_BITS
- 9) /* size - 1 */
1169 bool mte_probe(CPUARMState
*env
, uint32_t desc
, uint64_t ptr
);
1170 uint64_t mte_check(CPUARMState
*env
, uint32_t desc
, uint64_t ptr
, uintptr_t ra
);
1172 static inline int allocation_tag_from_addr(uint64_t ptr
)
1174 return extract64(ptr
, 56, 4);
1177 static inline uint64_t address_with_allocation_tag(uint64_t ptr
, int rtag
)
1179 return deposit64(ptr
, 56, 4, rtag
);
1182 /* Return true if tbi bits mean that the access is checked. */
1183 static inline bool tbi_check(uint32_t desc
, int bit55
)
1185 return (desc
>> (R_MTEDESC_TBI_SHIFT
+ bit55
)) & 1;
1188 /* Return true if tcma bits mean that the access is unchecked. */
1189 static inline bool tcma_check(uint32_t desc
, int bit55
, int ptr_tag
)
1192 * We had extracted bit55 and ptr_tag for other reasons, so fold
1193 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test.
1195 bool match
= ((ptr_tag
+ bit55
) & 0xf) == 0;
1196 bool tcma
= (desc
>> (R_MTEDESC_TCMA_SHIFT
+ bit55
)) & 1;
1197 return tcma
&& match
;
1201 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
1202 * for the tag to be present in the FAR_ELx register. But for user-only
1203 * mode, we do not have a TLB with which to implement this, so we must
1204 * remove the top byte.
1206 static inline uint64_t useronly_clean_ptr(uint64_t ptr
)
1208 #ifdef CONFIG_USER_ONLY
1209 /* TBI0 is known to be enabled, while TBI1 is disabled. */
1210 ptr
&= sextract64(ptr
, 0, 56);
1215 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc
, uint64_t ptr
)
1217 #ifdef CONFIG_USER_ONLY
1218 int64_t clean_ptr
= sextract64(ptr
, 0, 56);
1219 if (tbi_check(desc
, clean_ptr
< 0)) {
1226 /* Values for M-profile PSR.ECI for MVE insns */
1228 ECI_NONE
= 0, /* No completed beats */
1229 ECI_A0
= 1, /* Completed: A0 */
1230 ECI_A0A1
= 2, /* Completed: A0, A1 */
1232 ECI_A0A1A2
= 4, /* Completed: A0, A1, A2 */
1233 ECI_A0A1A2B0
= 5, /* Completed: A0, A1, A2, B0 */
1234 /* All other values reserved */
1237 /* Definitions for the PMU registers */
1238 #define PMCRN_MASK 0xf800
1239 #define PMCRN_SHIFT 11
1248 * Mask of PMCR bits writeable by guest (not including WO bits like C, P,
1249 * which can be written as 1 to trigger behaviour but which stay RAZ).
1251 #define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
1253 #define PMXEVTYPER_P 0x80000000
1254 #define PMXEVTYPER_U 0x40000000
1255 #define PMXEVTYPER_NSK 0x20000000
1256 #define PMXEVTYPER_NSU 0x10000000
1257 #define PMXEVTYPER_NSH 0x08000000
1258 #define PMXEVTYPER_M 0x04000000
1259 #define PMXEVTYPER_MT 0x02000000
1260 #define PMXEVTYPER_EVTCOUNT 0x0000ffff
1261 #define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
1262 PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
1263 PMXEVTYPER_M | PMXEVTYPER_MT | \
1264 PMXEVTYPER_EVTCOUNT)
1266 #define PMCCFILTR 0xf8000000
1267 #define PMCCFILTR_M PMXEVTYPER_M
1268 #define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
1270 static inline uint32_t pmu_num_counters(CPUARMState
*env
)
1272 return (env
->cp15
.c9_pmcr
& PMCRN_MASK
) >> PMCRN_SHIFT
;
1275 /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
1276 static inline uint64_t pmu_counter_mask(CPUARMState
*env
)
1278 return (1 << 31) | ((1 << pmu_num_counters(env
)) - 1);
1281 #ifdef TARGET_AARCH64
1282 int arm_gdb_get_svereg(CPUARMState
*env
, GByteArray
*buf
, int reg
);
1283 int arm_gdb_set_svereg(CPUARMState
*env
, uint8_t *buf
, int reg
);
1284 int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, GByteArray
*buf
, int reg
);
1285 int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
);