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Merge remote-tracking branch 'mst/for_anthony' into staging
[qemu.git] / hw / usb-ohci.c
blob32913ebb064204f5d091a0645027f60849598927
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
27 */
28
29 #include "hw.h"
30 #include "qemu-timer.h"
31 #include "usb.h"
32 #include "pci.h"
33 #include "usb-ohci.h"
34 #include "sysbus.h"
35 #include "qdev-addr.h"
36
37 //#define DEBUG_OHCI
38 /* Dump packet contents. */
39 //#define DEBUG_PACKET
40 //#define DEBUG_ISOCH
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #ifdef DEBUG_OHCI
45 #define DPRINTF printf
46 #else
47 #define DPRINTF(...)
48 #endif
49
50 /* Number of Downstream Ports on the root hub. */
51
52 #define OHCI_MAX_PORTS 15
53
54 static int64_t usb_frame_time;
55 static int64_t usb_bit_time;
56
57 typedef struct OHCIPort {
58 USBPort port;
59 uint32_t ctrl;
60 } OHCIPort;
61
62 typedef struct {
63 USBBus bus;
64 qemu_irq irq;
65 int mem;
66 int num_ports;
67 const char *name;
68
69 QEMUTimer *eof_timer;
70 int64_t sof_time;
71
72 /* OHCI state */
73 /* Control partition */
74 uint32_t ctl, status;
75 uint32_t intr_status;
76 uint32_t intr;
77
78 /* memory pointer partition */
79 uint32_t hcca;
80 uint32_t ctrl_head, ctrl_cur;
81 uint32_t bulk_head, bulk_cur;
82 uint32_t per_cur;
83 uint32_t done;
84 int done_count;
85
86 /* Frame counter partition */
87 uint32_t fsmps:15;
88 uint32_t fit:1;
89 uint32_t fi:14;
90 uint32_t frt:1;
91 uint16_t frame_number;
92 uint16_t padding;
93 uint32_t pstart;
94 uint32_t lst;
95
96 /* Root Hub partition */
97 uint32_t rhdesc_a, rhdesc_b;
98 uint32_t rhstatus;
99 OHCIPort rhport[OHCI_MAX_PORTS];
100
101 /* PXA27x Non-OHCI events */
102 uint32_t hstatus;
103 uint32_t hmask;
104 uint32_t hreset;
105 uint32_t htest;
106
107 /* SM501 local memory offset */
108 target_phys_addr_t localmem_base;
109
110 /* Active packets. */
111 uint32_t old_ctl;
112 USBPacket usb_packet;
113 uint8_t usb_buf[8192];
114 uint32_t async_td;
115 int async_complete;
116
117 } OHCIState;
118
119 /* Host Controller Communications Area */
120 struct ohci_hcca {
121 uint32_t intr[32];
122 uint16_t frame, pad;
123 uint32_t done;
124 };
125
126 static void ohci_bus_stop(OHCIState *ohci);
127
128 /* Bitfields for the first word of an Endpoint Desciptor. */
129 #define OHCI_ED_FA_SHIFT 0
130 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
131 #define OHCI_ED_EN_SHIFT 7
132 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
133 #define OHCI_ED_D_SHIFT 11
134 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
135 #define OHCI_ED_S (1<<13)
136 #define OHCI_ED_K (1<<14)
137 #define OHCI_ED_F (1<<15)
138 #define OHCI_ED_MPS_SHIFT 16
139 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
140
141 /* Flags in the head field of an Endpoint Desciptor. */
142 #define OHCI_ED_H 1
143 #define OHCI_ED_C 2
144
145 /* Bitfields for the first word of a Transfer Desciptor. */
146 #define OHCI_TD_R (1<<18)
147 #define OHCI_TD_DP_SHIFT 19
148 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
149 #define OHCI_TD_DI_SHIFT 21
150 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
151 #define OHCI_TD_T0 (1<<24)
152 #define OHCI_TD_T1 (1<<24)
153 #define OHCI_TD_EC_SHIFT 26
154 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
155 #define OHCI_TD_CC_SHIFT 28
156 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
157
158 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
159 /* CC & DI - same as in the General Transfer Desciptor */
160 #define OHCI_TD_SF_SHIFT 0
161 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
162 #define OHCI_TD_FC_SHIFT 24
163 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
164
165 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
166 #define OHCI_TD_PSW_CC_SHIFT 12
167 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
168 #define OHCI_TD_PSW_SIZE_SHIFT 0
169 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
170
171 #define OHCI_PAGE_MASK 0xfffff000
172 #define OHCI_OFFSET_MASK 0xfff
173
174 #define OHCI_DPTR_MASK 0xfffffff0
175
176 #define OHCI_BM(val, field) \
177 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
178
179 #define OHCI_SET_BM(val, field, newval) do { \
180 val &= ~OHCI_##field##_MASK; \
181 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
182 } while(0)
183
184 /* endpoint descriptor */
185 struct ohci_ed {
186 uint32_t flags;
187 uint32_t tail;
188 uint32_t head;
189 uint32_t next;
190 };
191
192 /* General transfer descriptor */
193 struct ohci_td {
194 uint32_t flags;
195 uint32_t cbp;
196 uint32_t next;
197 uint32_t be;
198 };
199
200 /* Isochronous transfer descriptor */
201 struct ohci_iso_td {
202 uint32_t flags;
203 uint32_t bp;
204 uint32_t next;
205 uint32_t be;
206 uint16_t offset[8];
207 };
208
209 #define USB_HZ 12000000
210
211 /* OHCI Local stuff */
212 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
213 #define OHCI_CTL_PLE (1<<2)
214 #define OHCI_CTL_IE (1<<3)
215 #define OHCI_CTL_CLE (1<<4)
216 #define OHCI_CTL_BLE (1<<5)
217 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
218 #define OHCI_USB_RESET 0x00
219 #define OHCI_USB_RESUME 0x40
220 #define OHCI_USB_OPERATIONAL 0x80
221 #define OHCI_USB_SUSPEND 0xc0
222 #define OHCI_CTL_IR (1<<8)
223 #define OHCI_CTL_RWC (1<<9)
224 #define OHCI_CTL_RWE (1<<10)
225
226 #define OHCI_STATUS_HCR (1<<0)
227 #define OHCI_STATUS_CLF (1<<1)
228 #define OHCI_STATUS_BLF (1<<2)
229 #define OHCI_STATUS_OCR (1<<3)
230 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
231
232 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
233 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
234 #define OHCI_INTR_SF (1<<2) /* Start of frame */
235 #define OHCI_INTR_RD (1<<3) /* Resume detect */
236 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
237 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
238 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
239 #define OHCI_INTR_OC (1<<30) /* Ownership change */
240 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
241
242 #define OHCI_HCCA_SIZE 0x100
243 #define OHCI_HCCA_MASK 0xffffff00
244
245 #define OHCI_EDPTR_MASK 0xfffffff0
246
247 #define OHCI_FMI_FI 0x00003fff
248 #define OHCI_FMI_FSMPS 0xffff0000
249 #define OHCI_FMI_FIT 0x80000000
250
251 #define OHCI_FR_RT (1<<31)
252
253 #define OHCI_LS_THRESH 0x628
254
255 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
256 #define OHCI_RHA_PSM (1<<8)
257 #define OHCI_RHA_NPS (1<<9)
258 #define OHCI_RHA_DT (1<<10)
259 #define OHCI_RHA_OCPM (1<<11)
260 #define OHCI_RHA_NOCP (1<<12)
261 #define OHCI_RHA_POTPGT_MASK 0xff000000
262
263 #define OHCI_RHS_LPS (1<<0)
264 #define OHCI_RHS_OCI (1<<1)
265 #define OHCI_RHS_DRWE (1<<15)
266 #define OHCI_RHS_LPSC (1<<16)
267 #define OHCI_RHS_OCIC (1<<17)
268 #define OHCI_RHS_CRWE (1<<31)
269
270 #define OHCI_PORT_CCS (1<<0)
271 #define OHCI_PORT_PES (1<<1)
272 #define OHCI_PORT_PSS (1<<2)
273 #define OHCI_PORT_POCI (1<<3)
274 #define OHCI_PORT_PRS (1<<4)
275 #define OHCI_PORT_PPS (1<<8)
276 #define OHCI_PORT_LSDA (1<<9)
277 #define OHCI_PORT_CSC (1<<16)
278 #define OHCI_PORT_PESC (1<<17)
279 #define OHCI_PORT_PSSC (1<<18)
280 #define OHCI_PORT_OCIC (1<<19)
281 #define OHCI_PORT_PRSC (1<<20)
282 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
283 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
284
285 #define OHCI_TD_DIR_SETUP 0x0
286 #define OHCI_TD_DIR_OUT 0x1
287 #define OHCI_TD_DIR_IN 0x2
288 #define OHCI_TD_DIR_RESERVED 0x3
289
290 #define OHCI_CC_NOERROR 0x0
291 #define OHCI_CC_CRC 0x1
292 #define OHCI_CC_BITSTUFFING 0x2
293 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
294 #define OHCI_CC_STALL 0x4
295 #define OHCI_CC_DEVICENOTRESPONDING 0x5
296 #define OHCI_CC_PIDCHECKFAILURE 0x6
297 #define OHCI_CC_UNDEXPETEDPID 0x7
298 #define OHCI_CC_DATAOVERRUN 0x8
299 #define OHCI_CC_DATAUNDERRUN 0x9
300 #define OHCI_CC_BUFFEROVERRUN 0xc
301 #define OHCI_CC_BUFFERUNDERRUN 0xd
302
303 #define OHCI_HRESET_FSBIR (1 << 0)
304
305 /* Update IRQ levels */
306 static inline void ohci_intr_update(OHCIState *ohci)
307 {
308 int level = 0;
309
310 if ((ohci->intr & OHCI_INTR_MIE) &&
311 (ohci->intr_status & ohci->intr))
312 level = 1;
313
314 qemu_set_irq(ohci->irq, level);
315 }
316
317 /* Set an interrupt */
318 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
319 {
320 ohci->intr_status |= intr;
321 ohci_intr_update(ohci);
322 }
323
324 /* Attach or detach a device on a root hub port. */
325 static void ohci_attach(USBPort *port1)
326 {
327 OHCIState *s = port1->opaque;
328 OHCIPort *port = &s->rhport[port1->index];
329
330 /* set connect status */
331 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
332
333 /* update speed */
334 if (port->port.dev->speed == USB_SPEED_LOW) {
335 port->ctrl |= OHCI_PORT_LSDA;
336 } else {
337 port->ctrl &= ~OHCI_PORT_LSDA;
338 }
339
340 /* notify of remote-wakeup */
341 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
342 ohci_set_interrupt(s, OHCI_INTR_RD);
343 }
344
345 DPRINTF("usb-ohci: Attached port %d\n", port1->index);
346 }
347
348 static void ohci_detach(USBPort *port1)
349 {
350 OHCIState *s = port1->opaque;
351 OHCIPort *port = &s->rhport[port1->index];
352 uint32_t old_state = port->ctrl;
353
354 /* set connect status */
355 if (port->ctrl & OHCI_PORT_CCS) {
356 port->ctrl &= ~OHCI_PORT_CCS;
357 port->ctrl |= OHCI_PORT_CSC;
358 }
359 /* disable port */
360 if (port->ctrl & OHCI_PORT_PES) {
361 port->ctrl &= ~OHCI_PORT_PES;
362 port->ctrl |= OHCI_PORT_PESC;
363 }
364 DPRINTF("usb-ohci: Detached port %d\n", port1->index);
365
366 if (old_state != port->ctrl)
367 ohci_set_interrupt(s, OHCI_INTR_RHSC);
368 }
369
370 /* Reset the controller */
371 static void ohci_reset(void *opaque)
372 {
373 OHCIState *ohci = opaque;
374 OHCIPort *port;
375 int i;
376
377 ohci_bus_stop(ohci);
378 ohci->ctl = 0;
379 ohci->old_ctl = 0;
380 ohci->status = 0;
381 ohci->intr_status = 0;
382 ohci->intr = OHCI_INTR_MIE;
383
384 ohci->hcca = 0;
385 ohci->ctrl_head = ohci->ctrl_cur = 0;
386 ohci->bulk_head = ohci->bulk_cur = 0;
387 ohci->per_cur = 0;
388 ohci->done = 0;
389 ohci->done_count = 7;
390
391 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
392 * I took the value linux sets ...
393 */
394 ohci->fsmps = 0x2778;
395 ohci->fi = 0x2edf;
396 ohci->fit = 0;
397 ohci->frt = 0;
398 ohci->frame_number = 0;
399 ohci->pstart = 0;
400 ohci->lst = OHCI_LS_THRESH;
401
402 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
403 ohci->rhdesc_b = 0x0; /* Impl. specific */
404 ohci->rhstatus = 0;
405
406 for (i = 0; i < ohci->num_ports; i++)
407 {
408 port = &ohci->rhport[i];
409 port->ctrl = 0;
410 if (port->port.dev) {
411 usb_attach(&port->port, port->port.dev);
412 }
413 }
414 if (ohci->async_td) {
415 usb_cancel_packet(&ohci->usb_packet);
416 ohci->async_td = 0;
417 }
418 DPRINTF("usb-ohci: Reset %s\n", ohci->name);
419 }
420
421 /* Get an array of dwords from main memory */
422 static inline int get_dwords(OHCIState *ohci,
423 uint32_t addr, uint32_t *buf, int num)
424 {
425 int i;
426
427 addr += ohci->localmem_base;
428
429 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
430 cpu_physical_memory_read(addr, buf, sizeof(*buf));
431 *buf = le32_to_cpu(*buf);
432 }
433
434 return 1;
435 }
436
437 /* Put an array of dwords in to main memory */
438 static inline int put_dwords(OHCIState *ohci,
439 uint32_t addr, uint32_t *buf, int num)
440 {
441 int i;
442
443 addr += ohci->localmem_base;
444
445 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
446 uint32_t tmp = cpu_to_le32(*buf);
447 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
448 }
449
450 return 1;
451 }
452
453 /* Get an array of words from main memory */
454 static inline int get_words(OHCIState *ohci,
455 uint32_t addr, uint16_t *buf, int num)
456 {
457 int i;
458
459 addr += ohci->localmem_base;
460
461 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
462 cpu_physical_memory_read(addr, buf, sizeof(*buf));
463 *buf = le16_to_cpu(*buf);
464 }
465
466 return 1;
467 }
468
469 /* Put an array of words in to main memory */
470 static inline int put_words(OHCIState *ohci,
471 uint32_t addr, uint16_t *buf, int num)
472 {
473 int i;
474
475 addr += ohci->localmem_base;
476
477 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
478 uint16_t tmp = cpu_to_le16(*buf);
479 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
480 }
481
482 return 1;
483 }
484
485 static inline int ohci_read_ed(OHCIState *ohci,
486 uint32_t addr, struct ohci_ed *ed)
487 {
488 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
489 }
490
491 static inline int ohci_read_td(OHCIState *ohci,
492 uint32_t addr, struct ohci_td *td)
493 {
494 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
495 }
496
497 static inline int ohci_read_iso_td(OHCIState *ohci,
498 uint32_t addr, struct ohci_iso_td *td)
499 {
500 return (get_dwords(ohci, addr, (uint32_t *)td, 4) &&
501 get_words(ohci, addr + 16, td->offset, 8));
502 }
503
504 static inline int ohci_read_hcca(OHCIState *ohci,
505 uint32_t addr, struct ohci_hcca *hcca)
506 {
507 cpu_physical_memory_read(addr + ohci->localmem_base, hcca, sizeof(*hcca));
508 return 1;
509 }
510
511 static inline int ohci_put_ed(OHCIState *ohci,
512 uint32_t addr, struct ohci_ed *ed)
513 {
514 return put_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
515 }
516
517 static inline int ohci_put_td(OHCIState *ohci,
518 uint32_t addr, struct ohci_td *td)
519 {
520 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
521 }
522
523 static inline int ohci_put_iso_td(OHCIState *ohci,
524 uint32_t addr, struct ohci_iso_td *td)
525 {
526 return (put_dwords(ohci, addr, (uint32_t *)td, 4) &&
527 put_words(ohci, addr + 16, td->offset, 8));
528 }
529
530 static inline int ohci_put_hcca(OHCIState *ohci,
531 uint32_t addr, struct ohci_hcca *hcca)
532 {
533 cpu_physical_memory_write(addr + ohci->localmem_base, hcca, sizeof(*hcca));
534 return 1;
535 }
536
537 /* Read/Write the contents of a TD from/to main memory. */
538 static void ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
539 uint8_t *buf, int len, int write)
540 {
541 uint32_t ptr;
542 uint32_t n;
543
544 ptr = td->cbp;
545 n = 0x1000 - (ptr & 0xfff);
546 if (n > len)
547 n = len;
548 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
549 if (n == len)
550 return;
551 ptr = td->be & ~0xfffu;
552 buf += n;
553 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
554 }
555
556 /* Read/Write the contents of an ISO TD from/to main memory. */
557 static void ohci_copy_iso_td(OHCIState *ohci,
558 uint32_t start_addr, uint32_t end_addr,
559 uint8_t *buf, int len, int write)
560 {
561 uint32_t ptr;
562 uint32_t n;
563
564 ptr = start_addr;
565 n = 0x1000 - (ptr & 0xfff);
566 if (n > len)
567 n = len;
568 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, n, write);
569 if (n == len)
570 return;
571 ptr = end_addr & ~0xfffu;
572 buf += n;
573 cpu_physical_memory_rw(ptr + ohci->localmem_base, buf, len - n, write);
574 }
575
576 static void ohci_process_lists(OHCIState *ohci, int completion);
577
578 static void ohci_async_complete_packet(USBDevice *dev, USBPacket *packet)
579 {
580 OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
581 #ifdef DEBUG_PACKET
582 DPRINTF("Async packet complete\n");
583 #endif
584 ohci->async_complete = 1;
585 ohci_process_lists(ohci, 1);
586 }
587
588 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
589
590 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed,
591 int completion)
592 {
593 int dir;
594 size_t len = 0;
595 #ifdef DEBUG_ISOCH
596 const char *str = NULL;
597 #endif
598 int pid;
599 int ret;
600 int i;
601 USBDevice *dev;
602 struct ohci_iso_td iso_td;
603 uint32_t addr;
604 uint16_t starting_frame;
605 int16_t relative_frame_number;
606 int frame_count;
607 uint32_t start_offset, next_offset, end_offset = 0;
608 uint32_t start_addr, end_addr;
609
610 addr = ed->head & OHCI_DPTR_MASK;
611
612 if (!ohci_read_iso_td(ohci, addr, &iso_td)) {
613 printf("usb-ohci: ISO_TD read error at %x\n", addr);
614 return 0;
615 }
616
617 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
618 frame_count = OHCI_BM(iso_td.flags, TD_FC);
619 relative_frame_number = USUB(ohci->frame_number, starting_frame);
620
621 #ifdef DEBUG_ISOCH
622 printf("--- ISO_TD ED head 0x%.8x tailp 0x%.8x\n"
623 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
624 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
625 "0x%.8x 0x%.8x 0x%.8x 0x%.8x\n"
626 "frame_number 0x%.8x starting_frame 0x%.8x\n"
627 "frame_count 0x%.8x relative %d\n"
628 "di 0x%.8x cc 0x%.8x\n",
629 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
630 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
631 iso_td.offset[0], iso_td.offset[1], iso_td.offset[2], iso_td.offset[3],
632 iso_td.offset[4], iso_td.offset[5], iso_td.offset[6], iso_td.offset[7],
633 ohci->frame_number, starting_frame,
634 frame_count, relative_frame_number,
635 OHCI_BM(iso_td.flags, TD_DI), OHCI_BM(iso_td.flags, TD_CC));
636 #endif
637
638 if (relative_frame_number < 0) {
639 DPRINTF("usb-ohci: ISO_TD R=%d < 0\n", relative_frame_number);
640 return 1;
641 } else if (relative_frame_number > frame_count) {
642 /* ISO TD expired - retire the TD to the Done Queue and continue with
643 the next ISO TD of the same ED */
644 DPRINTF("usb-ohci: ISO_TD R=%d > FC=%d\n", relative_frame_number,
645 frame_count);
646 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
647 ed->head &= ~OHCI_DPTR_MASK;
648 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
649 iso_td.next = ohci->done;
650 ohci->done = addr;
651 i = OHCI_BM(iso_td.flags, TD_DI);
652 if (i < ohci->done_count)
653 ohci->done_count = i;
654 ohci_put_iso_td(ohci, addr, &iso_td);
655 return 0;
656 }
657
658 dir = OHCI_BM(ed->flags, ED_D);
659 switch (dir) {
660 case OHCI_TD_DIR_IN:
661 #ifdef DEBUG_ISOCH
662 str = "in";
663 #endif
664 pid = USB_TOKEN_IN;
665 break;
666 case OHCI_TD_DIR_OUT:
667 #ifdef DEBUG_ISOCH
668 str = "out";
669 #endif
670 pid = USB_TOKEN_OUT;
671 break;
672 case OHCI_TD_DIR_SETUP:
673 #ifdef DEBUG_ISOCH
674 str = "setup";
675 #endif
676 pid = USB_TOKEN_SETUP;
677 break;
678 default:
679 printf("usb-ohci: Bad direction %d\n", dir);
680 return 1;
681 }
682
683 if (!iso_td.bp || !iso_td.be) {
684 printf("usb-ohci: ISO_TD bp 0x%.8x be 0x%.8x\n", iso_td.bp, iso_td.be);
685 return 1;
686 }
687
688 start_offset = iso_td.offset[relative_frame_number];
689 next_offset = iso_td.offset[relative_frame_number + 1];
690
691 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
692 ((relative_frame_number < frame_count) &&
693 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
694 printf("usb-ohci: ISO_TD cc != not accessed 0x%.8x 0x%.8x\n",
695 start_offset, next_offset);
696 return 1;
697 }
698
699 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
700 printf("usb-ohci: ISO_TD start_offset=0x%.8x > next_offset=0x%.8x\n",
701 start_offset, next_offset);
702 return 1;
703 }
704
705 if ((start_offset & 0x1000) == 0) {
706 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
707 (start_offset & OHCI_OFFSET_MASK);
708 } else {
709 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
710 (start_offset & OHCI_OFFSET_MASK);
711 }
712
713 if (relative_frame_number < frame_count) {
714 end_offset = next_offset - 1;
715 if ((end_offset & 0x1000) == 0) {
716 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
717 (end_offset & OHCI_OFFSET_MASK);
718 } else {
719 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
720 (end_offset & OHCI_OFFSET_MASK);
721 }
722 } else {
723 /* Last packet in the ISO TD */
724 end_addr = iso_td.be;
725 }
726
727 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
728 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
729 - (start_addr & OHCI_OFFSET_MASK);
730 } else {
731 len = end_addr - start_addr + 1;
732 }
733
734 if (len && dir != OHCI_TD_DIR_IN) {
735 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 0);
736 }
737
738 if (completion) {
739 ret = ohci->usb_packet.len;
740 } else {
741 ret = USB_RET_NODEV;
742 for (i = 0; i < ohci->num_ports; i++) {
743 dev = ohci->rhport[i].port.dev;
744 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
745 continue;
746 ohci->usb_packet.pid = pid;
747 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
748 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
749 ohci->usb_packet.data = ohci->usb_buf;
750 ohci->usb_packet.len = len;
751 ret = dev->info->handle_packet(dev, &ohci->usb_packet);
752 if (ret != USB_RET_NODEV)
753 break;
754 }
755
756 if (ret == USB_RET_ASYNC) {
757 return 1;
758 }
759 }
760
761 #ifdef DEBUG_ISOCH
762 printf("so 0x%.8x eo 0x%.8x\nsa 0x%.8x ea 0x%.8x\ndir %s len %zu ret %d\n",
763 start_offset, end_offset, start_addr, end_addr, str, len, ret);
764 #endif
765
766 /* Writeback */
767 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
768 /* IN transfer succeeded */
769 ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 1);
770 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
771 OHCI_CC_NOERROR);
772 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
773 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
774 /* OUT transfer succeeded */
775 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
776 OHCI_CC_NOERROR);
777 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
778 } else {
779 if (ret > (ssize_t) len) {
780 printf("usb-ohci: DataOverrun %d > %zu\n", ret, len);
781 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
782 OHCI_CC_DATAOVERRUN);
783 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
784 len);
785 } else if (ret >= 0) {
786 printf("usb-ohci: DataUnderrun %d\n", ret);
787 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
788 OHCI_CC_DATAUNDERRUN);
789 } else {
790 switch (ret) {
791 case USB_RET_NODEV:
792 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
793 OHCI_CC_DEVICENOTRESPONDING);
794 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
795 0);
796 break;
797 case USB_RET_NAK:
798 case USB_RET_STALL:
799 printf("usb-ohci: got NAK/STALL %d\n", ret);
800 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
801 OHCI_CC_STALL);
802 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
803 0);
804 break;
805 default:
806 printf("usb-ohci: Bad device response %d\n", ret);
807 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
808 OHCI_CC_UNDEXPETEDPID);
809 break;
810 }
811 }
812 }
813
814 if (relative_frame_number == frame_count) {
815 /* Last data packet of ISO TD - retire the TD to the Done Queue */
816 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
817 ed->head &= ~OHCI_DPTR_MASK;
818 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
819 iso_td.next = ohci->done;
820 ohci->done = addr;
821 i = OHCI_BM(iso_td.flags, TD_DI);
822 if (i < ohci->done_count)
823 ohci->done_count = i;
824 }
825 ohci_put_iso_td(ohci, addr, &iso_td);
826 return 1;
827 }
828
829 /* Service a transport descriptor.
830 Returns nonzero to terminate processing of this endpoint. */
831
832 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
833 {
834 int dir;
835 size_t len = 0;
836 #ifdef DEBUG_PACKET
837 const char *str = NULL;
838 #endif
839 int pid;
840 int ret;
841 int i;
842 USBDevice *dev;
843 struct ohci_td td;
844 uint32_t addr;
845 int flag_r;
846 int completion;
847
848 addr = ed->head & OHCI_DPTR_MASK;
849 /* See if this TD has already been submitted to the device. */
850 completion = (addr == ohci->async_td);
851 if (completion && !ohci->async_complete) {
852 #ifdef DEBUG_PACKET
853 DPRINTF("Skipping async TD\n");
854 #endif
855 return 1;
856 }
857 if (!ohci_read_td(ohci, addr, &td)) {
858 fprintf(stderr, "usb-ohci: TD read error at %x\n", addr);
859 return 0;
860 }
861
862 dir = OHCI_BM(ed->flags, ED_D);
863 switch (dir) {
864 case OHCI_TD_DIR_OUT:
865 case OHCI_TD_DIR_IN:
866 /* Same value. */
867 break;
868 default:
869 dir = OHCI_BM(td.flags, TD_DP);
870 break;
871 }
872
873 switch (dir) {
874 case OHCI_TD_DIR_IN:
875 #ifdef DEBUG_PACKET
876 str = "in";
877 #endif
878 pid = USB_TOKEN_IN;
879 break;
880 case OHCI_TD_DIR_OUT:
881 #ifdef DEBUG_PACKET
882 str = "out";
883 #endif
884 pid = USB_TOKEN_OUT;
885 break;
886 case OHCI_TD_DIR_SETUP:
887 #ifdef DEBUG_PACKET
888 str = "setup";
889 #endif
890 pid = USB_TOKEN_SETUP;
891 break;
892 default:
893 fprintf(stderr, "usb-ohci: Bad direction\n");
894 return 1;
895 }
896 if (td.cbp && td.be) {
897 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
898 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
899 } else {
900 len = (td.be - td.cbp) + 1;
901 }
902
903 if (len && dir != OHCI_TD_DIR_IN && !completion) {
904 ohci_copy_td(ohci, &td, ohci->usb_buf, len, 0);
905 }
906 }
907
908 flag_r = (td.flags & OHCI_TD_R) != 0;
909 #ifdef DEBUG_PACKET
910 DPRINTF(" TD @ 0x%.8x %" PRId64 " bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
911 addr, (int64_t)len, str, flag_r, td.cbp, td.be);
912
913 if (len > 0 && dir != OHCI_TD_DIR_IN) {
914 DPRINTF(" data:");
915 for (i = 0; i < len; i++)
916 printf(" %.2x", ohci->usb_buf[i]);
917 DPRINTF("\n");
918 }
919 #endif
920 if (completion) {
921 ret = ohci->usb_packet.len;
922 ohci->async_td = 0;
923 ohci->async_complete = 0;
924 } else {
925 ret = USB_RET_NODEV;
926 for (i = 0; i < ohci->num_ports; i++) {
927 dev = ohci->rhport[i].port.dev;
928 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0)
929 continue;
930
931 if (ohci->async_td) {
932 /* ??? The hardware should allow one active packet per
933 endpoint. We only allow one active packet per controller.
934 This should be sufficient as long as devices respond in a
935 timely manner.
936 */
937 #ifdef DEBUG_PACKET
938 DPRINTF("Too many pending packets\n");
939 #endif
940 return 1;
941 }
942 ohci->usb_packet.pid = pid;
943 ohci->usb_packet.devaddr = OHCI_BM(ed->flags, ED_FA);
944 ohci->usb_packet.devep = OHCI_BM(ed->flags, ED_EN);
945 ohci->usb_packet.data = ohci->usb_buf;
946 ohci->usb_packet.len = len;
947 ret = dev->info->handle_packet(dev, &ohci->usb_packet);
948 if (ret != USB_RET_NODEV)
949 break;
950 }
951 #ifdef DEBUG_PACKET
952 DPRINTF("ret=%d\n", ret);
953 #endif
954 if (ret == USB_RET_ASYNC) {
955 ohci->async_td = addr;
956 return 1;
957 }
958 }
959 if (ret >= 0) {
960 if (dir == OHCI_TD_DIR_IN) {
961 ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1);
962 #ifdef DEBUG_PACKET
963 DPRINTF(" data:");
964 for (i = 0; i < ret; i++)
965 printf(" %.2x", ohci->usb_buf[i]);
966 DPRINTF("\n");
967 #endif
968 } else {
969 ret = len;
970 }
971 }
972
973 /* Writeback */
974 if (ret == len || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
975 /* Transmission succeeded. */
976 if (ret == len) {
977 td.cbp = 0;
978 } else {
979 td.cbp += ret;
980 if ((td.cbp & 0xfff) + ret > 0xfff) {
981 td.cbp &= 0xfff;
982 td.cbp |= td.be & ~0xfff;
983 }
984 }
985 td.flags |= OHCI_TD_T1;
986 td.flags ^= OHCI_TD_T0;
987 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
988 OHCI_SET_BM(td.flags, TD_EC, 0);
989
990 ed->head &= ~OHCI_ED_C;
991 if (td.flags & OHCI_TD_T0)
992 ed->head |= OHCI_ED_C;
993 } else {
994 if (ret >= 0) {
995 DPRINTF("usb-ohci: Underrun\n");
996 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
997 } else {
998 switch (ret) {
999 case USB_RET_NODEV:
1000 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1001 case USB_RET_NAK:
1002 DPRINTF("usb-ohci: got NAK\n");
1003 return 1;
1004 case USB_RET_STALL:
1005 DPRINTF("usb-ohci: got STALL\n");
1006 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1007 break;
1008 case USB_RET_BABBLE:
1009 DPRINTF("usb-ohci: got BABBLE\n");
1010 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1011 break;
1012 default:
1013 fprintf(stderr, "usb-ohci: Bad device response %d\n", ret);
1014 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1015 OHCI_SET_BM(td.flags, TD_EC, 3);
1016 break;
1017 }
1018 }
1019 ed->head |= OHCI_ED_H;
1020 }
1021
1022 /* Retire this TD */
1023 ed->head &= ~OHCI_DPTR_MASK;
1024 ed->head |= td.next & OHCI_DPTR_MASK;
1025 td.next = ohci->done;
1026 ohci->done = addr;
1027 i = OHCI_BM(td.flags, TD_DI);
1028 if (i < ohci->done_count)
1029 ohci->done_count = i;
1030 ohci_put_td(ohci, addr, &td);
1031 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1032 }
1033
1034 /* Service an endpoint list. Returns nonzero if active TD were found. */
1035 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion)
1036 {
1037 struct ohci_ed ed;
1038 uint32_t next_ed;
1039 uint32_t cur;
1040 int active;
1041
1042 active = 0;
1043
1044 if (head == 0)
1045 return 0;
1046
1047 for (cur = head; cur; cur = next_ed) {
1048 if (!ohci_read_ed(ohci, cur, &ed)) {
1049 fprintf(stderr, "usb-ohci: ED read error at %x\n", cur);
1050 return 0;
1051 }
1052
1053 next_ed = ed.next & OHCI_DPTR_MASK;
1054
1055 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1056 uint32_t addr;
1057 /* Cancel pending packets for ED that have been paused. */
1058 addr = ed.head & OHCI_DPTR_MASK;
1059 if (ohci->async_td && addr == ohci->async_td) {
1060 usb_cancel_packet(&ohci->usb_packet);
1061 ohci->async_td = 0;
1062 }
1063 continue;
1064 }
1065
1066 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1067 #ifdef DEBUG_PACKET
1068 DPRINTF("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
1069 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur,
1070 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1071 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1072 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1073 OHCI_BM(ed.flags, ED_MPS), (ed.head & OHCI_ED_H) != 0,
1074 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1075 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1076 #endif
1077 active = 1;
1078
1079 if ((ed.flags & OHCI_ED_F) == 0) {
1080 if (ohci_service_td(ohci, &ed))
1081 break;
1082 } else {
1083 /* Handle isochronous endpoints */
1084 if (ohci_service_iso_td(ohci, &ed, completion))
1085 break;
1086 }
1087 }
1088
1089 ohci_put_ed(ohci, cur, &ed);
1090 }
1091
1092 return active;
1093 }
1094
1095 /* Generate a SOF event, and set a timer for EOF */
1096 static void ohci_sof(OHCIState *ohci)
1097 {
1098 ohci->sof_time = qemu_get_clock_ns(vm_clock);
1099 qemu_mod_timer(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1100 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1101 }
1102
1103 /* Process Control and Bulk lists. */
1104 static void ohci_process_lists(OHCIState *ohci, int completion)
1105 {
1106 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1107 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1108 DPRINTF("usb-ohci: head %x, cur %x\n",
1109 ohci->ctrl_head, ohci->ctrl_cur);
1110 }
1111 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) {
1112 ohci->ctrl_cur = 0;
1113 ohci->status &= ~OHCI_STATUS_CLF;
1114 }
1115 }
1116
1117 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1118 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) {
1119 ohci->bulk_cur = 0;
1120 ohci->status &= ~OHCI_STATUS_BLF;
1121 }
1122 }
1123 }
1124
1125 /* Do frame processing on frame boundary */
1126 static void ohci_frame_boundary(void *opaque)
1127 {
1128 OHCIState *ohci = opaque;
1129 struct ohci_hcca hcca;
1130
1131 ohci_read_hcca(ohci, ohci->hcca, &hcca);
1132
1133 /* Process all the lists at the end of the frame */
1134 if (ohci->ctl & OHCI_CTL_PLE) {
1135 int n;
1136
1137 n = ohci->frame_number & 0x1f;
1138 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0);
1139 }
1140
1141 /* Cancel all pending packets if either of the lists has been disabled. */
1142 if (ohci->async_td &&
1143 ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1144 usb_cancel_packet(&ohci->usb_packet);
1145 ohci->async_td = 0;
1146 }
1147 ohci->old_ctl = ohci->ctl;
1148 ohci_process_lists(ohci, 0);
1149
1150 /* Frame boundary, so do EOF stuf here */
1151 ohci->frt = ohci->fit;
1152
1153 /* Increment frame number and take care of endianness. */
1154 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1155 hcca.frame = cpu_to_le16(ohci->frame_number);
1156
1157 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1158 if (!ohci->done)
1159 abort();
1160 if (ohci->intr & ohci->intr_status)
1161 ohci->done |= 1;
1162 hcca.done = cpu_to_le32(ohci->done);
1163 ohci->done = 0;
1164 ohci->done_count = 7;
1165 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1166 }
1167
1168 if (ohci->done_count != 7 && ohci->done_count != 0)
1169 ohci->done_count--;
1170
1171 /* Do SOF stuff here */
1172 ohci_sof(ohci);
1173
1174 /* Writeback HCCA */
1175 ohci_put_hcca(ohci, ohci->hcca, &hcca);
1176 }
1177
1178 /* Start sending SOF tokens across the USB bus, lists are processed in
1179 * next frame
1180 */
1181 static int ohci_bus_start(OHCIState *ohci)
1182 {
1183 ohci->eof_timer = qemu_new_timer_ns(vm_clock,
1184 ohci_frame_boundary,
1185 ohci);
1186
1187 if (ohci->eof_timer == NULL) {
1188 fprintf(stderr, "usb-ohci: %s: qemu_new_timer_ns failed\n", ohci->name);
1189 /* TODO: Signal unrecoverable error */
1190 return 0;
1191 }
1192
1193 DPRINTF("usb-ohci: %s: USB Operational\n", ohci->name);
1194
1195 ohci_sof(ohci);
1196
1197 return 1;
1198 }
1199
1200 /* Stop sending SOF tokens on the bus */
1201 static void ohci_bus_stop(OHCIState *ohci)
1202 {
1203 if (ohci->eof_timer)
1204 qemu_del_timer(ohci->eof_timer);
1205 ohci->eof_timer = NULL;
1206 }
1207
1208 /* Sets a flag in a port status register but only set it if the port is
1209 * connected, if not set ConnectStatusChange flag. If flag is enabled
1210 * return 1.
1211 */
1212 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1213 {
1214 int ret = 1;
1215
1216 /* writing a 0 has no effect */
1217 if (val == 0)
1218 return 0;
1219
1220 /* If CurrentConnectStatus is cleared we set
1221 * ConnectStatusChange
1222 */
1223 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1224 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1225 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1226 /* TODO: CSC is a wakeup event */
1227 }
1228 return 0;
1229 }
1230
1231 if (ohci->rhport[i].ctrl & val)
1232 ret = 0;
1233
1234 /* set the bit */
1235 ohci->rhport[i].ctrl |= val;
1236
1237 return ret;
1238 }
1239
1240 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1241 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1242 {
1243 val &= OHCI_FMI_FI;
1244
1245 if (val != ohci->fi) {
1246 DPRINTF("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
1247 ohci->name, ohci->fi, ohci->fi);
1248 }
1249
1250 ohci->fi = val;
1251 }
1252
1253 static void ohci_port_power(OHCIState *ohci, int i, int p)
1254 {
1255 if (p) {
1256 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1257 } else {
1258 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1259 OHCI_PORT_CCS|
1260 OHCI_PORT_PSS|
1261 OHCI_PORT_PRS);
1262 }
1263 }
1264
1265 /* Set HcControlRegister */
1266 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1267 {
1268 uint32_t old_state;
1269 uint32_t new_state;
1270
1271 old_state = ohci->ctl & OHCI_CTL_HCFS;
1272 ohci->ctl = val;
1273 new_state = ohci->ctl & OHCI_CTL_HCFS;
1274
1275 /* no state change */
1276 if (old_state == new_state)
1277 return;
1278
1279 switch (new_state) {
1280 case OHCI_USB_OPERATIONAL:
1281 ohci_bus_start(ohci);
1282 break;
1283 case OHCI_USB_SUSPEND:
1284 ohci_bus_stop(ohci);
1285 DPRINTF("usb-ohci: %s: USB Suspended\n", ohci->name);
1286 break;
1287 case OHCI_USB_RESUME:
1288 DPRINTF("usb-ohci: %s: USB Resume\n", ohci->name);
1289 break;
1290 case OHCI_USB_RESET:
1291 ohci_reset(ohci);
1292 DPRINTF("usb-ohci: %s: USB Reset\n", ohci->name);
1293 break;
1294 }
1295 }
1296
1297 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1298 {
1299 uint16_t fr;
1300 int64_t tks;
1301
1302 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1303 return (ohci->frt << 31);
1304
1305 /* Being in USB operational state guarnatees sof_time was
1306 * set already.
1307 */
1308 tks = qemu_get_clock_ns(vm_clock) - ohci->sof_time;
1309
1310 /* avoid muldiv if possible */
1311 if (tks >= usb_frame_time)
1312 return (ohci->frt << 31);
1313
1314 tks = muldiv64(1, tks, usb_bit_time);
1315 fr = (uint16_t)(ohci->fi - tks);
1316
1317 return (ohci->frt << 31) | fr;
1318 }
1319
1320
1321 /* Set root hub status */
1322 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1323 {
1324 uint32_t old_state;
1325
1326 old_state = ohci->rhstatus;
1327
1328 /* write 1 to clear OCIC */
1329 if (val & OHCI_RHS_OCIC)
1330 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1331
1332 if (val & OHCI_RHS_LPS) {
1333 int i;
1334
1335 for (i = 0; i < ohci->num_ports; i++)
1336 ohci_port_power(ohci, i, 0);
1337 DPRINTF("usb-ohci: powered down all ports\n");
1338 }
1339
1340 if (val & OHCI_RHS_LPSC) {
1341 int i;
1342
1343 for (i = 0; i < ohci->num_ports; i++)
1344 ohci_port_power(ohci, i, 1);
1345 DPRINTF("usb-ohci: powered up all ports\n");
1346 }
1347
1348 if (val & OHCI_RHS_DRWE)
1349 ohci->rhstatus |= OHCI_RHS_DRWE;
1350
1351 if (val & OHCI_RHS_CRWE)
1352 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1353
1354 if (old_state != ohci->rhstatus)
1355 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1356 }
1357
1358 /* Set root hub port status */
1359 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1360 {
1361 uint32_t old_state;
1362 OHCIPort *port;
1363
1364 port = &ohci->rhport[portnum];
1365 old_state = port->ctrl;
1366
1367 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1368 if (val & OHCI_PORT_WTC)
1369 port->ctrl &= ~(val & OHCI_PORT_WTC);
1370
1371 if (val & OHCI_PORT_CCS)
1372 port->ctrl &= ~OHCI_PORT_PES;
1373
1374 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1375
1376 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1377 DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
1378 }
1379
1380 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1381 DPRINTF("usb-ohci: port %d: RESET\n", portnum);
1382 usb_send_msg(port->port.dev, USB_MSG_RESET);
1383 port->ctrl &= ~OHCI_PORT_PRS;
1384 /* ??? Should this also set OHCI_PORT_PESC. */
1385 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1386 }
1387
1388 /* Invert order here to ensure in ambiguous case, device is
1389 * powered up...
1390 */
1391 if (val & OHCI_PORT_LSDA)
1392 ohci_port_power(ohci, portnum, 0);
1393 if (val & OHCI_PORT_PPS)
1394 ohci_port_power(ohci, portnum, 1);
1395
1396 if (old_state != port->ctrl)
1397 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1398
1399 return;
1400 }
1401
1402 static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
1403 {
1404 OHCIState *ohci = ptr;
1405 uint32_t retval;
1406
1407 addr &= 0xff;
1408
1409 /* Only aligned reads are allowed on OHCI */
1410 if (addr & 3) {
1411 fprintf(stderr, "usb-ohci: Mis-aligned read\n");
1412 return 0xffffffff;
1413 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1414 /* HcRhPortStatus */
1415 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1416 } else {
1417 switch (addr >> 2) {
1418 case 0: /* HcRevision */
1419 retval = 0x10;
1420 break;
1421
1422 case 1: /* HcControl */
1423 retval = ohci->ctl;
1424 break;
1425
1426 case 2: /* HcCommandStatus */
1427 retval = ohci->status;
1428 break;
1429
1430 case 3: /* HcInterruptStatus */
1431 retval = ohci->intr_status;
1432 break;
1433
1434 case 4: /* HcInterruptEnable */
1435 case 5: /* HcInterruptDisable */
1436 retval = ohci->intr;
1437 break;
1438
1439 case 6: /* HcHCCA */
1440 retval = ohci->hcca;
1441 break;
1442
1443 case 7: /* HcPeriodCurrentED */
1444 retval = ohci->per_cur;
1445 break;
1446
1447 case 8: /* HcControlHeadED */
1448 retval = ohci->ctrl_head;
1449 break;
1450
1451 case 9: /* HcControlCurrentED */
1452 retval = ohci->ctrl_cur;
1453 break;
1454
1455 case 10: /* HcBulkHeadED */
1456 retval = ohci->bulk_head;
1457 break;
1458
1459 case 11: /* HcBulkCurrentED */
1460 retval = ohci->bulk_cur;
1461 break;
1462
1463 case 12: /* HcDoneHead */
1464 retval = ohci->done;
1465 break;
1466
1467 case 13: /* HcFmInterretval */
1468 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1469 break;
1470
1471 case 14: /* HcFmRemaining */
1472 retval = ohci_get_frame_remaining(ohci);
1473 break;
1474
1475 case 15: /* HcFmNumber */
1476 retval = ohci->frame_number;
1477 break;
1478
1479 case 16: /* HcPeriodicStart */
1480 retval = ohci->pstart;
1481 break;
1482
1483 case 17: /* HcLSThreshold */
1484 retval = ohci->lst;
1485 break;
1486
1487 case 18: /* HcRhDescriptorA */
1488 retval = ohci->rhdesc_a;
1489 break;
1490
1491 case 19: /* HcRhDescriptorB */
1492 retval = ohci->rhdesc_b;
1493 break;
1494
1495 case 20: /* HcRhStatus */
1496 retval = ohci->rhstatus;
1497 break;
1498
1499 /* PXA27x specific registers */
1500 case 24: /* HcStatus */
1501 retval = ohci->hstatus & ohci->hmask;
1502 break;
1503
1504 case 25: /* HcHReset */
1505 retval = ohci->hreset;
1506 break;
1507
1508 case 26: /* HcHInterruptEnable */
1509 retval = ohci->hmask;
1510 break;
1511
1512 case 27: /* HcHInterruptTest */
1513 retval = ohci->htest;
1514 break;
1515
1516 default:
1517 fprintf(stderr, "ohci_read: Bad offset %x\n", (int)addr);
1518 retval = 0xffffffff;
1519 }
1520 }
1521
1522 return retval;
1523 }
1524
1525 static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
1526 {
1527 OHCIState *ohci = ptr;
1528
1529 addr &= 0xff;
1530
1531 /* Only aligned reads are allowed on OHCI */
1532 if (addr & 3) {
1533 fprintf(stderr, "usb-ohci: Mis-aligned write\n");
1534 return;
1535 }
1536
1537 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1538 /* HcRhPortStatus */
1539 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1540 return;
1541 }
1542
1543 switch (addr >> 2) {
1544 case 1: /* HcControl */
1545 ohci_set_ctl(ohci, val);
1546 break;
1547
1548 case 2: /* HcCommandStatus */
1549 /* SOC is read-only */
1550 val = (val & ~OHCI_STATUS_SOC);
1551
1552 /* Bits written as '0' remain unchanged in the register */
1553 ohci->status |= val;
1554
1555 if (ohci->status & OHCI_STATUS_HCR)
1556 ohci_reset(ohci);
1557 break;
1558
1559 case 3: /* HcInterruptStatus */
1560 ohci->intr_status &= ~val;
1561 ohci_intr_update(ohci);
1562 break;
1563
1564 case 4: /* HcInterruptEnable */
1565 ohci->intr |= val;
1566 ohci_intr_update(ohci);
1567 break;
1568
1569 case 5: /* HcInterruptDisable */
1570 ohci->intr &= ~val;
1571 ohci_intr_update(ohci);
1572 break;
1573
1574 case 6: /* HcHCCA */
1575 ohci->hcca = val & OHCI_HCCA_MASK;
1576 break;
1577
1578 case 8: /* HcControlHeadED */
1579 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1580 break;
1581
1582 case 9: /* HcControlCurrentED */
1583 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1584 break;
1585
1586 case 10: /* HcBulkHeadED */
1587 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1588 break;
1589
1590 case 11: /* HcBulkCurrentED */
1591 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1592 break;
1593
1594 case 13: /* HcFmInterval */
1595 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1596 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1597 ohci_set_frame_interval(ohci, val);
1598 break;
1599
1600 case 15: /* HcFmNumber */
1601 break;
1602
1603 case 16: /* HcPeriodicStart */
1604 ohci->pstart = val & 0xffff;
1605 break;
1606
1607 case 17: /* HcLSThreshold */
1608 ohci->lst = val & 0xffff;
1609 break;
1610
1611 case 18: /* HcRhDescriptorA */
1612 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1613 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1614 break;
1615
1616 case 19: /* HcRhDescriptorB */
1617 break;
1618
1619 case 20: /* HcRhStatus */
1620 ohci_set_hub_status(ohci, val);
1621 break;
1622
1623 /* PXA27x specific registers */
1624 case 24: /* HcStatus */
1625 ohci->hstatus &= ~(val & ohci->hmask);
1626
1627 case 25: /* HcHReset */
1628 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1629 if (val & OHCI_HRESET_FSBIR)
1630 ohci_reset(ohci);
1631 break;
1632
1633 case 26: /* HcHInterruptEnable */
1634 ohci->hmask = val;
1635 break;
1636
1637 case 27: /* HcHInterruptTest */
1638 ohci->htest = val;
1639 break;
1640
1641 default:
1642 fprintf(stderr, "ohci_write: Bad offset %x\n", (int)addr);
1643 break;
1644 }
1645 }
1646
1647 /* Only dword reads are defined on OHCI register space */
1648 static CPUReadMemoryFunc * const ohci_readfn[3]={
1649 ohci_mem_read,
1650 ohci_mem_read,
1651 ohci_mem_read
1652 };
1653
1654 /* Only dword writes are defined on OHCI register space */
1655 static CPUWriteMemoryFunc * const ohci_writefn[3]={
1656 ohci_mem_write,
1657 ohci_mem_write,
1658 ohci_mem_write
1659 };
1660
1661 static USBPortOps ohci_port_ops = {
1662 .attach = ohci_attach,
1663 .detach = ohci_detach,
1664 .complete = ohci_async_complete_packet,
1665 };
1666
1667 static void usb_ohci_init(OHCIState *ohci, DeviceState *dev,
1668 int num_ports, uint32_t localmem_base)
1669 {
1670 int i;
1671
1672 if (usb_frame_time == 0) {
1673 #ifdef OHCI_TIME_WARP
1674 usb_frame_time = get_ticks_per_sec();
1675 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ/1000);
1676 #else
1677 usb_frame_time = muldiv64(1, get_ticks_per_sec(), 1000);
1678 if (get_ticks_per_sec() >= USB_HZ) {
1679 usb_bit_time = muldiv64(1, get_ticks_per_sec(), USB_HZ);
1680 } else {
1681 usb_bit_time = 1;
1682 }
1683 #endif
1684 DPRINTF("usb-ohci: usb_bit_time=%" PRId64 " usb_frame_time=%" PRId64 "\n",
1685 usb_frame_time, usb_bit_time);
1686 }
1687
1688 ohci->mem = cpu_register_io_memory(ohci_readfn, ohci_writefn, ohci,
1689 DEVICE_LITTLE_ENDIAN);
1690 ohci->localmem_base = localmem_base;
1691
1692 ohci->name = dev->info->name;
1693
1694 usb_bus_new(&ohci->bus, dev);
1695 ohci->num_ports = num_ports;
1696 for (i = 0; i < num_ports; i++) {
1697 usb_register_port(&ohci->bus, &ohci->rhport[i].port, ohci, i, &ohci_port_ops,
1698 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1699 usb_port_location(&ohci->rhport[i].port, NULL, i+1);
1700 }
1701
1702 ohci->async_td = 0;
1703 qemu_register_reset(ohci_reset, ohci);
1704 }
1705
1706 typedef struct {
1707 PCIDevice pci_dev;
1708 OHCIState state;
1709 } OHCIPCIState;
1710
1711 static int usb_ohci_initfn_pci(struct PCIDevice *dev)
1712 {
1713 OHCIPCIState *ohci = DO_UPCAST(OHCIPCIState, pci_dev, dev);
1714 int num_ports = 3;
1715
1716 pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
1717 pci_config_set_device_id(ohci->pci_dev.config,
1718 PCI_DEVICE_ID_APPLE_IPID_USB);
1719 ohci->pci_dev.config[PCI_CLASS_PROG] = 0x10; /* OHCI */
1720 pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
1721 /* TODO: RST# value should be 0. */
1722 ohci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
1723
1724 usb_ohci_init(&ohci->state, &dev->qdev, num_ports, 0);
1725 ohci->state.irq = ohci->pci_dev.irq[0];
1726
1727 /* TODO: avoid cast below by using dev */
1728 pci_register_bar_simple(&ohci->pci_dev, 0, 256, 0, ohci->state.mem);
1729 return 0;
1730 }
1731
1732 void usb_ohci_init_pci(struct PCIBus *bus, int devfn)
1733 {
1734 pci_create_simple(bus, devfn, "pci-ohci");
1735 }
1736
1737 typedef struct {
1738 SysBusDevice busdev;
1739 OHCIState ohci;
1740 uint32_t num_ports;
1741 target_phys_addr_t dma_offset;
1742 } OHCISysBusState;
1743
1744 static int ohci_init_pxa(SysBusDevice *dev)
1745 {
1746 OHCISysBusState *s = FROM_SYSBUS(OHCISysBusState, dev);
1747
1748 usb_ohci_init(&s->ohci, &dev->qdev, s->num_ports, s->dma_offset);
1749 sysbus_init_irq(dev, &s->ohci.irq);
1750 sysbus_init_mmio(dev, 0x1000, s->ohci.mem);
1751
1752 return 0;
1753 }
1754
1755 static PCIDeviceInfo ohci_pci_info = {
1756 .qdev.name = "pci-ohci",
1757 .qdev.desc = "Apple USB Controller",
1758 .qdev.size = sizeof(OHCIPCIState),
1759 .init = usb_ohci_initfn_pci,
1760 };
1761
1762 static SysBusDeviceInfo ohci_sysbus_info = {
1763 .init = ohci_init_pxa,
1764 .qdev.name = "sysbus-ohci",
1765 .qdev.desc = "OHCI USB Controller",
1766 .qdev.size = sizeof(OHCISysBusState),
1767 .qdev.props = (Property[]) {
1768 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
1769 DEFINE_PROP_TADDR("dma-offset", OHCISysBusState, dma_offset, 3),
1770 DEFINE_PROP_END_OF_LIST(),
1771 }
1772 };
1773
1774 static void ohci_register(void)
1775 {
1776 pci_qdev_register(&ohci_pci_info);
1777 sysbus_register_withprop(&ohci_sysbus_info);
1778 }
1779 device_init(ohci_register);
QEmu