2 * RISC-V emulation for qemu: main translation routines.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
34 /* global register indices */
35 static TCGv cpu_gpr
[32], cpu_pc
, cpu_vl
;
36 static TCGv_i64 cpu_fpr
[32]; /* assume F and D extensions */
40 #include "exec/gen-icount.h"
43 * If an operation is being performed on less than TARGET_LONG_BITS,
44 * it may require the inputs to be sign- or zero-extended; which will
45 * depend on the exact operation being performed.
53 typedef struct DisasContext
{
54 DisasContextBase base
;
55 /* pc_succ_insn points to the instruction following base.pc_next */
56 target_ulong pc_succ_insn
;
57 target_ulong priv_ver
;
62 /* Remember the rounding mode encoded in the previous fp instruction,
63 which we have already installed into env->fp_status. Or -1 for
64 no previous fp instruction. Note that we exit the TB when writing
65 to any system register, which includes CSR_FRM, so we do not have
66 to reset this known value. */
72 /* vector extension */
82 /* Space for 3 operands plus 1 extra for address computation. */
86 static inline bool has_ext(DisasContext
*ctx
, uint32_t ext
)
88 return ctx
->misa
& ext
;
92 # define is_32bit(ctx) true
93 #elif defined(CONFIG_USER_ONLY)
94 # define is_32bit(ctx) false
96 static inline bool is_32bit(DisasContext
*ctx
)
98 return (ctx
->misa
& RV32
) == RV32
;
102 /* The word size for this operation. */
103 static inline int oper_len(DisasContext
*ctx
)
105 return ctx
->w
? 32 : TARGET_LONG_BITS
;
110 * RISC-V requires NaN-boxing of narrower width floating point values.
111 * This applies when a 32-bit value is assigned to a 64-bit FP register.
112 * For consistency and simplicity, we nanbox results even when the RVD
113 * extension is not present.
115 static void gen_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
117 tcg_gen_ori_i64(out
, in
, MAKE_64BIT_MASK(32, 32));
121 * A narrow n-bit operation, where n < FLEN, checks that input operands
122 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
123 * If so, the least-significant bits of the input are used, otherwise the
124 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
126 * Here, the result is always nan-boxed, even the canonical nan.
128 static void gen_check_nanbox_s(TCGv_i64 out
, TCGv_i64 in
)
130 TCGv_i64 t_max
= tcg_constant_i64(0xffffffff00000000ull
);
131 TCGv_i64 t_nan
= tcg_constant_i64(0xffffffff7fc00000ull
);
133 tcg_gen_movcond_i64(TCG_COND_GEU
, out
, in
, t_max
, in
, t_nan
);
136 static void generate_exception(DisasContext
*ctx
, int excp
)
138 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
139 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
140 ctx
->base
.is_jmp
= DISAS_NORETURN
;
143 static void generate_exception_mtval(DisasContext
*ctx
, int excp
)
145 tcg_gen_movi_tl(cpu_pc
, ctx
->base
.pc_next
);
146 tcg_gen_st_tl(cpu_pc
, cpu_env
, offsetof(CPURISCVState
, badaddr
));
147 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
148 ctx
->base
.is_jmp
= DISAS_NORETURN
;
151 static void gen_exception_debug(void)
153 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(EXCP_DEBUG
));
156 /* Wrapper around tcg_gen_exit_tb that handles single stepping */
157 static void exit_tb(DisasContext
*ctx
)
159 if (ctx
->base
.singlestep_enabled
) {
160 gen_exception_debug();
162 tcg_gen_exit_tb(NULL
, 0);
166 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
167 static void lookup_and_goto_ptr(DisasContext
*ctx
)
169 if (ctx
->base
.singlestep_enabled
) {
170 gen_exception_debug();
172 tcg_gen_lookup_and_goto_ptr();
176 static void gen_exception_illegal(DisasContext
*ctx
)
178 generate_exception(ctx
, RISCV_EXCP_ILLEGAL_INST
);
181 static void gen_exception_inst_addr_mis(DisasContext
*ctx
)
183 generate_exception_mtval(ctx
, RISCV_EXCP_INST_ADDR_MIS
);
186 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
188 if (translator_use_goto_tb(&ctx
->base
, dest
)) {
190 tcg_gen_movi_tl(cpu_pc
, dest
);
191 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
193 tcg_gen_movi_tl(cpu_pc
, dest
);
194 lookup_and_goto_ptr(ctx
);
199 * Wrappers for getting reg values.
201 * The $zero register does not have cpu_gpr[0] allocated -- we supply the
202 * constant zero as a source, and an uninitialized sink as destination.
204 * Further, we may provide an extension for word operations.
206 static TCGv
temp_new(DisasContext
*ctx
)
208 assert(ctx
->ntemp
< ARRAY_SIZE(ctx
->temp
));
209 return ctx
->temp
[ctx
->ntemp
++] = tcg_temp_new();
212 static TCGv
get_gpr(DisasContext
*ctx
, int reg_num
, DisasExtend ext
)
220 switch (ctx
->w
? ext
: EXT_NONE
) {
222 return cpu_gpr
[reg_num
];
225 tcg_gen_ext32s_tl(t
, cpu_gpr
[reg_num
]);
229 tcg_gen_ext32u_tl(t
, cpu_gpr
[reg_num
]);
232 g_assert_not_reached();
235 static TCGv
dest_gpr(DisasContext
*ctx
, int reg_num
)
237 if (reg_num
== 0 || ctx
->w
) {
238 return temp_new(ctx
);
240 return cpu_gpr
[reg_num
];
243 static void gen_set_gpr(DisasContext
*ctx
, int reg_num
, TCGv t
)
247 tcg_gen_ext32s_tl(cpu_gpr
[reg_num
], t
);
249 tcg_gen_mov_tl(cpu_gpr
[reg_num
], t
);
254 static void gen_jal(DisasContext
*ctx
, int rd
, target_ulong imm
)
256 target_ulong next_pc
;
258 /* check misaligned: */
259 next_pc
= ctx
->base
.pc_next
+ imm
;
260 if (!has_ext(ctx
, RVC
)) {
261 if ((next_pc
& 0x3) != 0) {
262 gen_exception_inst_addr_mis(ctx
);
267 tcg_gen_movi_tl(cpu_gpr
[rd
], ctx
->pc_succ_insn
);
270 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ imm
); /* must use this for safety */
271 ctx
->base
.is_jmp
= DISAS_NORETURN
;
274 #ifndef CONFIG_USER_ONLY
275 /* The states of mstatus_fs are:
276 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
277 * We will have already diagnosed disabled state,
278 * and need to turn initial/clean into dirty.
280 static void mark_fs_dirty(DisasContext
*ctx
)
285 if (ctx
->mstatus_fs
== MSTATUS_FS
) {
288 /* Remember the state change for the rest of the TB. */
289 ctx
->mstatus_fs
= MSTATUS_FS
;
291 tmp
= tcg_temp_new();
292 sd
= is_32bit(ctx
) ? MSTATUS32_SD
: MSTATUS64_SD
;
294 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
295 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
| sd
);
296 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus
));
298 if (ctx
->virt_enabled
) {
299 tcg_gen_ld_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
300 tcg_gen_ori_tl(tmp
, tmp
, MSTATUS_FS
| sd
);
301 tcg_gen_st_tl(tmp
, cpu_env
, offsetof(CPURISCVState
, mstatus_hs
));
306 static inline void mark_fs_dirty(DisasContext
*ctx
) { }
309 static void gen_set_rm(DisasContext
*ctx
, int rm
)
311 if (ctx
->frm
== rm
) {
315 gen_helper_set_rounding_mode(cpu_env
, tcg_constant_i32(rm
));
318 static int ex_plus_1(DisasContext
*ctx
, int nf
)
323 #define EX_SH(amount) \
324 static int ex_shift_##amount(DisasContext *ctx, int imm) \
326 return imm << amount; \
334 #define REQUIRE_EXT(ctx, ext) do { \
335 if (!has_ext(ctx, ext)) { \
340 #define REQUIRE_64BIT(ctx) do { \
341 if (is_32bit(ctx)) { \
346 static int ex_rvc_register(DisasContext
*ctx
, int reg
)
351 static int ex_rvc_shifti(DisasContext
*ctx
, int imm
)
353 /* For RV128 a shamt of 0 means a shift by 64. */
354 return imm
? imm
: 64;
357 /* Include the auto-generated decoder for 32 bit insn */
358 #include "decode-insn32.c.inc"
360 static bool gen_arith_imm_fn(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
361 void (*func
)(TCGv
, TCGv
, target_long
))
363 TCGv dest
= dest_gpr(ctx
, a
->rd
);
364 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
366 func(dest
, src1
, a
->imm
);
368 gen_set_gpr(ctx
, a
->rd
, dest
);
372 static bool gen_arith_imm_tl(DisasContext
*ctx
, arg_i
*a
, DisasExtend ext
,
373 void (*func
)(TCGv
, TCGv
, TCGv
))
375 TCGv dest
= dest_gpr(ctx
, a
->rd
);
376 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
377 TCGv src2
= tcg_constant_tl(a
->imm
);
379 func(dest
, src1
, src2
);
381 gen_set_gpr(ctx
, a
->rd
, dest
);
385 static bool gen_arith(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
386 void (*func
)(TCGv
, TCGv
, TCGv
))
388 TCGv dest
= dest_gpr(ctx
, a
->rd
);
389 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
390 TCGv src2
= get_gpr(ctx
, a
->rs2
, ext
);
392 func(dest
, src1
, src2
);
394 gen_set_gpr(ctx
, a
->rd
, dest
);
398 static bool gen_shift_imm_fn(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
399 void (*func
)(TCGv
, TCGv
, target_long
))
402 int max_len
= oper_len(ctx
);
404 if (a
->shamt
>= max_len
) {
408 dest
= dest_gpr(ctx
, a
->rd
);
409 src1
= get_gpr(ctx
, a
->rs1
, ext
);
411 func(dest
, src1
, a
->shamt
);
413 gen_set_gpr(ctx
, a
->rd
, dest
);
417 static bool gen_shift_imm_tl(DisasContext
*ctx
, arg_shift
*a
, DisasExtend ext
,
418 void (*func
)(TCGv
, TCGv
, TCGv
))
420 TCGv dest
, src1
, src2
;
421 int max_len
= oper_len(ctx
);
423 if (a
->shamt
>= max_len
) {
427 dest
= dest_gpr(ctx
, a
->rd
);
428 src1
= get_gpr(ctx
, a
->rs1
, ext
);
429 src2
= tcg_constant_tl(a
->shamt
);
431 func(dest
, src1
, src2
);
433 gen_set_gpr(ctx
, a
->rd
, dest
);
437 static bool gen_shift(DisasContext
*ctx
, arg_r
*a
, DisasExtend ext
,
438 void (*func
)(TCGv
, TCGv
, TCGv
))
440 TCGv dest
= dest_gpr(ctx
, a
->rd
);
441 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
442 TCGv src2
= get_gpr(ctx
, a
->rs2
, EXT_NONE
);
443 TCGv ext2
= tcg_temp_new();
445 tcg_gen_andi_tl(ext2
, src2
, oper_len(ctx
) - 1);
446 func(dest
, src1
, ext2
);
448 gen_set_gpr(ctx
, a
->rd
, dest
);
453 static bool gen_unary(DisasContext
*ctx
, arg_r2
*a
, DisasExtend ext
,
454 void (*func
)(TCGv
, TCGv
))
456 TCGv dest
= dest_gpr(ctx
, a
->rd
);
457 TCGv src1
= get_gpr(ctx
, a
->rs1
, ext
);
461 gen_set_gpr(ctx
, a
->rd
, dest
);
465 static uint32_t opcode_at(DisasContextBase
*dcbase
, target_ulong pc
)
467 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
468 CPUState
*cpu
= ctx
->cs
;
469 CPURISCVState
*env
= cpu
->env_ptr
;
471 return cpu_ldl_code(env
, pc
);
474 /* Include insn module translation function */
475 #include "insn_trans/trans_rvi.c.inc"
476 #include "insn_trans/trans_rvm.c.inc"
477 #include "insn_trans/trans_rva.c.inc"
478 #include "insn_trans/trans_rvf.c.inc"
479 #include "insn_trans/trans_rvd.c.inc"
480 #include "insn_trans/trans_rvh.c.inc"
481 #include "insn_trans/trans_rvv.c.inc"
482 #include "insn_trans/trans_rvb.c.inc"
483 #include "insn_trans/trans_privileged.c.inc"
485 /* Include the auto-generated decoder for 16 bit insn */
486 #include "decode-insn16.c.inc"
488 static void decode_opc(CPURISCVState
*env
, DisasContext
*ctx
, uint16_t opcode
)
490 /* check for compressed insn */
491 if (extract16(opcode
, 0, 2) != 3) {
492 if (!has_ext(ctx
, RVC
)) {
493 gen_exception_illegal(ctx
);
495 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 2;
496 if (!decode_insn16(ctx
, opcode
)) {
497 gen_exception_illegal(ctx
);
501 uint32_t opcode32
= opcode
;
502 opcode32
= deposit32(opcode32
, 16, 16,
503 translator_lduw(env
, ctx
->base
.pc_next
+ 2));
504 ctx
->pc_succ_insn
= ctx
->base
.pc_next
+ 4;
505 if (!decode_insn32(ctx
, opcode32
)) {
506 gen_exception_illegal(ctx
);
511 static void riscv_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
513 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
514 CPURISCVState
*env
= cs
->env_ptr
;
515 RISCVCPU
*cpu
= RISCV_CPU(cs
);
516 uint32_t tb_flags
= ctx
->base
.tb
->flags
;
518 ctx
->pc_succ_insn
= ctx
->base
.pc_first
;
519 ctx
->mem_idx
= tb_flags
& TB_FLAGS_MMU_MASK
;
520 ctx
->mstatus_fs
= tb_flags
& TB_FLAGS_MSTATUS_FS
;
521 ctx
->priv_ver
= env
->priv_ver
;
522 #if !defined(CONFIG_USER_ONLY)
523 if (riscv_has_ext(env
, RVH
)) {
524 ctx
->virt_enabled
= riscv_cpu_virt_enabled(env
);
526 ctx
->virt_enabled
= false;
529 ctx
->virt_enabled
= false;
531 ctx
->misa
= env
->misa
;
532 ctx
->frm
= -1; /* unknown rounding mode */
533 ctx
->ext_ifencei
= cpu
->cfg
.ext_ifencei
;
534 ctx
->vlen
= cpu
->cfg
.vlen
;
535 ctx
->hlsx
= FIELD_EX32(tb_flags
, TB_FLAGS
, HLSX
);
536 ctx
->vill
= FIELD_EX32(tb_flags
, TB_FLAGS
, VILL
);
537 ctx
->sew
= FIELD_EX32(tb_flags
, TB_FLAGS
, SEW
);
538 ctx
->lmul
= FIELD_EX32(tb_flags
, TB_FLAGS
, LMUL
);
539 ctx
->mlen
= 1 << (ctx
->sew
+ 3 - ctx
->lmul
);
540 ctx
->vl_eq_vlmax
= FIELD_EX32(tb_flags
, TB_FLAGS
, VL_EQ_VLMAX
);
544 memset(ctx
->temp
, 0, sizeof(ctx
->temp
));
546 ctx
->zero
= tcg_constant_tl(0);
549 static void riscv_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
553 static void riscv_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
555 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
557 tcg_gen_insn_start(ctx
->base
.pc_next
);
560 static void riscv_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
562 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
563 CPURISCVState
*env
= cpu
->env_ptr
;
564 uint16_t opcode16
= translator_lduw(env
, ctx
->base
.pc_next
);
566 decode_opc(env
, ctx
, opcode16
);
567 ctx
->base
.pc_next
= ctx
->pc_succ_insn
;
570 for (int i
= ctx
->ntemp
- 1; i
>= 0; --i
) {
571 tcg_temp_free(ctx
->temp
[i
]);
576 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
577 target_ulong page_start
;
579 page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
580 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
) {
581 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
586 static void riscv_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
588 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
590 switch (ctx
->base
.is_jmp
) {
592 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
597 g_assert_not_reached();
601 static void riscv_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cpu
)
603 #ifndef CONFIG_USER_ONLY
604 RISCVCPU
*rvcpu
= RISCV_CPU(cpu
);
605 CPURISCVState
*env
= &rvcpu
->env
;
608 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
609 #ifndef CONFIG_USER_ONLY
610 qemu_log("Priv: "TARGET_FMT_ld
"; Virt: "TARGET_FMT_ld
"\n", env
->priv
, env
->virt
);
612 log_target_disas(cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
615 static const TranslatorOps riscv_tr_ops
= {
616 .init_disas_context
= riscv_tr_init_disas_context
,
617 .tb_start
= riscv_tr_tb_start
,
618 .insn_start
= riscv_tr_insn_start
,
619 .translate_insn
= riscv_tr_translate_insn
,
620 .tb_stop
= riscv_tr_tb_stop
,
621 .disas_log
= riscv_tr_disas_log
,
624 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
628 translator_loop(&riscv_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
631 void riscv_translate_init(void)
636 * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
637 * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
638 * unless you specifically block reads/writes to reg 0.
642 for (i
= 1; i
< 32; i
++) {
643 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
644 offsetof(CPURISCVState
, gpr
[i
]), riscv_int_regnames
[i
]);
647 for (i
= 0; i
< 32; i
++) {
648 cpu_fpr
[i
] = tcg_global_mem_new_i64(cpu_env
,
649 offsetof(CPURISCVState
, fpr
[i
]), riscv_fpr_regnames
[i
]);
652 cpu_pc
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, pc
), "pc");
653 cpu_vl
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, vl
), "vl");
654 load_res
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_res
),
656 load_val
= tcg_global_mem_new(cpu_env
, offsetof(CPURISCVState
, load_val
),