include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "hw/qdev.h"
   5 #include "exec/memory.h"
   6 #include "sysemu/dma.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "hw/isa/isa.h"
  10
  11 #include "hw/pci/pcie.h"
  12
  13 extern bool pci_available;
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
  19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  21 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
  22 #define PCI_BUS_MAX             256
  23 #define PCI_DEVFN_MAX           256
  24 #define PCI_SLOT_MAX            32
  25 #define PCI_FUNC_MAX            8
  26
  27 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  28 #include "hw/pci/pci_ids.h"
  29
  30 /* QEMU-specific Vendor and Device ID definitions */
  31
  32 /* IBM (0x1014) */
  33 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  34 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  35
  36 /* Hitachi (0x1054) */
  37 #define PCI_VENDOR_ID_HITACHI            0x1054
  38 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  39
  40 /* Apple (0x106b) */
  41 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  42 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  43 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  44 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  45 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  46
  47 /* Realtek (0x10ec) */
  48 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  49
  50 /* Xilinx (0x10ee) */
  51 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  52
  53 /* Marvell (0x11ab) */
  54 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  55
  56 /* QEMU/Bochs VGA (0x1234) */
  57 #define PCI_VENDOR_ID_QEMU               0x1234
  58 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  59
  60 /* VMWare (0x15ad) */
  61 #define PCI_VENDOR_ID_VMWARE             0x15ad
  62 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  63 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  64 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  65 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  66 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  67 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  68 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  69
  70 /* Intel (0x8086) */
  71 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  72 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  73 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  74
  75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  76 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  78 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  79
  80 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  81 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  82 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  83 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  84 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  85 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  86 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  87 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
  88
  89 #define PCI_VENDOR_ID_REDHAT             0x1b36
  90 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  91 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  92 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  93 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  94 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  95 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
  96 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
  97 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
  98 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
  99 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
 100 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
 101 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
 102 #define PCI_DEVICE_ID_REDHAT_XHCI        0x000d
 103 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
 104 #define PCI_DEVICE_ID_REDHAT_MDPY        0x000f
 105 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
 106
 107 #define FMT_PCIBUS                      PRIx64
 108
 109 typedef uint64_t pcibus_t;
 110
 111 struct PCIHostDeviceAddress {
 112     unsigned int domain;
 113     unsigned int bus;
 114     unsigned int slot;
 115     unsigned int function;
 116 };
 117
 118 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 119                                 uint32_t address, uint32_t data, int len);
 120 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 121                                    uint32_t address, int len);
 122 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 123                                 pcibus_t addr, pcibus_t size, int type);
 124 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 125
 126 typedef struct PCIIORegion {
 127     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 128 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 129     pcibus_t size;
 130     uint8_t type;
 131     MemoryRegion *memory;
 132     MemoryRegion *address_space;
 133 } PCIIORegion;
 134
 135 #define PCI_ROM_SLOT 6
 136 #define PCI_NUM_REGIONS 7
 137
 138 enum {
 139     QEMU_PCI_VGA_MEM,
 140     QEMU_PCI_VGA_IO_LO,
 141     QEMU_PCI_VGA_IO_HI,
 142     QEMU_PCI_VGA_NUM_REGIONS,
 143 };
 144
 145 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 146 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 147 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 148 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 149 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 150 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 151
 152 #include "hw/pci/pci_regs.h"
 153
 154 /* PCI HEADER_TYPE */
 155 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 156
 157 /* Size of the standard PCI config header */
 158 #define PCI_CONFIG_HEADER_SIZE 0x40
 159 /* Size of the standard PCI config space */
 160 #define PCI_CONFIG_SPACE_SIZE 0x100
 161 /* Size of the standard PCIe config space: 4KB */
 162 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 163
 164 #define PCI_NUM_PINS 4 /* A-D */
 165
 166 /* Bits in cap_present field. */
 167 enum {
 168     QEMU_PCI_CAP_MSI = 0x1,
 169     QEMU_PCI_CAP_MSIX = 0x2,
 170     QEMU_PCI_CAP_EXPRESS = 0x4,
 171
 172     /* multifunction capable device */
 173 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 174     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 175
 176     /* command register SERR bit enabled */
 177 #define QEMU_PCI_CAP_SERR_BITNR 4
 178     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 179     /* Standard hot plug controller. */
 180 #define QEMU_PCI_SHPC_BITNR 5
 181     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 182 #define QEMU_PCI_SLOTID_BITNR 6
 183     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 184     /* PCI Express capability - Power Controller Present */
 185 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 186     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 187     /* Link active status in endpoint capability is always set */
 188 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
 189     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
 190 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
 191     QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
 192 };
 193
 194 #define TYPE_PCI_DEVICE "pci-device"
 195 #define PCI_DEVICE(obj) \
 196      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 197 #define PCI_DEVICE_CLASS(klass) \
 198      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 199 #define PCI_DEVICE_GET_CLASS(obj) \
 200      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 201
 202 /* Implemented by devices that can be plugged on PCI Express buses */
 203 #define INTERFACE_PCIE_DEVICE "pci-express-device"
 204
 205 /* Implemented by devices that can be plugged on Conventional PCI buses */
 206 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
 207
 208 typedef struct PCIINTxRoute {
 209     enum {
 210         PCI_INTX_ENABLED,
 211         PCI_INTX_INVERTED,
 212         PCI_INTX_DISABLED,
 213     } mode;
 214     int irq;
 215 } PCIINTxRoute;
 216
 217 typedef struct PCIDeviceClass {
 218     DeviceClass parent_class;
 219
 220     void (*realize)(PCIDevice *dev, Error **errp);
 221     PCIUnregisterFunc *exit;
 222     PCIConfigReadFunc *config_read;
 223     PCIConfigWriteFunc *config_write;
 224
 225     uint16_t vendor_id;
 226     uint16_t device_id;
 227     uint8_t revision;
 228     uint16_t class_id;
 229     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 230     uint16_t subsystem_id;              /* only for header type = 0 */
 231
 232     /*
 233      * pci-to-pci bridge or normal device.
 234      * This doesn't mean pci host switch.
 235      * When card bus bridge is supported, this would be enhanced.
 236      */
 237     int is_bridge;
 238
 239     /* rom bar */
 240     const char *romfile;
 241 } PCIDeviceClass;
 242
 243 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 244 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 245                                       MSIMessage msg);
 246 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 247 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 248                                       unsigned int vector_start,
 249                                       unsigned int vector_end);
 250
 251 enum PCIReqIDType {
 252     PCI_REQ_ID_INVALID = 0,
 253     PCI_REQ_ID_BDF,
 254     PCI_REQ_ID_SECONDARY_BUS,
 255     PCI_REQ_ID_MAX,
 256 };
 257 typedef enum PCIReqIDType PCIReqIDType;
 258
 259 struct PCIReqIDCache {
 260     PCIDevice *dev;
 261     PCIReqIDType type;
 262 };
 263 typedef struct PCIReqIDCache PCIReqIDCache;
 264
 265 struct PCIDevice {
 266     DeviceState qdev;
 267
 268     /* PCI config space */
 269     uint8_t *config;
 270
 271     /* Used to enable config checks on load. Note that writable bits are
 272      * never checked even if set in cmask. */
 273     uint8_t *cmask;
 274
 275     /* Used to implement R/W bytes */
 276     uint8_t *wmask;
 277
 278     /* Used to implement RW1C(Write 1 to Clear) bytes */
 279     uint8_t *w1cmask;
 280
 281     /* Used to allocate config space for capabilities. */
 282     uint8_t *used;
 283
 284     /* the following fields are read only */
 285     int32_t devfn;
 286     /* Cached device to fetch requester ID from, to avoid the PCI
 287      * tree walking every time we invoke PCI request (e.g.,
 288      * MSI). For conventional PCI root complex, this field is
 289      * meaningless. */
 290     PCIReqIDCache requester_id_cache;
 291     char name[64];
 292     PCIIORegion io_regions[PCI_NUM_REGIONS];
 293     AddressSpace bus_master_as;
 294     MemoryRegion bus_master_container_region;
 295     MemoryRegion bus_master_enable_region;
 296
 297     /* do not access the following fields */
 298     PCIConfigReadFunc *config_read;
 299     PCIConfigWriteFunc *config_write;
 300
 301     /* Legacy PCI VGA regions */
 302     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 303     bool has_vga;
 304
 305     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 306     uint8_t irq_state;
 307
 308     /* Capability bits */
 309     uint32_t cap_present;
 310
 311     /* Offset of MSI-X capability in config space */
 312     uint8_t msix_cap;
 313
 314     /* MSI-X entries */
 315     int msix_entries_nr;
 316
 317     /* Space to store MSIX table & pending bit array */
 318     uint8_t *msix_table;
 319     uint8_t *msix_pba;
 320     /* MemoryRegion container for msix exclusive BAR setup */
 321     MemoryRegion msix_exclusive_bar;
 322     /* Memory Regions for MSIX table and pending bit entries. */
 323     MemoryRegion msix_table_mmio;
 324     MemoryRegion msix_pba_mmio;
 325     /* Reference-count for entries actually in use by driver. */
 326     unsigned *msix_entry_used;
 327     /* MSIX function mask set or MSIX disabled */
 328     bool msix_function_masked;
 329     /* Version id needed for VMState */
 330     int32_t version_id;
 331
 332     /* Offset of MSI capability in config space */
 333     uint8_t msi_cap;
 334
 335     /* PCI Express */
 336     PCIExpressDevice exp;
 337
 338     /* SHPC */
 339     SHPCDevice *shpc;
 340
 341     /* Location of option rom */
 342     char *romfile;
 343     bool has_rom;
 344     MemoryRegion rom;
 345     uint32_t rom_bar;
 346
 347     /* INTx routing notifier */
 348     PCIINTxRoutingNotifier intx_routing_notifier;
 349
 350     /* MSI-X notifiers */
 351     MSIVectorUseNotifier msix_vector_use_notifier;
 352     MSIVectorReleaseNotifier msix_vector_release_notifier;
 353     MSIVectorPollNotifier msix_vector_poll_notifier;
 354 };
 355
 356 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 357                       uint8_t attr, MemoryRegion *memory);
 358 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 359                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 360 void pci_unregister_vga(PCIDevice *pci_dev);
 361 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 362
 363 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 364                        uint8_t offset, uint8_t size,
 365                        Error **errp);
 366
 367 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 368
 369 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 370
 371
 372 uint32_t pci_default_read_config(PCIDevice *d,
 373                                  uint32_t address, int len);
 374 void pci_default_write_config(PCIDevice *d,
 375                               uint32_t address, uint32_t val, int len);
 376 void pci_device_save(PCIDevice *s, QEMUFile *f);
 377 int pci_device_load(PCIDevice *s, QEMUFile *f);
 378 MemoryRegion *pci_address_space(PCIDevice *dev);
 379 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 380
 381 /*
 382  * Should not normally be used by devices. For use by sPAPR target
 383  * where QEMU emulates firmware.
 384  */
 385 int pci_bar(PCIDevice *d, int reg);
 386
 387 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 388 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 389 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 390
 391 #define TYPE_PCI_BUS "PCI"
 392 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 393 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
 394 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
 395 #define TYPE_PCIE_BUS "PCIE"
 396
 397 bool pci_bus_is_express(PCIBus *bus);
 398 bool pci_bus_is_root(PCIBus *bus);
 399 void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
 400                               const char *name,
 401                               MemoryRegion *address_space_mem,
 402                               MemoryRegion *address_space_io,
 403                               uint8_t devfn_min, const char *typename);
 404 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
 405                          MemoryRegion *address_space_mem,
 406                          MemoryRegion *address_space_io,
 407                          uint8_t devfn_min, const char *typename);
 408 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 409                   void *irq_opaque, int nirq);
 410 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 411 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 412 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 413 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
 414                               pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 415                               void *irq_opaque,
 416                               MemoryRegion *address_space_mem,
 417                               MemoryRegion *address_space_io,
 418                               uint8_t devfn_min, int nirq,
 419                               const char *typename);
 420 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 421 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 422 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 423 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 424 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 425                                           PCIINTxRoutingNotifier notifier);
 426 void pci_device_reset(PCIDevice *dev);
 427
 428 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 429                                const char *default_model,
 430                                const char *default_devaddr);
 431
 432 PCIDevice *pci_vga_init(PCIBus *bus);
 433
 434 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
 435 {
 436     return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
 437 }
 438 int pci_bus_num(PCIBus *s);
 439 static inline int pci_dev_bus_num(const PCIDevice *dev)
 440 {
 441     return pci_bus_num(pci_get_bus(dev));
 442 }
 443
 444 int pci_bus_numa_node(PCIBus *bus);
 445 void pci_for_each_device(PCIBus *bus, int bus_num,
 446                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 447                          void *opaque);
 448 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
 449                                  void (*fn)(PCIBus *bus, PCIDevice *d,
 450                                             void *opaque),
 451                                  void *opaque);
 452 void pci_for_each_bus_depth_first(PCIBus *bus,
 453                                   void *(*begin)(PCIBus *bus, void *parent_state),
 454                                   void (*end)(PCIBus *bus, void *state),
 455                                   void *parent_state);
 456 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
 457
 458 /* Use this wrapper when specific scan order is not required. */
 459 static inline
 460 void pci_for_each_bus(PCIBus *bus,
 461                       void (*fn)(PCIBus *bus, void *opaque),
 462                       void *opaque)
 463 {
 464     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 465 }
 466
 467 PCIBus *pci_device_root_bus(const PCIDevice *d);
 468 const char *pci_root_bus_path(PCIDevice *dev);
 469 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 470 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 471 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 472
 473 void pci_device_deassert_intx(PCIDevice *dev);
 474
 475 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 476
 477 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 478 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 479
 480 static inline void
 481 pci_set_byte(uint8_t *config, uint8_t val)
 482 {
 483     *config = val;
 484 }
 485
 486 static inline uint8_t
 487 pci_get_byte(const uint8_t *config)
 488 {
 489     return *config;
 490 }
 491
 492 static inline void
 493 pci_set_word(uint8_t *config, uint16_t val)
 494 {
 495     stw_le_p(config, val);
 496 }
 497
 498 static inline uint16_t
 499 pci_get_word(const uint8_t *config)
 500 {
 501     return lduw_le_p(config);
 502 }
 503
 504 static inline void
 505 pci_set_long(uint8_t *config, uint32_t val)
 506 {
 507     stl_le_p(config, val);
 508 }
 509
 510 static inline uint32_t
 511 pci_get_long(const uint8_t *config)
 512 {
 513     return ldl_le_p(config);
 514 }
 515
 516 /*
 517  * PCI capabilities and/or their fields
 518  * are generally DWORD aligned only so
 519  * mechanism used by pci_set/get_quad()
 520  * must be tolerant to unaligned pointers
 521  *
 522  */
 523 static inline void
 524 pci_set_quad(uint8_t *config, uint64_t val)
 525 {
 526     stq_le_p(config, val);
 527 }
 528
 529 static inline uint64_t
 530 pci_get_quad(const uint8_t *config)
 531 {
 532     return ldq_le_p(config);
 533 }
 534
 535 static inline void
 536 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 537 {
 538     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 539 }
 540
 541 static inline void
 542 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 543 {
 544     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 545 }
 546
 547 static inline void
 548 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 549 {
 550     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 551 }
 552
 553 static inline void
 554 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 555 {
 556     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 557 }
 558
 559 static inline void
 560 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 561 {
 562     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 563 }
 564
 565 static inline void
 566 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 567 {
 568     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 569 }
 570
 571 /*
 572  * helper functions to do bit mask operation on configuration space.
 573  * Just to set bit, use test-and-set and discard returned value.
 574  * Just to clear bit, use test-and-clear and discard returned value.
 575  * NOTE: They aren't atomic.
 576  */
 577 static inline uint8_t
 578 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 579 {
 580     uint8_t val = pci_get_byte(config);
 581     pci_set_byte(config, val & ~mask);
 582     return val & mask;
 583 }
 584
 585 static inline uint8_t
 586 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 587 {
 588     uint8_t val = pci_get_byte(config);
 589     pci_set_byte(config, val | mask);
 590     return val & mask;
 591 }
 592
 593 static inline uint16_t
 594 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 595 {
 596     uint16_t val = pci_get_word(config);
 597     pci_set_word(config, val & ~mask);
 598     return val & mask;
 599 }
 600
 601 static inline uint16_t
 602 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 603 {
 604     uint16_t val = pci_get_word(config);
 605     pci_set_word(config, val | mask);
 606     return val & mask;
 607 }
 608
 609 static inline uint32_t
 610 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 611 {
 612     uint32_t val = pci_get_long(config);
 613     pci_set_long(config, val & ~mask);
 614     return val & mask;
 615 }
 616
 617 static inline uint32_t
 618 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 619 {
 620     uint32_t val = pci_get_long(config);
 621     pci_set_long(config, val | mask);
 622     return val & mask;
 623 }
 624
 625 static inline uint64_t
 626 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 627 {
 628     uint64_t val = pci_get_quad(config);
 629     pci_set_quad(config, val & ~mask);
 630     return val & mask;
 631 }
 632
 633 static inline uint64_t
 634 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 635 {
 636     uint64_t val = pci_get_quad(config);
 637     pci_set_quad(config, val | mask);
 638     return val & mask;
 639 }
 640
 641 /* Access a register specified by a mask */
 642 static inline void
 643 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 644 {
 645     uint8_t val = pci_get_byte(config);
 646     uint8_t rval = reg << ctz32(mask);
 647     pci_set_byte(config, (~mask & val) | (mask & rval));
 648 }
 649
 650 static inline uint8_t
 651 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 652 {
 653     uint8_t val = pci_get_byte(config);
 654     return (val & mask) >> ctz32(mask);
 655 }
 656
 657 static inline void
 658 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 659 {
 660     uint16_t val = pci_get_word(config);
 661     uint16_t rval = reg << ctz32(mask);
 662     pci_set_word(config, (~mask & val) | (mask & rval));
 663 }
 664
 665 static inline uint16_t
 666 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 667 {
 668     uint16_t val = pci_get_word(config);
 669     return (val & mask) >> ctz32(mask);
 670 }
 671
 672 static inline void
 673 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 674 {
 675     uint32_t val = pci_get_long(config);
 676     uint32_t rval = reg << ctz32(mask);
 677     pci_set_long(config, (~mask & val) | (mask & rval));
 678 }
 679
 680 static inline uint32_t
 681 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 682 {
 683     uint32_t val = pci_get_long(config);
 684     return (val & mask) >> ctz32(mask);
 685 }
 686
 687 static inline void
 688 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 689 {
 690     uint64_t val = pci_get_quad(config);
 691     uint64_t rval = reg << ctz32(mask);
 692     pci_set_quad(config, (~mask & val) | (mask & rval));
 693 }
 694
 695 static inline uint64_t
 696 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 697 {
 698     uint64_t val = pci_get_quad(config);
 699     return (val & mask) >> ctz32(mask);
 700 }
 701
 702 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 703                                     const char *name);
 704 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 705                                            bool multifunction,
 706                                            const char *name);
 707 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 708 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 709
 710 void lsi53c895a_create(PCIBus *bus);
 711 void lsi53c810_create(PCIBus *bus, int devfn);
 712
 713 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 714 void pci_set_irq(PCIDevice *pci_dev, int level);
 715
 716 static inline void pci_irq_assert(PCIDevice *pci_dev)
 717 {
 718     pci_set_irq(pci_dev, 1);
 719 }
 720
 721 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 722 {
 723     pci_set_irq(pci_dev, 0);
 724 }
 725
 726 /*
 727  * FIXME: PCI does not work this way.
 728  * All the callers to this method should be fixed.
 729  */
 730 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 731 {
 732     pci_irq_assert(pci_dev);
 733     pci_irq_deassert(pci_dev);
 734 }
 735
 736 static inline int pci_is_express(const PCIDevice *d)
 737 {
 738     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 739 }
 740
 741 static inline uint32_t pci_config_size(const PCIDevice *d)
 742 {
 743     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 744 }
 745
 746 static inline uint16_t pci_get_bdf(PCIDevice *dev)
 747 {
 748     return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
 749 }
 750
 751 uint16_t pci_requester_id(PCIDevice *dev);
 752
 753 /* DMA access functions */
 754 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 755 {
 756     return &dev->bus_master_as;
 757 }
 758
 759 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 760                              void *buf, dma_addr_t len, DMADirection dir)
 761 {
 762     dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
 763     return 0;
 764 }
 765
 766 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 767                                void *buf, dma_addr_t len)
 768 {
 769     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 770 }
 771
 772 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 773                                 const void *buf, dma_addr_t len)
 774 {
 775     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 776 }
 777
 778 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 779     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 780                                                    dma_addr_t addr)     \
 781     {                                                                   \
 782         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
 783     }                                                                   \
 784     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 785                                         dma_addr_t addr, uint##_bits##_t val) \
 786     {                                                                   \
 787         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
 788     }
 789
 790 PCI_DMA_DEFINE_LDST(ub, b, 8);
 791 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 792 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 793 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 794 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 795 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 796 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 797
 798 #undef PCI_DMA_DEFINE_LDST
 799
 800 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 801                                 dma_addr_t *plen, DMADirection dir)
 802 {
 803     void *buf;
 804
 805     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
 806     return buf;
 807 }
 808
 809 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 810                                  DMADirection dir, dma_addr_t access_len)
 811 {
 812     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 813 }
 814
 815 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 816                                        int alloc_hint)
 817 {
 818     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 819 }
 820
 821 extern const VMStateDescription vmstate_pci_device;
 822
 823 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 824     .name       = (stringify(_field)),                               \
 825     .size       = sizeof(PCIDevice),                                 \
 826     .vmsd       = &vmstate_pci_device,                               \
 827     .flags      = VMS_STRUCT,                                        \
 828     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 829 }
 830
 831 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 832     .name       = (stringify(_field)),                               \
 833     .size       = sizeof(PCIDevice),                                 \
 834     .vmsd       = &vmstate_pci_device,                               \
 835     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 836     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 837 }
 838
 839 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
 840
 841 #endif