target/alpha/cpu.c

   1 /*
   2  * QEMU Alpha CPU
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "qemu/qemu-print.h"
  25 #include "cpu.h"
  26 #include "exec/exec-all.h"
  27
  28
  29 static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     AlphaCPU *cpu = ALPHA_CPU(cs);
  32
  33     cpu->env.pc = value;
  34 }
  35
  36 static vaddr alpha_cpu_get_pc(CPUState *cs)
  37 {
  38     AlphaCPU *cpu = ALPHA_CPU(cs);
  39
  40     return cpu->env.pc;
  41 }
  42
  43
  44 static bool alpha_cpu_has_work(CPUState *cs)
  45 {
  46     /* Here we are checking to see if the CPU should wake up from HALT.
  47        We will have gotten into this state only for WTINT from PALmode.  */
  48     /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
  49        asleep even if (some) interrupts have been asserted.  For now,
  50        assume that if a CPU really wants to stay asleep, it will mask
  51        interrupts at the chipset level, which will prevent these bits
  52        from being set in the first place.  */
  53     return cs->interrupt_request & (CPU_INTERRUPT_HARD
  54                                     | CPU_INTERRUPT_TIMER
  55                                     | CPU_INTERRUPT_SMP
  56                                     | CPU_INTERRUPT_MCHK);
  57 }
  58
  59 static void alpha_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  60 {
  61     info->mach = bfd_mach_alpha_ev6;
  62     info->print_insn = print_insn_alpha;
  63 }
  64
  65 static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
  66 {
  67     CPUState *cs = CPU(dev);
  68     AlphaCPUClass *acc = ALPHA_CPU_GET_CLASS(dev);
  69     Error *local_err = NULL;
  70
  71     cpu_exec_realizefn(cs, &local_err);
  72     if (local_err != NULL) {
  73         error_propagate(errp, local_err);
  74         return;
  75     }
  76
  77     qemu_init_vcpu(cs);
  78
  79     acc->parent_realize(dev, errp);
  80 }
  81
  82 static void alpha_cpu_list_entry(gpointer data, gpointer user_data)
  83 {
  84     ObjectClass *oc = data;
  85
  86     qemu_printf("  %s\n", object_class_get_name(oc));
  87 }
  88
  89 void alpha_cpu_list(void)
  90 {
  91     GSList *list;
  92
  93     list = object_class_get_list_sorted(TYPE_ALPHA_CPU, false);
  94     qemu_printf("Available CPUs:\n");
  95     g_slist_foreach(list, alpha_cpu_list_entry, NULL);
  96     g_slist_free(list);
  97 }
  98
  99 /* Models */
 100 typedef struct AlphaCPUAlias {
 101     const char *alias;
 102     const char *typename;
 103 } AlphaCPUAlias;
 104
 105 static const AlphaCPUAlias alpha_cpu_aliases[] = {
 106     { "21064",   ALPHA_CPU_TYPE_NAME("ev4") },
 107     { "21164",   ALPHA_CPU_TYPE_NAME("ev5") },
 108     { "21164a",  ALPHA_CPU_TYPE_NAME("ev56") },
 109     { "21164pc", ALPHA_CPU_TYPE_NAME("pca56") },
 110     { "21264",   ALPHA_CPU_TYPE_NAME("ev6") },
 111     { "21264a",  ALPHA_CPU_TYPE_NAME("ev67") },
 112 };
 113
 114 static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
 115 {
 116     ObjectClass *oc;
 117     char *typename;
 118     int i;
 119
 120     oc = object_class_by_name(cpu_model);
 121     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_ALPHA_CPU) != NULL &&
 122         !object_class_is_abstract(oc)) {
 123         return oc;
 124     }
 125
 126     for (i = 0; i < ARRAY_SIZE(alpha_cpu_aliases); i++) {
 127         if (strcmp(cpu_model, alpha_cpu_aliases[i].alias) == 0) {
 128             oc = object_class_by_name(alpha_cpu_aliases[i].typename);
 129             assert(oc != NULL && !object_class_is_abstract(oc));
 130             return oc;
 131         }
 132     }
 133
 134     typename = g_strdup_printf(ALPHA_CPU_TYPE_NAME("%s"), cpu_model);
 135     oc = object_class_by_name(typename);
 136     g_free(typename);
 137     if (oc != NULL && object_class_is_abstract(oc)) {
 138         oc = NULL;
 139     }
 140
 141     /* TODO: remove match everything nonsense */
 142     /* Default to ev67; no reason not to emulate insns by default. */
 143     if (!oc) {
 144         oc = object_class_by_name(ALPHA_CPU_TYPE_NAME("ev67"));
 145     }
 146
 147     return oc;
 148 }
 149
 150 static void ev4_cpu_initfn(Object *obj)
 151 {
 152     AlphaCPU *cpu = ALPHA_CPU(obj);
 153     CPUAlphaState *env = &cpu->env;
 154
 155     env->implver = IMPLVER_2106x;
 156 }
 157
 158 static void ev5_cpu_initfn(Object *obj)
 159 {
 160     AlphaCPU *cpu = ALPHA_CPU(obj);
 161     CPUAlphaState *env = &cpu->env;
 162
 163     env->implver = IMPLVER_21164;
 164 }
 165
 166 static void ev56_cpu_initfn(Object *obj)
 167 {
 168     AlphaCPU *cpu = ALPHA_CPU(obj);
 169     CPUAlphaState *env = &cpu->env;
 170
 171     env->amask |= AMASK_BWX;
 172 }
 173
 174 static void pca56_cpu_initfn(Object *obj)
 175 {
 176     AlphaCPU *cpu = ALPHA_CPU(obj);
 177     CPUAlphaState *env = &cpu->env;
 178
 179     env->amask |= AMASK_MVI;
 180 }
 181
 182 static void ev6_cpu_initfn(Object *obj)
 183 {
 184     AlphaCPU *cpu = ALPHA_CPU(obj);
 185     CPUAlphaState *env = &cpu->env;
 186
 187     env->implver = IMPLVER_21264;
 188     env->amask = AMASK_BWX | AMASK_FIX | AMASK_MVI | AMASK_TRAP;
 189 }
 190
 191 static void ev67_cpu_initfn(Object *obj)
 192 {
 193     AlphaCPU *cpu = ALPHA_CPU(obj);
 194     CPUAlphaState *env = &cpu->env;
 195
 196     env->amask |= AMASK_CIX | AMASK_PREFETCH;
 197 }
 198
 199 static void alpha_cpu_initfn(Object *obj)
 200 {
 201     AlphaCPU *cpu = ALPHA_CPU(obj);
 202     CPUAlphaState *env = &cpu->env;
 203
 204     cpu_set_cpustate_pointers(cpu);
 205
 206     env->lock_addr = -1;
 207 #if defined(CONFIG_USER_ONLY)
 208     env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
 209     cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
 210                                          | FPCR_UNFD | FPCR_INED | FPCR_DNOD
 211                                          | FPCR_DYN_NORMAL) << 32);
 212 #else
 213     env->flags = ENV_FLAG_PAL_MODE | ENV_FLAG_FEN;
 214 #endif
 215 }
 216
 217 #ifndef CONFIG_USER_ONLY
 218 #include "hw/core/sysemu-cpu-ops.h"
 219
 220 static const struct SysemuCPUOps alpha_sysemu_ops = {
 221     .get_phys_page_debug = alpha_cpu_get_phys_page_debug,
 222 };
 223 #endif
 224
 225 #include "hw/core/tcg-cpu-ops.h"
 226
 227 static const struct TCGCPUOps alpha_tcg_ops = {
 228     .initialize = alpha_translate_init,
 229
 230 #ifdef CONFIG_USER_ONLY
 231     .record_sigsegv = alpha_cpu_record_sigsegv,
 232     .record_sigbus = alpha_cpu_record_sigbus,
 233 #else
 234     .tlb_fill = alpha_cpu_tlb_fill,
 235     .cpu_exec_interrupt = alpha_cpu_exec_interrupt,
 236     .do_interrupt = alpha_cpu_do_interrupt,
 237     .do_transaction_failed = alpha_cpu_do_transaction_failed,
 238     .do_unaligned_access = alpha_cpu_do_unaligned_access,
 239 #endif /* !CONFIG_USER_ONLY */
 240 };
 241
 242 static void alpha_cpu_class_init(ObjectClass *oc, void *data)
 243 {
 244     DeviceClass *dc = DEVICE_CLASS(oc);
 245     CPUClass *cc = CPU_CLASS(oc);
 246     AlphaCPUClass *acc = ALPHA_CPU_CLASS(oc);
 247
 248     device_class_set_parent_realize(dc, alpha_cpu_realizefn,
 249                                     &acc->parent_realize);
 250
 251     cc->class_by_name = alpha_cpu_class_by_name;
 252     cc->has_work = alpha_cpu_has_work;
 253     cc->dump_state = alpha_cpu_dump_state;
 254     cc->set_pc = alpha_cpu_set_pc;
 255     cc->get_pc = alpha_cpu_get_pc;
 256     cc->gdb_read_register = alpha_cpu_gdb_read_register;
 257     cc->gdb_write_register = alpha_cpu_gdb_write_register;
 258 #ifndef CONFIG_USER_ONLY
 259     dc->vmsd = &vmstate_alpha_cpu;
 260     cc->sysemu_ops = &alpha_sysemu_ops;
 261 #endif
 262     cc->disas_set_info = alpha_cpu_disas_set_info;
 263
 264     cc->tcg_ops = &alpha_tcg_ops;
 265     cc->gdb_num_core_regs = 67;
 266 }
 267
 268 #define DEFINE_ALPHA_CPU_TYPE(base_type, cpu_model, initfn) \
 269      {                                                      \
 270          .parent = base_type,                               \
 271          .instance_init = initfn,                           \
 272          .name = ALPHA_CPU_TYPE_NAME(cpu_model),            \
 273      }
 274
 275 static const TypeInfo alpha_cpu_type_infos[] = {
 276     {
 277         .name = TYPE_ALPHA_CPU,
 278         .parent = TYPE_CPU,
 279         .instance_size = sizeof(AlphaCPU),
 280         .instance_init = alpha_cpu_initfn,
 281         .abstract = true,
 282         .class_size = sizeof(AlphaCPUClass),
 283         .class_init = alpha_cpu_class_init,
 284     },
 285     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev4", ev4_cpu_initfn),
 286     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev5", ev5_cpu_initfn),
 287     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev5"), "ev56", ev56_cpu_initfn),
 288     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev56"), "pca56",
 289                           pca56_cpu_initfn),
 290     DEFINE_ALPHA_CPU_TYPE(TYPE_ALPHA_CPU, "ev6", ev6_cpu_initfn),
 291     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev6"), "ev67", ev67_cpu_initfn),
 292     DEFINE_ALPHA_CPU_TYPE(ALPHA_CPU_TYPE_NAME("ev67"), "ev68", NULL),
 293 };
 294
 295 DEFINE_TYPES(alpha_cpu_type_infos)