2 * OpenRISC system instructions helper routines
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Zhizhou Zhang <etouzh@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "exec/helper-proto.h"
24 #define TO_SPR(group, number) (((group) << 11) + (number))
26 void HELPER(mtspr
)(CPUOpenRISCState
*env
,
27 target_ulong ra
, target_ulong rb
, target_ulong offset
)
29 #ifndef CONFIG_USER_ONLY
30 int spr
= (ra
| offset
);
33 OpenRISCCPU
*cpu
= openrisc_env_get_cpu(env
);
34 CPUState
*cs
= CPU(cpu
);
37 case TO_SPR(0, 0): /* VR */
41 case TO_SPR(0, 16): /* NPC */
45 case TO_SPR(0, 17): /* SR */
46 if ((env
->sr
& (SR_IME
| SR_DME
| SR_SM
)) ^
47 (rb
& (SR_IME
| SR_DME
| SR_SM
))) {
51 env
->sr
|= SR_FO
; /* FO is const equal to 1 */
52 if (env
->sr
& SR_DME
) {
53 env
->tlb
->cpu_openrisc_map_address_data
=
54 &cpu_openrisc_get_phys_data
;
56 env
->tlb
->cpu_openrisc_map_address_data
=
57 &cpu_openrisc_get_phys_nommu
;
60 if (env
->sr
& SR_IME
) {
61 env
->tlb
->cpu_openrisc_map_address_code
=
62 &cpu_openrisc_get_phys_code
;
64 env
->tlb
->cpu_openrisc_map_address_code
=
65 &cpu_openrisc_get_phys_nommu
;
69 case TO_SPR(0, 18): /* PPC */
73 case TO_SPR(0, 32): /* EPCR */
77 case TO_SPR(0, 48): /* EEAR */
81 case TO_SPR(0, 64): /* ESR */
84 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE
-1): /* DTLBW0MR 0-127 */
85 idx
= spr
- TO_SPR(1, 512);
87 tlb_flush_page(cs
, env
->tlb
->dtlb
[0][idx
].mr
& TARGET_PAGE_MASK
);
89 env
->tlb
->dtlb
[0][idx
].mr
= rb
;
92 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE
-1): /* DTLBW0TR 0-127 */
93 idx
= spr
- TO_SPR(1, 640);
94 env
->tlb
->dtlb
[0][idx
].tr
= rb
;
96 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
97 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
98 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
99 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
100 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
101 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
103 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE
-1): /* ITLBW0MR 0-127 */
104 idx
= spr
- TO_SPR(2, 512);
106 tlb_flush_page(cs
, env
->tlb
->itlb
[0][idx
].mr
& TARGET_PAGE_MASK
);
108 env
->tlb
->itlb
[0][idx
].mr
= rb
;
111 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE
-1): /* ITLBW0TR 0-127 */
112 idx
= spr
- TO_SPR(2, 640);
113 env
->tlb
->itlb
[0][idx
].tr
= rb
;
115 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
116 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
117 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
118 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
119 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
120 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
122 case TO_SPR(9, 0): /* PICMR */
125 case TO_SPR(9, 2): /* PICSR */
128 case TO_SPR(10, 0): /* TTMR */
130 if ((env
->ttmr
& TTMR_M
) ^ (rb
& TTMR_M
)) {
131 switch (rb
& TTMR_M
) {
133 cpu_openrisc_count_stop(cpu
);
138 cpu_openrisc_count_start(cpu
);
145 int ip
= env
->ttmr
& TTMR_IP
;
147 if (rb
& TTMR_IP
) { /* Keep IP bit. */
148 env
->ttmr
= (rb
& ~TTMR_IP
) | ip
;
149 } else { /* Clear IP bit. */
150 env
->ttmr
= rb
& ~TTMR_IP
;
151 cs
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
154 cpu_openrisc_timer_update(cpu
);
158 case TO_SPR(10, 1): /* TTCR */
160 if (env
->ttmr
& TIMER_NONE
) {
163 cpu_openrisc_timer_update(cpu
);
172 target_ulong
HELPER(mfspr
)(CPUOpenRISCState
*env
,
173 target_ulong rd
, target_ulong ra
, uint32_t offset
)
175 #ifndef CONFIG_USER_ONLY
176 int spr
= (ra
| offset
);
179 OpenRISCCPU
*cpu
= openrisc_env_get_cpu(env
);
182 case TO_SPR(0, 0): /* VR */
183 return env
->vr
& SPR_VR
;
185 case TO_SPR(0, 1): /* UPR */
186 return env
->upr
; /* TT, DM, IM, UP present */
188 case TO_SPR(0, 2): /* CPUCFGR */
191 case TO_SPR(0, 3): /* DMMUCFGR */
192 return env
->dmmucfgr
; /* 1Way, 64 entries */
194 case TO_SPR(0, 4): /* IMMUCFGR */
195 return env
->immucfgr
;
197 case TO_SPR(0, 16): /* NPC */
200 case TO_SPR(0, 17): /* SR */
203 case TO_SPR(0, 18): /* PPC */
206 case TO_SPR(0, 32): /* EPCR */
209 case TO_SPR(0, 48): /* EEAR */
212 case TO_SPR(0, 64): /* ESR */
215 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE
-1): /* DTLBW0MR 0-127 */
216 idx
= spr
- TO_SPR(1, 512);
217 return env
->tlb
->dtlb
[0][idx
].mr
;
219 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE
-1): /* DTLBW0TR 0-127 */
220 idx
= spr
- TO_SPR(1, 640);
221 return env
->tlb
->dtlb
[0][idx
].tr
;
223 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
224 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
225 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
226 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
227 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
228 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
231 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE
-1): /* ITLBW0MR 0-127 */
232 idx
= spr
- TO_SPR(2, 512);
233 return env
->tlb
->itlb
[0][idx
].mr
;
235 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE
-1): /* ITLBW0TR 0-127 */
236 idx
= spr
- TO_SPR(2, 640);
237 return env
->tlb
->itlb
[0][idx
].tr
;
239 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
240 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
241 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
242 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
243 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
244 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
247 case TO_SPR(9, 0): /* PICMR */
250 case TO_SPR(9, 2): /* PICSR */
253 case TO_SPR(10, 0): /* TTMR */
256 case TO_SPR(10, 1): /* TTCR */
257 cpu_openrisc_count_update(cpu
);
265 /*If we later need to add tracepoints (or debug printfs) for the return
266 value, it may be useful to structure the code like this:
268 target_ulong ret = 0;
280 later something like trace_spr_read(ret);
284 /* for rd is passed in, if rd unchanged, just keep it back. */