2 * UniCore32 translation
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
18 #include "disas/disas.h"
26 /* internal defines */
27 typedef struct DisasContext
{
30 /* Nonzero if this instruction has been conditionally skipped. */
32 /* The label that will be jumped to when the instruction is skipped. */
34 struct TranslationBlock
*tb
;
35 int singlestep_enabled
;
36 #ifndef CONFIG_USER_ONLY
41 #ifndef CONFIG_USER_ONLY
42 #define IS_USER(s) (s->user)
47 /* These instructions trap after executing, so defer them until after the
48 conditional executions state has been updated. */
49 #define DISAS_SYSCALL 5
51 static TCGv_ptr cpu_env
;
52 static TCGv_i32 cpu_R
[32];
54 /* FIXME: These should be removed. */
55 static TCGv cpu_F0s
, cpu_F1s
;
56 static TCGv_i64 cpu_F0d
, cpu_F1d
;
58 #include "exec/gen-icount.h"
60 static const char *regnames
[] = {
61 "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",
62 "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",
63 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
64 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };
66 /* initialize TCG globals. */
67 void uc32_translate_init(void)
71 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
73 for (i
= 0; i
< 32; i
++) {
74 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
75 offsetof(CPUUniCore32State
, regs
[i
]), regnames
[i
]);
81 /* Allocate a temporary variable. */
82 static TCGv_i32
new_tmp(void)
85 return tcg_temp_new_i32();
88 /* Release a temporary variable. */
89 static void dead_tmp(TCGv tmp
)
95 static inline TCGv
load_cpu_offset(int offset
)
98 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
102 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
104 static inline void store_cpu_offset(TCGv var
, int offset
)
106 tcg_gen_st_i32(var
, cpu_env
, offset
);
110 #define store_cpu_field(var, name) \
111 store_cpu_offset(var, offsetof(CPUUniCore32State, name))
113 /* Set a variable to the value of a CPU register. */
114 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
118 /* normaly, since we updated PC */
120 tcg_gen_movi_i32(var
, addr
);
122 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
126 /* Create a new temporary and set it to the value of a CPU register. */
127 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
129 TCGv tmp
= new_tmp();
130 load_reg_var(s
, tmp
, reg
);
134 /* Set a CPU register. The source must be a temporary and will be
136 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
139 tcg_gen_andi_i32(var
, var
, ~3);
140 s
->is_jmp
= DISAS_JUMP
;
142 tcg_gen_mov_i32(cpu_R
[reg
], var
);
146 /* Value extensions. */
147 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
148 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
149 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
150 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
152 #define UCOP_REG_M (((insn) >> 0) & 0x1f)
153 #define UCOP_REG_N (((insn) >> 19) & 0x1f)
154 #define UCOP_REG_D (((insn) >> 14) & 0x1f)
155 #define UCOP_REG_S (((insn) >> 9) & 0x1f)
156 #define UCOP_REG_LO (((insn) >> 14) & 0x1f)
157 #define UCOP_REG_HI (((insn) >> 9) & 0x1f)
158 #define UCOP_SH_OP (((insn) >> 6) & 0x03)
159 #define UCOP_SH_IM (((insn) >> 9) & 0x1f)
160 #define UCOP_OPCODES (((insn) >> 25) & 0x0f)
161 #define UCOP_IMM_9 (((insn) >> 0) & 0x1ff)
162 #define UCOP_IMM10 (((insn) >> 0) & 0x3ff)
163 #define UCOP_IMM14 (((insn) >> 0) & 0x3fff)
164 #define UCOP_COND (((insn) >> 25) & 0x0f)
165 #define UCOP_CMOV_COND (((insn) >> 19) & 0x0f)
166 #define UCOP_CPNUM (((insn) >> 10) & 0x0f)
167 #define UCOP_UCF64_FMT (((insn) >> 24) & 0x03)
168 #define UCOP_UCF64_FUNC (((insn) >> 6) & 0x0f)
169 #define UCOP_UCF64_COND (((insn) >> 6) & 0x0f)
171 #define UCOP_SET(i) ((insn) & (1 << (i)))
172 #define UCOP_SET_P UCOP_SET(28)
173 #define UCOP_SET_U UCOP_SET(27)
174 #define UCOP_SET_B UCOP_SET(26)
175 #define UCOP_SET_W UCOP_SET(25)
176 #define UCOP_SET_L UCOP_SET(24)
177 #define UCOP_SET_S UCOP_SET(24)
179 #define ILLEGAL cpu_abort(env, \
180 "Illegal UniCore32 instruction %x at line %d!", \
183 #ifndef CONFIG_USER_ONLY
184 static void disas_cp0_insn(CPUUniCore32State
*env
, DisasContext
*s
,
187 TCGv tmp
, tmp2
, tmp3
;
188 if ((insn
& 0xfe000000) == 0xe0000000) {
191 tcg_gen_movi_i32(tmp2
, UCOP_REG_N
);
192 tcg_gen_movi_i32(tmp3
, UCOP_IMM10
);
195 gen_helper_cp0_get(tmp
, cpu_env
, tmp2
, tmp3
);
196 store_reg(s
, UCOP_REG_D
, tmp
);
198 tmp
= load_reg(s
, UCOP_REG_D
);
199 gen_helper_cp0_set(cpu_env
, tmp
, tmp2
, tmp3
);
209 static void disas_ocd_insn(CPUUniCore32State
*env
, DisasContext
*s
,
214 if ((insn
& 0xff003fff) == 0xe1000400) {
216 * movc rd, pp.nn, #imm9
218 * nn: UCOP_REG_N (must be 0)
221 if (UCOP_REG_N
== 0) {
223 tcg_gen_movi_i32(tmp
, 0);
224 store_reg(s
, UCOP_REG_D
, tmp
);
230 if ((insn
& 0xff003fff) == 0xe0000401) {
232 * movc pp.nn, rn, #imm9
234 * nn: UCOP_REG_N (must be 1)
237 if (UCOP_REG_N
== 1) {
238 tmp
= load_reg(s
, UCOP_REG_D
);
239 gen_helper_cp1_putc(tmp
);
250 static inline void gen_set_asr(TCGv var
, uint32_t mask
)
252 TCGv tmp_mask
= tcg_const_i32(mask
);
253 gen_helper_asr_write(cpu_env
, var
, tmp_mask
);
254 tcg_temp_free_i32(tmp_mask
);
256 /* Set NZCV flags from the high 4 bits of var. */
257 #define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)
259 static void gen_exception(int excp
)
261 TCGv tmp
= new_tmp();
262 tcg_gen_movi_i32(tmp
, excp
);
263 gen_helper_exception(cpu_env
, tmp
);
267 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
269 /* Set CF to the top bit of var. */
270 static void gen_set_CF_bit31(TCGv var
)
272 TCGv tmp
= new_tmp();
273 tcg_gen_shri_i32(tmp
, var
, 31);
278 /* Set N and Z flags from var. */
279 static inline void gen_logic_CC(TCGv var
)
281 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, NF
));
282 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, ZF
));
285 /* dest = T0 + T1 + CF. */
286 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
289 tcg_gen_add_i32(dest
, t0
, t1
);
290 tmp
= load_cpu_field(CF
);
291 tcg_gen_add_i32(dest
, dest
, tmp
);
295 /* dest = T0 - T1 + CF - 1. */
296 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
299 tcg_gen_sub_i32(dest
, t0
, t1
);
300 tmp
= load_cpu_field(CF
);
301 tcg_gen_add_i32(dest
, dest
, tmp
);
302 tcg_gen_subi_i32(dest
, dest
, 1);
306 static void shifter_out_im(TCGv var
, int shift
)
308 TCGv tmp
= new_tmp();
310 tcg_gen_andi_i32(tmp
, var
, 1);
312 tcg_gen_shri_i32(tmp
, var
, shift
);
314 tcg_gen_andi_i32(tmp
, tmp
, 1);
321 /* Shift by immediate. Includes special handling for shift == 0. */
322 static inline void gen_uc32_shift_im(TCGv var
, int shiftop
, int shift
,
329 shifter_out_im(var
, 32 - shift
);
331 tcg_gen_shli_i32(var
, var
, shift
);
337 tcg_gen_shri_i32(var
, var
, 31);
340 tcg_gen_movi_i32(var
, 0);
343 shifter_out_im(var
, shift
- 1);
345 tcg_gen_shri_i32(var
, var
, shift
);
353 shifter_out_im(var
, shift
- 1);
358 tcg_gen_sari_i32(var
, var
, shift
);
360 case 3: /* ROR/RRX */
363 shifter_out_im(var
, shift
- 1);
365 tcg_gen_rotri_i32(var
, var
, shift
); break;
367 TCGv tmp
= load_cpu_field(CF
);
369 shifter_out_im(var
, 0);
371 tcg_gen_shri_i32(var
, var
, 1);
372 tcg_gen_shli_i32(tmp
, tmp
, 31);
373 tcg_gen_or_i32(var
, var
, tmp
);
379 static inline void gen_uc32_shift_reg(TCGv var
, int shiftop
,
380 TCGv shift
, int flags
)
385 gen_helper_shl_cc(var
, cpu_env
, var
, shift
);
388 gen_helper_shr_cc(var
, cpu_env
, var
, shift
);
391 gen_helper_sar_cc(var
, cpu_env
, var
, shift
);
394 gen_helper_ror_cc(var
, cpu_env
, var
, shift
);
400 gen_helper_shl(var
, var
, shift
);
403 gen_helper_shr(var
, var
, shift
);
406 gen_helper_sar(var
, var
, shift
);
409 tcg_gen_andi_i32(shift
, shift
, 0x1f);
410 tcg_gen_rotr_i32(var
, var
, shift
);
417 static void gen_test_cc(int cc
, int label
)
425 tmp
= load_cpu_field(ZF
);
426 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
429 tmp
= load_cpu_field(ZF
);
430 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
433 tmp
= load_cpu_field(CF
);
434 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
437 tmp
= load_cpu_field(CF
);
438 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
441 tmp
= load_cpu_field(NF
);
442 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
445 tmp
= load_cpu_field(NF
);
446 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
449 tmp
= load_cpu_field(VF
);
450 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
453 tmp
= load_cpu_field(VF
);
454 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
456 case 8: /* hi: C && !Z */
457 inv
= gen_new_label();
458 tmp
= load_cpu_field(CF
);
459 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
461 tmp
= load_cpu_field(ZF
);
462 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
465 case 9: /* ls: !C || Z */
466 tmp
= load_cpu_field(CF
);
467 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
469 tmp
= load_cpu_field(ZF
);
470 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
472 case 10: /* ge: N == V -> N ^ V == 0 */
473 tmp
= load_cpu_field(VF
);
474 tmp2
= load_cpu_field(NF
);
475 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
477 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
479 case 11: /* lt: N != V -> N ^ V != 0 */
480 tmp
= load_cpu_field(VF
);
481 tmp2
= load_cpu_field(NF
);
482 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
484 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
486 case 12: /* gt: !Z && N == V */
487 inv
= gen_new_label();
488 tmp
= load_cpu_field(ZF
);
489 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
491 tmp
= load_cpu_field(VF
);
492 tmp2
= load_cpu_field(NF
);
493 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
495 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
498 case 13: /* le: Z || N != V */
499 tmp
= load_cpu_field(ZF
);
500 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
502 tmp
= load_cpu_field(VF
);
503 tmp2
= load_cpu_field(NF
);
504 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
506 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
509 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
515 static const uint8_t table_logic_cc
[16] = {
516 1, /* and */ 1, /* xor */ 0, /* sub */ 0, /* rsb */
517 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */
518 1, /* andl */ 1, /* xorl */ 0, /* cmp */ 0, /* cmn */
519 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */
522 /* Set PC state from an immediate address. */
523 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
525 s
->is_jmp
= DISAS_UPDATE
;
526 tcg_gen_movi_i32(cpu_R
[31], addr
& ~3);
529 /* Set PC state from var. var is marked as dead. */
530 static inline void gen_bx(DisasContext
*s
, TCGv var
)
532 s
->is_jmp
= DISAS_UPDATE
;
533 tcg_gen_andi_i32(cpu_R
[31], var
, ~3);
537 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv var
)
539 store_reg(s
, reg
, var
);
542 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
544 TCGv tmp
= new_tmp();
545 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
549 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
551 TCGv tmp
= new_tmp();
552 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
556 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
558 TCGv tmp
= new_tmp();
559 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
563 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
565 TCGv tmp
= new_tmp();
566 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
570 static inline TCGv
gen_ld32(TCGv addr
, int index
)
572 TCGv tmp
= new_tmp();
573 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
577 static inline TCGv_i64
gen_ld64(TCGv addr
, int index
)
579 TCGv_i64 tmp
= tcg_temp_new_i64();
580 tcg_gen_qemu_ld64(tmp
, addr
, index
);
584 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
586 tcg_gen_qemu_st8(val
, addr
, index
);
590 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
592 tcg_gen_qemu_st16(val
, addr
, index
);
596 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
598 tcg_gen_qemu_st32(val
, addr
, index
);
602 static inline void gen_st64(TCGv_i64 val
, TCGv addr
, int index
)
604 tcg_gen_qemu_st64(val
, addr
, index
);
605 tcg_temp_free_i64(val
);
608 static inline void gen_set_pc_im(uint32_t val
)
610 tcg_gen_movi_i32(cpu_R
[31], val
);
613 /* Force a TB lookup after an instruction that changes the CPU state. */
614 static inline void gen_lookup_tb(DisasContext
*s
)
616 tcg_gen_movi_i32(cpu_R
[31], s
->pc
& ~1);
617 s
->is_jmp
= DISAS_UPDATE
;
620 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
633 tcg_gen_addi_i32(var
, var
, val
);
637 offset
= load_reg(s
, UCOP_REG_M
);
638 gen_uc32_shift_im(offset
, UCOP_SH_OP
, UCOP_SH_IM
, 0);
640 tcg_gen_sub_i32(var
, var
, offset
);
642 tcg_gen_add_i32(var
, var
, offset
);
648 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
656 val
= (insn
& 0x1f) | ((insn
>> 4) & 0x3e0);
661 tcg_gen_addi_i32(var
, var
, val
);
665 offset
= load_reg(s
, UCOP_REG_M
);
667 tcg_gen_sub_i32(var
, var
, offset
);
669 tcg_gen_add_i32(var
, var
, offset
);
675 static inline long ucf64_reg_offset(int reg
)
678 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
679 + offsetof(CPU_DoubleU
, l
.upper
);
681 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
682 + offsetof(CPU_DoubleU
, l
.lower
);
686 #define ucf64_gen_ld32(reg) load_cpu_offset(ucf64_reg_offset(reg))
687 #define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
689 /* UniCore-F64 single load/store I_offset */
690 static void do_ucf64_ldst_i(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
696 addr
= load_reg(s
, UCOP_REG_N
);
697 if (!UCOP_SET_P
&& !UCOP_SET_W
) {
702 offset
= UCOP_IMM10
<< 2;
707 tcg_gen_addi_i32(addr
, addr
, offset
);
711 if (UCOP_SET_L
) { /* load */
712 tmp
= gen_ld32(addr
, IS_USER(s
));
713 ucf64_gen_st32(tmp
, UCOP_REG_D
);
715 tmp
= ucf64_gen_ld32(UCOP_REG_D
);
716 gen_st32(tmp
, addr
, IS_USER(s
));
720 offset
= UCOP_IMM10
<< 2;
725 tcg_gen_addi_i32(addr
, addr
, offset
);
729 store_reg(s
, UCOP_REG_N
, addr
);
735 /* UniCore-F64 load/store multiple words */
736 static void do_ucf64_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
743 if (UCOP_REG_D
!= 0) {
746 if (UCOP_REG_N
== 31) {
749 if ((insn
<< 24) == 0) {
753 addr
= load_reg(s
, UCOP_REG_N
);
756 for (i
= 0; i
< 8; i
++) {
763 if (UCOP_SET_P
) { /* pre increment */
764 tcg_gen_addi_i32(addr
, addr
, 4);
765 } /* unnecessary to do anything when post increment */
767 if (UCOP_SET_P
) { /* pre decrement */
768 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
769 } else { /* post decrement */
771 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
776 freg
= ((insn
>> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */
778 for (i
= 0, j
= 0; i
< 8; i
++, freg
++) {
783 if (UCOP_SET_L
) { /* load */
784 tmp
= gen_ld32(addr
, IS_USER(s
));
785 ucf64_gen_st32(tmp
, freg
);
787 tmp
= ucf64_gen_ld32(freg
);
788 gen_st32(tmp
, addr
, IS_USER(s
));
792 /* unnecessary to add after the last transfer */
794 tcg_gen_addi_i32(addr
, addr
, 4);
798 if (UCOP_SET_W
) { /* write back */
800 if (!UCOP_SET_P
) { /* post increment */
801 tcg_gen_addi_i32(addr
, addr
, 4);
802 } /* unnecessary to do anything when pre increment */
807 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
811 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
814 store_reg(s
, UCOP_REG_N
, addr
);
820 /* UniCore-F64 mrc/mcr */
821 static void do_ucf64_trans(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
825 if ((insn
& 0xfe0003ff) == 0xe2000000) {
826 /* control register */
827 if ((UCOP_REG_N
!= UC32_UCF64_FPSCR
) || (UCOP_REG_D
== 31)) {
833 gen_helper_ucf64_get_fpscr(tmp
, cpu_env
);
834 store_reg(s
, UCOP_REG_D
, tmp
);
837 tmp
= load_reg(s
, UCOP_REG_D
);
838 gen_helper_ucf64_set_fpscr(cpu_env
, tmp
);
844 if ((insn
& 0xfe0003ff) == 0xe0000000) {
845 /* general register */
846 if (UCOP_REG_D
== 31) {
849 if (UCOP_SET(24)) { /* MFF */
850 tmp
= ucf64_gen_ld32(UCOP_REG_N
);
851 store_reg(s
, UCOP_REG_D
, tmp
);
853 tmp
= load_reg(s
, UCOP_REG_D
);
854 ucf64_gen_st32(tmp
, UCOP_REG_N
);
858 if ((insn
& 0xfb000000) == 0xe9000000) {
860 if (UCOP_REG_D
!= 31) {
863 if (UCOP_UCF64_COND
& 0x8) {
868 tcg_gen_movi_i32(tmp
, UCOP_UCF64_COND
);
870 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
871 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
872 gen_helper_ucf64_cmpd(cpu_F0d
, cpu_F1d
, tmp
, cpu_env
);
874 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
875 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
876 gen_helper_ucf64_cmps(cpu_F0s
, cpu_F1s
, tmp
, cpu_env
);
884 /* UniCore-F64 convert instructions */
885 static void do_ucf64_fcvt(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
887 if (UCOP_UCF64_FMT
== 3) {
890 if (UCOP_REG_N
!= 0) {
893 switch (UCOP_UCF64_FUNC
) {
895 switch (UCOP_UCF64_FMT
) {
897 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
898 gen_helper_ucf64_df2sf(cpu_F0s
, cpu_F0d
, cpu_env
);
899 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
902 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
903 gen_helper_ucf64_si2sf(cpu_F0s
, cpu_F0s
, cpu_env
);
904 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
912 switch (UCOP_UCF64_FMT
) {
914 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
915 gen_helper_ucf64_sf2df(cpu_F0d
, cpu_F0s
, cpu_env
);
916 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
919 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
920 gen_helper_ucf64_si2df(cpu_F0d
, cpu_F0s
, cpu_env
);
921 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
929 switch (UCOP_UCF64_FMT
) {
931 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
932 gen_helper_ucf64_sf2si(cpu_F0s
, cpu_F0s
, cpu_env
);
933 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
936 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
937 gen_helper_ucf64_df2si(cpu_F0s
, cpu_F0d
, cpu_env
);
938 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
950 /* UniCore-F64 compare instructions */
951 static void do_ucf64_fcmp(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
956 if (UCOP_REG_D
!= 0) {
962 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
963 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
964 /* gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, cpu_env); */
966 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
967 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
968 /* gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, cpu_env); */
972 #define gen_helper_ucf64_movs(x, y) do { } while (0)
973 #define gen_helper_ucf64_movd(x, y) do { } while (0)
975 #define UCF64_OP1(name) do { \
976 if (UCOP_REG_N != 0) { \
979 switch (UCOP_UCF64_FMT) { \
981 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
982 ucf64_reg_offset(UCOP_REG_M)); \
983 gen_helper_ucf64_##name##s(cpu_F0s, cpu_F0s); \
984 tcg_gen_st_i32(cpu_F0s, cpu_env, \
985 ucf64_reg_offset(UCOP_REG_D)); \
988 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
989 ucf64_reg_offset(UCOP_REG_M)); \
990 gen_helper_ucf64_##name##d(cpu_F0d, cpu_F0d); \
991 tcg_gen_st_i64(cpu_F0d, cpu_env, \
992 ucf64_reg_offset(UCOP_REG_D)); \
1000 #define UCF64_OP2(name) do { \
1001 switch (UCOP_UCF64_FMT) { \
1003 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
1004 ucf64_reg_offset(UCOP_REG_N)); \
1005 tcg_gen_ld_i32(cpu_F1s, cpu_env, \
1006 ucf64_reg_offset(UCOP_REG_M)); \
1007 gen_helper_ucf64_##name##s(cpu_F0s, \
1008 cpu_F0s, cpu_F1s, cpu_env); \
1009 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1010 ucf64_reg_offset(UCOP_REG_D)); \
1013 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1014 ucf64_reg_offset(UCOP_REG_N)); \
1015 tcg_gen_ld_i64(cpu_F1d, cpu_env, \
1016 ucf64_reg_offset(UCOP_REG_M)); \
1017 gen_helper_ucf64_##name##d(cpu_F0d, \
1018 cpu_F0d, cpu_F1d, cpu_env); \
1019 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1020 ucf64_reg_offset(UCOP_REG_D)); \
1028 /* UniCore-F64 data processing */
1029 static void do_ucf64_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1031 if (UCOP_UCF64_FMT
== 3) {
1034 switch (UCOP_UCF64_FUNC
) {
1061 /* Disassemble an F64 instruction */
1062 static void disas_ucf64_insn(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1064 if (!UCOP_SET(29)) {
1066 do_ucf64_ldst_m(env
, s
, insn
);
1068 do_ucf64_ldst_i(env
, s
, insn
);
1072 switch ((insn
>> 26) & 0x3) {
1074 do_ucf64_datap(env
, s
, insn
);
1080 do_ucf64_fcvt(env
, s
, insn
);
1083 do_ucf64_fcmp(env
, s
, insn
);
1087 do_ucf64_trans(env
, s
, insn
);
1092 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
1094 TranslationBlock
*tb
;
1097 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1099 gen_set_pc_im(dest
);
1100 tcg_gen_exit_tb((uintptr_t)tb
+ n
);
1102 gen_set_pc_im(dest
);
1107 static inline void gen_jmp(DisasContext
*s
, uint32_t dest
)
1109 if (unlikely(s
->singlestep_enabled
)) {
1110 /* An indirect jump so that we still trigger the debug exception. */
1113 gen_goto_tb(s
, 0, dest
);
1114 s
->is_jmp
= DISAS_TB_JUMP
;
1118 static inline void gen_mulxy(TCGv t0
, TCGv t1
, int x
, int y
)
1121 tcg_gen_sari_i32(t0
, t0
, 16);
1126 tcg_gen_sari_i32(t1
, t1
, 16);
1130 tcg_gen_mul_i32(t0
, t0
, t1
);
1133 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
1134 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int bsr
, TCGv t0
)
1138 /* ??? This is also undefined in system mode. */
1143 tmp
= load_cpu_field(bsr
);
1144 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
1145 tcg_gen_andi_i32(t0
, t0
, mask
);
1146 tcg_gen_or_i32(tmp
, tmp
, t0
);
1147 store_cpu_field(tmp
, bsr
);
1149 gen_set_asr(t0
, mask
);
1156 /* Generate an old-style exception return. Marks pc as dead. */
1157 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
1160 store_reg(s
, 31, pc
);
1161 tmp
= load_cpu_field(bsr
);
1162 gen_set_asr(tmp
, 0xffffffff);
1164 s
->is_jmp
= DISAS_UPDATE
;
1167 static void disas_coproc_insn(CPUUniCore32State
*env
, DisasContext
*s
,
1170 switch (UCOP_CPNUM
) {
1171 #ifndef CONFIG_USER_ONLY
1173 disas_cp0_insn(env
, s
, insn
);
1176 disas_ocd_insn(env
, s
, insn
);
1180 disas_ucf64_insn(env
, s
, insn
);
1183 /* Unknown coprocessor. */
1184 cpu_abort(env
, "Unknown coprocessor!");
1188 /* data processing instructions */
1189 static void do_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1195 if (UCOP_OPCODES
== 0x0f || UCOP_OPCODES
== 0x0d) {
1196 if (UCOP_SET(23)) { /* CMOV instructions */
1197 if ((UCOP_CMOV_COND
== 0xe) || (UCOP_CMOV_COND
== 0xf)) {
1200 /* if not always execute, we generate a conditional jump to
1202 s
->condlabel
= gen_new_label();
1203 gen_test_cc(UCOP_CMOV_COND
^ 1, s
->condlabel
);
1208 logic_cc
= table_logic_cc
[UCOP_OPCODES
] & (UCOP_SET_S
>> 24);
1212 /* immediate operand */
1215 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1218 tcg_gen_movi_i32(tmp2
, val
);
1219 if (logic_cc
&& UCOP_SH_IM
) {
1220 gen_set_CF_bit31(tmp2
);
1224 tmp2
= load_reg(s
, UCOP_REG_M
);
1226 tmp
= load_reg(s
, UCOP_REG_S
);
1227 gen_uc32_shift_reg(tmp2
, UCOP_SH_OP
, tmp
, logic_cc
);
1229 gen_uc32_shift_im(tmp2
, UCOP_SH_OP
, UCOP_SH_IM
, logic_cc
);
1233 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1234 tmp
= load_reg(s
, UCOP_REG_N
);
1239 switch (UCOP_OPCODES
) {
1241 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1245 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1248 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1252 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1255 if (UCOP_SET_S
&& UCOP_REG_D
== 31) {
1256 /* SUBS r31, ... is used for exception return. */
1260 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1261 gen_exception_return(s
, tmp
);
1264 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1266 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
1268 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1273 gen_helper_sub_cc(tmp
, cpu_env
, tmp2
, tmp
);
1275 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
1277 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1281 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1283 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1285 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1289 gen_helper_adc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1291 gen_add_carry(tmp
, tmp
, tmp2
);
1293 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1297 gen_helper_sbc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1299 gen_sub_carry(tmp
, tmp
, tmp2
);
1301 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1305 gen_helper_sbc_cc(tmp
, cpu_env
, tmp2
, tmp
);
1307 gen_sub_carry(tmp
, tmp2
, tmp
);
1309 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1313 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1320 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1327 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1333 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1338 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1342 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1345 if (logic_cc
&& UCOP_REG_D
== 31) {
1346 /* MOVS r31, ... is used for exception return. */
1350 gen_exception_return(s
, tmp2
);
1355 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1359 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1363 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1367 tcg_gen_not_i32(tmp2
, tmp2
);
1371 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1374 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1380 static void do_mult(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1382 TCGv tmp
, tmp2
, tmp3
, tmp4
;
1386 tmp
= load_reg(s
, UCOP_REG_M
);
1387 tmp2
= load_reg(s
, UCOP_REG_N
);
1389 tcg_gen_muls2_i32(tmp
, tmp2
, tmp
, tmp2
);
1391 tcg_gen_mulu2_i32(tmp
, tmp2
, tmp
, tmp2
);
1393 if (UCOP_SET(25)) { /* mult accumulate */
1394 tmp3
= load_reg(s
, UCOP_REG_LO
);
1395 tmp4
= load_reg(s
, UCOP_REG_HI
);
1396 tcg_gen_add2_i32(tmp
, tmp2
, tmp
, tmp2
, tmp3
, tmp4
);
1400 store_reg(s
, UCOP_REG_LO
, tmp
);
1401 store_reg(s
, UCOP_REG_HI
, tmp2
);
1404 tmp
= load_reg(s
, UCOP_REG_M
);
1405 tmp2
= load_reg(s
, UCOP_REG_N
);
1406 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
1410 tmp2
= load_reg(s
, UCOP_REG_S
);
1411 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1417 store_reg(s
, UCOP_REG_D
, tmp
);
1421 /* miscellaneous instructions */
1422 static void do_misc(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1427 if ((insn
& 0xffffffe0) == 0x10ffc120) {
1428 /* Trivial implementation equivalent to bx. */
1429 tmp
= load_reg(s
, UCOP_REG_M
);
1434 if ((insn
& 0xfbffc000) == 0x30ffc000) {
1435 /* PSR = immediate */
1438 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1441 tcg_gen_movi_i32(tmp
, val
);
1442 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1448 if ((insn
& 0xfbffffe0) == 0x12ffc020) {
1449 /* PSR.flag = reg */
1450 tmp
= load_reg(s
, UCOP_REG_M
);
1451 if (gen_set_psr(s
, ASR_NZCV
, UCOP_SET_B
, tmp
)) {
1457 if ((insn
& 0xfbffffe0) == 0x10ffc020) {
1459 tmp
= load_reg(s
, UCOP_REG_M
);
1460 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1466 if ((insn
& 0xfbf83fff) == 0x10f80000) {
1472 tmp
= load_cpu_field(bsr
);
1475 gen_helper_asr_read(tmp
, cpu_env
);
1477 store_reg(s
, UCOP_REG_D
, tmp
);
1481 if ((insn
& 0xfbf83fe0) == 0x12f80120) {
1483 tmp
= load_reg(s
, UCOP_REG_M
);
1485 gen_helper_clo(tmp
, tmp
);
1487 gen_helper_clz(tmp
, tmp
);
1489 store_reg(s
, UCOP_REG_D
, tmp
);
1497 /* load/store I_offset and R_offset */
1498 static void do_ldst_ir(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1500 unsigned int mmu_idx
;
1504 tmp2
= load_reg(s
, UCOP_REG_N
);
1505 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1509 gen_add_data_offset(s
, insn
, tmp2
);
1515 tmp
= gen_ld8u(tmp2
, mmu_idx
);
1517 tmp
= gen_ld32(tmp2
, mmu_idx
);
1521 tmp
= load_reg(s
, UCOP_REG_D
);
1523 gen_st8(tmp
, tmp2
, mmu_idx
);
1525 gen_st32(tmp
, tmp2
, mmu_idx
);
1529 gen_add_data_offset(s
, insn
, tmp2
);
1530 store_reg(s
, UCOP_REG_N
, tmp2
);
1531 } else if (UCOP_SET_W
) {
1532 store_reg(s
, UCOP_REG_N
, tmp2
);
1537 /* Complete the load. */
1538 if (UCOP_REG_D
== 31) {
1541 store_reg(s
, UCOP_REG_D
, tmp
);
1546 /* SWP instruction */
1547 static void do_swap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1553 if ((insn
& 0xff003fe0) != 0x40000120) {
1557 /* ??? This is not really atomic. However we know
1558 we never have multiple CPUs running in parallel,
1559 so it is good enough. */
1560 addr
= load_reg(s
, UCOP_REG_N
);
1561 tmp
= load_reg(s
, UCOP_REG_M
);
1563 tmp2
= gen_ld8u(addr
, IS_USER(s
));
1564 gen_st8(tmp
, addr
, IS_USER(s
));
1566 tmp2
= gen_ld32(addr
, IS_USER(s
));
1567 gen_st32(tmp
, addr
, IS_USER(s
));
1570 store_reg(s
, UCOP_REG_D
, tmp2
);
1573 /* load/store hw/sb */
1574 static void do_ldst_hwsb(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1579 if (UCOP_SH_OP
== 0) {
1580 do_swap(env
, s
, insn
);
1584 addr
= load_reg(s
, UCOP_REG_N
);
1586 gen_add_datah_offset(s
, insn
, addr
);
1589 if (UCOP_SET_L
) { /* load */
1590 switch (UCOP_SH_OP
) {
1592 tmp
= gen_ld16u(addr
, IS_USER(s
));
1595 tmp
= gen_ld8s(addr
, IS_USER(s
));
1597 default: /* see do_swap */
1599 tmp
= gen_ld16s(addr
, IS_USER(s
));
1602 } else { /* store */
1603 if (UCOP_SH_OP
!= 1) {
1606 tmp
= load_reg(s
, UCOP_REG_D
);
1607 gen_st16(tmp
, addr
, IS_USER(s
));
1609 /* Perform base writeback before the loaded value to
1610 ensure correct behavior with overlapping index registers. */
1612 gen_add_datah_offset(s
, insn
, addr
);
1613 store_reg(s
, UCOP_REG_N
, addr
);
1614 } else if (UCOP_SET_W
) {
1615 store_reg(s
, UCOP_REG_N
, addr
);
1620 /* Complete the load. */
1621 store_reg(s
, UCOP_REG_D
, tmp
);
1625 /* load/store multiple words */
1626 static void do_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1628 unsigned int val
, i
, mmu_idx
;
1629 int j
, n
, reg
, user
, loaded_base
;
1638 /* XXX: store correct base if write back */
1640 if (UCOP_SET_B
) { /* S bit in instruction table */
1642 ILLEGAL
; /* only usable in supervisor mode */
1644 if (UCOP_SET(18) == 0) { /* pc reg */
1649 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1650 addr
= load_reg(s
, UCOP_REG_N
);
1652 /* compute total size */
1654 TCGV_UNUSED(loaded_var
);
1656 for (i
= 0; i
< 6; i
++) {
1661 for (i
= 9; i
< 19; i
++) {
1666 /* XXX: test invalid n == 0 case ? */
1670 tcg_gen_addi_i32(addr
, addr
, 4);
1672 /* post increment */
1677 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1679 /* post decrement */
1681 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1687 reg
= UCOP_SET(6) ? 16 : 0;
1688 for (i
= 0; i
< 19; i
++, reg
++) {
1693 if (UCOP_SET_L
) { /* load */
1694 tmp
= gen_ld32(addr
, mmu_idx
);
1698 tmp2
= tcg_const_i32(reg
);
1699 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
1700 tcg_temp_free_i32(tmp2
);
1702 } else if (reg
== UCOP_REG_N
) {
1706 store_reg(s
, reg
, tmp
);
1708 } else { /* store */
1710 /* special case: r31 = PC + 4 */
1713 tcg_gen_movi_i32(tmp
, val
);
1716 tmp2
= tcg_const_i32(reg
);
1717 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
1718 tcg_temp_free_i32(tmp2
);
1720 tmp
= load_reg(s
, reg
);
1722 gen_st32(tmp
, addr
, mmu_idx
);
1725 /* no need to add after the last transfer */
1727 tcg_gen_addi_i32(addr
, addr
, 4);
1731 if (UCOP_SET_W
) { /* write back */
1736 /* post increment */
1737 tcg_gen_addi_i32(addr
, addr
, 4);
1743 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1746 /* post decrement */
1747 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1750 store_reg(s
, UCOP_REG_N
, addr
);
1755 store_reg(s
, UCOP_REG_N
, loaded_var
);
1757 if (UCOP_SET_B
&& !user
) {
1758 /* Restore ASR from BSR. */
1759 tmp
= load_cpu_field(bsr
);
1760 gen_set_asr(tmp
, 0xffffffff);
1762 s
->is_jmp
= DISAS_UPDATE
;
1766 /* branch (and link) */
1767 static void do_branch(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1773 if (UCOP_COND
== 0xf) {
1777 if (UCOP_COND
!= 0xe) {
1778 /* if not always execute, we generate a conditional jump to
1780 s
->condlabel
= gen_new_label();
1781 gen_test_cc(UCOP_COND
^ 1, s
->condlabel
);
1785 val
= (int32_t)s
->pc
;
1788 tcg_gen_movi_i32(tmp
, val
);
1789 store_reg(s
, 30, tmp
);
1791 offset
= (((int32_t)insn
<< 8) >> 8);
1792 val
+= (offset
<< 2); /* unicore is pc+4 */
1796 static void disas_uc32_insn(CPUUniCore32State
*env
, DisasContext
*s
)
1800 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
1801 tcg_gen_debug_insn_start(s
->pc
);
1804 insn
= cpu_ldl_code(env
, s
->pc
);
1807 /* UniCore instructions class:
1808 * AAAB BBBC xxxx xxxx xxxx xxxD xxEx xxxx
1809 * AAA : see switch case
1810 * BBBB : opcodes or cond or PUBW
1815 switch (insn
>> 29) {
1817 if (UCOP_SET(5) && UCOP_SET(8) && !UCOP_SET(28)) {
1818 do_mult(env
, s
, insn
);
1823 do_misc(env
, s
, insn
);
1827 if (((UCOP_OPCODES
>> 2) == 2) && !UCOP_SET_S
) {
1828 do_misc(env
, s
, insn
);
1831 do_datap(env
, s
, insn
);
1835 if (UCOP_SET(8) && UCOP_SET(5)) {
1836 do_ldst_hwsb(env
, s
, insn
);
1839 if (UCOP_SET(8) || UCOP_SET(5)) {
1843 do_ldst_ir(env
, s
, insn
);
1848 ILLEGAL
; /* extended instructions */
1850 do_ldst_m(env
, s
, insn
);
1853 do_branch(env
, s
, insn
);
1857 disas_coproc_insn(env
, s
, insn
);
1860 if (!UCOP_SET(28)) {
1861 disas_coproc_insn(env
, s
, insn
);
1864 if ((insn
& 0xff000000) == 0xff000000) { /* syscall */
1865 gen_set_pc_im(s
->pc
);
1866 s
->is_jmp
= DISAS_SYSCALL
;
1873 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
1874 basic block 'tb'. If search_pc is TRUE, also generate PC
1875 information for each intermediate instruction. */
1876 static inline void gen_intermediate_code_internal(UniCore32CPU
*cpu
,
1877 TranslationBlock
*tb
, bool search_pc
)
1879 CPUState
*cs
= CPU(cpu
);
1880 CPUUniCore32State
*env
= &cpu
->env
;
1881 DisasContext dc1
, *dc
= &dc1
;
1883 uint16_t *gen_opc_end
;
1885 target_ulong pc_start
;
1886 uint32_t next_page_start
;
1890 /* generate intermediate code */
1897 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
1899 dc
->is_jmp
= DISAS_NEXT
;
1901 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
1903 cpu_F0s
= tcg_temp_new_i32();
1904 cpu_F1s
= tcg_temp_new_i32();
1905 cpu_F0d
= tcg_temp_new_i64();
1906 cpu_F1d
= tcg_temp_new_i64();
1907 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1910 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1911 if (max_insns
== 0) {
1912 max_insns
= CF_COUNT_MASK
;
1915 #ifndef CONFIG_USER_ONLY
1916 if ((env
->uncached_asr
& ASR_M
) == ASR_MODE_USER
) {
1925 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1926 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1927 if (bp
->pc
== dc
->pc
) {
1928 gen_set_pc_im(dc
->pc
);
1929 gen_exception(EXCP_DEBUG
);
1930 dc
->is_jmp
= DISAS_JUMP
;
1931 /* Advance PC so that clearing the breakpoint will
1932 invalidate this TB. */
1933 dc
->pc
+= 2; /* FIXME */
1934 goto done_generating
;
1939 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
1943 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
1946 tcg_ctx
.gen_opc_pc
[lj
] = dc
->pc
;
1947 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
1948 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
1951 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
1955 disas_uc32_insn(env
, dc
);
1958 fprintf(stderr
, "Internal resource leak before %08x\n", dc
->pc
);
1962 if (dc
->condjmp
&& !dc
->is_jmp
) {
1963 gen_set_label(dc
->condlabel
);
1966 /* Translation stops when a conditional branch is encountered.
1967 * Otherwise the subsequent code could get translated several times.
1968 * Also stop translation when a page boundary is reached. This
1969 * ensures prefetch aborts occur at the right place. */
1971 } while (!dc
->is_jmp
&& tcg_ctx
.gen_opc_ptr
< gen_opc_end
&&
1972 !cs
->singlestep_enabled
&&
1974 dc
->pc
< next_page_start
&&
1975 num_insns
< max_insns
);
1977 if (tb
->cflags
& CF_LAST_IO
) {
1979 /* FIXME: This can theoretically happen with self-modifying
1981 cpu_abort(env
, "IO on conditional branch instruction");
1986 /* At this stage dc->condjmp will only be set when the skipped
1987 instruction was a conditional branch or trap, and the PC has
1988 already been written. */
1989 if (unlikely(cs
->singlestep_enabled
)) {
1990 /* Make sure the pc is updated, and raise a debug exception. */
1992 if (dc
->is_jmp
== DISAS_SYSCALL
) {
1993 gen_exception(UC32_EXCP_PRIV
);
1995 gen_exception(EXCP_DEBUG
);
1997 gen_set_label(dc
->condlabel
);
1999 if (dc
->condjmp
|| !dc
->is_jmp
) {
2000 gen_set_pc_im(dc
->pc
);
2003 if (dc
->is_jmp
== DISAS_SYSCALL
&& !dc
->condjmp
) {
2004 gen_exception(UC32_EXCP_PRIV
);
2006 gen_exception(EXCP_DEBUG
);
2009 /* While branches must always occur at the end of an IT block,
2010 there are a few other things that can cause us to terminate
2011 the TB in the middel of an IT block:
2012 - Exception generating instructions (bkpt, swi, undefined).
2014 - Hardware watchpoints.
2015 Hardware breakpoints have already been handled and skip this code.
2017 switch (dc
->is_jmp
) {
2019 gen_goto_tb(dc
, 1, dc
->pc
);
2024 /* indicate that the hash table must be used to find the next TB */
2028 /* nothing more to generate */
2031 gen_exception(UC32_EXCP_PRIV
);
2035 gen_set_label(dc
->condlabel
);
2036 gen_goto_tb(dc
, 1, dc
->pc
);
2042 gen_tb_end(tb
, num_insns
);
2043 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
2046 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
2047 qemu_log("----------------\n");
2048 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
2049 log_target_disas(env
, pc_start
, dc
->pc
- pc_start
, 0);
2054 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
2057 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
2060 tb
->size
= dc
->pc
- pc_start
;
2061 tb
->icount
= num_insns
;
2065 void gen_intermediate_code(CPUUniCore32State
*env
, TranslationBlock
*tb
)
2067 gen_intermediate_code_internal(uc32_env_get_cpu(env
), tb
, false);
2070 void gen_intermediate_code_pc(CPUUniCore32State
*env
, TranslationBlock
*tb
)
2072 gen_intermediate_code_internal(uc32_env_get_cpu(env
), tb
, true);
2075 static const char *cpu_mode_names
[16] = {
2076 "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP",
2077 "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
2080 #undef UCF64_DUMP_STATE
2081 #ifdef UCF64_DUMP_STATE
2082 static void cpu_dump_state_ucf64(CPUUniCore32State
*env
, FILE *f
,
2083 fprintf_function cpu_fprintf
, int flags
)
2091 /* ??? This assumes float64 and double have the same layout.
2092 Oh well, it's only debug dumps. */
2098 for (i
= 0; i
< 16; i
++) {
2099 d
.d
= env
->ucf64
.regs
[i
];
2103 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
2104 i
* 2, (int)s0
.i
, s0
.s
,
2105 i
* 2 + 1, (int)s1
.i
, s1
.s
);
2106 cpu_fprintf(f
, " d%02d=%" PRIx64
"(%8g)\n",
2107 i
, (uint64_t)d0
.f64
, d0
.d
);
2109 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->ucf64
.xregs
[UC32_UCF64_FPSCR
]);
2112 #define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
2115 void uc32_cpu_dump_state(CPUState
*cs
, FILE *f
,
2116 fprintf_function cpu_fprintf
, int flags
)
2118 UniCore32CPU
*cpu
= UNICORE32_CPU(cs
);
2119 CPUUniCore32State
*env
= &cpu
->env
;
2123 for (i
= 0; i
< 32; i
++) {
2124 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
2126 cpu_fprintf(f
, "\n");
2128 cpu_fprintf(f
, " ");
2131 psr
= cpu_asr_read(env
);
2132 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %s\n",
2134 psr
& (1 << 31) ? 'N' : '-',
2135 psr
& (1 << 30) ? 'Z' : '-',
2136 psr
& (1 << 29) ? 'C' : '-',
2137 psr
& (1 << 28) ? 'V' : '-',
2138 cpu_mode_names
[psr
& 0xf]);
2140 cpu_dump_state_ucf64(env
, f
, cpu_fprintf
, flags
);
2143 void restore_state_to_opc(CPUUniCore32State
*env
, TranslationBlock
*tb
, int pc_pos
)
2145 env
->regs
[31] = tcg_ctx
.gen_opc_pc
[pc_pos
];