hw/acpi/piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  *
  18  * Contributions after 2012-01-13 are licensed under the terms of the
  19  * GNU GPL, version 2 or (at your option) any later version.
  20  */
  21 #include "hw/hw.h"
  22 #include "hw/i386/pc.h"
  23 #include "hw/isa/apm.h"
  24 #include "hw/i2c/pm_smbus.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/acpi/acpi.h"
  27 #include "sysemu/sysemu.h"
  28 #include "qemu/range.h"
  29 #include "exec/ioport.h"
  30 #include "hw/nvram/fw_cfg.h"
  31 #include "exec/address-spaces.h"
  32 #include "hw/acpi/piix4.h"
  33 #include "hw/acpi/pcihp.h"
  34 #include "hw/acpi/cpu_hotplug.h"
  35 #include "hw/hotplug.h"
  36
  37 //#define DEBUG
  38
  39 #ifdef DEBUG
  40 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  41 #else
  42 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  43 #endif
  44
  45 #define GPE_BASE 0xafe0
  46 #define GPE_LEN 4
  47
  48 struct pci_status {
  49     uint32_t up; /* deprecated, maintained for migration compatibility */
  50     uint32_t down;
  51 };
  52
  53 typedef struct PIIX4PMState {
  54     /*< private >*/
  55     PCIDevice parent_obj;
  56     /*< public >*/
  57
  58     MemoryRegion io;
  59     uint32_t io_base;
  60
  61     MemoryRegion io_gpe;
  62     ACPIREGS ar;
  63
  64     APMState apm;
  65
  66     PMSMBus smb;
  67     uint32_t smb_io_base;
  68
  69     qemu_irq irq;
  70     qemu_irq smi_irq;
  71     int kvm_enabled;
  72     Notifier machine_ready;
  73     Notifier powerdown_notifier;
  74
  75     AcpiPciHpState acpi_pci_hotplug;
  76     bool use_acpi_pci_hotplug;
  77
  78     uint8_t disable_s3;
  79     uint8_t disable_s4;
  80     uint8_t s4_val;
  81
  82     AcpiCpuHotplug gpe_cpu;
  83     Notifier cpu_added_notifier;
  84 } PIIX4PMState;
  85
  86 #define TYPE_PIIX4_PM "PIIX4_PM"
  87
  88 #define PIIX4_PM(obj) \
  89     OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
  90
  91 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
  92                                            PCIBus *bus, PIIX4PMState *s);
  93
  94 #define ACPI_ENABLE 0xf1
  95 #define ACPI_DISABLE 0xf0
  96
  97 static void pm_tmr_timer(ACPIREGS *ar)
  98 {
  99     PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
 100     acpi_update_sci(&s->ar, s->irq);
 101 }
 102
 103 static void apm_ctrl_changed(uint32_t val, void *arg)
 104 {
 105     PIIX4PMState *s = arg;
 106     PCIDevice *d = PCI_DEVICE(s);
 107
 108     /* ACPI specs 3.0, 4.7.2.5 */
 109     acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
 110
 111     if (d->config[0x5b] & (1 << 1)) {
 112         if (s->smi_irq) {
 113             qemu_irq_raise(s->smi_irq);
 114         }
 115     }
 116 }
 117
 118 static void pm_io_space_update(PIIX4PMState *s)
 119 {
 120     PCIDevice *d = PCI_DEVICE(s);
 121
 122     s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
 123     s->io_base &= 0xffc0;
 124
 125     memory_region_transaction_begin();
 126     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
 127     memory_region_set_address(&s->io, s->io_base);
 128     memory_region_transaction_commit();
 129 }
 130
 131 static void smbus_io_space_update(PIIX4PMState *s)
 132 {
 133     PCIDevice *d = PCI_DEVICE(s);
 134
 135     s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
 136     s->smb_io_base &= 0xffc0;
 137
 138     memory_region_transaction_begin();
 139     memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
 140     memory_region_set_address(&s->smb.io, s->smb_io_base);
 141     memory_region_transaction_commit();
 142 }
 143
 144 static void pm_write_config(PCIDevice *d,
 145                             uint32_t address, uint32_t val, int len)
 146 {
 147     pci_default_write_config(d, address, val, len);
 148     if (range_covers_byte(address, len, 0x80) ||
 149         ranges_overlap(address, len, 0x40, 4)) {
 150         pm_io_space_update((PIIX4PMState *)d);
 151     }
 152     if (range_covers_byte(address, len, 0xd2) ||
 153         ranges_overlap(address, len, 0x90, 4)) {
 154         smbus_io_space_update((PIIX4PMState *)d);
 155     }
 156 }
 157
 158 static int vmstate_acpi_post_load(void *opaque, int version_id)
 159 {
 160     PIIX4PMState *s = opaque;
 161
 162     pm_io_space_update(s);
 163     return 0;
 164 }
 165
 166 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 167  {                                                                   \
 168      .name       = (stringify(_field)),                              \
 169      .version_id = 0,                                                \
 170      .info       = &vmstate_info_uint16,                             \
 171      .size       = sizeof(uint16_t),                                 \
 172      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 173      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 174  }
 175
 176 static const VMStateDescription vmstate_gpe = {
 177     .name = "gpe",
 178     .version_id = 1,
 179     .minimum_version_id = 1,
 180     .minimum_version_id_old = 1,
 181     .fields      = (VMStateField []) {
 182         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 183         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 184         VMSTATE_END_OF_LIST()
 185     }
 186 };
 187
 188 static const VMStateDescription vmstate_pci_status = {
 189     .name = "pci_status",
 190     .version_id = 1,
 191     .minimum_version_id = 1,
 192     .minimum_version_id_old = 1,
 193     .fields      = (VMStateField []) {
 194         VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
 195         VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
 196         VMSTATE_END_OF_LIST()
 197     }
 198 };
 199
 200 static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
 201 {
 202     PIIX4PMState *s = opaque;
 203     int ret, i;
 204     uint16_t temp;
 205
 206     ret = pci_device_load(PCI_DEVICE(s), f);
 207     if (ret < 0) {
 208         return ret;
 209     }
 210     qemu_get_be16s(f, &s->ar.pm1.evt.sts);
 211     qemu_get_be16s(f, &s->ar.pm1.evt.en);
 212     qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
 213
 214     ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
 215     if (ret) {
 216         return ret;
 217     }
 218
 219     timer_get(f, s->ar.tmr.timer);
 220     qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
 221
 222     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
 223     for (i = 0; i < 3; i++) {
 224         qemu_get_be16s(f, &temp);
 225     }
 226
 227     qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
 228     for (i = 0; i < 3; i++) {
 229         qemu_get_be16s(f, &temp);
 230     }
 231
 232     ret = vmstate_load_state(f, &vmstate_pci_status,
 233         &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
 234     return ret;
 235 }
 236
 237 static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
 238 {
 239     PIIX4PMState *s = opaque;
 240     return s->use_acpi_pci_hotplug;
 241 }
 242
 243 static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
 244 {
 245     PIIX4PMState *s = opaque;
 246     return !s->use_acpi_pci_hotplug;
 247 }
 248
 249 /* qemu-kvm 1.2 uses version 3 but advertised as 2
 250  * To support incoming qemu-kvm 1.2 migration, change version_id
 251  * and minimum_version_id to 2 below (which breaks migration from
 252  * qemu 1.2).
 253  *
 254  */
 255 static const VMStateDescription vmstate_acpi = {
 256     .name = "piix4_pm",
 257     .version_id = 3,
 258     .minimum_version_id = 3,
 259     .minimum_version_id_old = 1,
 260     .load_state_old = acpi_load_old,
 261     .post_load = vmstate_acpi_post_load,
 262     .fields      = (VMStateField []) {
 263         VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
 264         VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
 265         VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 266         VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 267         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 268         VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
 269         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 270         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 271         VMSTATE_STRUCT_TEST(
 272             acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
 273             PIIX4PMState,
 274             vmstate_test_no_use_acpi_pci_hotplug,
 275             2, vmstate_pci_status,
 276             struct AcpiPciHpPciStatus),
 277         VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
 278                             vmstate_test_use_acpi_pci_hotplug),
 279         VMSTATE_END_OF_LIST()
 280     }
 281 };
 282
 283 static void piix4_reset(void *opaque)
 284 {
 285     PIIX4PMState *s = opaque;
 286     PCIDevice *d = PCI_DEVICE(s);
 287     uint8_t *pci_conf = d->config;
 288
 289     pci_conf[0x58] = 0;
 290     pci_conf[0x59] = 0;
 291     pci_conf[0x5a] = 0;
 292     pci_conf[0x5b] = 0;
 293
 294     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 295     pci_conf[0x80] = 0;
 296
 297     if (s->kvm_enabled) {
 298         /* Mark SMM as already inited (until KVM supports SMM). */
 299         pci_conf[0x5B] = 0x02;
 300     }
 301     pm_io_space_update(s);
 302     acpi_pcihp_reset(&s->acpi_pci_hotplug);
 303 }
 304
 305 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
 306 {
 307     PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
 308
 309     assert(s != NULL);
 310     acpi_pm1_evt_power_down(&s->ar);
 311 }
 312
 313 static void piix4_pci_device_plug_cb(HotplugHandler *hotplug_dev,
 314                                      DeviceState *dev, Error **errp)
 315 {
 316     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 317     acpi_pcihp_device_plug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev, errp);
 318 }
 319
 320 static void piix4_pci_device_unplug_cb(HotplugHandler *hotplug_dev,
 321                                        DeviceState *dev, Error **errp)
 322 {
 323     PIIX4PMState *s = PIIX4_PM(hotplug_dev);
 324     acpi_pcihp_device_unplug_cb(&s->ar, s->irq, &s->acpi_pci_hotplug, dev,
 325                                 errp);
 326 }
 327
 328 static void piix4_update_bus_hotplug(PCIBus *pci_bus, void *opaque)
 329 {
 330     PIIX4PMState *s = opaque;
 331
 332     qbus_set_hotplug_handler(BUS(pci_bus), DEVICE(s), &error_abort);
 333 }
 334
 335 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 336 {
 337     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 338     PCIDevice *d = PCI_DEVICE(s);
 339     MemoryRegion *io_as = pci_address_space_io(d);
 340     uint8_t *pci_conf;
 341
 342     pci_conf = d->config;
 343     pci_conf[0x5f] = 0x10 |
 344         (memory_region_present(io_as, 0x378) ? 0x80 : 0);
 345     pci_conf[0x63] = 0x60;
 346     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
 347         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 348
 349     if (s->use_acpi_pci_hotplug) {
 350         pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
 351     } else {
 352         piix4_update_bus_hotplug(d->bus, s);
 353     }
 354 }
 355
 356 static void piix4_pm_add_propeties(PIIX4PMState *s)
 357 {
 358     static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
 359     static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
 360     static const uint32_t gpe0_blk = GPE_BASE;
 361     static const uint32_t gpe0_blk_len = GPE_LEN;
 362     static const uint16_t sci_int = 9;
 363
 364     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
 365                                   &acpi_enable_cmd, NULL);
 366     object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
 367                                   &acpi_disable_cmd, NULL);
 368     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
 369                                   &gpe0_blk, NULL);
 370     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
 371                                   &gpe0_blk_len, NULL);
 372     object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
 373                                   &sci_int, NULL);
 374     object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
 375                                   &s->io_base, NULL);
 376 }
 377
 378 static int piix4_pm_initfn(PCIDevice *dev)
 379 {
 380     PIIX4PMState *s = PIIX4_PM(dev);
 381     uint8_t *pci_conf;
 382
 383     pci_conf = dev->config;
 384     pci_conf[0x06] = 0x80;
 385     pci_conf[0x07] = 0x02;
 386     pci_conf[0x09] = 0x00;
 387     pci_conf[0x3d] = 0x01; // interrupt pin 1
 388
 389     /* APM */
 390     apm_init(dev, &s->apm, apm_ctrl_changed, s);
 391
 392     if (s->kvm_enabled) {
 393         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 394          * support SMM mode. */
 395         pci_conf[0x5B] = 0x02;
 396     }
 397
 398     /* XXX: which specification is used ? The i82731AB has different
 399        mappings */
 400     pci_conf[0x90] = s->smb_io_base | 1;
 401     pci_conf[0x91] = s->smb_io_base >> 8;
 402     pci_conf[0xd2] = 0x09;
 403     pm_smbus_init(DEVICE(dev), &s->smb);
 404     memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
 405     memory_region_add_subregion(pci_address_space_io(dev),
 406                                 s->smb_io_base, &s->smb.io);
 407
 408     memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
 409     memory_region_set_enabled(&s->io, false);
 410     memory_region_add_subregion(pci_address_space_io(dev),
 411                                 0, &s->io);
 412
 413     acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
 414     acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
 415     acpi_pm1_cnt_init(&s->ar, &s->io, s->s4_val);
 416     acpi_gpe_init(&s->ar, GPE_LEN);
 417
 418     s->powerdown_notifier.notify = piix4_pm_powerdown_req;
 419     qemu_register_powerdown_notifier(&s->powerdown_notifier);
 420
 421     s->machine_ready.notify = piix4_pm_machine_ready;
 422     qemu_add_machine_init_done_notifier(&s->machine_ready);
 423     qemu_register_reset(piix4_reset, s);
 424
 425     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 426
 427     piix4_pm_add_propeties(s);
 428     return 0;
 429 }
 430
 431 Object *piix4_pm_find(void)
 432 {
 433     bool ambig;
 434     Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
 435
 436     if (ambig || !o) {
 437         return NULL;
 438     }
 439     return o;
 440 }
 441
 442 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 443                       qemu_irq sci_irq, qemu_irq smi_irq,
 444                       int kvm_enabled, FWCfgState *fw_cfg)
 445 {
 446     DeviceState *dev;
 447     PIIX4PMState *s;
 448
 449     dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
 450     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
 451
 452     s = PIIX4_PM(dev);
 453     s->irq = sci_irq;
 454     s->smi_irq = smi_irq;
 455     s->kvm_enabled = kvm_enabled;
 456
 457     qdev_init_nofail(dev);
 458
 459     if (fw_cfg) {
 460         uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
 461         suspend[3] = 1 | ((!s->disable_s3) << 7);
 462         suspend[4] = s->s4_val | ((!s->disable_s4) << 7);
 463
 464         fw_cfg_add_file(fw_cfg, "etc/system-states", g_memdup(suspend, 6), 6);
 465     }
 466
 467     return s->smb.smbus;
 468 }
 469
 470 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
 471 {
 472     PIIX4PMState *s = opaque;
 473     uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
 474
 475     PIIX4_DPRINTF("gpe read %" HWADDR_PRIx " == %" PRIu32 "\n", addr, val);
 476     return val;
 477 }
 478
 479 static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
 480                        unsigned width)
 481 {
 482     PIIX4PMState *s = opaque;
 483
 484     acpi_gpe_ioport_writeb(&s->ar, addr, val);
 485     acpi_update_sci(&s->ar, s->irq);
 486
 487     PIIX4_DPRINTF("gpe write %" HWADDR_PRIx " <== %" PRIu64 "\n", addr, val);
 488 }
 489
 490 static const MemoryRegionOps piix4_gpe_ops = {
 491     .read = gpe_readb,
 492     .write = gpe_writeb,
 493     .valid.min_access_size = 1,
 494     .valid.max_access_size = 4,
 495     .impl.min_access_size = 1,
 496     .impl.max_access_size = 1,
 497     .endianness = DEVICE_LITTLE_ENDIAN,
 498 };
 499
 500 static void piix4_cpu_added_req(Notifier *n, void *opaque)
 501 {
 502     PIIX4PMState *s = container_of(n, PIIX4PMState, cpu_added_notifier);
 503
 504     assert(s != NULL);
 505     AcpiCpuHotplug_add(&s->ar.gpe, &s->gpe_cpu, CPU(opaque));
 506     acpi_update_sci(&s->ar, s->irq);
 507 }
 508
 509 static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
 510                                            PCIBus *bus, PIIX4PMState *s)
 511 {
 512     memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
 513                           "acpi-gpe0", GPE_LEN);
 514     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 515
 516     acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent,
 517                     s->use_acpi_pci_hotplug);
 518
 519     AcpiCpuHotplug_init(parent, OBJECT(s), &s->gpe_cpu,
 520                         PIIX4_CPU_HOTPLUG_IO_BASE);
 521     s->cpu_added_notifier.notify = piix4_cpu_added_req;
 522     qemu_register_cpu_added_notifier(&s->cpu_added_notifier);
 523 }
 524
 525 static Property piix4_pm_properties[] = {
 526     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 527     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
 528     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
 529     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
 530     DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
 531                      use_acpi_pci_hotplug, true),
 532     DEFINE_PROP_END_OF_LIST(),
 533 };
 534
 535 static void piix4_pm_class_init(ObjectClass *klass, void *data)
 536 {
 537     DeviceClass *dc = DEVICE_CLASS(klass);
 538     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 539     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
 540
 541     k->init = piix4_pm_initfn;
 542     k->config_write = pm_write_config;
 543     k->vendor_id = PCI_VENDOR_ID_INTEL;
 544     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
 545     k->revision = 0x03;
 546     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 547     dc->desc = "PM";
 548     dc->vmsd = &vmstate_acpi;
 549     dc->props = piix4_pm_properties;
 550     /*
 551      * Reason: part of PIIX4 southbridge, needs to be wired up,
 552      * e.g. by mips_malta_init()
 553      */
 554     dc->cannot_instantiate_with_device_add_yet = true;
 555     dc->hotpluggable = false;
 556     hc->plug = piix4_pci_device_plug_cb;
 557     hc->unplug = piix4_pci_device_unplug_cb;
 558 }
 559
 560 static const TypeInfo piix4_pm_info = {
 561     .name          = TYPE_PIIX4_PM,
 562     .parent        = TYPE_PCI_DEVICE,
 563     .instance_size = sizeof(PIIX4PMState),
 564     .class_init    = piix4_pm_class_init,
 565     .interfaces = (InterfaceInfo[]) {
 566         { TYPE_HOTPLUG_HANDLER },
 567         { }
 568     }
 569 };
 570
 571 static void piix4_pm_register_types(void)
 572 {
 573     type_register_static(&piix4_pm_info);
 574 }
 575
 576 type_init(piix4_pm_register_types)