4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu/host-utils.h"
28 #include "disas/disas.h"
35 #define PREFIX_REPZ 0x01
36 #define PREFIX_REPNZ 0x02
37 #define PREFIX_LOCK 0x04
38 #define PREFIX_DATA 0x08
39 #define PREFIX_ADR 0x10
40 #define PREFIX_VEX 0x20
43 #define CODE64(s) ((s)->code64)
44 #define REX_X(s) ((s)->rex_x)
45 #define REX_B(s) ((s)->rex_b)
60 //#define MACRO_TEST 1
62 /* global register indexes */
63 static TCGv_ptr cpu_env
;
65 static TCGv cpu_cc_dst
, cpu_cc_src
, cpu_cc_src2
, cpu_cc_srcT
;
66 static TCGv_i32 cpu_cc_op
;
67 static TCGv cpu_regs
[CPU_NB_REGS
];
70 /* local register indexes (only used inside old micro ops) */
71 static TCGv cpu_tmp0
, cpu_tmp4
;
72 static TCGv_ptr cpu_ptr0
, cpu_ptr1
;
73 static TCGv_i32 cpu_tmp2_i32
, cpu_tmp3_i32
;
74 static TCGv_i64 cpu_tmp1_i64
;
76 static uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
78 #include "exec/gen-icount.h"
81 static int x86_64_hregs
;
84 typedef struct DisasContext
{
85 /* current insn context */
86 int override
; /* -1 if no override */
89 target_ulong pc
; /* pc = eip + cs_base */
90 int is_jmp
; /* 1 = means jump (stop translation), 2 means CPU
91 static state change (stop translation) */
92 /* current block context */
93 target_ulong cs_base
; /* base of CS segment */
94 int pe
; /* protected mode */
95 int code32
; /* 32 bit code segment */
97 int lma
; /* long mode active */
98 int code64
; /* 64 bit code segment */
101 int vex_l
; /* vex vector length */
102 int vex_v
; /* vex vvvv register, without 1's compliment. */
103 int ss32
; /* 32 bit stack segment */
104 CCOp cc_op
; /* current CC operation */
106 int addseg
; /* non zero if either DS/ES/SS have a non zero base */
107 int f_st
; /* currently unused */
108 int vm86
; /* vm86 mode */
111 int tf
; /* TF cpu flag */
112 int singlestep_enabled
; /* "hardware" single step enabled */
113 int jmp_opt
; /* use direct block chaining for direct jumps */
114 int mem_index
; /* select memory access functions */
115 uint64_t flags
; /* all execution flags */
116 struct TranslationBlock
*tb
;
117 int popl_esp_hack
; /* for correct popl with esp base handling */
118 int rip_offset
; /* only used in x86_64, but left for simplicity */
120 int cpuid_ext_features
;
121 int cpuid_ext2_features
;
122 int cpuid_ext3_features
;
123 int cpuid_7_0_ebx_features
;
126 static void gen_eob(DisasContext
*s
);
127 static void gen_jmp(DisasContext
*s
, target_ulong eip
);
128 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
);
129 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
);
131 /* i386 arith/logic operations */
151 OP_SHL1
, /* undocumented */
167 /* I386 int registers */
168 OR_EAX
, /* MUST be even numbered */
177 OR_TMP0
= 16, /* temporary operand register */
179 OR_A0
, /* temporary register used when doing address evaluation */
189 /* Bit set if the global variable is live after setting CC_OP to X. */
190 static const uint8_t cc_op_live
[CC_OP_NB
] = {
191 [CC_OP_DYNAMIC
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
192 [CC_OP_EFLAGS
] = USES_CC_SRC
,
193 [CC_OP_MULB
... CC_OP_MULQ
] = USES_CC_DST
| USES_CC_SRC
,
194 [CC_OP_ADDB
... CC_OP_ADDQ
] = USES_CC_DST
| USES_CC_SRC
,
195 [CC_OP_ADCB
... CC_OP_ADCQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
196 [CC_OP_SUBB
... CC_OP_SUBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRCT
,
197 [CC_OP_SBBB
... CC_OP_SBBQ
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
198 [CC_OP_LOGICB
... CC_OP_LOGICQ
] = USES_CC_DST
,
199 [CC_OP_INCB
... CC_OP_INCQ
] = USES_CC_DST
| USES_CC_SRC
,
200 [CC_OP_DECB
... CC_OP_DECQ
] = USES_CC_DST
| USES_CC_SRC
,
201 [CC_OP_SHLB
... CC_OP_SHLQ
] = USES_CC_DST
| USES_CC_SRC
,
202 [CC_OP_SARB
... CC_OP_SARQ
] = USES_CC_DST
| USES_CC_SRC
,
203 [CC_OP_BMILGB
... CC_OP_BMILGQ
] = USES_CC_DST
| USES_CC_SRC
,
204 [CC_OP_ADCX
] = USES_CC_DST
| USES_CC_SRC
,
205 [CC_OP_ADOX
] = USES_CC_SRC
| USES_CC_SRC2
,
206 [CC_OP_ADCOX
] = USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
,
210 static void set_cc_op(DisasContext
*s
, CCOp op
)
214 if (s
->cc_op
== op
) {
218 /* Discard CC computation that will no longer be used. */
219 dead
= cc_op_live
[s
->cc_op
] & ~cc_op_live
[op
];
220 if (dead
& USES_CC_DST
) {
221 tcg_gen_discard_tl(cpu_cc_dst
);
223 if (dead
& USES_CC_SRC
) {
224 tcg_gen_discard_tl(cpu_cc_src
);
226 if (dead
& USES_CC_SRC2
) {
227 tcg_gen_discard_tl(cpu_cc_src2
);
229 if (dead
& USES_CC_SRCT
) {
230 tcg_gen_discard_tl(cpu_cc_srcT
);
233 if (op
== CC_OP_DYNAMIC
) {
234 /* The DYNAMIC setting is translator only, and should never be
235 stored. Thus we always consider it clean. */
236 s
->cc_op_dirty
= false;
238 /* Discard any computed CC_OP value (see shifts). */
239 if (s
->cc_op
== CC_OP_DYNAMIC
) {
240 tcg_gen_discard_i32(cpu_cc_op
);
242 s
->cc_op_dirty
= true;
247 static void gen_update_cc_op(DisasContext
*s
)
249 if (s
->cc_op_dirty
) {
250 tcg_gen_movi_i32(cpu_cc_op
, s
->cc_op
);
251 s
->cc_op_dirty
= false;
255 static inline void gen_op_movl_T0_0(void)
257 tcg_gen_movi_tl(cpu_T
[0], 0);
260 static inline void gen_op_movl_T0_im(int32_t val
)
262 tcg_gen_movi_tl(cpu_T
[0], val
);
265 static inline void gen_op_movl_T0_imu(uint32_t val
)
267 tcg_gen_movi_tl(cpu_T
[0], val
);
270 static inline void gen_op_movl_T1_im(int32_t val
)
272 tcg_gen_movi_tl(cpu_T
[1], val
);
275 static inline void gen_op_movl_T1_imu(uint32_t val
)
277 tcg_gen_movi_tl(cpu_T
[1], val
);
280 static inline void gen_op_movl_A0_im(uint32_t val
)
282 tcg_gen_movi_tl(cpu_A0
, val
);
286 static inline void gen_op_movq_A0_im(int64_t val
)
288 tcg_gen_movi_tl(cpu_A0
, val
);
292 static inline void gen_movtl_T0_im(target_ulong val
)
294 tcg_gen_movi_tl(cpu_T
[0], val
);
297 static inline void gen_movtl_T1_im(target_ulong val
)
299 tcg_gen_movi_tl(cpu_T
[1], val
);
302 static inline void gen_op_andl_T0_ffff(void)
304 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
307 static inline void gen_op_andl_T0_im(uint32_t val
)
309 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], val
);
312 static inline void gen_op_movl_T0_T1(void)
314 tcg_gen_mov_tl(cpu_T
[0], cpu_T
[1]);
317 static inline void gen_op_andl_A0_ffff(void)
319 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffff);
324 #define NB_OP_SIZES 4
326 #else /* !TARGET_X86_64 */
328 #define NB_OP_SIZES 3
330 #endif /* !TARGET_X86_64 */
332 #if defined(HOST_WORDS_BIGENDIAN)
333 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
334 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
335 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
336 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
337 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
339 #define REG_B_OFFSET 0
340 #define REG_H_OFFSET 1
341 #define REG_W_OFFSET 0
342 #define REG_L_OFFSET 0
343 #define REG_LH_OFFSET 4
346 /* In instruction encodings for byte register accesses the
347 * register number usually indicates "low 8 bits of register N";
348 * however there are some special cases where N 4..7 indicates
349 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
350 * true for this special case, false otherwise.
352 static inline bool byte_reg_is_xH(int reg
)
358 if (reg
>= 8 || x86_64_hregs
) {
365 static inline void gen_op_mov_reg_v(int ot
, int reg
, TCGv t0
)
369 if (!byte_reg_is_xH(reg
)) {
370 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 8);
372 tcg_gen_deposit_tl(cpu_regs
[reg
- 4], cpu_regs
[reg
- 4], t0
, 8, 8);
376 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], t0
, 0, 16);
378 default: /* XXX this shouldn't be reached; abort? */
380 /* For x86_64, this sets the higher half of register to zero.
381 For i386, this is equivalent to a mov. */
382 tcg_gen_ext32u_tl(cpu_regs
[reg
], t0
);
386 tcg_gen_mov_tl(cpu_regs
[reg
], t0
);
392 static inline void gen_op_mov_reg_T0(int ot
, int reg
)
394 gen_op_mov_reg_v(ot
, reg
, cpu_T
[0]);
397 static inline void gen_op_mov_reg_T1(int ot
, int reg
)
399 gen_op_mov_reg_v(ot
, reg
, cpu_T
[1]);
402 static inline void gen_op_mov_reg_A0(int size
, int reg
)
406 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_A0
, 0, 16);
408 default: /* XXX this shouldn't be reached; abort? */
410 /* For x86_64, this sets the higher half of register to zero.
411 For i386, this is equivalent to a mov. */
412 tcg_gen_ext32u_tl(cpu_regs
[reg
], cpu_A0
);
416 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_A0
);
422 static inline void gen_op_mov_v_reg(int ot
, TCGv t0
, int reg
)
424 if (ot
== MO_8
&& byte_reg_is_xH(reg
)) {
425 tcg_gen_shri_tl(t0
, cpu_regs
[reg
- 4], 8);
426 tcg_gen_ext8u_tl(t0
, t0
);
428 tcg_gen_mov_tl(t0
, cpu_regs
[reg
]);
432 static inline void gen_op_mov_TN_reg(int ot
, int t_index
, int reg
)
434 gen_op_mov_v_reg(ot
, cpu_T
[t_index
], reg
);
437 static inline void gen_op_movl_A0_reg(int reg
)
439 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
442 static inline void gen_op_addl_A0_im(int32_t val
)
444 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
446 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
451 static inline void gen_op_addq_A0_im(int64_t val
)
453 tcg_gen_addi_tl(cpu_A0
, cpu_A0
, val
);
457 static void gen_add_A0_im(DisasContext
*s
, int val
)
461 gen_op_addq_A0_im(val
);
464 gen_op_addl_A0_im(val
);
467 static inline void gen_op_addl_T0_T1(void)
469 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
472 static inline void gen_op_jmp_T0(void)
474 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, eip
));
477 static inline void gen_op_add_reg_im(int size
, int reg
, int32_t val
)
481 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
482 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
485 tcg_gen_addi_tl(cpu_tmp0
, cpu_regs
[reg
], val
);
486 /* For x86_64, this sets the higher half of register to zero.
487 For i386, this is equivalent to a nop. */
488 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
489 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
493 tcg_gen_addi_tl(cpu_regs
[reg
], cpu_regs
[reg
], val
);
499 static inline void gen_op_add_reg_T0(int size
, int reg
)
503 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
504 tcg_gen_deposit_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_tmp0
, 0, 16);
507 tcg_gen_add_tl(cpu_tmp0
, cpu_regs
[reg
], cpu_T
[0]);
508 /* For x86_64, this sets the higher half of register to zero.
509 For i386, this is equivalent to a nop. */
510 tcg_gen_ext32u_tl(cpu_tmp0
, cpu_tmp0
);
511 tcg_gen_mov_tl(cpu_regs
[reg
], cpu_tmp0
);
515 tcg_gen_add_tl(cpu_regs
[reg
], cpu_regs
[reg
], cpu_T
[0]);
521 static inline void gen_op_addl_A0_reg_sN(int shift
, int reg
)
523 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
525 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
526 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
527 /* For x86_64, this sets the higher half of register to zero.
528 For i386, this is equivalent to a nop. */
529 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
532 static inline void gen_op_movl_A0_seg(int reg
)
534 tcg_gen_ld32u_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
) + REG_L_OFFSET
);
537 static inline void gen_op_addl_A0_seg(DisasContext
*s
, int reg
)
539 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
542 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
543 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
545 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
546 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
549 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
554 static inline void gen_op_movq_A0_seg(int reg
)
556 tcg_gen_ld_tl(cpu_A0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
559 static inline void gen_op_addq_A0_seg(int reg
)
561 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, segs
[reg
].base
));
562 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
565 static inline void gen_op_movq_A0_reg(int reg
)
567 tcg_gen_mov_tl(cpu_A0
, cpu_regs
[reg
]);
570 static inline void gen_op_addq_A0_reg_sN(int shift
, int reg
)
572 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[reg
]);
574 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, shift
);
575 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
579 static inline void gen_op_ld_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
581 tcg_gen_qemu_ld_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
584 static inline void gen_op_st_v(DisasContext
*s
, int idx
, TCGv t0
, TCGv a0
)
586 tcg_gen_qemu_st_tl(t0
, a0
, s
->mem_index
, idx
| MO_LE
);
589 static inline void gen_op_st_rm_T0_A0(DisasContext
*s
, int idx
, int d
)
592 gen_op_st_v(s
, idx
, cpu_T
[0], cpu_A0
);
594 gen_op_mov_reg_T0(idx
, d
);
598 static inline void gen_jmp_im(target_ulong pc
)
600 tcg_gen_movi_tl(cpu_tmp0
, pc
);
601 tcg_gen_st_tl(cpu_tmp0
, cpu_env
, offsetof(CPUX86State
, eip
));
604 static inline void gen_string_movl_A0_ESI(DisasContext
*s
)
608 override
= s
->override
;
612 gen_op_movq_A0_seg(override
);
613 gen_op_addq_A0_reg_sN(0, R_ESI
);
615 gen_op_movq_A0_reg(R_ESI
);
621 if (s
->addseg
&& override
< 0)
624 gen_op_movl_A0_seg(override
);
625 gen_op_addl_A0_reg_sN(0, R_ESI
);
627 gen_op_movl_A0_reg(R_ESI
);
630 /* 16 address, always override */
633 gen_op_movl_A0_reg(R_ESI
);
634 gen_op_andl_A0_ffff();
635 gen_op_addl_A0_seg(s
, override
);
639 static inline void gen_string_movl_A0_EDI(DisasContext
*s
)
643 gen_op_movq_A0_reg(R_EDI
);
648 gen_op_movl_A0_seg(R_ES
);
649 gen_op_addl_A0_reg_sN(0, R_EDI
);
651 gen_op_movl_A0_reg(R_EDI
);
654 gen_op_movl_A0_reg(R_EDI
);
655 gen_op_andl_A0_ffff();
656 gen_op_addl_A0_seg(s
, R_ES
);
660 static inline void gen_op_movl_T0_Dshift(int ot
)
662 tcg_gen_ld32s_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, df
));
663 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], ot
);
666 static TCGv
gen_ext_tl(TCGv dst
, TCGv src
, int size
, bool sign
)
671 tcg_gen_ext8s_tl(dst
, src
);
673 tcg_gen_ext8u_tl(dst
, src
);
678 tcg_gen_ext16s_tl(dst
, src
);
680 tcg_gen_ext16u_tl(dst
, src
);
686 tcg_gen_ext32s_tl(dst
, src
);
688 tcg_gen_ext32u_tl(dst
, src
);
697 static void gen_extu(int ot
, TCGv reg
)
699 gen_ext_tl(reg
, reg
, ot
, false);
702 static void gen_exts(int ot
, TCGv reg
)
704 gen_ext_tl(reg
, reg
, ot
, true);
707 static inline void gen_op_jnz_ecx(int size
, int label1
)
709 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
710 gen_extu(size
+ 1, cpu_tmp0
);
711 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_tmp0
, 0, label1
);
714 static inline void gen_op_jz_ecx(int size
, int label1
)
716 tcg_gen_mov_tl(cpu_tmp0
, cpu_regs
[R_ECX
]);
717 gen_extu(size
+ 1, cpu_tmp0
);
718 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
721 static void gen_helper_in_func(int ot
, TCGv v
, TCGv_i32 n
)
725 gen_helper_inb(v
, n
);
728 gen_helper_inw(v
, n
);
731 gen_helper_inl(v
, n
);
736 static void gen_helper_out_func(int ot
, TCGv_i32 v
, TCGv_i32 n
)
740 gen_helper_outb(v
, n
);
743 gen_helper_outw(v
, n
);
746 gen_helper_outl(v
, n
);
751 static void gen_check_io(DisasContext
*s
, int ot
, target_ulong cur_eip
,
755 target_ulong next_eip
;
758 if (s
->pe
&& (s
->cpl
> s
->iopl
|| s
->vm86
)) {
762 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
765 gen_helper_check_iob(cpu_env
, cpu_tmp2_i32
);
768 gen_helper_check_iow(cpu_env
, cpu_tmp2_i32
);
771 gen_helper_check_iol(cpu_env
, cpu_tmp2_i32
);
775 if(s
->flags
& HF_SVMI_MASK
) {
780 svm_flags
|= (1 << (4 + ot
));
781 next_eip
= s
->pc
- s
->cs_base
;
782 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
783 gen_helper_svm_check_io(cpu_env
, cpu_tmp2_i32
,
784 tcg_const_i32(svm_flags
),
785 tcg_const_i32(next_eip
- cur_eip
));
789 static inline void gen_movs(DisasContext
*s
, int ot
)
791 gen_string_movl_A0_ESI(s
);
792 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
793 gen_string_movl_A0_EDI(s
);
794 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
795 gen_op_movl_T0_Dshift(ot
);
796 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
797 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
800 static void gen_op_update1_cc(void)
802 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
805 static void gen_op_update2_cc(void)
807 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
808 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
811 static void gen_op_update3_cc(TCGv reg
)
813 tcg_gen_mov_tl(cpu_cc_src2
, reg
);
814 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
815 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
818 static inline void gen_op_testl_T0_T1_cc(void)
820 tcg_gen_and_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
823 static void gen_op_update_neg_cc(void)
825 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
826 tcg_gen_neg_tl(cpu_cc_src
, cpu_T
[0]);
827 tcg_gen_movi_tl(cpu_cc_srcT
, 0);
830 /* compute all eflags to cc_src */
831 static void gen_compute_eflags(DisasContext
*s
)
833 TCGv zero
, dst
, src1
, src2
;
836 if (s
->cc_op
== CC_OP_EFLAGS
) {
839 if (s
->cc_op
== CC_OP_CLR
) {
840 tcg_gen_movi_tl(cpu_cc_src
, CC_Z
);
841 set_cc_op(s
, CC_OP_EFLAGS
);
850 /* Take care to not read values that are not live. */
851 live
= cc_op_live
[s
->cc_op
] & ~USES_CC_SRCT
;
852 dead
= live
^ (USES_CC_DST
| USES_CC_SRC
| USES_CC_SRC2
);
854 zero
= tcg_const_tl(0);
855 if (dead
& USES_CC_DST
) {
858 if (dead
& USES_CC_SRC
) {
861 if (dead
& USES_CC_SRC2
) {
867 gen_helper_cc_compute_all(cpu_cc_src
, dst
, src1
, src2
, cpu_cc_op
);
868 set_cc_op(s
, CC_OP_EFLAGS
);
875 typedef struct CCPrepare
{
885 /* compute eflags.C to reg */
886 static CCPrepare
gen_prepare_eflags_c(DisasContext
*s
, TCGv reg
)
892 case CC_OP_SUBB
... CC_OP_SUBQ
:
893 /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */
894 size
= s
->cc_op
- CC_OP_SUBB
;
895 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
896 /* If no temporary was used, be careful not to alias t1 and t0. */
897 t0
= TCGV_EQUAL(t1
, cpu_cc_src
) ? cpu_tmp0
: reg
;
898 tcg_gen_mov_tl(t0
, cpu_cc_srcT
);
902 case CC_OP_ADDB
... CC_OP_ADDQ
:
903 /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
904 size
= s
->cc_op
- CC_OP_ADDB
;
905 t1
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
906 t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
908 return (CCPrepare
) { .cond
= TCG_COND_LTU
, .reg
= t0
,
909 .reg2
= t1
, .mask
= -1, .use_reg2
= true };
911 case CC_OP_LOGICB
... CC_OP_LOGICQ
:
913 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
915 case CC_OP_INCB
... CC_OP_INCQ
:
916 case CC_OP_DECB
... CC_OP_DECQ
:
917 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
918 .mask
= -1, .no_setcond
= true };
920 case CC_OP_SHLB
... CC_OP_SHLQ
:
921 /* (CC_SRC >> (DATA_BITS - 1)) & 1 */
922 size
= s
->cc_op
- CC_OP_SHLB
;
923 shift
= (8 << size
) - 1;
924 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
925 .mask
= (target_ulong
)1 << shift
};
927 case CC_OP_MULB
... CC_OP_MULQ
:
928 return (CCPrepare
) { .cond
= TCG_COND_NE
,
929 .reg
= cpu_cc_src
, .mask
= -1 };
931 case CC_OP_BMILGB
... CC_OP_BMILGQ
:
932 size
= s
->cc_op
- CC_OP_BMILGB
;
933 t0
= gen_ext_tl(reg
, cpu_cc_src
, size
, false);
934 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
938 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_dst
,
939 .mask
= -1, .no_setcond
= true };
942 case CC_OP_SARB
... CC_OP_SARQ
:
944 return (CCPrepare
) { .cond
= TCG_COND_NE
,
945 .reg
= cpu_cc_src
, .mask
= CC_C
};
948 /* The need to compute only C from CC_OP_DYNAMIC is important
949 in efficiently implementing e.g. INC at the start of a TB. */
951 gen_helper_cc_compute_c(reg
, cpu_cc_dst
, cpu_cc_src
,
952 cpu_cc_src2
, cpu_cc_op
);
953 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
954 .mask
= -1, .no_setcond
= true };
958 /* compute eflags.P to reg */
959 static CCPrepare
gen_prepare_eflags_p(DisasContext
*s
, TCGv reg
)
961 gen_compute_eflags(s
);
962 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
966 /* compute eflags.S to reg */
967 static CCPrepare
gen_prepare_eflags_s(DisasContext
*s
, TCGv reg
)
971 gen_compute_eflags(s
);
977 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
980 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
983 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
984 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, true);
985 return (CCPrepare
) { .cond
= TCG_COND_LT
, .reg
= t0
, .mask
= -1 };
990 /* compute eflags.O to reg */
991 static CCPrepare
gen_prepare_eflags_o(DisasContext
*s
, TCGv reg
)
996 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src2
,
997 .mask
= -1, .no_setcond
= true };
999 return (CCPrepare
) { .cond
= TCG_COND_NEVER
, .mask
= -1 };
1001 gen_compute_eflags(s
);
1002 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1007 /* compute eflags.Z to reg */
1008 static CCPrepare
gen_prepare_eflags_z(DisasContext
*s
, TCGv reg
)
1012 gen_compute_eflags(s
);
1018 return (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1021 return (CCPrepare
) { .cond
= TCG_COND_ALWAYS
, .mask
= -1 };
1024 int size
= (s
->cc_op
- CC_OP_ADDB
) & 3;
1025 TCGv t0
= gen_ext_tl(reg
, cpu_cc_dst
, size
, false);
1026 return (CCPrepare
) { .cond
= TCG_COND_EQ
, .reg
= t0
, .mask
= -1 };
1031 /* perform a conditional store into register 'reg' according to jump opcode
1032 value 'b'. In the fast case, T0 is guaranted not to be used. */
1033 static CCPrepare
gen_prepare_cc(DisasContext
*s
, int b
, TCGv reg
)
1035 int inv
, jcc_op
, size
, cond
;
1040 jcc_op
= (b
>> 1) & 7;
1043 case CC_OP_SUBB
... CC_OP_SUBQ
:
1044 /* We optimize relational operators for the cmp/jcc case. */
1045 size
= s
->cc_op
- CC_OP_SUBB
;
1048 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
1049 gen_extu(size
, cpu_tmp4
);
1050 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, false);
1051 cc
= (CCPrepare
) { .cond
= TCG_COND_LEU
, .reg
= cpu_tmp4
,
1052 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1061 tcg_gen_mov_tl(cpu_tmp4
, cpu_cc_srcT
);
1062 gen_exts(size
, cpu_tmp4
);
1063 t0
= gen_ext_tl(cpu_tmp0
, cpu_cc_src
, size
, true);
1064 cc
= (CCPrepare
) { .cond
= cond
, .reg
= cpu_tmp4
,
1065 .reg2
= t0
, .mask
= -1, .use_reg2
= true };
1075 /* This actually generates good code for JC, JZ and JS. */
1078 cc
= gen_prepare_eflags_o(s
, reg
);
1081 cc
= gen_prepare_eflags_c(s
, reg
);
1084 cc
= gen_prepare_eflags_z(s
, reg
);
1087 gen_compute_eflags(s
);
1088 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= cpu_cc_src
,
1089 .mask
= CC_Z
| CC_C
};
1092 cc
= gen_prepare_eflags_s(s
, reg
);
1095 cc
= gen_prepare_eflags_p(s
, reg
);
1098 gen_compute_eflags(s
);
1099 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1102 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1103 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1104 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1109 gen_compute_eflags(s
);
1110 if (TCGV_EQUAL(reg
, cpu_cc_src
)) {
1113 tcg_gen_shri_tl(reg
, cpu_cc_src
, 4); /* CC_O -> CC_S */
1114 tcg_gen_xor_tl(reg
, reg
, cpu_cc_src
);
1115 cc
= (CCPrepare
) { .cond
= TCG_COND_NE
, .reg
= reg
,
1116 .mask
= CC_S
| CC_Z
};
1123 cc
.cond
= tcg_invert_cond(cc
.cond
);
1128 static void gen_setcc1(DisasContext
*s
, int b
, TCGv reg
)
1130 CCPrepare cc
= gen_prepare_cc(s
, b
, reg
);
1132 if (cc
.no_setcond
) {
1133 if (cc
.cond
== TCG_COND_EQ
) {
1134 tcg_gen_xori_tl(reg
, cc
.reg
, 1);
1136 tcg_gen_mov_tl(reg
, cc
.reg
);
1141 if (cc
.cond
== TCG_COND_NE
&& !cc
.use_reg2
&& cc
.imm
== 0 &&
1142 cc
.mask
!= 0 && (cc
.mask
& (cc
.mask
- 1)) == 0) {
1143 tcg_gen_shri_tl(reg
, cc
.reg
, ctztl(cc
.mask
));
1144 tcg_gen_andi_tl(reg
, reg
, 1);
1147 if (cc
.mask
!= -1) {
1148 tcg_gen_andi_tl(reg
, cc
.reg
, cc
.mask
);
1152 tcg_gen_setcond_tl(cc
.cond
, reg
, cc
.reg
, cc
.reg2
);
1154 tcg_gen_setcondi_tl(cc
.cond
, reg
, cc
.reg
, cc
.imm
);
1158 static inline void gen_compute_eflags_c(DisasContext
*s
, TCGv reg
)
1160 gen_setcc1(s
, JCC_B
<< 1, reg
);
1163 /* generate a conditional jump to label 'l1' according to jump opcode
1164 value 'b'. In the fast case, T0 is guaranted not to be used. */
1165 static inline void gen_jcc1_noeob(DisasContext
*s
, int b
, int l1
)
1167 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1169 if (cc
.mask
!= -1) {
1170 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1174 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1176 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1180 /* Generate a conditional jump to label 'l1' according to jump opcode
1181 value 'b'. In the fast case, T0 is guaranted not to be used.
1182 A translation block must end soon. */
1183 static inline void gen_jcc1(DisasContext
*s
, int b
, int l1
)
1185 CCPrepare cc
= gen_prepare_cc(s
, b
, cpu_T
[0]);
1187 gen_update_cc_op(s
);
1188 if (cc
.mask
!= -1) {
1189 tcg_gen_andi_tl(cpu_T
[0], cc
.reg
, cc
.mask
);
1192 set_cc_op(s
, CC_OP_DYNAMIC
);
1194 tcg_gen_brcond_tl(cc
.cond
, cc
.reg
, cc
.reg2
, l1
);
1196 tcg_gen_brcondi_tl(cc
.cond
, cc
.reg
, cc
.imm
, l1
);
1200 /* XXX: does not work with gdbstub "ice" single step - not a
1202 static int gen_jz_ecx_string(DisasContext
*s
, target_ulong next_eip
)
1206 l1
= gen_new_label();
1207 l2
= gen_new_label();
1208 gen_op_jnz_ecx(s
->aflag
, l1
);
1210 gen_jmp_tb(s
, next_eip
, 1);
1215 static inline void gen_stos(DisasContext
*s
, int ot
)
1217 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
1218 gen_string_movl_A0_EDI(s
);
1219 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1220 gen_op_movl_T0_Dshift(ot
);
1221 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1224 static inline void gen_lods(DisasContext
*s
, int ot
)
1226 gen_string_movl_A0_ESI(s
);
1227 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1228 gen_op_mov_reg_T0(ot
, R_EAX
);
1229 gen_op_movl_T0_Dshift(ot
);
1230 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1233 static inline void gen_scas(DisasContext
*s
, int ot
)
1235 gen_string_movl_A0_EDI(s
);
1236 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1237 gen_op(s
, OP_CMPL
, ot
, R_EAX
);
1238 gen_op_movl_T0_Dshift(ot
);
1239 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1242 static inline void gen_cmps(DisasContext
*s
, int ot
)
1244 gen_string_movl_A0_EDI(s
);
1245 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
1246 gen_string_movl_A0_ESI(s
);
1247 gen_op(s
, OP_CMPL
, ot
, OR_TMP0
);
1248 gen_op_movl_T0_Dshift(ot
);
1249 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1250 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1253 static inline void gen_ins(DisasContext
*s
, int ot
)
1257 gen_string_movl_A0_EDI(s
);
1258 /* Note: we must do this dummy write first to be restartable in
1259 case of page fault. */
1261 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1262 gen_op_mov_TN_reg(MO_16
, 1, R_EDX
);
1263 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1264 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1265 gen_helper_in_func(ot
, cpu_T
[0], cpu_tmp2_i32
);
1266 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
1267 gen_op_movl_T0_Dshift(ot
);
1268 gen_op_add_reg_T0(s
->aflag
, R_EDI
);
1273 static inline void gen_outs(DisasContext
*s
, int ot
)
1277 gen_string_movl_A0_ESI(s
);
1278 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1280 gen_op_mov_TN_reg(MO_16
, 1, R_EDX
);
1281 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[1]);
1282 tcg_gen_andi_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 0xffff);
1283 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[0]);
1284 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1286 gen_op_movl_T0_Dshift(ot
);
1287 gen_op_add_reg_T0(s
->aflag
, R_ESI
);
1292 /* same method as Valgrind : we generate jumps to current or next
1294 #define GEN_REPZ(op) \
1295 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1296 target_ulong cur_eip, target_ulong next_eip) \
1299 gen_update_cc_op(s); \
1300 l2 = gen_jz_ecx_string(s, next_eip); \
1301 gen_ ## op(s, ot); \
1302 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1303 /* a loop would cause two single step exceptions if ECX = 1 \
1304 before rep string_insn */ \
1306 gen_op_jz_ecx(s->aflag, l2); \
1307 gen_jmp(s, cur_eip); \
1310 #define GEN_REPZ2(op) \
1311 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1312 target_ulong cur_eip, \
1313 target_ulong next_eip, \
1317 gen_update_cc_op(s); \
1318 l2 = gen_jz_ecx_string(s, next_eip); \
1319 gen_ ## op(s, ot); \
1320 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1321 gen_update_cc_op(s); \
1322 gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \
1324 gen_op_jz_ecx(s->aflag, l2); \
1325 gen_jmp(s, cur_eip); \
1336 static void gen_helper_fp_arith_ST0_FT0(int op
)
1340 gen_helper_fadd_ST0_FT0(cpu_env
);
1343 gen_helper_fmul_ST0_FT0(cpu_env
);
1346 gen_helper_fcom_ST0_FT0(cpu_env
);
1349 gen_helper_fcom_ST0_FT0(cpu_env
);
1352 gen_helper_fsub_ST0_FT0(cpu_env
);
1355 gen_helper_fsubr_ST0_FT0(cpu_env
);
1358 gen_helper_fdiv_ST0_FT0(cpu_env
);
1361 gen_helper_fdivr_ST0_FT0(cpu_env
);
1366 /* NOTE the exception in "r" op ordering */
1367 static void gen_helper_fp_arith_STN_ST0(int op
, int opreg
)
1369 TCGv_i32 tmp
= tcg_const_i32(opreg
);
1372 gen_helper_fadd_STN_ST0(cpu_env
, tmp
);
1375 gen_helper_fmul_STN_ST0(cpu_env
, tmp
);
1378 gen_helper_fsubr_STN_ST0(cpu_env
, tmp
);
1381 gen_helper_fsub_STN_ST0(cpu_env
, tmp
);
1384 gen_helper_fdivr_STN_ST0(cpu_env
, tmp
);
1387 gen_helper_fdiv_STN_ST0(cpu_env
, tmp
);
1392 /* if d == OR_TMP0, it means memory operand (address in A0) */
1393 static void gen_op(DisasContext
*s1
, int op
, int ot
, int d
)
1396 gen_op_mov_TN_reg(ot
, 0, d
);
1398 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1402 gen_compute_eflags_c(s1
, cpu_tmp4
);
1403 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1404 tcg_gen_add_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1405 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1406 gen_op_update3_cc(cpu_tmp4
);
1407 set_cc_op(s1
, CC_OP_ADCB
+ ot
);
1410 gen_compute_eflags_c(s1
, cpu_tmp4
);
1411 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1412 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_tmp4
);
1413 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1414 gen_op_update3_cc(cpu_tmp4
);
1415 set_cc_op(s1
, CC_OP_SBBB
+ ot
);
1418 gen_op_addl_T0_T1();
1419 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1420 gen_op_update2_cc();
1421 set_cc_op(s1
, CC_OP_ADDB
+ ot
);
1424 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1425 tcg_gen_sub_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1426 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1427 gen_op_update2_cc();
1428 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1432 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1433 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1434 gen_op_update1_cc();
1435 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1438 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1439 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1440 gen_op_update1_cc();
1441 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1444 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1445 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1446 gen_op_update1_cc();
1447 set_cc_op(s1
, CC_OP_LOGICB
+ ot
);
1450 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[1]);
1451 tcg_gen_mov_tl(cpu_cc_srcT
, cpu_T
[0]);
1452 tcg_gen_sub_tl(cpu_cc_dst
, cpu_T
[0], cpu_T
[1]);
1453 set_cc_op(s1
, CC_OP_SUBB
+ ot
);
1458 /* if d == OR_TMP0, it means memory operand (address in A0) */
1459 static void gen_inc(DisasContext
*s1
, int ot
, int d
, int c
)
1462 gen_op_mov_TN_reg(ot
, 0, d
);
1464 gen_op_ld_v(s1
, ot
, cpu_T
[0], cpu_A0
);
1466 gen_compute_eflags_c(s1
, cpu_cc_src
);
1468 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], 1);
1469 set_cc_op(s1
, CC_OP_INCB
+ ot
);
1471 tcg_gen_addi_tl(cpu_T
[0], cpu_T
[0], -1);
1472 set_cc_op(s1
, CC_OP_DECB
+ ot
);
1474 gen_op_st_rm_T0_A0(s1
, ot
, d
);
1475 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1478 static void gen_shift_flags(DisasContext
*s
, int ot
, TCGv result
, TCGv shm1
,
1479 TCGv count
, bool is_right
)
1481 TCGv_i32 z32
, s32
, oldop
;
1484 /* Store the results into the CC variables. If we know that the
1485 variable must be dead, store unconditionally. Otherwise we'll
1486 need to not disrupt the current contents. */
1487 z_tl
= tcg_const_tl(0);
1488 if (cc_op_live
[s
->cc_op
] & USES_CC_DST
) {
1489 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_dst
, count
, z_tl
,
1490 result
, cpu_cc_dst
);
1492 tcg_gen_mov_tl(cpu_cc_dst
, result
);
1494 if (cc_op_live
[s
->cc_op
] & USES_CC_SRC
) {
1495 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_cc_src
, count
, z_tl
,
1498 tcg_gen_mov_tl(cpu_cc_src
, shm1
);
1500 tcg_temp_free(z_tl
);
1502 /* Get the two potential CC_OP values into temporaries. */
1503 tcg_gen_movi_i32(cpu_tmp2_i32
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1504 if (s
->cc_op
== CC_OP_DYNAMIC
) {
1507 tcg_gen_movi_i32(cpu_tmp3_i32
, s
->cc_op
);
1508 oldop
= cpu_tmp3_i32
;
1511 /* Conditionally store the CC_OP value. */
1512 z32
= tcg_const_i32(0);
1513 s32
= tcg_temp_new_i32();
1514 tcg_gen_trunc_tl_i32(s32
, count
);
1515 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, s32
, z32
, cpu_tmp2_i32
, oldop
);
1516 tcg_temp_free_i32(z32
);
1517 tcg_temp_free_i32(s32
);
1519 /* The CC_OP value is no longer predictable. */
1520 set_cc_op(s
, CC_OP_DYNAMIC
);
1523 static void gen_shift_rm_T1(DisasContext
*s
, int ot
, int op1
,
1524 int is_right
, int is_arith
)
1526 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1529 if (op1
== OR_TMP0
) {
1530 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1532 gen_op_mov_TN_reg(ot
, 0, op1
);
1535 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1536 tcg_gen_subi_tl(cpu_tmp0
, cpu_T
[1], 1);
1540 gen_exts(ot
, cpu_T
[0]);
1541 tcg_gen_sar_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1542 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1544 gen_extu(ot
, cpu_T
[0]);
1545 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1546 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1549 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1550 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1554 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1556 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, cpu_T
[1], is_right
);
1559 static void gen_shift_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1560 int is_right
, int is_arith
)
1562 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1566 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1568 gen_op_mov_TN_reg(ot
, 0, op1
);
1574 gen_exts(ot
, cpu_T
[0]);
1575 tcg_gen_sari_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1576 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], op2
);
1578 gen_extu(ot
, cpu_T
[0]);
1579 tcg_gen_shri_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1580 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], op2
);
1583 tcg_gen_shli_tl(cpu_tmp4
, cpu_T
[0], op2
- 1);
1584 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], op2
);
1589 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1591 /* update eflags if non zero shift */
1593 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
1594 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
1595 set_cc_op(s
, (is_right
? CC_OP_SARB
: CC_OP_SHLB
) + ot
);
1599 static inline void tcg_gen_lshift(TCGv ret
, TCGv arg1
, target_long arg2
)
1602 tcg_gen_shli_tl(ret
, arg1
, arg2
);
1604 tcg_gen_shri_tl(ret
, arg1
, -arg2
);
1607 static void gen_rot_rm_T1(DisasContext
*s
, int ot
, int op1
, int is_right
)
1609 target_ulong mask
= (ot
== MO_64
? 0x3f : 0x1f);
1613 if (op1
== OR_TMP0
) {
1614 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1616 gen_op_mov_TN_reg(ot
, 0, op1
);
1619 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], mask
);
1623 /* Replicate the 8-bit input so that a 32-bit rotate works. */
1624 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
1625 tcg_gen_muli_tl(cpu_T
[0], cpu_T
[0], 0x01010101);
1628 /* Replicate the 16-bit input so that a 32-bit rotate works. */
1629 tcg_gen_deposit_tl(cpu_T
[0], cpu_T
[0], cpu_T
[0], 16, 16);
1632 #ifdef TARGET_X86_64
1634 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1635 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
1637 tcg_gen_rotr_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1639 tcg_gen_rotl_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
1641 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1646 tcg_gen_rotr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1648 tcg_gen_rotl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1654 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1656 /* We'll need the flags computed into CC_SRC. */
1657 gen_compute_eflags(s
);
1659 /* The value that was "rotated out" is now present at the other end
1660 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1661 since we've computed the flags into CC_SRC, these variables are
1664 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1665 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1666 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1668 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1669 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1671 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1672 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1674 /* Now conditionally store the new CC_OP value. If the shift count
1675 is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
1676 Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
1677 exactly as we computed above. */
1678 t0
= tcg_const_i32(0);
1679 t1
= tcg_temp_new_i32();
1680 tcg_gen_trunc_tl_i32(t1
, cpu_T
[1]);
1681 tcg_gen_movi_i32(cpu_tmp2_i32
, CC_OP_ADCOX
);
1682 tcg_gen_movi_i32(cpu_tmp3_i32
, CC_OP_EFLAGS
);
1683 tcg_gen_movcond_i32(TCG_COND_NE
, cpu_cc_op
, t1
, t0
,
1684 cpu_tmp2_i32
, cpu_tmp3_i32
);
1685 tcg_temp_free_i32(t0
);
1686 tcg_temp_free_i32(t1
);
1688 /* The CC_OP value is no longer predictable. */
1689 set_cc_op(s
, CC_OP_DYNAMIC
);
1692 static void gen_rot_rm_im(DisasContext
*s
, int ot
, int op1
, int op2
,
1695 int mask
= (ot
== MO_64
? 0x3f : 0x1f);
1699 if (op1
== OR_TMP0
) {
1700 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1702 gen_op_mov_TN_reg(ot
, 0, op1
);
1708 #ifdef TARGET_X86_64
1710 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
1712 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1714 tcg_gen_rotli_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, op2
);
1716 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
1721 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], op2
);
1723 tcg_gen_rotli_tl(cpu_T
[0], cpu_T
[0], op2
);
1734 shift
= mask
+ 1 - shift
;
1736 gen_extu(ot
, cpu_T
[0]);
1737 tcg_gen_shli_tl(cpu_tmp0
, cpu_T
[0], shift
);
1738 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], mask
+ 1 - shift
);
1739 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
1745 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1748 /* Compute the flags into CC_SRC. */
1749 gen_compute_eflags(s
);
1751 /* The value that was "rotated out" is now present at the other end
1752 of the word. Compute C into CC_DST and O into CC_SRC2. Note that
1753 since we've computed the flags into CC_SRC, these variables are
1756 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
- 1);
1757 tcg_gen_shri_tl(cpu_cc_dst
, cpu_T
[0], mask
);
1758 tcg_gen_andi_tl(cpu_cc_dst
, cpu_cc_dst
, 1);
1760 tcg_gen_shri_tl(cpu_cc_src2
, cpu_T
[0], mask
);
1761 tcg_gen_andi_tl(cpu_cc_dst
, cpu_T
[0], 1);
1763 tcg_gen_andi_tl(cpu_cc_src2
, cpu_cc_src2
, 1);
1764 tcg_gen_xor_tl(cpu_cc_src2
, cpu_cc_src2
, cpu_cc_dst
);
1765 set_cc_op(s
, CC_OP_ADCOX
);
1769 /* XXX: add faster immediate = 1 case */
1770 static void gen_rotc_rm_T1(DisasContext
*s
, int ot
, int op1
,
1773 gen_compute_eflags(s
);
1774 assert(s
->cc_op
== CC_OP_EFLAGS
);
1778 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1780 gen_op_mov_TN_reg(ot
, 0, op1
);
1785 gen_helper_rcrb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1788 gen_helper_rcrw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1791 gen_helper_rcrl(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1793 #ifdef TARGET_X86_64
1795 gen_helper_rcrq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1802 gen_helper_rclb(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1805 gen_helper_rclw(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1808 gen_helper_rcll(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1810 #ifdef TARGET_X86_64
1812 gen_helper_rclq(cpu_T
[0], cpu_env
, cpu_T
[0], cpu_T
[1]);
1818 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1821 /* XXX: add faster immediate case */
1822 static void gen_shiftd_rm_T1(DisasContext
*s
, int ot
, int op1
,
1823 bool is_right
, TCGv count_in
)
1825 target_ulong mask
= (ot
== MO_64
? 63 : 31);
1829 if (op1
== OR_TMP0
) {
1830 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
1832 gen_op_mov_TN_reg(ot
, 0, op1
);
1835 count
= tcg_temp_new();
1836 tcg_gen_andi_tl(count
, count_in
, mask
);
1840 /* Note: we implement the Intel behaviour for shift count > 16.
1841 This means "shrdw C, B, A" shifts A:B:A >> C. Build the B:A
1842 portion by constructing it as a 32-bit value. */
1844 tcg_gen_deposit_tl(cpu_tmp0
, cpu_T
[0], cpu_T
[1], 16, 16);
1845 tcg_gen_mov_tl(cpu_T
[1], cpu_T
[0]);
1846 tcg_gen_mov_tl(cpu_T
[0], cpu_tmp0
);
1848 tcg_gen_deposit_tl(cpu_T
[1], cpu_T
[0], cpu_T
[1], 16, 16);
1851 #ifdef TARGET_X86_64
1853 /* Concatenate the two 32-bit values and use a 64-bit shift. */
1854 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1856 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1857 tcg_gen_shr_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1858 tcg_gen_shr_i64(cpu_T
[0], cpu_T
[0], count
);
1860 tcg_gen_concat_tl_i64(cpu_T
[0], cpu_T
[1], cpu_T
[0]);
1861 tcg_gen_shl_i64(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1862 tcg_gen_shl_i64(cpu_T
[0], cpu_T
[0], count
);
1863 tcg_gen_shri_i64(cpu_tmp0
, cpu_tmp0
, 32);
1864 tcg_gen_shri_i64(cpu_T
[0], cpu_T
[0], 32);
1869 tcg_gen_subi_tl(cpu_tmp0
, count
, 1);
1871 tcg_gen_shr_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1873 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1874 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], count
);
1875 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1877 tcg_gen_shl_tl(cpu_tmp0
, cpu_T
[0], cpu_tmp0
);
1879 /* Only needed if count > 16, for Intel behaviour. */
1880 tcg_gen_subfi_tl(cpu_tmp4
, 33, count
);
1881 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[1], cpu_tmp4
);
1882 tcg_gen_or_tl(cpu_tmp0
, cpu_tmp0
, cpu_tmp4
);
1885 tcg_gen_subfi_tl(cpu_tmp4
, mask
+ 1, count
);
1886 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], count
);
1887 tcg_gen_shr_tl(cpu_T
[1], cpu_T
[1], cpu_tmp4
);
1889 tcg_gen_movi_tl(cpu_tmp4
, 0);
1890 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[1], count
, cpu_tmp4
,
1891 cpu_tmp4
, cpu_T
[1]);
1892 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
1897 gen_op_st_rm_T0_A0(s
, ot
, op1
);
1899 gen_shift_flags(s
, ot
, cpu_T
[0], cpu_tmp0
, count
, is_right
);
1900 tcg_temp_free(count
);
1903 static void gen_shift(DisasContext
*s1
, int op
, int ot
, int d
, int s
)
1906 gen_op_mov_TN_reg(ot
, 1, s
);
1909 gen_rot_rm_T1(s1
, ot
, d
, 0);
1912 gen_rot_rm_T1(s1
, ot
, d
, 1);
1916 gen_shift_rm_T1(s1
, ot
, d
, 0, 0);
1919 gen_shift_rm_T1(s1
, ot
, d
, 1, 0);
1922 gen_shift_rm_T1(s1
, ot
, d
, 1, 1);
1925 gen_rotc_rm_T1(s1
, ot
, d
, 0);
1928 gen_rotc_rm_T1(s1
, ot
, d
, 1);
1933 static void gen_shifti(DisasContext
*s1
, int op
, int ot
, int d
, int c
)
1937 gen_rot_rm_im(s1
, ot
, d
, c
, 0);
1940 gen_rot_rm_im(s1
, ot
, d
, c
, 1);
1944 gen_shift_rm_im(s1
, ot
, d
, c
, 0, 0);
1947 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 0);
1950 gen_shift_rm_im(s1
, ot
, d
, c
, 1, 1);
1953 /* currently not optimized */
1954 gen_op_movl_T1_im(c
);
1955 gen_shift(s1
, op
, ot
, d
, OR_TMP1
);
1960 static void gen_lea_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
1967 int mod
, rm
, code
, override
, must_add_seg
;
1970 override
= s
->override
;
1971 must_add_seg
= s
->addseg
;
1974 mod
= (modrm
>> 6) & 3;
1985 code
= cpu_ldub_code(env
, s
->pc
++);
1986 scale
= (code
>> 6) & 3;
1987 index
= ((code
>> 3) & 7) | REX_X(s
);
1989 index
= -1; /* no index */
1997 if ((base
& 7) == 5) {
1999 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2001 if (CODE64(s
) && !havesib
) {
2002 disp
+= s
->pc
+ s
->rip_offset
;
2009 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2013 disp
= (int32_t)cpu_ldl_code(env
, s
->pc
);
2018 /* For correct popl handling with esp. */
2019 if (base
== R_ESP
&& s
->popl_esp_hack
) {
2020 disp
+= s
->popl_esp_hack
;
2023 /* Compute the address, with a minimum number of TCG ops. */
2027 sum
= cpu_regs
[index
];
2029 tcg_gen_shli_tl(cpu_A0
, cpu_regs
[index
], scale
);
2033 tcg_gen_add_tl(cpu_A0
, sum
, cpu_regs
[base
]);
2036 } else if (base
>= 0) {
2037 sum
= cpu_regs
[base
];
2039 if (TCGV_IS_UNUSED(sum
)) {
2040 tcg_gen_movi_tl(cpu_A0
, disp
);
2042 tcg_gen_addi_tl(cpu_A0
, sum
, disp
);
2047 if (base
== R_EBP
|| base
== R_ESP
) {
2054 tcg_gen_ld_tl(cpu_tmp0
, cpu_env
,
2055 offsetof(CPUX86State
, segs
[override
].base
));
2057 if (s
->aflag
!= 2) {
2058 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2060 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
2064 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
2067 if (s
->aflag
!= 2) {
2068 tcg_gen_ext32u_tl(cpu_A0
, cpu_A0
);
2074 disp
= cpu_lduw_code(env
, s
->pc
);
2076 gen_op_movl_A0_im(disp
);
2077 rm
= 0; /* avoid SS override */
2084 disp
= (int8_t)cpu_ldub_code(env
, s
->pc
++);
2088 disp
= cpu_lduw_code(env
, s
->pc
);
2094 gen_op_movl_A0_reg(R_EBX
);
2095 gen_op_addl_A0_reg_sN(0, R_ESI
);
2098 gen_op_movl_A0_reg(R_EBX
);
2099 gen_op_addl_A0_reg_sN(0, R_EDI
);
2102 gen_op_movl_A0_reg(R_EBP
);
2103 gen_op_addl_A0_reg_sN(0, R_ESI
);
2106 gen_op_movl_A0_reg(R_EBP
);
2107 gen_op_addl_A0_reg_sN(0, R_EDI
);
2110 gen_op_movl_A0_reg(R_ESI
);
2113 gen_op_movl_A0_reg(R_EDI
);
2116 gen_op_movl_A0_reg(R_EBP
);
2120 gen_op_movl_A0_reg(R_EBX
);
2124 gen_op_addl_A0_im(disp
);
2125 gen_op_andl_A0_ffff();
2129 if (rm
== 2 || rm
== 3 || rm
== 6)
2134 gen_op_addl_A0_seg(s
, override
);
2139 static void gen_nop_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
)
2141 int mod
, rm
, base
, code
;
2143 mod
= (modrm
>> 6) & 3;
2153 code
= cpu_ldub_code(env
, s
->pc
++);
2189 /* used for LEA and MOV AX, mem */
2190 static void gen_add_A0_ds_seg(DisasContext
*s
)
2192 int override
, must_add_seg
;
2193 must_add_seg
= s
->addseg
;
2195 if (s
->override
>= 0) {
2196 override
= s
->override
;
2200 #ifdef TARGET_X86_64
2202 gen_op_addq_A0_seg(override
);
2206 gen_op_addl_A0_seg(s
, override
);
2211 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2213 static void gen_ldst_modrm(CPUX86State
*env
, DisasContext
*s
, int modrm
,
2214 int ot
, int reg
, int is_store
)
2218 mod
= (modrm
>> 6) & 3;
2219 rm
= (modrm
& 7) | REX_B(s
);
2223 gen_op_mov_TN_reg(ot
, 0, reg
);
2224 gen_op_mov_reg_T0(ot
, rm
);
2226 gen_op_mov_TN_reg(ot
, 0, rm
);
2228 gen_op_mov_reg_T0(ot
, reg
);
2231 gen_lea_modrm(env
, s
, modrm
);
2234 gen_op_mov_TN_reg(ot
, 0, reg
);
2235 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2237 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
2239 gen_op_mov_reg_T0(ot
, reg
);
2244 static inline uint32_t insn_get(CPUX86State
*env
, DisasContext
*s
, int ot
)
2250 ret
= cpu_ldub_code(env
, s
->pc
);
2254 ret
= cpu_lduw_code(env
, s
->pc
);
2259 ret
= cpu_ldl_code(env
, s
->pc
);
2266 static inline int insn_const_size(unsigned int ot
)
2275 static inline void gen_goto_tb(DisasContext
*s
, int tb_num
, target_ulong eip
)
2277 TranslationBlock
*tb
;
2280 pc
= s
->cs_base
+ eip
;
2282 /* NOTE: we handle the case where the TB spans two pages here */
2283 if ((pc
& TARGET_PAGE_MASK
) == (tb
->pc
& TARGET_PAGE_MASK
) ||
2284 (pc
& TARGET_PAGE_MASK
) == ((s
->pc
- 1) & TARGET_PAGE_MASK
)) {
2285 /* jump to same page: we can use a direct jump */
2286 tcg_gen_goto_tb(tb_num
);
2288 tcg_gen_exit_tb((uintptr_t)tb
+ tb_num
);
2290 /* jump to another page: currently not optimized */
2296 static inline void gen_jcc(DisasContext
*s
, int b
,
2297 target_ulong val
, target_ulong next_eip
)
2302 l1
= gen_new_label();
2305 gen_goto_tb(s
, 0, next_eip
);
2308 gen_goto_tb(s
, 1, val
);
2309 s
->is_jmp
= DISAS_TB_JUMP
;
2311 l1
= gen_new_label();
2312 l2
= gen_new_label();
2315 gen_jmp_im(next_eip
);
2325 static void gen_cmovcc1(CPUX86State
*env
, DisasContext
*s
, int ot
, int b
,
2330 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
2332 cc
= gen_prepare_cc(s
, b
, cpu_T
[1]);
2333 if (cc
.mask
!= -1) {
2334 TCGv t0
= tcg_temp_new();
2335 tcg_gen_andi_tl(t0
, cc
.reg
, cc
.mask
);
2339 cc
.reg2
= tcg_const_tl(cc
.imm
);
2342 tcg_gen_movcond_tl(cc
.cond
, cpu_T
[0], cc
.reg
, cc
.reg2
,
2343 cpu_T
[0], cpu_regs
[reg
]);
2344 gen_op_mov_reg_T0(ot
, reg
);
2346 if (cc
.mask
!= -1) {
2347 tcg_temp_free(cc
.reg
);
2350 tcg_temp_free(cc
.reg2
);
2354 static inline void gen_op_movl_T0_seg(int seg_reg
)
2356 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
2357 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2360 static inline void gen_op_movl_seg_T0_vm(int seg_reg
)
2362 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xffff);
2363 tcg_gen_st32_tl(cpu_T
[0], cpu_env
,
2364 offsetof(CPUX86State
,segs
[seg_reg
].selector
));
2365 tcg_gen_shli_tl(cpu_T
[0], cpu_T
[0], 4);
2366 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
2367 offsetof(CPUX86State
,segs
[seg_reg
].base
));
2370 /* move T0 to seg_reg and compute if the CPU state may change. Never
2371 call this function with seg_reg == R_CS */
2372 static void gen_movl_seg_T0(DisasContext
*s
, int seg_reg
, target_ulong cur_eip
)
2374 if (s
->pe
&& !s
->vm86
) {
2375 /* XXX: optimize by finding processor state dynamically */
2376 gen_update_cc_op(s
);
2377 gen_jmp_im(cur_eip
);
2378 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
2379 gen_helper_load_seg(cpu_env
, tcg_const_i32(seg_reg
), cpu_tmp2_i32
);
2380 /* abort translation because the addseg value may change or
2381 because ss32 may change. For R_SS, translation must always
2382 stop as a special handling must be done to disable hardware
2383 interrupts for the next instruction */
2384 if (seg_reg
== R_SS
|| (s
->code32
&& seg_reg
< R_FS
))
2385 s
->is_jmp
= DISAS_TB_JUMP
;
2387 gen_op_movl_seg_T0_vm(seg_reg
);
2388 if (seg_reg
== R_SS
)
2389 s
->is_jmp
= DISAS_TB_JUMP
;
2393 static inline int svm_is_rep(int prefixes
)
2395 return ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) ? 8 : 0);
2399 gen_svm_check_intercept_param(DisasContext
*s
, target_ulong pc_start
,
2400 uint32_t type
, uint64_t param
)
2402 /* no SVM activated; fast case */
2403 if (likely(!(s
->flags
& HF_SVMI_MASK
)))
2405 gen_update_cc_op(s
);
2406 gen_jmp_im(pc_start
- s
->cs_base
);
2407 gen_helper_svm_check_intercept_param(cpu_env
, tcg_const_i32(type
),
2408 tcg_const_i64(param
));
2412 gen_svm_check_intercept(DisasContext
*s
, target_ulong pc_start
, uint64_t type
)
2414 gen_svm_check_intercept_param(s
, pc_start
, type
, 0);
2417 static inline void gen_stack_update(DisasContext
*s
, int addend
)
2419 #ifdef TARGET_X86_64
2421 gen_op_add_reg_im(2, R_ESP
, addend
);
2425 gen_op_add_reg_im(1, R_ESP
, addend
);
2427 gen_op_add_reg_im(0, R_ESP
, addend
);
2431 /* generate a push. It depends on ss32, addseg and dflag */
2432 static void gen_push_T0(DisasContext
*s
)
2434 #ifdef TARGET_X86_64
2436 gen_op_movq_A0_reg(R_ESP
);
2438 gen_op_addq_A0_im(-8);
2439 gen_op_st_v(s
, MO_64
, cpu_T
[0], cpu_A0
);
2441 gen_op_addq_A0_im(-2);
2442 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
2444 gen_op_mov_reg_A0(2, R_ESP
);
2448 gen_op_movl_A0_reg(R_ESP
);
2450 gen_op_addl_A0_im(-2);
2452 gen_op_addl_A0_im(-4);
2455 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2456 gen_op_addl_A0_seg(s
, R_SS
);
2459 gen_op_andl_A0_ffff();
2460 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2461 gen_op_addl_A0_seg(s
, R_SS
);
2463 gen_op_st_v(s
, s
->dflag
+ 1, cpu_T
[0], cpu_A0
);
2464 if (s
->ss32
&& !s
->addseg
)
2465 gen_op_mov_reg_A0(1, R_ESP
);
2467 gen_op_mov_reg_T1(s
->ss32
+ 1, R_ESP
);
2471 /* generate a push. It depends on ss32, addseg and dflag */
2472 /* slower version for T1, only used for call Ev */
2473 static void gen_push_T1(DisasContext
*s
)
2475 #ifdef TARGET_X86_64
2477 gen_op_movq_A0_reg(R_ESP
);
2479 gen_op_addq_A0_im(-8);
2480 gen_op_st_v(s
, MO_64
, cpu_T
[1], cpu_A0
);
2482 gen_op_addq_A0_im(-2);
2483 gen_op_st_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
2485 gen_op_mov_reg_A0(2, R_ESP
);
2489 gen_op_movl_A0_reg(R_ESP
);
2491 gen_op_addl_A0_im(-2);
2493 gen_op_addl_A0_im(-4);
2496 gen_op_addl_A0_seg(s
, R_SS
);
2499 gen_op_andl_A0_ffff();
2500 gen_op_addl_A0_seg(s
, R_SS
);
2502 gen_op_st_v(s
, s
->dflag
+ 1, cpu_T
[1], cpu_A0
);
2504 if (s
->ss32
&& !s
->addseg
)
2505 gen_op_mov_reg_A0(1, R_ESP
);
2507 gen_stack_update(s
, (-2) << s
->dflag
);
2511 /* two step pop is necessary for precise exceptions */
2512 static void gen_pop_T0(DisasContext
*s
)
2514 #ifdef TARGET_X86_64
2516 gen_op_movq_A0_reg(R_ESP
);
2517 gen_op_ld_v(s
, s
->dflag
? MO_64
: MO_16
, cpu_T
[0], cpu_A0
);
2521 gen_op_movl_A0_reg(R_ESP
);
2524 gen_op_addl_A0_seg(s
, R_SS
);
2526 gen_op_andl_A0_ffff();
2527 gen_op_addl_A0_seg(s
, R_SS
);
2529 gen_op_ld_v(s
, s
->dflag
+ 1, cpu_T
[0], cpu_A0
);
2533 static void gen_pop_update(DisasContext
*s
)
2535 #ifdef TARGET_X86_64
2536 if (CODE64(s
) && s
->dflag
) {
2537 gen_stack_update(s
, 8);
2541 gen_stack_update(s
, 2 << s
->dflag
);
2545 static void gen_stack_A0(DisasContext
*s
)
2547 gen_op_movl_A0_reg(R_ESP
);
2549 gen_op_andl_A0_ffff();
2550 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2552 gen_op_addl_A0_seg(s
, R_SS
);
2555 /* NOTE: wrap around in 16 bit not fully handled */
2556 static void gen_pusha(DisasContext
*s
)
2559 gen_op_movl_A0_reg(R_ESP
);
2560 gen_op_addl_A0_im(-16 << s
->dflag
);
2562 gen_op_andl_A0_ffff();
2563 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2565 gen_op_addl_A0_seg(s
, R_SS
);
2566 for(i
= 0;i
< 8; i
++) {
2567 gen_op_mov_TN_reg(MO_32
, 0, 7 - i
);
2568 gen_op_st_v(s
, MO_16
+ s
->dflag
, cpu_T
[0], cpu_A0
);
2569 gen_op_addl_A0_im(2 << s
->dflag
);
2571 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2574 /* NOTE: wrap around in 16 bit not fully handled */
2575 static void gen_popa(DisasContext
*s
)
2578 gen_op_movl_A0_reg(R_ESP
);
2580 gen_op_andl_A0_ffff();
2581 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2582 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], 16 << s
->dflag
);
2584 gen_op_addl_A0_seg(s
, R_SS
);
2585 for(i
= 0;i
< 8; i
++) {
2586 /* ESP is not reloaded */
2588 gen_op_ld_v(s
, MO_16
+ s
->dflag
, cpu_T
[0], cpu_A0
);
2589 gen_op_mov_reg_T0(MO_16
+ s
->dflag
, 7 - i
);
2591 gen_op_addl_A0_im(2 << s
->dflag
);
2593 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2596 static void gen_enter(DisasContext
*s
, int esp_addend
, int level
)
2601 #ifdef TARGET_X86_64
2603 ot
= s
->dflag
? MO_64
: MO_16
;
2606 gen_op_movl_A0_reg(R_ESP
);
2607 gen_op_addq_A0_im(-opsize
);
2608 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2611 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2612 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2614 /* XXX: must save state */
2615 gen_helper_enter64_level(cpu_env
, tcg_const_i32(level
),
2616 tcg_const_i32((ot
== MO_64
)),
2619 gen_op_mov_reg_T1(ot
, R_EBP
);
2620 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2621 gen_op_mov_reg_T1(MO_64
, R_ESP
);
2625 ot
= s
->dflag
+ MO_16
;
2626 opsize
= 2 << s
->dflag
;
2628 gen_op_movl_A0_reg(R_ESP
);
2629 gen_op_addl_A0_im(-opsize
);
2631 gen_op_andl_A0_ffff();
2632 tcg_gen_mov_tl(cpu_T
[1], cpu_A0
);
2634 gen_op_addl_A0_seg(s
, R_SS
);
2636 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
2637 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
2639 /* XXX: must save state */
2640 gen_helper_enter_level(cpu_env
, tcg_const_i32(level
),
2641 tcg_const_i32(s
->dflag
),
2644 gen_op_mov_reg_T1(ot
, R_EBP
);
2645 tcg_gen_addi_tl(cpu_T
[1], cpu_T
[1], -esp_addend
+ (-opsize
* level
));
2646 gen_op_mov_reg_T1(MO_16
+ s
->ss32
, R_ESP
);
2650 static void gen_exception(DisasContext
*s
, int trapno
, target_ulong cur_eip
)
2652 gen_update_cc_op(s
);
2653 gen_jmp_im(cur_eip
);
2654 gen_helper_raise_exception(cpu_env
, tcg_const_i32(trapno
));
2655 s
->is_jmp
= DISAS_TB_JUMP
;
2658 /* an interrupt is different from an exception because of the
2660 static void gen_interrupt(DisasContext
*s
, int intno
,
2661 target_ulong cur_eip
, target_ulong next_eip
)
2663 gen_update_cc_op(s
);
2664 gen_jmp_im(cur_eip
);
2665 gen_helper_raise_interrupt(cpu_env
, tcg_const_i32(intno
),
2666 tcg_const_i32(next_eip
- cur_eip
));
2667 s
->is_jmp
= DISAS_TB_JUMP
;
2670 static void gen_debug(DisasContext
*s
, target_ulong cur_eip
)
2672 gen_update_cc_op(s
);
2673 gen_jmp_im(cur_eip
);
2674 gen_helper_debug(cpu_env
);
2675 s
->is_jmp
= DISAS_TB_JUMP
;
2678 /* generate a generic end of block. Trace exception is also generated
2680 static void gen_eob(DisasContext
*s
)
2682 gen_update_cc_op(s
);
2683 if (s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
) {
2684 gen_helper_reset_inhibit_irq(cpu_env
);
2686 if (s
->tb
->flags
& HF_RF_MASK
) {
2687 gen_helper_reset_rf(cpu_env
);
2689 if (s
->singlestep_enabled
) {
2690 gen_helper_debug(cpu_env
);
2692 gen_helper_single_step(cpu_env
);
2696 s
->is_jmp
= DISAS_TB_JUMP
;
2699 /* generate a jump to eip. No segment change must happen before as a
2700 direct call to the next block may occur */
2701 static void gen_jmp_tb(DisasContext
*s
, target_ulong eip
, int tb_num
)
2703 gen_update_cc_op(s
);
2704 set_cc_op(s
, CC_OP_DYNAMIC
);
2706 gen_goto_tb(s
, tb_num
, eip
);
2707 s
->is_jmp
= DISAS_TB_JUMP
;
2714 static void gen_jmp(DisasContext
*s
, target_ulong eip
)
2716 gen_jmp_tb(s
, eip
, 0);
2719 static inline void gen_ldq_env_A0(DisasContext
*s
, int offset
)
2721 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2722 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2725 static inline void gen_stq_env_A0(DisasContext
*s
, int offset
)
2727 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
);
2728 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
2731 static inline void gen_ldo_env_A0(DisasContext
*s
, int offset
)
2733 int mem_index
= s
->mem_index
;
2734 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2735 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2736 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2737 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2738 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2741 static inline void gen_sto_env_A0(DisasContext
*s
, int offset
)
2743 int mem_index
= s
->mem_index
;
2744 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(0)));
2745 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, mem_index
, MO_LEQ
);
2746 tcg_gen_addi_tl(cpu_tmp0
, cpu_A0
, 8);
2747 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, offset
+ offsetof(XMMReg
, XMM_Q(1)));
2748 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_tmp0
, mem_index
, MO_LEQ
);
2751 static inline void gen_op_movo(int d_offset
, int s_offset
)
2753 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2754 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2755 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
+ 8);
2756 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
+ 8);
2759 static inline void gen_op_movq(int d_offset
, int s_offset
)
2761 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
, s_offset
);
2762 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2765 static inline void gen_op_movl(int d_offset
, int s_offset
)
2767 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
, s_offset
);
2768 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, d_offset
);
2771 static inline void gen_op_movq_env_0(int d_offset
)
2773 tcg_gen_movi_i64(cpu_tmp1_i64
, 0);
2774 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
, d_offset
);
2777 typedef void (*SSEFunc_i_ep
)(TCGv_i32 val
, TCGv_ptr env
, TCGv_ptr reg
);
2778 typedef void (*SSEFunc_l_ep
)(TCGv_i64 val
, TCGv_ptr env
, TCGv_ptr reg
);
2779 typedef void (*SSEFunc_0_epi
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i32 val
);
2780 typedef void (*SSEFunc_0_epl
)(TCGv_ptr env
, TCGv_ptr reg
, TCGv_i64 val
);
2781 typedef void (*SSEFunc_0_epp
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
);
2782 typedef void (*SSEFunc_0_eppi
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2784 typedef void (*SSEFunc_0_ppi
)(TCGv_ptr reg_a
, TCGv_ptr reg_b
, TCGv_i32 val
);
2785 typedef void (*SSEFunc_0_eppt
)(TCGv_ptr env
, TCGv_ptr reg_a
, TCGv_ptr reg_b
,
2788 #define SSE_SPECIAL ((void *)1)
2789 #define SSE_DUMMY ((void *)2)
2791 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2792 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2793 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2795 static const SSEFunc_0_epp sse_op_table1
[256][4] = {
2796 /* 3DNow! extensions */
2797 [0x0e] = { SSE_DUMMY
}, /* femms */
2798 [0x0f] = { SSE_DUMMY
}, /* pf... */
2799 /* pure SSE operations */
2800 [0x10] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2801 [0x11] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movups, movupd, movss, movsd */
2802 [0x12] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd, movsldup, movddup */
2803 [0x13] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movlps, movlpd */
2804 [0x14] = { gen_helper_punpckldq_xmm
, gen_helper_punpcklqdq_xmm
},
2805 [0x15] = { gen_helper_punpckhdq_xmm
, gen_helper_punpckhqdq_xmm
},
2806 [0x16] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd, movshdup */
2807 [0x17] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movhps, movhpd */
2809 [0x28] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2810 [0x29] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movaps, movapd */
2811 [0x2a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2812 [0x2b] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movntps, movntpd, movntss, movntsd */
2813 [0x2c] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2814 [0x2d] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2815 [0x2e] = { gen_helper_ucomiss
, gen_helper_ucomisd
},
2816 [0x2f] = { gen_helper_comiss
, gen_helper_comisd
},
2817 [0x50] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movmskps, movmskpd */
2818 [0x51] = SSE_FOP(sqrt
),
2819 [0x52] = { gen_helper_rsqrtps
, NULL
, gen_helper_rsqrtss
, NULL
},
2820 [0x53] = { gen_helper_rcpps
, NULL
, gen_helper_rcpss
, NULL
},
2821 [0x54] = { gen_helper_pand_xmm
, gen_helper_pand_xmm
}, /* andps, andpd */
2822 [0x55] = { gen_helper_pandn_xmm
, gen_helper_pandn_xmm
}, /* andnps, andnpd */
2823 [0x56] = { gen_helper_por_xmm
, gen_helper_por_xmm
}, /* orps, orpd */
2824 [0x57] = { gen_helper_pxor_xmm
, gen_helper_pxor_xmm
}, /* xorps, xorpd */
2825 [0x58] = SSE_FOP(add
),
2826 [0x59] = SSE_FOP(mul
),
2827 [0x5a] = { gen_helper_cvtps2pd
, gen_helper_cvtpd2ps
,
2828 gen_helper_cvtss2sd
, gen_helper_cvtsd2ss
},
2829 [0x5b] = { gen_helper_cvtdq2ps
, gen_helper_cvtps2dq
, gen_helper_cvttps2dq
},
2830 [0x5c] = SSE_FOP(sub
),
2831 [0x5d] = SSE_FOP(min
),
2832 [0x5e] = SSE_FOP(div
),
2833 [0x5f] = SSE_FOP(max
),
2835 [0xc2] = SSE_FOP(cmpeq
),
2836 [0xc6] = { (SSEFunc_0_epp
)gen_helper_shufps
,
2837 (SSEFunc_0_epp
)gen_helper_shufpd
}, /* XXX: casts */
2839 /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */
2840 [0x38] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2841 [0x3a] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2843 /* MMX ops and their SSE extensions */
2844 [0x60] = MMX_OP2(punpcklbw
),
2845 [0x61] = MMX_OP2(punpcklwd
),
2846 [0x62] = MMX_OP2(punpckldq
),
2847 [0x63] = MMX_OP2(packsswb
),
2848 [0x64] = MMX_OP2(pcmpgtb
),
2849 [0x65] = MMX_OP2(pcmpgtw
),
2850 [0x66] = MMX_OP2(pcmpgtl
),
2851 [0x67] = MMX_OP2(packuswb
),
2852 [0x68] = MMX_OP2(punpckhbw
),
2853 [0x69] = MMX_OP2(punpckhwd
),
2854 [0x6a] = MMX_OP2(punpckhdq
),
2855 [0x6b] = MMX_OP2(packssdw
),
2856 [0x6c] = { NULL
, gen_helper_punpcklqdq_xmm
},
2857 [0x6d] = { NULL
, gen_helper_punpckhqdq_xmm
},
2858 [0x6e] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movd mm, ea */
2859 [0x6f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, , movqdu */
2860 [0x70] = { (SSEFunc_0_epp
)gen_helper_pshufw_mmx
,
2861 (SSEFunc_0_epp
)gen_helper_pshufd_xmm
,
2862 (SSEFunc_0_epp
)gen_helper_pshufhw_xmm
,
2863 (SSEFunc_0_epp
)gen_helper_pshuflw_xmm
}, /* XXX: casts */
2864 [0x71] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftw */
2865 [0x72] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftd */
2866 [0x73] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* shiftq */
2867 [0x74] = MMX_OP2(pcmpeqb
),
2868 [0x75] = MMX_OP2(pcmpeqw
),
2869 [0x76] = MMX_OP2(pcmpeql
),
2870 [0x77] = { SSE_DUMMY
}, /* emms */
2871 [0x78] = { NULL
, SSE_SPECIAL
, NULL
, SSE_SPECIAL
}, /* extrq_i, insertq_i */
2872 [0x79] = { NULL
, gen_helper_extrq_r
, NULL
, gen_helper_insertq_r
},
2873 [0x7c] = { NULL
, gen_helper_haddpd
, NULL
, gen_helper_haddps
},
2874 [0x7d] = { NULL
, gen_helper_hsubpd
, NULL
, gen_helper_hsubps
},
2875 [0x7e] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movd, movd, , movq */
2876 [0x7f] = { SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
}, /* movq, movdqa, movdqu */
2877 [0xc4] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pinsrw */
2878 [0xc5] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pextrw */
2879 [0xd0] = { NULL
, gen_helper_addsubpd
, NULL
, gen_helper_addsubps
},
2880 [0xd1] = MMX_OP2(psrlw
),
2881 [0xd2] = MMX_OP2(psrld
),
2882 [0xd3] = MMX_OP2(psrlq
),
2883 [0xd4] = MMX_OP2(paddq
),
2884 [0xd5] = MMX_OP2(pmullw
),
2885 [0xd6] = { NULL
, SSE_SPECIAL
, SSE_SPECIAL
, SSE_SPECIAL
},
2886 [0xd7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* pmovmskb */
2887 [0xd8] = MMX_OP2(psubusb
),
2888 [0xd9] = MMX_OP2(psubusw
),
2889 [0xda] = MMX_OP2(pminub
),
2890 [0xdb] = MMX_OP2(pand
),
2891 [0xdc] = MMX_OP2(paddusb
),
2892 [0xdd] = MMX_OP2(paddusw
),
2893 [0xde] = MMX_OP2(pmaxub
),
2894 [0xdf] = MMX_OP2(pandn
),
2895 [0xe0] = MMX_OP2(pavgb
),
2896 [0xe1] = MMX_OP2(psraw
),
2897 [0xe2] = MMX_OP2(psrad
),
2898 [0xe3] = MMX_OP2(pavgw
),
2899 [0xe4] = MMX_OP2(pmulhuw
),
2900 [0xe5] = MMX_OP2(pmulhw
),
2901 [0xe6] = { NULL
, gen_helper_cvttpd2dq
, gen_helper_cvtdq2pd
, gen_helper_cvtpd2dq
},
2902 [0xe7] = { SSE_SPECIAL
, SSE_SPECIAL
}, /* movntq, movntq */
2903 [0xe8] = MMX_OP2(psubsb
),
2904 [0xe9] = MMX_OP2(psubsw
),
2905 [0xea] = MMX_OP2(pminsw
),
2906 [0xeb] = MMX_OP2(por
),
2907 [0xec] = MMX_OP2(paddsb
),
2908 [0xed] = MMX_OP2(paddsw
),
2909 [0xee] = MMX_OP2(pmaxsw
),
2910 [0xef] = MMX_OP2(pxor
),
2911 [0xf0] = { NULL
, NULL
, NULL
, SSE_SPECIAL
}, /* lddqu */
2912 [0xf1] = MMX_OP2(psllw
),
2913 [0xf2] = MMX_OP2(pslld
),
2914 [0xf3] = MMX_OP2(psllq
),
2915 [0xf4] = MMX_OP2(pmuludq
),
2916 [0xf5] = MMX_OP2(pmaddwd
),
2917 [0xf6] = MMX_OP2(psadbw
),
2918 [0xf7] = { (SSEFunc_0_epp
)gen_helper_maskmov_mmx
,
2919 (SSEFunc_0_epp
)gen_helper_maskmov_xmm
}, /* XXX: casts */
2920 [0xf8] = MMX_OP2(psubb
),
2921 [0xf9] = MMX_OP2(psubw
),
2922 [0xfa] = MMX_OP2(psubl
),
2923 [0xfb] = MMX_OP2(psubq
),
2924 [0xfc] = MMX_OP2(paddb
),
2925 [0xfd] = MMX_OP2(paddw
),
2926 [0xfe] = MMX_OP2(paddl
),
2929 static const SSEFunc_0_epp sse_op_table2
[3 * 8][2] = {
2930 [0 + 2] = MMX_OP2(psrlw
),
2931 [0 + 4] = MMX_OP2(psraw
),
2932 [0 + 6] = MMX_OP2(psllw
),
2933 [8 + 2] = MMX_OP2(psrld
),
2934 [8 + 4] = MMX_OP2(psrad
),
2935 [8 + 6] = MMX_OP2(pslld
),
2936 [16 + 2] = MMX_OP2(psrlq
),
2937 [16 + 3] = { NULL
, gen_helper_psrldq_xmm
},
2938 [16 + 6] = MMX_OP2(psllq
),
2939 [16 + 7] = { NULL
, gen_helper_pslldq_xmm
},
2942 static const SSEFunc_0_epi sse_op_table3ai
[] = {
2943 gen_helper_cvtsi2ss
,
2947 #ifdef TARGET_X86_64
2948 static const SSEFunc_0_epl sse_op_table3aq
[] = {
2949 gen_helper_cvtsq2ss
,
2954 static const SSEFunc_i_ep sse_op_table3bi
[] = {
2955 gen_helper_cvttss2si
,
2956 gen_helper_cvtss2si
,
2957 gen_helper_cvttsd2si
,
2961 #ifdef TARGET_X86_64
2962 static const SSEFunc_l_ep sse_op_table3bq
[] = {
2963 gen_helper_cvttss2sq
,
2964 gen_helper_cvtss2sq
,
2965 gen_helper_cvttsd2sq
,
2970 static const SSEFunc_0_epp sse_op_table4
[8][4] = {
2981 static const SSEFunc_0_epp sse_op_table5
[256] = {
2982 [0x0c] = gen_helper_pi2fw
,
2983 [0x0d] = gen_helper_pi2fd
,
2984 [0x1c] = gen_helper_pf2iw
,
2985 [0x1d] = gen_helper_pf2id
,
2986 [0x8a] = gen_helper_pfnacc
,
2987 [0x8e] = gen_helper_pfpnacc
,
2988 [0x90] = gen_helper_pfcmpge
,
2989 [0x94] = gen_helper_pfmin
,
2990 [0x96] = gen_helper_pfrcp
,
2991 [0x97] = gen_helper_pfrsqrt
,
2992 [0x9a] = gen_helper_pfsub
,
2993 [0x9e] = gen_helper_pfadd
,
2994 [0xa0] = gen_helper_pfcmpgt
,
2995 [0xa4] = gen_helper_pfmax
,
2996 [0xa6] = gen_helper_movq
, /* pfrcpit1; no need to actually increase precision */
2997 [0xa7] = gen_helper_movq
, /* pfrsqit1 */
2998 [0xaa] = gen_helper_pfsubr
,
2999 [0xae] = gen_helper_pfacc
,
3000 [0xb0] = gen_helper_pfcmpeq
,
3001 [0xb4] = gen_helper_pfmul
,
3002 [0xb6] = gen_helper_movq
, /* pfrcpit2 */
3003 [0xb7] = gen_helper_pmulhrw_mmx
,
3004 [0xbb] = gen_helper_pswapd
,
3005 [0xbf] = gen_helper_pavgb_mmx
/* pavgusb */
3008 struct SSEOpHelper_epp
{
3009 SSEFunc_0_epp op
[2];
3013 struct SSEOpHelper_eppi
{
3014 SSEFunc_0_eppi op
[2];
3018 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3019 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3020 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3021 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3022 #define PCLMULQDQ_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, \
3023 CPUID_EXT_PCLMULQDQ }
3024 #define AESNI_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_AES }
3026 static const struct SSEOpHelper_epp sse_op_table6
[256] = {
3027 [0x00] = SSSE3_OP(pshufb
),
3028 [0x01] = SSSE3_OP(phaddw
),
3029 [0x02] = SSSE3_OP(phaddd
),
3030 [0x03] = SSSE3_OP(phaddsw
),
3031 [0x04] = SSSE3_OP(pmaddubsw
),
3032 [0x05] = SSSE3_OP(phsubw
),
3033 [0x06] = SSSE3_OP(phsubd
),
3034 [0x07] = SSSE3_OP(phsubsw
),
3035 [0x08] = SSSE3_OP(psignb
),
3036 [0x09] = SSSE3_OP(psignw
),
3037 [0x0a] = SSSE3_OP(psignd
),
3038 [0x0b] = SSSE3_OP(pmulhrsw
),
3039 [0x10] = SSE41_OP(pblendvb
),
3040 [0x14] = SSE41_OP(blendvps
),
3041 [0x15] = SSE41_OP(blendvpd
),
3042 [0x17] = SSE41_OP(ptest
),
3043 [0x1c] = SSSE3_OP(pabsb
),
3044 [0x1d] = SSSE3_OP(pabsw
),
3045 [0x1e] = SSSE3_OP(pabsd
),
3046 [0x20] = SSE41_OP(pmovsxbw
),
3047 [0x21] = SSE41_OP(pmovsxbd
),
3048 [0x22] = SSE41_OP(pmovsxbq
),
3049 [0x23] = SSE41_OP(pmovsxwd
),
3050 [0x24] = SSE41_OP(pmovsxwq
),
3051 [0x25] = SSE41_OP(pmovsxdq
),
3052 [0x28] = SSE41_OP(pmuldq
),
3053 [0x29] = SSE41_OP(pcmpeqq
),
3054 [0x2a] = SSE41_SPECIAL
, /* movntqda */
3055 [0x2b] = SSE41_OP(packusdw
),
3056 [0x30] = SSE41_OP(pmovzxbw
),
3057 [0x31] = SSE41_OP(pmovzxbd
),
3058 [0x32] = SSE41_OP(pmovzxbq
),
3059 [0x33] = SSE41_OP(pmovzxwd
),
3060 [0x34] = SSE41_OP(pmovzxwq
),
3061 [0x35] = SSE41_OP(pmovzxdq
),
3062 [0x37] = SSE42_OP(pcmpgtq
),
3063 [0x38] = SSE41_OP(pminsb
),
3064 [0x39] = SSE41_OP(pminsd
),
3065 [0x3a] = SSE41_OP(pminuw
),
3066 [0x3b] = SSE41_OP(pminud
),
3067 [0x3c] = SSE41_OP(pmaxsb
),
3068 [0x3d] = SSE41_OP(pmaxsd
),
3069 [0x3e] = SSE41_OP(pmaxuw
),
3070 [0x3f] = SSE41_OP(pmaxud
),
3071 [0x40] = SSE41_OP(pmulld
),
3072 [0x41] = SSE41_OP(phminposuw
),
3073 [0xdb] = AESNI_OP(aesimc
),
3074 [0xdc] = AESNI_OP(aesenc
),
3075 [0xdd] = AESNI_OP(aesenclast
),
3076 [0xde] = AESNI_OP(aesdec
),
3077 [0xdf] = AESNI_OP(aesdeclast
),
3080 static const struct SSEOpHelper_eppi sse_op_table7
[256] = {
3081 [0x08] = SSE41_OP(roundps
),
3082 [0x09] = SSE41_OP(roundpd
),
3083 [0x0a] = SSE41_OP(roundss
),
3084 [0x0b] = SSE41_OP(roundsd
),
3085 [0x0c] = SSE41_OP(blendps
),
3086 [0x0d] = SSE41_OP(blendpd
),
3087 [0x0e] = SSE41_OP(pblendw
),
3088 [0x0f] = SSSE3_OP(palignr
),
3089 [0x14] = SSE41_SPECIAL
, /* pextrb */
3090 [0x15] = SSE41_SPECIAL
, /* pextrw */
3091 [0x16] = SSE41_SPECIAL
, /* pextrd/pextrq */
3092 [0x17] = SSE41_SPECIAL
, /* extractps */
3093 [0x20] = SSE41_SPECIAL
, /* pinsrb */
3094 [0x21] = SSE41_SPECIAL
, /* insertps */
3095 [0x22] = SSE41_SPECIAL
, /* pinsrd/pinsrq */
3096 [0x40] = SSE41_OP(dpps
),
3097 [0x41] = SSE41_OP(dppd
),
3098 [0x42] = SSE41_OP(mpsadbw
),
3099 [0x44] = PCLMULQDQ_OP(pclmulqdq
),
3100 [0x60] = SSE42_OP(pcmpestrm
),
3101 [0x61] = SSE42_OP(pcmpestri
),
3102 [0x62] = SSE42_OP(pcmpistrm
),
3103 [0x63] = SSE42_OP(pcmpistri
),
3104 [0xdf] = AESNI_OP(aeskeygenassist
),
3107 static void gen_sse(CPUX86State
*env
, DisasContext
*s
, int b
,
3108 target_ulong pc_start
, int rex_r
)
3110 int b1
, op1_offset
, op2_offset
, is_xmm
, val
, ot
;
3111 int modrm
, mod
, rm
, reg
;
3112 SSEFunc_0_epp sse_fn_epp
;
3113 SSEFunc_0_eppi sse_fn_eppi
;
3114 SSEFunc_0_ppi sse_fn_ppi
;
3115 SSEFunc_0_eppt sse_fn_eppt
;
3118 if (s
->prefix
& PREFIX_DATA
)
3120 else if (s
->prefix
& PREFIX_REPZ
)
3122 else if (s
->prefix
& PREFIX_REPNZ
)
3126 sse_fn_epp
= sse_op_table1
[b
][b1
];
3130 if ((b
<= 0x5f && b
>= 0x10) || b
== 0xc6 || b
== 0xc2) {
3140 /* simple MMX/SSE operation */
3141 if (s
->flags
& HF_TS_MASK
) {
3142 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
3145 if (s
->flags
& HF_EM_MASK
) {
3147 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
3150 if (is_xmm
&& !(s
->flags
& HF_OSFXSR_MASK
))
3151 if ((b
!= 0x38 && b
!= 0x3a) || (s
->prefix
& PREFIX_DATA
))
3154 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
3157 gen_helper_emms(cpu_env
);
3162 gen_helper_emms(cpu_env
);
3165 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3166 the static cpu state) */
3168 gen_helper_enter_mmx(cpu_env
);
3171 modrm
= cpu_ldub_code(env
, s
->pc
++);
3172 reg
= ((modrm
>> 3) & 7);
3175 mod
= (modrm
>> 6) & 3;
3176 if (sse_fn_epp
== SSE_SPECIAL
) {
3179 case 0x0e7: /* movntq */
3182 gen_lea_modrm(env
, s
, modrm
);
3183 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3185 case 0x1e7: /* movntdq */
3186 case 0x02b: /* movntps */
3187 case 0x12b: /* movntps */
3190 gen_lea_modrm(env
, s
, modrm
);
3191 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3193 case 0x3f0: /* lddqu */
3196 gen_lea_modrm(env
, s
, modrm
);
3197 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3199 case 0x22b: /* movntss */
3200 case 0x32b: /* movntsd */
3203 gen_lea_modrm(env
, s
, modrm
);
3205 gen_stq_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3207 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
3208 xmm_regs
[reg
].XMM_L(0)));
3209 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3212 case 0x6e: /* movd mm, ea */
3213 #ifdef TARGET_X86_64
3214 if (s
->dflag
== 2) {
3215 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3216 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3220 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3221 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3222 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3223 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3224 gen_helper_movl_mm_T0_mmx(cpu_ptr0
, cpu_tmp2_i32
);
3227 case 0x16e: /* movd xmm, ea */
3228 #ifdef TARGET_X86_64
3229 if (s
->dflag
== 2) {
3230 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 0);
3231 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3232 offsetof(CPUX86State
,xmm_regs
[reg
]));
3233 gen_helper_movq_mm_T0_xmm(cpu_ptr0
, cpu_T
[0]);
3237 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 0);
3238 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3239 offsetof(CPUX86State
,xmm_regs
[reg
]));
3240 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3241 gen_helper_movl_mm_T0_xmm(cpu_ptr0
, cpu_tmp2_i32
);
3244 case 0x6f: /* movq mm, ea */
3246 gen_lea_modrm(env
, s
, modrm
);
3247 gen_ldq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3250 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
3251 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3252 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
3253 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3256 case 0x010: /* movups */
3257 case 0x110: /* movupd */
3258 case 0x028: /* movaps */
3259 case 0x128: /* movapd */
3260 case 0x16f: /* movdqa xmm, ea */
3261 case 0x26f: /* movdqu xmm, ea */
3263 gen_lea_modrm(env
, s
, modrm
);
3264 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3266 rm
= (modrm
& 7) | REX_B(s
);
3267 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[reg
]),
3268 offsetof(CPUX86State
,xmm_regs
[rm
]));
3271 case 0x210: /* movss xmm, ea */
3273 gen_lea_modrm(env
, s
, modrm
);
3274 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3275 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3277 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3278 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3279 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3281 rm
= (modrm
& 7) | REX_B(s
);
3282 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3283 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3286 case 0x310: /* movsd xmm, ea */
3288 gen_lea_modrm(env
, s
, modrm
);
3289 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3290 xmm_regs
[reg
].XMM_Q(0)));
3292 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3293 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3295 rm
= (modrm
& 7) | REX_B(s
);
3296 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3297 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3300 case 0x012: /* movlps */
3301 case 0x112: /* movlpd */
3303 gen_lea_modrm(env
, s
, modrm
);
3304 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3305 xmm_regs
[reg
].XMM_Q(0)));
3308 rm
= (modrm
& 7) | REX_B(s
);
3309 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3310 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3313 case 0x212: /* movsldup */
3315 gen_lea_modrm(env
, s
, modrm
);
3316 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3318 rm
= (modrm
& 7) | REX_B(s
);
3319 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3320 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)));
3321 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3322 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(2)));
3324 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3325 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3326 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3327 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)));
3329 case 0x312: /* movddup */
3331 gen_lea_modrm(env
, s
, modrm
);
3332 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3333 xmm_regs
[reg
].XMM_Q(0)));
3335 rm
= (modrm
& 7) | REX_B(s
);
3336 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3337 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3339 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3340 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3342 case 0x016: /* movhps */
3343 case 0x116: /* movhpd */
3345 gen_lea_modrm(env
, s
, modrm
);
3346 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3347 xmm_regs
[reg
].XMM_Q(1)));
3350 rm
= (modrm
& 7) | REX_B(s
);
3351 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)),
3352 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3355 case 0x216: /* movshdup */
3357 gen_lea_modrm(env
, s
, modrm
);
3358 gen_ldo_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3360 rm
= (modrm
& 7) | REX_B(s
);
3361 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)),
3362 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(1)));
3363 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)),
3364 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(3)));
3366 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)),
3367 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(1)));
3368 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(2)),
3369 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(3)));
3374 int bit_index
, field_length
;
3376 if (b1
== 1 && reg
!= 0)
3378 field_length
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3379 bit_index
= cpu_ldub_code(env
, s
->pc
++) & 0x3F;
3380 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3381 offsetof(CPUX86State
,xmm_regs
[reg
]));
3383 gen_helper_extrq_i(cpu_env
, cpu_ptr0
,
3384 tcg_const_i32(bit_index
),
3385 tcg_const_i32(field_length
));
3387 gen_helper_insertq_i(cpu_env
, cpu_ptr0
,
3388 tcg_const_i32(bit_index
),
3389 tcg_const_i32(field_length
));
3392 case 0x7e: /* movd ea, mm */
3393 #ifdef TARGET_X86_64
3394 if (s
->dflag
== 2) {
3395 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3396 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3397 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3401 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3402 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_L(0)));
3403 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3406 case 0x17e: /* movd ea, xmm */
3407 #ifdef TARGET_X86_64
3408 if (s
->dflag
== 2) {
3409 tcg_gen_ld_i64(cpu_T
[0], cpu_env
,
3410 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3411 gen_ldst_modrm(env
, s
, modrm
, MO_64
, OR_TMP0
, 1);
3415 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
,
3416 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3417 gen_ldst_modrm(env
, s
, modrm
, MO_32
, OR_TMP0
, 1);
3420 case 0x27e: /* movq xmm, ea */
3422 gen_lea_modrm(env
, s
, modrm
);
3423 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
3424 xmm_regs
[reg
].XMM_Q(0)));
3426 rm
= (modrm
& 7) | REX_B(s
);
3427 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3428 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3430 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3432 case 0x7f: /* movq ea, mm */
3434 gen_lea_modrm(env
, s
, modrm
);
3435 gen_stq_env_A0(s
, offsetof(CPUX86State
, fpregs
[reg
].mmx
));
3438 gen_op_movq(offsetof(CPUX86State
,fpregs
[rm
].mmx
),
3439 offsetof(CPUX86State
,fpregs
[reg
].mmx
));
3442 case 0x011: /* movups */
3443 case 0x111: /* movupd */
3444 case 0x029: /* movaps */
3445 case 0x129: /* movapd */
3446 case 0x17f: /* movdqa ea, xmm */
3447 case 0x27f: /* movdqu ea, xmm */
3449 gen_lea_modrm(env
, s
, modrm
);
3450 gen_sto_env_A0(s
, offsetof(CPUX86State
, xmm_regs
[reg
]));
3452 rm
= (modrm
& 7) | REX_B(s
);
3453 gen_op_movo(offsetof(CPUX86State
,xmm_regs
[rm
]),
3454 offsetof(CPUX86State
,xmm_regs
[reg
]));
3457 case 0x211: /* movss ea, xmm */
3459 gen_lea_modrm(env
, s
, modrm
);
3460 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3461 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3463 rm
= (modrm
& 7) | REX_B(s
);
3464 gen_op_movl(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_L(0)),
3465 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_L(0)));
3468 case 0x311: /* movsd ea, xmm */
3470 gen_lea_modrm(env
, s
, modrm
);
3471 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3472 xmm_regs
[reg
].XMM_Q(0)));
3474 rm
= (modrm
& 7) | REX_B(s
);
3475 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3476 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3479 case 0x013: /* movlps */
3480 case 0x113: /* movlpd */
3482 gen_lea_modrm(env
, s
, modrm
);
3483 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3484 xmm_regs
[reg
].XMM_Q(0)));
3489 case 0x017: /* movhps */
3490 case 0x117: /* movhpd */
3492 gen_lea_modrm(env
, s
, modrm
);
3493 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3494 xmm_regs
[reg
].XMM_Q(1)));
3499 case 0x71: /* shift mm, im */
3502 case 0x171: /* shift xmm, im */
3508 val
= cpu_ldub_code(env
, s
->pc
++);
3510 gen_op_movl_T0_im(val
);
3511 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3513 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(1)));
3514 op1_offset
= offsetof(CPUX86State
,xmm_t0
);
3516 gen_op_movl_T0_im(val
);
3517 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(0)));
3519 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,mmx_t0
.MMX_L(1)));
3520 op1_offset
= offsetof(CPUX86State
,mmx_t0
);
3522 sse_fn_epp
= sse_op_table2
[((b
- 1) & 3) * 8 +
3523 (((modrm
>> 3)) & 7)][b1
];
3528 rm
= (modrm
& 7) | REX_B(s
);
3529 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3532 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3534 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3535 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op1_offset
);
3536 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3538 case 0x050: /* movmskps */
3539 rm
= (modrm
& 7) | REX_B(s
);
3540 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3541 offsetof(CPUX86State
,xmm_regs
[rm
]));
3542 gen_helper_movmskps(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3543 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3544 gen_op_mov_reg_T0(MO_32
, reg
);
3546 case 0x150: /* movmskpd */
3547 rm
= (modrm
& 7) | REX_B(s
);
3548 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
,
3549 offsetof(CPUX86State
,xmm_regs
[rm
]));
3550 gen_helper_movmskpd(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3551 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3552 gen_op_mov_reg_T0(MO_32
, reg
);
3554 case 0x02a: /* cvtpi2ps */
3555 case 0x12a: /* cvtpi2pd */
3556 gen_helper_enter_mmx(cpu_env
);
3558 gen_lea_modrm(env
, s
, modrm
);
3559 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3560 gen_ldq_env_A0(s
, op2_offset
);
3563 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3565 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3566 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3567 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3570 gen_helper_cvtpi2ps(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3574 gen_helper_cvtpi2pd(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3578 case 0x22a: /* cvtsi2ss */
3579 case 0x32a: /* cvtsi2sd */
3580 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
3581 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3582 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3583 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3585 SSEFunc_0_epi sse_fn_epi
= sse_op_table3ai
[(b
>> 8) & 1];
3586 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3587 sse_fn_epi(cpu_env
, cpu_ptr0
, cpu_tmp2_i32
);
3589 #ifdef TARGET_X86_64
3590 SSEFunc_0_epl sse_fn_epl
= sse_op_table3aq
[(b
>> 8) & 1];
3591 sse_fn_epl(cpu_env
, cpu_ptr0
, cpu_T
[0]);
3597 case 0x02c: /* cvttps2pi */
3598 case 0x12c: /* cvttpd2pi */
3599 case 0x02d: /* cvtps2pi */
3600 case 0x12d: /* cvtpd2pi */
3601 gen_helper_enter_mmx(cpu_env
);
3603 gen_lea_modrm(env
, s
, modrm
);
3604 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3605 gen_ldo_env_A0(s
, op2_offset
);
3607 rm
= (modrm
& 7) | REX_B(s
);
3608 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3610 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
);
3611 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3612 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3615 gen_helper_cvttps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3618 gen_helper_cvttpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3621 gen_helper_cvtps2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3624 gen_helper_cvtpd2pi(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3628 case 0x22c: /* cvttss2si */
3629 case 0x32c: /* cvttsd2si */
3630 case 0x22d: /* cvtss2si */
3631 case 0x32d: /* cvtsd2si */
3632 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
3634 gen_lea_modrm(env
, s
, modrm
);
3636 gen_ldq_env_A0(s
, offsetof(CPUX86State
, xmm_t0
.XMM_Q(0)));
3638 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
3639 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
3641 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3643 rm
= (modrm
& 7) | REX_B(s
);
3644 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
3646 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op2_offset
);
3648 SSEFunc_i_ep sse_fn_i_ep
=
3649 sse_op_table3bi
[((b
>> 7) & 2) | (b
& 1)];
3650 sse_fn_i_ep(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3651 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3653 #ifdef TARGET_X86_64
3654 SSEFunc_l_ep sse_fn_l_ep
=
3655 sse_op_table3bq
[((b
>> 7) & 2) | (b
& 1)];
3656 sse_fn_l_ep(cpu_T
[0], cpu_env
, cpu_ptr0
);
3661 gen_op_mov_reg_T0(ot
, reg
);
3663 case 0xc4: /* pinsrw */
3666 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
3667 val
= cpu_ldub_code(env
, s
->pc
++);
3670 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3671 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_W(val
)));
3674 tcg_gen_st16_tl(cpu_T
[0], cpu_env
,
3675 offsetof(CPUX86State
,fpregs
[reg
].mmx
.MMX_W(val
)));
3678 case 0xc5: /* pextrw */
3682 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
3683 val
= cpu_ldub_code(env
, s
->pc
++);
3686 rm
= (modrm
& 7) | REX_B(s
);
3687 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3688 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_W(val
)));
3692 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
,
3693 offsetof(CPUX86State
,fpregs
[rm
].mmx
.MMX_W(val
)));
3695 reg
= ((modrm
>> 3) & 7) | rex_r
;
3696 gen_op_mov_reg_T0(ot
, reg
);
3698 case 0x1d6: /* movq ea, xmm */
3700 gen_lea_modrm(env
, s
, modrm
);
3701 gen_stq_env_A0(s
, offsetof(CPUX86State
,
3702 xmm_regs
[reg
].XMM_Q(0)));
3704 rm
= (modrm
& 7) | REX_B(s
);
3705 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)),
3706 offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)));
3707 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(1)));
3710 case 0x2d6: /* movq2dq */
3711 gen_helper_enter_mmx(cpu_env
);
3713 gen_op_movq(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(0)),
3714 offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3715 gen_op_movq_env_0(offsetof(CPUX86State
,xmm_regs
[reg
].XMM_Q(1)));
3717 case 0x3d6: /* movdq2q */
3718 gen_helper_enter_mmx(cpu_env
);
3719 rm
= (modrm
& 7) | REX_B(s
);
3720 gen_op_movq(offsetof(CPUX86State
,fpregs
[reg
& 7].mmx
),
3721 offsetof(CPUX86State
,xmm_regs
[rm
].XMM_Q(0)));
3723 case 0xd7: /* pmovmskb */
3728 rm
= (modrm
& 7) | REX_B(s
);
3729 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,xmm_regs
[rm
]));
3730 gen_helper_pmovmskb_xmm(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3733 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, offsetof(CPUX86State
,fpregs
[rm
].mmx
));
3734 gen_helper_pmovmskb_mmx(cpu_tmp2_i32
, cpu_env
, cpu_ptr0
);
3736 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
3737 reg
= ((modrm
>> 3) & 7) | rex_r
;
3738 gen_op_mov_reg_T0(MO_32
, reg
);
3744 if ((b
& 0xf0) == 0xf0) {
3747 modrm
= cpu_ldub_code(env
, s
->pc
++);
3749 reg
= ((modrm
>> 3) & 7) | rex_r
;
3750 mod
= (modrm
>> 6) & 3;
3755 sse_fn_epp
= sse_op_table6
[b
].op
[b1
];
3759 if (!(s
->cpuid_ext_features
& sse_op_table6
[b
].ext_mask
))
3763 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
3765 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
3767 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
3768 gen_lea_modrm(env
, s
, modrm
);
3770 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3771 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3772 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3773 gen_ldq_env_A0(s
, op2_offset
+
3774 offsetof(XMMReg
, XMM_Q(0)));
3776 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3777 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3778 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
3779 s
->mem_index
, MO_LEUL
);
3780 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, op2_offset
+
3781 offsetof(XMMReg
, XMM_L(0)));
3783 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3784 tcg_gen_qemu_ld_tl(cpu_tmp0
, cpu_A0
,
3785 s
->mem_index
, MO_LEUW
);
3786 tcg_gen_st16_tl(cpu_tmp0
, cpu_env
, op2_offset
+
3787 offsetof(XMMReg
, XMM_W(0)));
3789 case 0x2a: /* movntqda */
3790 gen_ldo_env_A0(s
, op1_offset
);
3793 gen_ldo_env_A0(s
, op2_offset
);
3797 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
3799 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
3801 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
3802 gen_lea_modrm(env
, s
, modrm
);
3803 gen_ldq_env_A0(s
, op2_offset
);
3806 if (sse_fn_epp
== SSE_SPECIAL
) {
3810 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
3811 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
3812 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
3815 set_cc_op(s
, CC_OP_EFLAGS
);
3822 /* Various integer extensions at 0f 38 f[0-f]. */
3823 b
= modrm
| (b1
<< 8);
3824 modrm
= cpu_ldub_code(env
, s
->pc
++);
3825 reg
= ((modrm
>> 3) & 7) | rex_r
;
3828 case 0x3f0: /* crc32 Gd,Eb */
3829 case 0x3f1: /* crc32 Gd,Ey */
3831 if (!(s
->cpuid_ext_features
& CPUID_EXT_SSE42
)) {
3834 if ((b
& 0xff) == 0xf0) {
3836 } else if (s
->dflag
!= 2) {
3837 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3842 gen_op_mov_TN_reg(MO_32
, 0, reg
);
3843 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3844 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3845 gen_helper_crc32(cpu_T
[0], cpu_tmp2_i32
,
3846 cpu_T
[0], tcg_const_i32(8 << ot
));
3848 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
3849 gen_op_mov_reg_T0(ot
, reg
);
3852 case 0x1f0: /* crc32 or movbe */
3854 /* For these insns, the f3 prefix is supposed to have priority
3855 over the 66 prefix, but that's not what we implement above
3857 if (s
->prefix
& PREFIX_REPNZ
) {
3861 case 0x0f0: /* movbe Gy,My */
3862 case 0x0f1: /* movbe My,Gy */
3863 if (!(s
->cpuid_ext_features
& CPUID_EXT_MOVBE
)) {
3866 if (s
->dflag
!= 2) {
3867 ot
= (s
->prefix
& PREFIX_DATA
? MO_16
: MO_32
);
3872 gen_lea_modrm(env
, s
, modrm
);
3874 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
3875 s
->mem_index
, ot
| MO_BE
);
3876 gen_op_mov_reg_T0(ot
, reg
);
3878 tcg_gen_qemu_st_tl(cpu_regs
[reg
], cpu_A0
,
3879 s
->mem_index
, ot
| MO_BE
);
3883 case 0x0f2: /* andn Gy, By, Ey */
3884 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3885 || !(s
->prefix
& PREFIX_VEX
)
3889 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3890 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3891 tcg_gen_andc_tl(cpu_T
[0], cpu_regs
[s
->vex_v
], cpu_T
[0]);
3892 gen_op_mov_reg_T0(ot
, reg
);
3893 gen_op_update1_cc();
3894 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3897 case 0x0f7: /* bextr Gy, Ey, By */
3898 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
3899 || !(s
->prefix
& PREFIX_VEX
)
3903 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3907 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3908 /* Extract START, and shift the operand.
3909 Shifts larger than operand size get zeros. */
3910 tcg_gen_ext8u_tl(cpu_A0
, cpu_regs
[s
->vex_v
]);
3911 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3913 bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3914 zero
= tcg_const_tl(0);
3915 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_T
[0], cpu_A0
, bound
,
3917 tcg_temp_free(zero
);
3919 /* Extract the LEN into a mask. Lengths larger than
3920 operand size get all ones. */
3921 tcg_gen_shri_tl(cpu_A0
, cpu_regs
[s
->vex_v
], 8);
3922 tcg_gen_ext8u_tl(cpu_A0
, cpu_A0
);
3923 tcg_gen_movcond_tl(TCG_COND_LEU
, cpu_A0
, cpu_A0
, bound
,
3925 tcg_temp_free(bound
);
3926 tcg_gen_movi_tl(cpu_T
[1], 1);
3927 tcg_gen_shl_tl(cpu_T
[1], cpu_T
[1], cpu_A0
);
3928 tcg_gen_subi_tl(cpu_T
[1], cpu_T
[1], 1);
3929 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
3931 gen_op_mov_reg_T0(ot
, reg
);
3932 gen_op_update1_cc();
3933 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
3937 case 0x0f5: /* bzhi Gy, Ey, By */
3938 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3939 || !(s
->prefix
& PREFIX_VEX
)
3943 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3944 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3945 tcg_gen_ext8u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
3947 TCGv bound
= tcg_const_tl(ot
== MO_64
? 63 : 31);
3948 /* Note that since we're using BMILG (in order to get O
3949 cleared) we need to store the inverse into C. */
3950 tcg_gen_setcond_tl(TCG_COND_LT
, cpu_cc_src
,
3952 tcg_gen_movcond_tl(TCG_COND_GT
, cpu_T
[1], cpu_T
[1],
3953 bound
, bound
, cpu_T
[1]);
3954 tcg_temp_free(bound
);
3956 tcg_gen_movi_tl(cpu_A0
, -1);
3957 tcg_gen_shl_tl(cpu_A0
, cpu_A0
, cpu_T
[1]);
3958 tcg_gen_andc_tl(cpu_T
[0], cpu_T
[0], cpu_A0
);
3959 gen_op_mov_reg_T0(ot
, reg
);
3960 gen_op_update1_cc();
3961 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
3964 case 0x3f6: /* mulx By, Gy, rdx, Ey */
3965 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3966 || !(s
->prefix
& PREFIX_VEX
)
3970 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3971 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3974 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
3975 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EDX
]);
3976 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
3977 cpu_tmp2_i32
, cpu_tmp3_i32
);
3978 tcg_gen_extu_i32_tl(cpu_regs
[s
->vex_v
], cpu_tmp2_i32
);
3979 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp3_i32
);
3981 #ifdef TARGET_X86_64
3983 tcg_gen_mulu2_i64(cpu_regs
[s
->vex_v
], cpu_regs
[reg
],
3984 cpu_T
[0], cpu_regs
[R_EDX
]);
3990 case 0x3f5: /* pdep Gy, By, Ey */
3991 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
3992 || !(s
->prefix
& PREFIX_VEX
)
3996 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
3997 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
3998 /* Note that by zero-extending the mask operand, we
3999 automatically handle zero-extending the result. */
4000 if (s
->dflag
== 2) {
4001 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
4003 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
4005 gen_helper_pdep(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
4008 case 0x2f5: /* pext Gy, By, Ey */
4009 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4010 || !(s
->prefix
& PREFIX_VEX
)
4014 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
4015 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4016 /* Note that by zero-extending the mask operand, we
4017 automatically handle zero-extending the result. */
4018 if (s
->dflag
== 2) {
4019 tcg_gen_mov_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
4021 tcg_gen_ext32u_tl(cpu_T
[1], cpu_regs
[s
->vex_v
]);
4023 gen_helper_pext(cpu_regs
[reg
], cpu_T
[0], cpu_T
[1]);
4026 case 0x1f6: /* adcx Gy, Ey */
4027 case 0x2f6: /* adox Gy, Ey */
4028 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_ADX
)) {
4031 TCGv carry_in
, carry_out
, zero
;
4034 ot
= (s
->dflag
== 2 ? MO_64
: MO_32
);
4035 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4037 /* Re-use the carry-out from a previous round. */
4038 TCGV_UNUSED(carry_in
);
4039 carry_out
= (b
== 0x1f6 ? cpu_cc_dst
: cpu_cc_src2
);
4043 carry_in
= cpu_cc_dst
;
4044 end_op
= CC_OP_ADCX
;
4046 end_op
= CC_OP_ADCOX
;
4051 end_op
= CC_OP_ADCOX
;
4053 carry_in
= cpu_cc_src2
;
4054 end_op
= CC_OP_ADOX
;
4058 end_op
= CC_OP_ADCOX
;
4059 carry_in
= carry_out
;
4062 end_op
= (b
== 0x1f6 ? CC_OP_ADCX
: CC_OP_ADOX
);
4065 /* If we can't reuse carry-out, get it out of EFLAGS. */
4066 if (TCGV_IS_UNUSED(carry_in
)) {
4067 if (s
->cc_op
!= CC_OP_ADCX
&& s
->cc_op
!= CC_OP_ADOX
) {
4068 gen_compute_eflags(s
);
4070 carry_in
= cpu_tmp0
;
4071 tcg_gen_shri_tl(carry_in
, cpu_cc_src
,
4072 ctz32(b
== 0x1f6 ? CC_C
: CC_O
));
4073 tcg_gen_andi_tl(carry_in
, carry_in
, 1);
4077 #ifdef TARGET_X86_64
4079 /* If we know TL is 64-bit, and we want a 32-bit
4080 result, just do everything in 64-bit arithmetic. */
4081 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_regs
[reg
]);
4082 tcg_gen_ext32u_i64(cpu_T
[0], cpu_T
[0]);
4083 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], cpu_regs
[reg
]);
4084 tcg_gen_add_i64(cpu_T
[0], cpu_T
[0], carry_in
);
4085 tcg_gen_ext32u_i64(cpu_regs
[reg
], cpu_T
[0]);
4086 tcg_gen_shri_i64(carry_out
, cpu_T
[0], 32);
4090 /* Otherwise compute the carry-out in two steps. */
4091 zero
= tcg_const_tl(0);
4092 tcg_gen_add2_tl(cpu_T
[0], carry_out
,
4095 tcg_gen_add2_tl(cpu_regs
[reg
], carry_out
,
4096 cpu_regs
[reg
], carry_out
,
4098 tcg_temp_free(zero
);
4101 set_cc_op(s
, end_op
);
4105 case 0x1f7: /* shlx Gy, Ey, By */
4106 case 0x2f7: /* sarx Gy, Ey, By */
4107 case 0x3f7: /* shrx Gy, Ey, By */
4108 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4109 || !(s
->prefix
& PREFIX_VEX
)
4113 ot
= (s
->dflag
== 2 ? MO_64
: MO_32
);
4114 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4116 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 63);
4118 tcg_gen_andi_tl(cpu_T
[1], cpu_regs
[s
->vex_v
], 31);
4121 tcg_gen_shl_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4122 } else if (b
== 0x2f7) {
4124 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
4126 tcg_gen_sar_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4129 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
4131 tcg_gen_shr_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4133 gen_op_mov_reg_T0(ot
, reg
);
4139 case 0x3f3: /* Group 17 */
4140 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)
4141 || !(s
->prefix
& PREFIX_VEX
)
4145 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
4146 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4149 case 1: /* blsr By,Ey */
4150 tcg_gen_neg_tl(cpu_T
[1], cpu_T
[0]);
4151 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4152 gen_op_mov_reg_T0(ot
, s
->vex_v
);
4153 gen_op_update2_cc();
4154 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4157 case 2: /* blsmsk By,Ey */
4158 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4159 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4160 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4161 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4162 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4165 case 3: /* blsi By, Ey */
4166 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4167 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], 1);
4168 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_cc_src
);
4169 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4170 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
4186 modrm
= cpu_ldub_code(env
, s
->pc
++);
4188 reg
= ((modrm
>> 3) & 7) | rex_r
;
4189 mod
= (modrm
>> 6) & 3;
4194 sse_fn_eppi
= sse_op_table7
[b
].op
[b1
];
4198 if (!(s
->cpuid_ext_features
& sse_op_table7
[b
].ext_mask
))
4201 if (sse_fn_eppi
== SSE_SPECIAL
) {
4202 ot
= (s
->dflag
== 2) ? MO_64
: MO_32
;
4203 rm
= (modrm
& 7) | REX_B(s
);
4205 gen_lea_modrm(env
, s
, modrm
);
4206 reg
= ((modrm
>> 3) & 7) | rex_r
;
4207 val
= cpu_ldub_code(env
, s
->pc
++);
4209 case 0x14: /* pextrb */
4210 tcg_gen_ld8u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4211 xmm_regs
[reg
].XMM_B(val
& 15)));
4213 gen_op_mov_reg_T0(ot
, rm
);
4215 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4216 s
->mem_index
, MO_UB
);
4219 case 0x15: /* pextrw */
4220 tcg_gen_ld16u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4221 xmm_regs
[reg
].XMM_W(val
& 7)));
4223 gen_op_mov_reg_T0(ot
, rm
);
4225 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4226 s
->mem_index
, MO_LEUW
);
4230 if (ot
== MO_32
) { /* pextrd */
4231 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4232 offsetof(CPUX86State
,
4233 xmm_regs
[reg
].XMM_L(val
& 3)));
4234 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4236 gen_op_mov_reg_v(ot
, rm
, cpu_T
[0]);
4238 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4239 s
->mem_index
, MO_LEUL
);
4241 } else { /* pextrq */
4242 #ifdef TARGET_X86_64
4243 tcg_gen_ld_i64(cpu_tmp1_i64
, cpu_env
,
4244 offsetof(CPUX86State
,
4245 xmm_regs
[reg
].XMM_Q(val
& 1)));
4247 gen_op_mov_reg_v(ot
, rm
, cpu_tmp1_i64
);
4249 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
4250 s
->mem_index
, MO_LEQ
);
4257 case 0x17: /* extractps */
4258 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4259 xmm_regs
[reg
].XMM_L(val
& 3)));
4261 gen_op_mov_reg_T0(ot
, rm
);
4263 tcg_gen_qemu_st_tl(cpu_T
[0], cpu_A0
,
4264 s
->mem_index
, MO_LEUL
);
4267 case 0x20: /* pinsrb */
4269 gen_op_mov_TN_reg(MO_32
, 0, rm
);
4271 tcg_gen_qemu_ld_tl(cpu_T
[0], cpu_A0
,
4272 s
->mem_index
, MO_UB
);
4274 tcg_gen_st8_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,
4275 xmm_regs
[reg
].XMM_B(val
& 15)));
4277 case 0x21: /* insertps */
4279 tcg_gen_ld_i32(cpu_tmp2_i32
, cpu_env
,
4280 offsetof(CPUX86State
,xmm_regs
[rm
]
4281 .XMM_L((val
>> 6) & 3)));
4283 tcg_gen_qemu_ld_i32(cpu_tmp2_i32
, cpu_A0
,
4284 s
->mem_index
, MO_LEUL
);
4286 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4287 offsetof(CPUX86State
,xmm_regs
[reg
]
4288 .XMM_L((val
>> 4) & 3)));
4290 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4291 cpu_env
, offsetof(CPUX86State
,
4292 xmm_regs
[reg
].XMM_L(0)));
4294 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4295 cpu_env
, offsetof(CPUX86State
,
4296 xmm_regs
[reg
].XMM_L(1)));
4298 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4299 cpu_env
, offsetof(CPUX86State
,
4300 xmm_regs
[reg
].XMM_L(2)));
4302 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4303 cpu_env
, offsetof(CPUX86State
,
4304 xmm_regs
[reg
].XMM_L(3)));
4307 if (ot
== MO_32
) { /* pinsrd */
4309 gen_op_mov_v_reg(ot
, cpu_tmp0
, rm
);
4311 tcg_gen_qemu_ld_tl(cpu_tmp0
, cpu_A0
,
4312 s
->mem_index
, MO_LEUL
);
4314 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_tmp0
);
4315 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
,
4316 offsetof(CPUX86State
,
4317 xmm_regs
[reg
].XMM_L(val
& 3)));
4318 } else { /* pinsrq */
4319 #ifdef TARGET_X86_64
4321 gen_op_mov_v_reg(ot
, cpu_tmp1_i64
, rm
);
4323 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
4324 s
->mem_index
, MO_LEQ
);
4326 tcg_gen_st_i64(cpu_tmp1_i64
, cpu_env
,
4327 offsetof(CPUX86State
,
4328 xmm_regs
[reg
].XMM_Q(val
& 1)));
4339 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4341 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
| REX_B(s
)]);
4343 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4344 gen_lea_modrm(env
, s
, modrm
);
4345 gen_ldo_env_A0(s
, op2_offset
);
4348 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4350 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4352 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4353 gen_lea_modrm(env
, s
, modrm
);
4354 gen_ldq_env_A0(s
, op2_offset
);
4357 val
= cpu_ldub_code(env
, s
->pc
++);
4359 if ((b
& 0xfc) == 0x60) { /* pcmpXstrX */
4360 set_cc_op(s
, CC_OP_EFLAGS
);
4363 /* The helper must use entire 64-bit gp registers */
4367 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4368 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4369 sse_fn_eppi(cpu_env
, cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4373 /* Various integer extensions at 0f 3a f[0-f]. */
4374 b
= modrm
| (b1
<< 8);
4375 modrm
= cpu_ldub_code(env
, s
->pc
++);
4376 reg
= ((modrm
>> 3) & 7) | rex_r
;
4379 case 0x3f0: /* rorx Gy,Ey, Ib */
4380 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI2
)
4381 || !(s
->prefix
& PREFIX_VEX
)
4385 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
4386 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
4387 b
= cpu_ldub_code(env
, s
->pc
++);
4389 tcg_gen_rotri_tl(cpu_T
[0], cpu_T
[0], b
& 63);
4391 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4392 tcg_gen_rotri_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, b
& 31);
4393 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
4395 gen_op_mov_reg_T0(ot
, reg
);
4407 /* generic MMX or SSE operation */
4409 case 0x70: /* pshufx insn */
4410 case 0xc6: /* pshufx insn */
4411 case 0xc2: /* compare insns */
4418 op1_offset
= offsetof(CPUX86State
,xmm_regs
[reg
]);
4420 gen_lea_modrm(env
, s
, modrm
);
4421 op2_offset
= offsetof(CPUX86State
,xmm_t0
);
4422 if (b1
>= 2 && ((b
>= 0x50 && b
<= 0x5f && b
!= 0x5b) ||
4424 /* specific case for SSE single instructions */
4427 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
4428 tcg_gen_st32_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,xmm_t0
.XMM_L(0)));
4431 gen_ldq_env_A0(s
, offsetof(CPUX86State
,
4435 gen_ldo_env_A0(s
, op2_offset
);
4438 rm
= (modrm
& 7) | REX_B(s
);
4439 op2_offset
= offsetof(CPUX86State
,xmm_regs
[rm
]);
4442 op1_offset
= offsetof(CPUX86State
,fpregs
[reg
].mmx
);
4444 gen_lea_modrm(env
, s
, modrm
);
4445 op2_offset
= offsetof(CPUX86State
,mmx_t0
);
4446 gen_ldq_env_A0(s
, op2_offset
);
4449 op2_offset
= offsetof(CPUX86State
,fpregs
[rm
].mmx
);
4453 case 0x0f: /* 3DNow! data insns */
4454 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_3DNOW
))
4456 val
= cpu_ldub_code(env
, s
->pc
++);
4457 sse_fn_epp
= sse_op_table5
[val
];
4461 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4462 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4463 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4465 case 0x70: /* pshufx insn */
4466 case 0xc6: /* pshufx insn */
4467 val
= cpu_ldub_code(env
, s
->pc
++);
4468 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4469 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4470 /* XXX: introduce a new table? */
4471 sse_fn_ppi
= (SSEFunc_0_ppi
)sse_fn_epp
;
4472 sse_fn_ppi(cpu_ptr0
, cpu_ptr1
, tcg_const_i32(val
));
4476 val
= cpu_ldub_code(env
, s
->pc
++);
4479 sse_fn_epp
= sse_op_table4
[val
][b1
];
4481 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4482 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4483 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4486 /* maskmov : we must prepare A0 */
4489 #ifdef TARGET_X86_64
4490 if (s
->aflag
== 2) {
4491 gen_op_movq_A0_reg(R_EDI
);
4495 gen_op_movl_A0_reg(R_EDI
);
4497 gen_op_andl_A0_ffff();
4499 gen_add_A0_ds_seg(s
);
4501 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4502 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4503 /* XXX: introduce a new table? */
4504 sse_fn_eppt
= (SSEFunc_0_eppt
)sse_fn_epp
;
4505 sse_fn_eppt(cpu_env
, cpu_ptr0
, cpu_ptr1
, cpu_A0
);
4508 tcg_gen_addi_ptr(cpu_ptr0
, cpu_env
, op1_offset
);
4509 tcg_gen_addi_ptr(cpu_ptr1
, cpu_env
, op2_offset
);
4510 sse_fn_epp(cpu_env
, cpu_ptr0
, cpu_ptr1
);
4513 if (b
== 0x2e || b
== 0x2f) {
4514 set_cc_op(s
, CC_OP_EFLAGS
);
4519 /* convert one instruction. s->is_jmp is set if the translation must
4520 be stopped. Return the next pc value */
4521 static target_ulong
disas_insn(CPUX86State
*env
, DisasContext
*s
,
4522 target_ulong pc_start
)
4524 int b
, prefixes
, aflag
, dflag
;
4526 int modrm
, reg
, rm
, mod
, op
, opreg
, val
;
4527 target_ulong next_eip
, tval
;
4530 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
4531 tcg_gen_debug_insn_start(pc_start
);
4538 #ifdef TARGET_X86_64
4543 s
->rip_offset
= 0; /* for relative ip address */
4547 b
= cpu_ldub_code(env
, s
->pc
);
4549 /* Collect prefixes. */
4552 prefixes
|= PREFIX_REPZ
;
4555 prefixes
|= PREFIX_REPNZ
;
4558 prefixes
|= PREFIX_LOCK
;
4579 prefixes
|= PREFIX_DATA
;
4582 prefixes
|= PREFIX_ADR
;
4584 #ifdef TARGET_X86_64
4588 rex_w
= (b
>> 3) & 1;
4589 rex_r
= (b
& 0x4) << 1;
4590 s
->rex_x
= (b
& 0x2) << 2;
4591 REX_B(s
) = (b
& 0x1) << 3;
4592 x86_64_hregs
= 1; /* select uniform byte register addressing */
4597 case 0xc5: /* 2-byte VEX */
4598 case 0xc4: /* 3-byte VEX */
4599 /* VEX prefixes cannot be used except in 32-bit mode.
4600 Otherwise the instruction is LES or LDS. */
4601 if (s
->code32
&& !s
->vm86
) {
4602 static const int pp_prefix
[4] = {
4603 0, PREFIX_DATA
, PREFIX_REPZ
, PREFIX_REPNZ
4605 int vex3
, vex2
= cpu_ldub_code(env
, s
->pc
);
4607 if (!CODE64(s
) && (vex2
& 0xc0) != 0xc0) {
4608 /* 4.1.4.6: In 32-bit mode, bits [7:6] must be 11b,
4609 otherwise the instruction is LES or LDS. */
4614 /* 4.1.1-4.1.3: No preceding lock, 66, f2, f3, or rex prefixes. */
4615 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
4616 | PREFIX_LOCK
| PREFIX_DATA
)) {
4619 #ifdef TARGET_X86_64
4624 rex_r
= (~vex2
>> 4) & 8;
4627 b
= cpu_ldub_code(env
, s
->pc
++);
4629 #ifdef TARGET_X86_64
4630 s
->rex_x
= (~vex2
>> 3) & 8;
4631 s
->rex_b
= (~vex2
>> 2) & 8;
4633 vex3
= cpu_ldub_code(env
, s
->pc
++);
4634 rex_w
= (vex3
>> 7) & 1;
4635 switch (vex2
& 0x1f) {
4636 case 0x01: /* Implied 0f leading opcode bytes. */
4637 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4639 case 0x02: /* Implied 0f 38 leading opcode bytes. */
4642 case 0x03: /* Implied 0f 3a leading opcode bytes. */
4645 default: /* Reserved for future use. */
4649 s
->vex_v
= (~vex3
>> 3) & 0xf;
4650 s
->vex_l
= (vex3
>> 2) & 1;
4651 prefixes
|= pp_prefix
[vex3
& 3] | PREFIX_VEX
;
4656 /* Post-process prefixes. */
4658 /* In 64-bit mode, the default data size is 32-bit. Select 64-bit
4659 data with rex_w, and 16-bit data with 0x66; rex_w takes precedence
4660 over 0x66 if both are present. */
4661 dflag
= (rex_w
> 0 ? 2 : prefixes
& PREFIX_DATA
? 0 : 1);
4662 /* In 64-bit mode, 0x67 selects 32-bit addressing. */
4663 aflag
= (prefixes
& PREFIX_ADR
? 1 : 2);
4665 /* In 16/32-bit mode, 0x66 selects the opposite data size. */
4667 if (prefixes
& PREFIX_DATA
) {
4670 /* In 16/32-bit mode, 0x67 selects the opposite addressing. */
4672 if (prefixes
& PREFIX_ADR
) {
4677 s
->prefix
= prefixes
;
4681 /* lock generation */
4682 if (prefixes
& PREFIX_LOCK
)
4685 /* now check op code */
4689 /**************************/
4690 /* extended op code */
4691 b
= cpu_ldub_code(env
, s
->pc
++) | 0x100;
4694 /**************************/
4715 case 0: /* OP Ev, Gv */
4716 modrm
= cpu_ldub_code(env
, s
->pc
++);
4717 reg
= ((modrm
>> 3) & 7) | rex_r
;
4718 mod
= (modrm
>> 6) & 3;
4719 rm
= (modrm
& 7) | REX_B(s
);
4721 gen_lea_modrm(env
, s
, modrm
);
4723 } else if (op
== OP_XORL
&& rm
== reg
) {
4725 /* xor reg, reg optimisation */
4726 set_cc_op(s
, CC_OP_CLR
);
4728 gen_op_mov_reg_T0(ot
, reg
);
4733 gen_op_mov_TN_reg(ot
, 1, reg
);
4734 gen_op(s
, op
, ot
, opreg
);
4736 case 1: /* OP Gv, Ev */
4737 modrm
= cpu_ldub_code(env
, s
->pc
++);
4738 mod
= (modrm
>> 6) & 3;
4739 reg
= ((modrm
>> 3) & 7) | rex_r
;
4740 rm
= (modrm
& 7) | REX_B(s
);
4742 gen_lea_modrm(env
, s
, modrm
);
4743 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
4744 } else if (op
== OP_XORL
&& rm
== reg
) {
4747 gen_op_mov_TN_reg(ot
, 1, rm
);
4749 gen_op(s
, op
, ot
, reg
);
4751 case 2: /* OP A, Iv */
4752 val
= insn_get(env
, s
, ot
);
4753 gen_op_movl_T1_im(val
);
4754 gen_op(s
, op
, ot
, OR_EAX
);
4763 case 0x80: /* GRP1 */
4774 modrm
= cpu_ldub_code(env
, s
->pc
++);
4775 mod
= (modrm
>> 6) & 3;
4776 rm
= (modrm
& 7) | REX_B(s
);
4777 op
= (modrm
>> 3) & 7;
4783 s
->rip_offset
= insn_const_size(ot
);
4784 gen_lea_modrm(env
, s
, modrm
);
4795 val
= insn_get(env
, s
, ot
);
4798 val
= (int8_t)insn_get(env
, s
, MO_8
);
4801 gen_op_movl_T1_im(val
);
4802 gen_op(s
, op
, ot
, opreg
);
4806 /**************************/
4807 /* inc, dec, and other misc arith */
4808 case 0x40 ... 0x47: /* inc Gv */
4809 ot
= dflag
? MO_32
: MO_16
;
4810 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), 1);
4812 case 0x48 ... 0x4f: /* dec Gv */
4813 ot
= dflag
? MO_32
: MO_16
;
4814 gen_inc(s
, ot
, OR_EAX
+ (b
& 7), -1);
4816 case 0xf6: /* GRP3 */
4823 modrm
= cpu_ldub_code(env
, s
->pc
++);
4824 mod
= (modrm
>> 6) & 3;
4825 rm
= (modrm
& 7) | REX_B(s
);
4826 op
= (modrm
>> 3) & 7;
4829 s
->rip_offset
= insn_const_size(ot
);
4830 gen_lea_modrm(env
, s
, modrm
);
4831 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
4833 gen_op_mov_TN_reg(ot
, 0, rm
);
4838 val
= insn_get(env
, s
, ot
);
4839 gen_op_movl_T1_im(val
);
4840 gen_op_testl_T0_T1_cc();
4841 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
4844 tcg_gen_not_tl(cpu_T
[0], cpu_T
[0]);
4846 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4848 gen_op_mov_reg_T0(ot
, rm
);
4852 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
4854 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
4856 gen_op_mov_reg_T0(ot
, rm
);
4858 gen_op_update_neg_cc();
4859 set_cc_op(s
, CC_OP_SUBB
+ ot
);
4864 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4865 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
4866 tcg_gen_ext8u_tl(cpu_T
[1], cpu_T
[1]);
4867 /* XXX: use 32 bit mul which could be faster */
4868 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4869 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4870 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4871 tcg_gen_andi_tl(cpu_cc_src
, cpu_T
[0], 0xff00);
4872 set_cc_op(s
, CC_OP_MULB
);
4875 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4876 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
4877 tcg_gen_ext16u_tl(cpu_T
[1], cpu_T
[1]);
4878 /* XXX: use 32 bit mul which could be faster */
4879 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4880 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4881 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4882 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4883 gen_op_mov_reg_T0(MO_16
, R_EDX
);
4884 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
4885 set_cc_op(s
, CC_OP_MULW
);
4889 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4890 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4891 tcg_gen_mulu2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4892 cpu_tmp2_i32
, cpu_tmp3_i32
);
4893 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4894 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4895 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4896 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4897 set_cc_op(s
, CC_OP_MULL
);
4899 #ifdef TARGET_X86_64
4901 tcg_gen_mulu2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4902 cpu_T
[0], cpu_regs
[R_EAX
]);
4903 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4904 tcg_gen_mov_tl(cpu_cc_src
, cpu_regs
[R_EDX
]);
4905 set_cc_op(s
, CC_OP_MULQ
);
4913 gen_op_mov_TN_reg(MO_8
, 1, R_EAX
);
4914 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
4915 tcg_gen_ext8s_tl(cpu_T
[1], cpu_T
[1]);
4916 /* XXX: use 32 bit mul which could be faster */
4917 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4918 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4919 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4920 tcg_gen_ext8s_tl(cpu_tmp0
, cpu_T
[0]);
4921 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4922 set_cc_op(s
, CC_OP_MULB
);
4925 gen_op_mov_TN_reg(MO_16
, 1, R_EAX
);
4926 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
4927 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
4928 /* XXX: use 32 bit mul which could be faster */
4929 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
4930 gen_op_mov_reg_T0(MO_16
, R_EAX
);
4931 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
4932 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
4933 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
4934 tcg_gen_shri_tl(cpu_T
[0], cpu_T
[0], 16);
4935 gen_op_mov_reg_T0(MO_16
, R_EDX
);
4936 set_cc_op(s
, CC_OP_MULW
);
4940 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
4941 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_regs
[R_EAX
]);
4942 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
4943 cpu_tmp2_i32
, cpu_tmp3_i32
);
4944 tcg_gen_extu_i32_tl(cpu_regs
[R_EAX
], cpu_tmp2_i32
);
4945 tcg_gen_extu_i32_tl(cpu_regs
[R_EDX
], cpu_tmp3_i32
);
4946 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
4947 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4948 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
4949 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
4950 set_cc_op(s
, CC_OP_MULL
);
4952 #ifdef TARGET_X86_64
4954 tcg_gen_muls2_i64(cpu_regs
[R_EAX
], cpu_regs
[R_EDX
],
4955 cpu_T
[0], cpu_regs
[R_EAX
]);
4956 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[R_EAX
]);
4957 tcg_gen_sari_tl(cpu_cc_src
, cpu_regs
[R_EAX
], 63);
4958 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_regs
[R_EDX
]);
4959 set_cc_op(s
, CC_OP_MULQ
);
4967 gen_jmp_im(pc_start
- s
->cs_base
);
4968 gen_helper_divb_AL(cpu_env
, cpu_T
[0]);
4971 gen_jmp_im(pc_start
- s
->cs_base
);
4972 gen_helper_divw_AX(cpu_env
, cpu_T
[0]);
4976 gen_jmp_im(pc_start
- s
->cs_base
);
4977 gen_helper_divl_EAX(cpu_env
, cpu_T
[0]);
4979 #ifdef TARGET_X86_64
4981 gen_jmp_im(pc_start
- s
->cs_base
);
4982 gen_helper_divq_EAX(cpu_env
, cpu_T
[0]);
4990 gen_jmp_im(pc_start
- s
->cs_base
);
4991 gen_helper_idivb_AL(cpu_env
, cpu_T
[0]);
4994 gen_jmp_im(pc_start
- s
->cs_base
);
4995 gen_helper_idivw_AX(cpu_env
, cpu_T
[0]);
4999 gen_jmp_im(pc_start
- s
->cs_base
);
5000 gen_helper_idivl_EAX(cpu_env
, cpu_T
[0]);
5002 #ifdef TARGET_X86_64
5004 gen_jmp_im(pc_start
- s
->cs_base
);
5005 gen_helper_idivq_EAX(cpu_env
, cpu_T
[0]);
5015 case 0xfe: /* GRP4 */
5016 case 0xff: /* GRP5 */
5022 modrm
= cpu_ldub_code(env
, s
->pc
++);
5023 mod
= (modrm
>> 6) & 3;
5024 rm
= (modrm
& 7) | REX_B(s
);
5025 op
= (modrm
>> 3) & 7;
5026 if (op
>= 2 && b
== 0xfe) {
5030 if (op
== 2 || op
== 4) {
5031 /* operand size for jumps is 64 bit */
5033 } else if (op
== 3 || op
== 5) {
5034 ot
= dflag
? MO_32
+ (rex_w
== 1) : MO_16
;
5035 } else if (op
== 6) {
5036 /* default push size is 64 bit */
5037 ot
= dflag
? MO_64
: MO_16
;
5041 gen_lea_modrm(env
, s
, modrm
);
5042 if (op
>= 2 && op
!= 3 && op
!= 5)
5043 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5045 gen_op_mov_TN_reg(ot
, 0, rm
);
5049 case 0: /* inc Ev */
5054 gen_inc(s
, ot
, opreg
, 1);
5056 case 1: /* dec Ev */
5061 gen_inc(s
, ot
, opreg
, -1);
5063 case 2: /* call Ev */
5064 /* XXX: optimize if memory (no 'and' is necessary) */
5066 gen_op_andl_T0_ffff();
5067 next_eip
= s
->pc
- s
->cs_base
;
5068 gen_movtl_T1_im(next_eip
);
5073 case 3: /* lcall Ev */
5074 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5075 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5076 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5078 if (s
->pe
&& !s
->vm86
) {
5079 gen_update_cc_op(s
);
5080 gen_jmp_im(pc_start
- s
->cs_base
);
5081 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5082 gen_helper_lcall_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5083 tcg_const_i32(dflag
),
5084 tcg_const_i32(s
->pc
- pc_start
));
5086 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5087 gen_helper_lcall_real(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5088 tcg_const_i32(dflag
),
5089 tcg_const_i32(s
->pc
- s
->cs_base
));
5093 case 4: /* jmp Ev */
5095 gen_op_andl_T0_ffff();
5099 case 5: /* ljmp Ev */
5100 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5101 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5102 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5104 if (s
->pe
&& !s
->vm86
) {
5105 gen_update_cc_op(s
);
5106 gen_jmp_im(pc_start
- s
->cs_base
);
5107 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5108 gen_helper_ljmp_protected(cpu_env
, cpu_tmp2_i32
, cpu_T
[1],
5109 tcg_const_i32(s
->pc
- pc_start
));
5111 gen_op_movl_seg_T0_vm(R_CS
);
5112 gen_op_movl_T0_T1();
5117 case 6: /* push Ev */
5125 case 0x84: /* test Ev, Gv */
5132 modrm
= cpu_ldub_code(env
, s
->pc
++);
5133 reg
= ((modrm
>> 3) & 7) | rex_r
;
5135 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5136 gen_op_mov_TN_reg(ot
, 1, reg
);
5137 gen_op_testl_T0_T1_cc();
5138 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5141 case 0xa8: /* test eAX, Iv */
5147 val
= insn_get(env
, s
, ot
);
5149 gen_op_mov_TN_reg(ot
, 0, OR_EAX
);
5150 gen_op_movl_T1_im(val
);
5151 gen_op_testl_T0_T1_cc();
5152 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
5155 case 0x98: /* CWDE/CBW */
5156 #ifdef TARGET_X86_64
5158 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5159 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5160 gen_op_mov_reg_T0(MO_64
, R_EAX
);
5164 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5165 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5166 gen_op_mov_reg_T0(MO_32
, R_EAX
);
5168 gen_op_mov_TN_reg(MO_8
, 0, R_EAX
);
5169 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5170 gen_op_mov_reg_T0(MO_16
, R_EAX
);
5173 case 0x99: /* CDQ/CWD */
5174 #ifdef TARGET_X86_64
5176 gen_op_mov_TN_reg(MO_64
, 0, R_EAX
);
5177 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 63);
5178 gen_op_mov_reg_T0(MO_64
, R_EDX
);
5182 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5183 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
5184 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 31);
5185 gen_op_mov_reg_T0(MO_32
, R_EDX
);
5187 gen_op_mov_TN_reg(MO_16
, 0, R_EAX
);
5188 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5189 tcg_gen_sari_tl(cpu_T
[0], cpu_T
[0], 15);
5190 gen_op_mov_reg_T0(MO_16
, R_EDX
);
5193 case 0x1af: /* imul Gv, Ev */
5194 case 0x69: /* imul Gv, Ev, I */
5197 modrm
= cpu_ldub_code(env
, s
->pc
++);
5198 reg
= ((modrm
>> 3) & 7) | rex_r
;
5200 s
->rip_offset
= insn_const_size(ot
);
5203 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5205 val
= insn_get(env
, s
, ot
);
5206 gen_op_movl_T1_im(val
);
5207 } else if (b
== 0x6b) {
5208 val
= (int8_t)insn_get(env
, s
, MO_8
);
5209 gen_op_movl_T1_im(val
);
5211 gen_op_mov_TN_reg(ot
, 1, reg
);
5214 #ifdef TARGET_X86_64
5216 tcg_gen_muls2_i64(cpu_regs
[reg
], cpu_T
[1], cpu_T
[0], cpu_T
[1]);
5217 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5218 tcg_gen_sari_tl(cpu_cc_src
, cpu_cc_dst
, 63);
5219 tcg_gen_sub_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[1]);
5223 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5224 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
5225 tcg_gen_muls2_i32(cpu_tmp2_i32
, cpu_tmp3_i32
,
5226 cpu_tmp2_i32
, cpu_tmp3_i32
);
5227 tcg_gen_extu_i32_tl(cpu_regs
[reg
], cpu_tmp2_i32
);
5228 tcg_gen_sari_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, 31);
5229 tcg_gen_mov_tl(cpu_cc_dst
, cpu_regs
[reg
]);
5230 tcg_gen_sub_i32(cpu_tmp2_i32
, cpu_tmp2_i32
, cpu_tmp3_i32
);
5231 tcg_gen_extu_i32_tl(cpu_cc_src
, cpu_tmp2_i32
);
5234 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5235 tcg_gen_ext16s_tl(cpu_T
[1], cpu_T
[1]);
5236 /* XXX: use 32 bit mul which could be faster */
5237 tcg_gen_mul_tl(cpu_T
[0], cpu_T
[0], cpu_T
[1]);
5238 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
5239 tcg_gen_ext16s_tl(cpu_tmp0
, cpu_T
[0]);
5240 tcg_gen_sub_tl(cpu_cc_src
, cpu_T
[0], cpu_tmp0
);
5241 gen_op_mov_reg_T0(ot
, reg
);
5244 set_cc_op(s
, CC_OP_MULB
+ ot
);
5247 case 0x1c1: /* xadd Ev, Gv */
5252 modrm
= cpu_ldub_code(env
, s
->pc
++);
5253 reg
= ((modrm
>> 3) & 7) | rex_r
;
5254 mod
= (modrm
>> 6) & 3;
5256 rm
= (modrm
& 7) | REX_B(s
);
5257 gen_op_mov_TN_reg(ot
, 0, reg
);
5258 gen_op_mov_TN_reg(ot
, 1, rm
);
5259 gen_op_addl_T0_T1();
5260 gen_op_mov_reg_T1(ot
, reg
);
5261 gen_op_mov_reg_T0(ot
, rm
);
5263 gen_lea_modrm(env
, s
, modrm
);
5264 gen_op_mov_TN_reg(ot
, 0, reg
);
5265 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5266 gen_op_addl_T0_T1();
5267 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5268 gen_op_mov_reg_T1(ot
, reg
);
5270 gen_op_update2_cc();
5271 set_cc_op(s
, CC_OP_ADDB
+ ot
);
5274 case 0x1b1: /* cmpxchg Ev, Gv */
5277 TCGv t0
, t1
, t2
, a0
;
5283 modrm
= cpu_ldub_code(env
, s
->pc
++);
5284 reg
= ((modrm
>> 3) & 7) | rex_r
;
5285 mod
= (modrm
>> 6) & 3;
5286 t0
= tcg_temp_local_new();
5287 t1
= tcg_temp_local_new();
5288 t2
= tcg_temp_local_new();
5289 a0
= tcg_temp_local_new();
5290 gen_op_mov_v_reg(ot
, t1
, reg
);
5292 rm
= (modrm
& 7) | REX_B(s
);
5293 gen_op_mov_v_reg(ot
, t0
, rm
);
5295 gen_lea_modrm(env
, s
, modrm
);
5296 tcg_gen_mov_tl(a0
, cpu_A0
);
5297 gen_op_ld_v(s
, ot
, t0
, a0
);
5298 rm
= 0; /* avoid warning */
5300 label1
= gen_new_label();
5301 tcg_gen_mov_tl(t2
, cpu_regs
[R_EAX
]);
5304 tcg_gen_brcond_tl(TCG_COND_EQ
, t2
, t0
, label1
);
5305 label2
= gen_new_label();
5307 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5309 gen_set_label(label1
);
5310 gen_op_mov_reg_v(ot
, rm
, t1
);
5312 /* perform no-op store cycle like physical cpu; must be
5313 before changing accumulator to ensure idempotency if
5314 the store faults and the instruction is restarted */
5315 gen_op_st_v(s
, ot
, t0
, a0
);
5316 gen_op_mov_reg_v(ot
, R_EAX
, t0
);
5318 gen_set_label(label1
);
5319 gen_op_st_v(s
, ot
, t1
, a0
);
5321 gen_set_label(label2
);
5322 tcg_gen_mov_tl(cpu_cc_src
, t0
);
5323 tcg_gen_mov_tl(cpu_cc_srcT
, t2
);
5324 tcg_gen_sub_tl(cpu_cc_dst
, t2
, t0
);
5325 set_cc_op(s
, CC_OP_SUBB
+ ot
);
5332 case 0x1c7: /* cmpxchg8b */
5333 modrm
= cpu_ldub_code(env
, s
->pc
++);
5334 mod
= (modrm
>> 6) & 3;
5335 if ((mod
== 3) || ((modrm
& 0x38) != 0x8))
5337 #ifdef TARGET_X86_64
5339 if (!(s
->cpuid_ext_features
& CPUID_EXT_CX16
))
5341 gen_jmp_im(pc_start
- s
->cs_base
);
5342 gen_update_cc_op(s
);
5343 gen_lea_modrm(env
, s
, modrm
);
5344 gen_helper_cmpxchg16b(cpu_env
, cpu_A0
);
5348 if (!(s
->cpuid_features
& CPUID_CX8
))
5350 gen_jmp_im(pc_start
- s
->cs_base
);
5351 gen_update_cc_op(s
);
5352 gen_lea_modrm(env
, s
, modrm
);
5353 gen_helper_cmpxchg8b(cpu_env
, cpu_A0
);
5355 set_cc_op(s
, CC_OP_EFLAGS
);
5358 /**************************/
5360 case 0x50 ... 0x57: /* push */
5361 gen_op_mov_TN_reg(MO_32
, 0, (b
& 7) | REX_B(s
));
5364 case 0x58 ... 0x5f: /* pop */
5366 ot
= dflag
? MO_64
: MO_16
;
5371 /* NOTE: order is important for pop %sp */
5373 gen_op_mov_reg_T0(ot
, (b
& 7) | REX_B(s
));
5375 case 0x60: /* pusha */
5380 case 0x61: /* popa */
5385 case 0x68: /* push Iv */
5388 ot
= dflag
? MO_64
: MO_16
;
5393 val
= insn_get(env
, s
, ot
);
5395 val
= (int8_t)insn_get(env
, s
, MO_8
);
5396 gen_op_movl_T0_im(val
);
5399 case 0x8f: /* pop Ev */
5401 ot
= dflag
? MO_64
: MO_16
;
5405 modrm
= cpu_ldub_code(env
, s
->pc
++);
5406 mod
= (modrm
>> 6) & 3;
5409 /* NOTE: order is important for pop %sp */
5411 rm
= (modrm
& 7) | REX_B(s
);
5412 gen_op_mov_reg_T0(ot
, rm
);
5414 /* NOTE: order is important too for MMU exceptions */
5415 s
->popl_esp_hack
= 1 << ot
;
5416 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5417 s
->popl_esp_hack
= 0;
5421 case 0xc8: /* enter */
5424 val
= cpu_lduw_code(env
, s
->pc
);
5426 level
= cpu_ldub_code(env
, s
->pc
++);
5427 gen_enter(s
, val
, level
);
5430 case 0xc9: /* leave */
5431 /* XXX: exception not precise (ESP is updated before potential exception) */
5433 gen_op_mov_TN_reg(MO_64
, 0, R_EBP
);
5434 gen_op_mov_reg_T0(MO_64
, R_ESP
);
5435 } else if (s
->ss32
) {
5436 gen_op_mov_TN_reg(MO_32
, 0, R_EBP
);
5437 gen_op_mov_reg_T0(MO_32
, R_ESP
);
5439 gen_op_mov_TN_reg(MO_16
, 0, R_EBP
);
5440 gen_op_mov_reg_T0(MO_16
, R_ESP
);
5444 ot
= dflag
? MO_64
: MO_16
;
5448 gen_op_mov_reg_T0(ot
, R_EBP
);
5451 case 0x06: /* push es */
5452 case 0x0e: /* push cs */
5453 case 0x16: /* push ss */
5454 case 0x1e: /* push ds */
5457 gen_op_movl_T0_seg(b
>> 3);
5460 case 0x1a0: /* push fs */
5461 case 0x1a8: /* push gs */
5462 gen_op_movl_T0_seg((b
>> 3) & 7);
5465 case 0x07: /* pop es */
5466 case 0x17: /* pop ss */
5467 case 0x1f: /* pop ds */
5472 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5475 /* if reg == SS, inhibit interrupts/trace. */
5476 /* If several instructions disable interrupts, only the
5478 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5479 gen_helper_set_inhibit_irq(cpu_env
);
5483 gen_jmp_im(s
->pc
- s
->cs_base
);
5487 case 0x1a1: /* pop fs */
5488 case 0x1a9: /* pop gs */
5490 gen_movl_seg_T0(s
, (b
>> 3) & 7, pc_start
- s
->cs_base
);
5493 gen_jmp_im(s
->pc
- s
->cs_base
);
5498 /**************************/
5501 case 0x89: /* mov Gv, Ev */
5506 modrm
= cpu_ldub_code(env
, s
->pc
++);
5507 reg
= ((modrm
>> 3) & 7) | rex_r
;
5509 /* generate a generic store */
5510 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
5513 case 0xc7: /* mov Ev, Iv */
5518 modrm
= cpu_ldub_code(env
, s
->pc
++);
5519 mod
= (modrm
>> 6) & 3;
5521 s
->rip_offset
= insn_const_size(ot
);
5522 gen_lea_modrm(env
, s
, modrm
);
5524 val
= insn_get(env
, s
, ot
);
5525 gen_op_movl_T0_im(val
);
5527 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5529 gen_op_mov_reg_T0(ot
, (modrm
& 7) | REX_B(s
));
5533 case 0x8b: /* mov Ev, Gv */
5538 modrm
= cpu_ldub_code(env
, s
->pc
++);
5539 reg
= ((modrm
>> 3) & 7) | rex_r
;
5541 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
5542 gen_op_mov_reg_T0(ot
, reg
);
5544 case 0x8e: /* mov seg, Gv */
5545 modrm
= cpu_ldub_code(env
, s
->pc
++);
5546 reg
= (modrm
>> 3) & 7;
5547 if (reg
>= 6 || reg
== R_CS
)
5549 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
5550 gen_movl_seg_T0(s
, reg
, pc_start
- s
->cs_base
);
5552 /* if reg == SS, inhibit interrupts/trace */
5553 /* If several instructions disable interrupts, only the
5555 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
5556 gen_helper_set_inhibit_irq(cpu_env
);
5560 gen_jmp_im(s
->pc
- s
->cs_base
);
5564 case 0x8c: /* mov Gv, seg */
5565 modrm
= cpu_ldub_code(env
, s
->pc
++);
5566 reg
= (modrm
>> 3) & 7;
5567 mod
= (modrm
>> 6) & 3;
5570 gen_op_movl_T0_seg(reg
);
5575 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
5578 case 0x1b6: /* movzbS Gv, Eb */
5579 case 0x1b7: /* movzwS Gv, Eb */
5580 case 0x1be: /* movsbS Gv, Eb */
5581 case 0x1bf: /* movswS Gv, Eb */
5586 /* d_ot is the size of destination */
5587 d_ot
= dflag
+ MO_16
;
5588 /* ot is the size of source */
5589 ot
= (b
& 1) + MO_8
;
5590 /* s_ot is the sign+size of source */
5591 s_ot
= b
& 8 ? MO_SIGN
| ot
: ot
;
5593 modrm
= cpu_ldub_code(env
, s
->pc
++);
5594 reg
= ((modrm
>> 3) & 7) | rex_r
;
5595 mod
= (modrm
>> 6) & 3;
5596 rm
= (modrm
& 7) | REX_B(s
);
5599 gen_op_mov_TN_reg(ot
, 0, rm
);
5602 tcg_gen_ext8u_tl(cpu_T
[0], cpu_T
[0]);
5605 tcg_gen_ext8s_tl(cpu_T
[0], cpu_T
[0]);
5608 tcg_gen_ext16u_tl(cpu_T
[0], cpu_T
[0]);
5612 tcg_gen_ext16s_tl(cpu_T
[0], cpu_T
[0]);
5615 gen_op_mov_reg_T0(d_ot
, reg
);
5617 gen_lea_modrm(env
, s
, modrm
);
5618 gen_op_ld_v(s
, s_ot
, cpu_T
[0], cpu_A0
);
5619 gen_op_mov_reg_T0(d_ot
, reg
);
5624 case 0x8d: /* lea */
5626 modrm
= cpu_ldub_code(env
, s
->pc
++);
5627 mod
= (modrm
>> 6) & 3;
5630 reg
= ((modrm
>> 3) & 7) | rex_r
;
5631 /* we must ensure that no segment is added */
5635 gen_lea_modrm(env
, s
, modrm
);
5637 gen_op_mov_reg_A0(ot
- MO_16
, reg
);
5640 case 0xa0: /* mov EAX, Ov */
5642 case 0xa2: /* mov Ov, EAX */
5645 target_ulong offset_addr
;
5651 #ifdef TARGET_X86_64
5652 if (s
->aflag
== 2) {
5653 offset_addr
= cpu_ldq_code(env
, s
->pc
);
5655 gen_op_movq_A0_im(offset_addr
);
5660 offset_addr
= insn_get(env
, s
, MO_32
);
5662 offset_addr
= insn_get(env
, s
, MO_16
);
5664 gen_op_movl_A0_im(offset_addr
);
5666 gen_add_A0_ds_seg(s
);
5668 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
5669 gen_op_mov_reg_T0(ot
, R_EAX
);
5671 gen_op_mov_TN_reg(ot
, 0, R_EAX
);
5672 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5676 case 0xd7: /* xlat */
5677 #ifdef TARGET_X86_64
5678 if (s
->aflag
== 2) {
5679 gen_op_movq_A0_reg(R_EBX
);
5680 gen_op_mov_TN_reg(MO_64
, 0, R_EAX
);
5681 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5682 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5686 gen_op_movl_A0_reg(R_EBX
);
5687 gen_op_mov_TN_reg(MO_32
, 0, R_EAX
);
5688 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], 0xff);
5689 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_T
[0]);
5691 gen_op_andl_A0_ffff();
5693 tcg_gen_andi_tl(cpu_A0
, cpu_A0
, 0xffffffff);
5695 gen_add_A0_ds_seg(s
);
5696 gen_op_ld_v(s
, MO_8
, cpu_T
[0], cpu_A0
);
5697 gen_op_mov_reg_T0(MO_8
, R_EAX
);
5699 case 0xb0 ... 0xb7: /* mov R, Ib */
5700 val
= insn_get(env
, s
, MO_8
);
5701 gen_op_movl_T0_im(val
);
5702 gen_op_mov_reg_T0(MO_8
, (b
& 7) | REX_B(s
));
5704 case 0xb8 ... 0xbf: /* mov R, Iv */
5705 #ifdef TARGET_X86_64
5709 tmp
= cpu_ldq_code(env
, s
->pc
);
5711 reg
= (b
& 7) | REX_B(s
);
5712 gen_movtl_T0_im(tmp
);
5713 gen_op_mov_reg_T0(MO_64
, reg
);
5717 ot
= dflag
? MO_32
: MO_16
;
5718 val
= insn_get(env
, s
, ot
);
5719 reg
= (b
& 7) | REX_B(s
);
5720 gen_op_movl_T0_im(val
);
5721 gen_op_mov_reg_T0(ot
, reg
);
5725 case 0x91 ... 0x97: /* xchg R, EAX */
5728 reg
= (b
& 7) | REX_B(s
);
5732 case 0x87: /* xchg Ev, Gv */
5737 modrm
= cpu_ldub_code(env
, s
->pc
++);
5738 reg
= ((modrm
>> 3) & 7) | rex_r
;
5739 mod
= (modrm
>> 6) & 3;
5741 rm
= (modrm
& 7) | REX_B(s
);
5743 gen_op_mov_TN_reg(ot
, 0, reg
);
5744 gen_op_mov_TN_reg(ot
, 1, rm
);
5745 gen_op_mov_reg_T0(ot
, rm
);
5746 gen_op_mov_reg_T1(ot
, reg
);
5748 gen_lea_modrm(env
, s
, modrm
);
5749 gen_op_mov_TN_reg(ot
, 0, reg
);
5750 /* for xchg, lock is implicit */
5751 if (!(prefixes
& PREFIX_LOCK
))
5753 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5754 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
5755 if (!(prefixes
& PREFIX_LOCK
))
5756 gen_helper_unlock();
5757 gen_op_mov_reg_T1(ot
, reg
);
5760 case 0xc4: /* les Gv */
5761 /* In CODE64 this is VEX3; see above. */
5764 case 0xc5: /* lds Gv */
5765 /* In CODE64 this is VEX2; see above. */
5768 case 0x1b2: /* lss Gv */
5771 case 0x1b4: /* lfs Gv */
5774 case 0x1b5: /* lgs Gv */
5777 ot
= dflag
? MO_32
: MO_16
;
5778 modrm
= cpu_ldub_code(env
, s
->pc
++);
5779 reg
= ((modrm
>> 3) & 7) | rex_r
;
5780 mod
= (modrm
>> 6) & 3;
5783 gen_lea_modrm(env
, s
, modrm
);
5784 gen_op_ld_v(s
, ot
, cpu_T
[1], cpu_A0
);
5785 gen_add_A0_im(s
, 1 << (ot
- MO_16
+ 1));
5786 /* load the segment first to handle exceptions properly */
5787 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5788 gen_movl_seg_T0(s
, op
, pc_start
- s
->cs_base
);
5789 /* then put the data */
5790 gen_op_mov_reg_T1(ot
, reg
);
5792 gen_jmp_im(s
->pc
- s
->cs_base
);
5797 /************************/
5810 modrm
= cpu_ldub_code(env
, s
->pc
++);
5811 mod
= (modrm
>> 6) & 3;
5812 op
= (modrm
>> 3) & 7;
5818 gen_lea_modrm(env
, s
, modrm
);
5821 opreg
= (modrm
& 7) | REX_B(s
);
5826 gen_shift(s
, op
, ot
, opreg
, OR_ECX
);
5829 shift
= cpu_ldub_code(env
, s
->pc
++);
5831 gen_shifti(s
, op
, ot
, opreg
, shift
);
5846 case 0x1a4: /* shld imm */
5850 case 0x1a5: /* shld cl */
5854 case 0x1ac: /* shrd imm */
5858 case 0x1ad: /* shrd cl */
5863 modrm
= cpu_ldub_code(env
, s
->pc
++);
5864 mod
= (modrm
>> 6) & 3;
5865 rm
= (modrm
& 7) | REX_B(s
);
5866 reg
= ((modrm
>> 3) & 7) | rex_r
;
5868 gen_lea_modrm(env
, s
, modrm
);
5873 gen_op_mov_TN_reg(ot
, 1, reg
);
5876 TCGv imm
= tcg_const_tl(cpu_ldub_code(env
, s
->pc
++));
5877 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, imm
);
5880 gen_shiftd_rm_T1(s
, ot
, opreg
, op
, cpu_regs
[R_ECX
]);
5884 /************************/
5887 if (s
->flags
& (HF_EM_MASK
| HF_TS_MASK
)) {
5888 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5889 /* XXX: what to do if illegal op ? */
5890 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
5893 modrm
= cpu_ldub_code(env
, s
->pc
++);
5894 mod
= (modrm
>> 6) & 3;
5896 op
= ((b
& 7) << 3) | ((modrm
>> 3) & 7);
5899 gen_lea_modrm(env
, s
, modrm
);
5901 case 0x00 ... 0x07: /* fxxxs */
5902 case 0x10 ... 0x17: /* fixxxl */
5903 case 0x20 ... 0x27: /* fxxxl */
5904 case 0x30 ... 0x37: /* fixxx */
5911 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
5912 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5913 gen_helper_flds_FT0(cpu_env
, cpu_tmp2_i32
);
5916 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
5917 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5918 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5921 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5922 s
->mem_index
, MO_LEQ
);
5923 gen_helper_fldl_FT0(cpu_env
, cpu_tmp1_i64
);
5927 gen_op_ld_v(s
, MO_SW
, cpu_T
[0], cpu_A0
);
5928 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5929 gen_helper_fildl_FT0(cpu_env
, cpu_tmp2_i32
);
5933 gen_helper_fp_arith_ST0_FT0(op1
);
5935 /* fcomp needs pop */
5936 gen_helper_fpop(cpu_env
);
5940 case 0x08: /* flds */
5941 case 0x0a: /* fsts */
5942 case 0x0b: /* fstps */
5943 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5944 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5945 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5950 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
5951 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5952 gen_helper_flds_ST0(cpu_env
, cpu_tmp2_i32
);
5955 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
5956 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5957 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5960 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
,
5961 s
->mem_index
, MO_LEQ
);
5962 gen_helper_fldl_ST0(cpu_env
, cpu_tmp1_i64
);
5966 gen_op_ld_v(s
, MO_SW
, cpu_T
[0], cpu_A0
);
5967 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
5968 gen_helper_fildl_ST0(cpu_env
, cpu_tmp2_i32
);
5973 /* XXX: the corresponding CPUID bit must be tested ! */
5976 gen_helper_fisttl_ST0(cpu_tmp2_i32
, cpu_env
);
5977 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5978 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
5981 gen_helper_fisttll_ST0(cpu_tmp1_i64
, cpu_env
);
5982 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
5983 s
->mem_index
, MO_LEQ
);
5987 gen_helper_fistt_ST0(cpu_tmp2_i32
, cpu_env
);
5988 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5989 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
5992 gen_helper_fpop(cpu_env
);
5997 gen_helper_fsts_ST0(cpu_tmp2_i32
, cpu_env
);
5998 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
5999 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
6002 gen_helper_fistl_ST0(cpu_tmp2_i32
, cpu_env
);
6003 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6004 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
6007 gen_helper_fstl_ST0(cpu_tmp1_i64
, cpu_env
);
6008 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
,
6009 s
->mem_index
, MO_LEQ
);
6013 gen_helper_fist_ST0(cpu_tmp2_i32
, cpu_env
);
6014 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6015 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
6019 gen_helper_fpop(cpu_env
);
6023 case 0x0c: /* fldenv mem */
6024 gen_update_cc_op(s
);
6025 gen_jmp_im(pc_start
- s
->cs_base
);
6026 gen_helper_fldenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
6028 case 0x0d: /* fldcw mem */
6029 gen_op_ld_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
6030 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6031 gen_helper_fldcw(cpu_env
, cpu_tmp2_i32
);
6033 case 0x0e: /* fnstenv mem */
6034 gen_update_cc_op(s
);
6035 gen_jmp_im(pc_start
- s
->cs_base
);
6036 gen_helper_fstenv(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
6038 case 0x0f: /* fnstcw mem */
6039 gen_helper_fnstcw(cpu_tmp2_i32
, cpu_env
);
6040 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6041 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
6043 case 0x1d: /* fldt mem */
6044 gen_update_cc_op(s
);
6045 gen_jmp_im(pc_start
- s
->cs_base
);
6046 gen_helper_fldt_ST0(cpu_env
, cpu_A0
);
6048 case 0x1f: /* fstpt mem */
6049 gen_update_cc_op(s
);
6050 gen_jmp_im(pc_start
- s
->cs_base
);
6051 gen_helper_fstt_ST0(cpu_env
, cpu_A0
);
6052 gen_helper_fpop(cpu_env
);
6054 case 0x2c: /* frstor mem */
6055 gen_update_cc_op(s
);
6056 gen_jmp_im(pc_start
- s
->cs_base
);
6057 gen_helper_frstor(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
6059 case 0x2e: /* fnsave mem */
6060 gen_update_cc_op(s
);
6061 gen_jmp_im(pc_start
- s
->cs_base
);
6062 gen_helper_fsave(cpu_env
, cpu_A0
, tcg_const_i32(s
->dflag
));
6064 case 0x2f: /* fnstsw mem */
6065 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6066 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6067 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
6069 case 0x3c: /* fbld */
6070 gen_update_cc_op(s
);
6071 gen_jmp_im(pc_start
- s
->cs_base
);
6072 gen_helper_fbld_ST0(cpu_env
, cpu_A0
);
6074 case 0x3e: /* fbstp */
6075 gen_update_cc_op(s
);
6076 gen_jmp_im(pc_start
- s
->cs_base
);
6077 gen_helper_fbst_ST0(cpu_env
, cpu_A0
);
6078 gen_helper_fpop(cpu_env
);
6080 case 0x3d: /* fildll */
6081 tcg_gen_qemu_ld_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
6082 gen_helper_fildll_ST0(cpu_env
, cpu_tmp1_i64
);
6084 case 0x3f: /* fistpll */
6085 gen_helper_fistll_ST0(cpu_tmp1_i64
, cpu_env
);
6086 tcg_gen_qemu_st_i64(cpu_tmp1_i64
, cpu_A0
, s
->mem_index
, MO_LEQ
);
6087 gen_helper_fpop(cpu_env
);
6093 /* register float ops */
6097 case 0x08: /* fld sti */
6098 gen_helper_fpush(cpu_env
);
6099 gen_helper_fmov_ST0_STN(cpu_env
,
6100 tcg_const_i32((opreg
+ 1) & 7));
6102 case 0x09: /* fxchg sti */
6103 case 0x29: /* fxchg4 sti, undocumented op */
6104 case 0x39: /* fxchg7 sti, undocumented op */
6105 gen_helper_fxchg_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6107 case 0x0a: /* grp d9/2 */
6110 /* check exceptions (FreeBSD FPU probe) */
6111 gen_update_cc_op(s
);
6112 gen_jmp_im(pc_start
- s
->cs_base
);
6113 gen_helper_fwait(cpu_env
);
6119 case 0x0c: /* grp d9/4 */
6122 gen_helper_fchs_ST0(cpu_env
);
6125 gen_helper_fabs_ST0(cpu_env
);
6128 gen_helper_fldz_FT0(cpu_env
);
6129 gen_helper_fcom_ST0_FT0(cpu_env
);
6132 gen_helper_fxam_ST0(cpu_env
);
6138 case 0x0d: /* grp d9/5 */
6142 gen_helper_fpush(cpu_env
);
6143 gen_helper_fld1_ST0(cpu_env
);
6146 gen_helper_fpush(cpu_env
);
6147 gen_helper_fldl2t_ST0(cpu_env
);
6150 gen_helper_fpush(cpu_env
);
6151 gen_helper_fldl2e_ST0(cpu_env
);
6154 gen_helper_fpush(cpu_env
);
6155 gen_helper_fldpi_ST0(cpu_env
);
6158 gen_helper_fpush(cpu_env
);
6159 gen_helper_fldlg2_ST0(cpu_env
);
6162 gen_helper_fpush(cpu_env
);
6163 gen_helper_fldln2_ST0(cpu_env
);
6166 gen_helper_fpush(cpu_env
);
6167 gen_helper_fldz_ST0(cpu_env
);
6174 case 0x0e: /* grp d9/6 */
6177 gen_helper_f2xm1(cpu_env
);
6180 gen_helper_fyl2x(cpu_env
);
6183 gen_helper_fptan(cpu_env
);
6185 case 3: /* fpatan */
6186 gen_helper_fpatan(cpu_env
);
6188 case 4: /* fxtract */
6189 gen_helper_fxtract(cpu_env
);
6191 case 5: /* fprem1 */
6192 gen_helper_fprem1(cpu_env
);
6194 case 6: /* fdecstp */
6195 gen_helper_fdecstp(cpu_env
);
6198 case 7: /* fincstp */
6199 gen_helper_fincstp(cpu_env
);
6203 case 0x0f: /* grp d9/7 */
6206 gen_helper_fprem(cpu_env
);
6208 case 1: /* fyl2xp1 */
6209 gen_helper_fyl2xp1(cpu_env
);
6212 gen_helper_fsqrt(cpu_env
);
6214 case 3: /* fsincos */
6215 gen_helper_fsincos(cpu_env
);
6217 case 5: /* fscale */
6218 gen_helper_fscale(cpu_env
);
6220 case 4: /* frndint */
6221 gen_helper_frndint(cpu_env
);
6224 gen_helper_fsin(cpu_env
);
6228 gen_helper_fcos(cpu_env
);
6232 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
6233 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
6234 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
6240 gen_helper_fp_arith_STN_ST0(op1
, opreg
);
6242 gen_helper_fpop(cpu_env
);
6244 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6245 gen_helper_fp_arith_ST0_FT0(op1
);
6249 case 0x02: /* fcom */
6250 case 0x22: /* fcom2, undocumented op */
6251 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6252 gen_helper_fcom_ST0_FT0(cpu_env
);
6254 case 0x03: /* fcomp */
6255 case 0x23: /* fcomp3, undocumented op */
6256 case 0x32: /* fcomp5, undocumented op */
6257 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6258 gen_helper_fcom_ST0_FT0(cpu_env
);
6259 gen_helper_fpop(cpu_env
);
6261 case 0x15: /* da/5 */
6263 case 1: /* fucompp */
6264 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6265 gen_helper_fucom_ST0_FT0(cpu_env
);
6266 gen_helper_fpop(cpu_env
);
6267 gen_helper_fpop(cpu_env
);
6275 case 0: /* feni (287 only, just do nop here) */
6277 case 1: /* fdisi (287 only, just do nop here) */
6280 gen_helper_fclex(cpu_env
);
6282 case 3: /* fninit */
6283 gen_helper_fninit(cpu_env
);
6285 case 4: /* fsetpm (287 only, just do nop here) */
6291 case 0x1d: /* fucomi */
6292 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6295 gen_update_cc_op(s
);
6296 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6297 gen_helper_fucomi_ST0_FT0(cpu_env
);
6298 set_cc_op(s
, CC_OP_EFLAGS
);
6300 case 0x1e: /* fcomi */
6301 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6304 gen_update_cc_op(s
);
6305 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6306 gen_helper_fcomi_ST0_FT0(cpu_env
);
6307 set_cc_op(s
, CC_OP_EFLAGS
);
6309 case 0x28: /* ffree sti */
6310 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6312 case 0x2a: /* fst sti */
6313 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6315 case 0x2b: /* fstp sti */
6316 case 0x0b: /* fstp1 sti, undocumented op */
6317 case 0x3a: /* fstp8 sti, undocumented op */
6318 case 0x3b: /* fstp9 sti, undocumented op */
6319 gen_helper_fmov_STN_ST0(cpu_env
, tcg_const_i32(opreg
));
6320 gen_helper_fpop(cpu_env
);
6322 case 0x2c: /* fucom st(i) */
6323 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6324 gen_helper_fucom_ST0_FT0(cpu_env
);
6326 case 0x2d: /* fucomp st(i) */
6327 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6328 gen_helper_fucom_ST0_FT0(cpu_env
);
6329 gen_helper_fpop(cpu_env
);
6331 case 0x33: /* de/3 */
6333 case 1: /* fcompp */
6334 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(1));
6335 gen_helper_fcom_ST0_FT0(cpu_env
);
6336 gen_helper_fpop(cpu_env
);
6337 gen_helper_fpop(cpu_env
);
6343 case 0x38: /* ffreep sti, undocumented op */
6344 gen_helper_ffree_STN(cpu_env
, tcg_const_i32(opreg
));
6345 gen_helper_fpop(cpu_env
);
6347 case 0x3c: /* df/4 */
6350 gen_helper_fnstsw(cpu_tmp2_i32
, cpu_env
);
6351 tcg_gen_extu_i32_tl(cpu_T
[0], cpu_tmp2_i32
);
6352 gen_op_mov_reg_T0(MO_16
, R_EAX
);
6358 case 0x3d: /* fucomip */
6359 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6362 gen_update_cc_op(s
);
6363 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6364 gen_helper_fucomi_ST0_FT0(cpu_env
);
6365 gen_helper_fpop(cpu_env
);
6366 set_cc_op(s
, CC_OP_EFLAGS
);
6368 case 0x3e: /* fcomip */
6369 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6372 gen_update_cc_op(s
);
6373 gen_helper_fmov_FT0_STN(cpu_env
, tcg_const_i32(opreg
));
6374 gen_helper_fcomi_ST0_FT0(cpu_env
);
6375 gen_helper_fpop(cpu_env
);
6376 set_cc_op(s
, CC_OP_EFLAGS
);
6378 case 0x10 ... 0x13: /* fcmovxx */
6382 static const uint8_t fcmov_cc
[8] = {
6389 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6392 op1
= fcmov_cc
[op
& 3] | (((op
>> 3) & 1) ^ 1);
6393 l1
= gen_new_label();
6394 gen_jcc1_noeob(s
, op1
, l1
);
6395 gen_helper_fmov_ST0_STN(cpu_env
, tcg_const_i32(opreg
));
6404 /************************/
6407 case 0xa4: /* movsS */
6414 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6415 gen_repz_movs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6421 case 0xaa: /* stosS */
6428 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6429 gen_repz_stos(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6434 case 0xac: /* lodsS */
6440 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6441 gen_repz_lods(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6446 case 0xae: /* scasS */
6452 if (prefixes
& PREFIX_REPNZ
) {
6453 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6454 } else if (prefixes
& PREFIX_REPZ
) {
6455 gen_repz_scas(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6461 case 0xa6: /* cmpsS */
6467 if (prefixes
& PREFIX_REPNZ
) {
6468 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 1);
6469 } else if (prefixes
& PREFIX_REPZ
) {
6470 gen_repz_cmps(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
, 0);
6475 case 0x6c: /* insS */
6480 ot
= dflag
? MO_32
: MO_16
;
6481 gen_op_mov_TN_reg(MO_16
, 0, R_EDX
);
6482 gen_op_andl_T0_ffff();
6483 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6484 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
) | 4);
6485 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6486 gen_repz_ins(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6490 gen_jmp(s
, s
->pc
- s
->cs_base
);
6494 case 0x6e: /* outsS */
6499 ot
= dflag
? MO_32
: MO_16
;
6500 gen_op_mov_TN_reg(MO_16
, 0, R_EDX
);
6501 gen_op_andl_T0_ffff();
6502 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6503 svm_is_rep(prefixes
) | 4);
6504 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) {
6505 gen_repz_outs(s
, ot
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
6509 gen_jmp(s
, s
->pc
- s
->cs_base
);
6514 /************************/
6522 ot
= dflag
? MO_32
: MO_16
;
6523 val
= cpu_ldub_code(env
, s
->pc
++);
6524 gen_op_movl_T0_im(val
);
6525 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6526 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6529 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6530 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6531 gen_op_mov_reg_T1(ot
, R_EAX
);
6534 gen_jmp(s
, s
->pc
- s
->cs_base
);
6542 ot
= dflag
? MO_32
: MO_16
;
6543 val
= cpu_ldub_code(env
, s
->pc
++);
6544 gen_op_movl_T0_im(val
);
6545 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6546 svm_is_rep(prefixes
));
6547 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6551 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6552 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6553 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6556 gen_jmp(s
, s
->pc
- s
->cs_base
);
6564 ot
= dflag
? MO_32
: MO_16
;
6565 gen_op_mov_TN_reg(MO_16
, 0, R_EDX
);
6566 gen_op_andl_T0_ffff();
6567 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6568 SVM_IOIO_TYPE_MASK
| svm_is_rep(prefixes
));
6571 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6572 gen_helper_in_func(ot
, cpu_T
[1], cpu_tmp2_i32
);
6573 gen_op_mov_reg_T1(ot
, R_EAX
);
6576 gen_jmp(s
, s
->pc
- s
->cs_base
);
6584 ot
= dflag
? MO_32
: MO_16
;
6585 gen_op_mov_TN_reg(MO_16
, 0, R_EDX
);
6586 gen_op_andl_T0_ffff();
6587 gen_check_io(s
, ot
, pc_start
- s
->cs_base
,
6588 svm_is_rep(prefixes
));
6589 gen_op_mov_TN_reg(ot
, 1, R_EAX
);
6593 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
6594 tcg_gen_trunc_tl_i32(cpu_tmp3_i32
, cpu_T
[1]);
6595 gen_helper_out_func(ot
, cpu_tmp2_i32
, cpu_tmp3_i32
);
6598 gen_jmp(s
, s
->pc
- s
->cs_base
);
6602 /************************/
6604 case 0xc2: /* ret im */
6605 val
= cpu_ldsw_code(env
, s
->pc
);
6608 if (CODE64(s
) && s
->dflag
)
6610 gen_stack_update(s
, val
+ (2 << s
->dflag
));
6612 gen_op_andl_T0_ffff();
6616 case 0xc3: /* ret */
6620 gen_op_andl_T0_ffff();
6624 case 0xca: /* lret im */
6625 val
= cpu_ldsw_code(env
, s
->pc
);
6628 if (s
->pe
&& !s
->vm86
) {
6629 gen_update_cc_op(s
);
6630 gen_jmp_im(pc_start
- s
->cs_base
);
6631 gen_helper_lret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6632 tcg_const_i32(val
));
6636 gen_op_ld_v(s
, 1 + s
->dflag
, cpu_T
[0], cpu_A0
);
6638 gen_op_andl_T0_ffff();
6639 /* NOTE: keeping EIP updated is not a problem in case of
6643 gen_op_addl_A0_im(2 << s
->dflag
);
6644 gen_op_ld_v(s
, 1 + s
->dflag
, cpu_T
[0], cpu_A0
);
6645 gen_op_movl_seg_T0_vm(R_CS
);
6646 /* add stack offset */
6647 gen_stack_update(s
, val
+ (4 << s
->dflag
));
6651 case 0xcb: /* lret */
6654 case 0xcf: /* iret */
6655 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IRET
);
6658 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6659 set_cc_op(s
, CC_OP_EFLAGS
);
6660 } else if (s
->vm86
) {
6662 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6664 gen_helper_iret_real(cpu_env
, tcg_const_i32(s
->dflag
));
6665 set_cc_op(s
, CC_OP_EFLAGS
);
6668 gen_update_cc_op(s
);
6669 gen_jmp_im(pc_start
- s
->cs_base
);
6670 gen_helper_iret_protected(cpu_env
, tcg_const_i32(s
->dflag
),
6671 tcg_const_i32(s
->pc
- s
->cs_base
));
6672 set_cc_op(s
, CC_OP_EFLAGS
);
6676 case 0xe8: /* call im */
6679 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6681 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6682 next_eip
= s
->pc
- s
->cs_base
;
6688 gen_movtl_T0_im(next_eip
);
6693 case 0x9a: /* lcall im */
6695 unsigned int selector
, offset
;
6699 ot
= dflag
? MO_32
: MO_16
;
6700 offset
= insn_get(env
, s
, ot
);
6701 selector
= insn_get(env
, s
, MO_16
);
6703 gen_op_movl_T0_im(selector
);
6704 gen_op_movl_T1_imu(offset
);
6707 case 0xe9: /* jmp im */
6709 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6711 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6712 tval
+= s
->pc
- s
->cs_base
;
6719 case 0xea: /* ljmp im */
6721 unsigned int selector
, offset
;
6725 ot
= dflag
? MO_32
: MO_16
;
6726 offset
= insn_get(env
, s
, ot
);
6727 selector
= insn_get(env
, s
, MO_16
);
6729 gen_op_movl_T0_im(selector
);
6730 gen_op_movl_T1_imu(offset
);
6733 case 0xeb: /* jmp Jb */
6734 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6735 tval
+= s
->pc
- s
->cs_base
;
6740 case 0x70 ... 0x7f: /* jcc Jb */
6741 tval
= (int8_t)insn_get(env
, s
, MO_8
);
6743 case 0x180 ... 0x18f: /* jcc Jv */
6745 tval
= (int32_t)insn_get(env
, s
, MO_32
);
6747 tval
= (int16_t)insn_get(env
, s
, MO_16
);
6750 next_eip
= s
->pc
- s
->cs_base
;
6754 gen_jcc(s
, b
, tval
, next_eip
);
6757 case 0x190 ... 0x19f: /* setcc Gv */
6758 modrm
= cpu_ldub_code(env
, s
->pc
++);
6759 gen_setcc1(s
, b
, cpu_T
[0]);
6760 gen_ldst_modrm(env
, s
, modrm
, MO_8
, OR_TMP0
, 1);
6762 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6763 if (!(s
->cpuid_features
& CPUID_CMOV
)) {
6767 modrm
= cpu_ldub_code(env
, s
->pc
++);
6768 reg
= ((modrm
>> 3) & 7) | rex_r
;
6769 gen_cmovcc1(env
, s
, ot
, b
, modrm
, reg
);
6772 /************************/
6774 case 0x9c: /* pushf */
6775 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_PUSHF
);
6776 if (s
->vm86
&& s
->iopl
!= 3) {
6777 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6779 gen_update_cc_op(s
);
6780 gen_helper_read_eflags(cpu_T
[0], cpu_env
);
6784 case 0x9d: /* popf */
6785 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_POPF
);
6786 if (s
->vm86
&& s
->iopl
!= 3) {
6787 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
6792 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6793 tcg_const_i32((TF_MASK
| AC_MASK
|
6798 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6799 tcg_const_i32((TF_MASK
| AC_MASK
|
6801 IF_MASK
| IOPL_MASK
)
6805 if (s
->cpl
<= s
->iopl
) {
6807 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6808 tcg_const_i32((TF_MASK
|
6814 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6815 tcg_const_i32((TF_MASK
|
6824 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6825 tcg_const_i32((TF_MASK
| AC_MASK
|
6826 ID_MASK
| NT_MASK
)));
6828 gen_helper_write_eflags(cpu_env
, cpu_T
[0],
6829 tcg_const_i32((TF_MASK
| AC_MASK
|
6836 set_cc_op(s
, CC_OP_EFLAGS
);
6837 /* abort translation because TF/AC flag may change */
6838 gen_jmp_im(s
->pc
- s
->cs_base
);
6842 case 0x9e: /* sahf */
6843 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6845 gen_op_mov_TN_reg(MO_8
, 0, R_AH
);
6846 gen_compute_eflags(s
);
6847 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, CC_O
);
6848 tcg_gen_andi_tl(cpu_T
[0], cpu_T
[0], CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
6849 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, cpu_T
[0]);
6851 case 0x9f: /* lahf */
6852 if (CODE64(s
) && !(s
->cpuid_ext3_features
& CPUID_EXT3_LAHF_LM
))
6854 gen_compute_eflags(s
);
6855 /* Note: gen_compute_eflags() only gives the condition codes */
6856 tcg_gen_ori_tl(cpu_T
[0], cpu_cc_src
, 0x02);
6857 gen_op_mov_reg_T0(MO_8
, R_AH
);
6859 case 0xf5: /* cmc */
6860 gen_compute_eflags(s
);
6861 tcg_gen_xori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6863 case 0xf8: /* clc */
6864 gen_compute_eflags(s
);
6865 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_C
);
6867 case 0xf9: /* stc */
6868 gen_compute_eflags(s
);
6869 tcg_gen_ori_tl(cpu_cc_src
, cpu_cc_src
, CC_C
);
6871 case 0xfc: /* cld */
6872 tcg_gen_movi_i32(cpu_tmp2_i32
, 1);
6873 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6875 case 0xfd: /* std */
6876 tcg_gen_movi_i32(cpu_tmp2_i32
, -1);
6877 tcg_gen_st_i32(cpu_tmp2_i32
, cpu_env
, offsetof(CPUX86State
, df
));
6880 /************************/
6881 /* bit operations */
6882 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6884 modrm
= cpu_ldub_code(env
, s
->pc
++);
6885 op
= (modrm
>> 3) & 7;
6886 mod
= (modrm
>> 6) & 3;
6887 rm
= (modrm
& 7) | REX_B(s
);
6890 gen_lea_modrm(env
, s
, modrm
);
6891 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6893 gen_op_mov_TN_reg(ot
, 0, rm
);
6896 val
= cpu_ldub_code(env
, s
->pc
++);
6897 gen_op_movl_T1_im(val
);
6902 case 0x1a3: /* bt Gv, Ev */
6905 case 0x1ab: /* bts */
6908 case 0x1b3: /* btr */
6911 case 0x1bb: /* btc */
6915 modrm
= cpu_ldub_code(env
, s
->pc
++);
6916 reg
= ((modrm
>> 3) & 7) | rex_r
;
6917 mod
= (modrm
>> 6) & 3;
6918 rm
= (modrm
& 7) | REX_B(s
);
6919 gen_op_mov_TN_reg(MO_32
, 1, reg
);
6921 gen_lea_modrm(env
, s
, modrm
);
6922 /* specific case: we need to add a displacement */
6923 gen_exts(ot
, cpu_T
[1]);
6924 tcg_gen_sari_tl(cpu_tmp0
, cpu_T
[1], 3 + ot
);
6925 tcg_gen_shli_tl(cpu_tmp0
, cpu_tmp0
, ot
);
6926 tcg_gen_add_tl(cpu_A0
, cpu_A0
, cpu_tmp0
);
6927 gen_op_ld_v(s
, ot
, cpu_T
[0], cpu_A0
);
6929 gen_op_mov_TN_reg(ot
, 0, rm
);
6932 tcg_gen_andi_tl(cpu_T
[1], cpu_T
[1], (1 << (3 + ot
)) - 1);
6935 tcg_gen_shr_tl(cpu_cc_src
, cpu_T
[0], cpu_T
[1]);
6936 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6939 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6940 tcg_gen_movi_tl(cpu_tmp0
, 1);
6941 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6942 tcg_gen_or_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6945 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6946 tcg_gen_movi_tl(cpu_tmp0
, 1);
6947 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6948 tcg_gen_not_tl(cpu_tmp0
, cpu_tmp0
);
6949 tcg_gen_and_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6953 tcg_gen_shr_tl(cpu_tmp4
, cpu_T
[0], cpu_T
[1]);
6954 tcg_gen_movi_tl(cpu_tmp0
, 1);
6955 tcg_gen_shl_tl(cpu_tmp0
, cpu_tmp0
, cpu_T
[1]);
6956 tcg_gen_xor_tl(cpu_T
[0], cpu_T
[0], cpu_tmp0
);
6959 set_cc_op(s
, CC_OP_SARB
+ ot
);
6962 gen_op_st_v(s
, ot
, cpu_T
[0], cpu_A0
);
6964 gen_op_mov_reg_T0(ot
, rm
);
6966 tcg_gen_mov_tl(cpu_cc_src
, cpu_tmp4
);
6967 tcg_gen_movi_tl(cpu_cc_dst
, 0);
6970 case 0x1bc: /* bsf / tzcnt */
6971 case 0x1bd: /* bsr / lzcnt */
6973 modrm
= cpu_ldub_code(env
, s
->pc
++);
6974 reg
= ((modrm
>> 3) & 7) | rex_r
;
6975 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
6976 gen_extu(ot
, cpu_T
[0]);
6978 /* Note that lzcnt and tzcnt are in different extensions. */
6979 if ((prefixes
& PREFIX_REPZ
)
6981 ? s
->cpuid_ext3_features
& CPUID_EXT3_ABM
6982 : s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_BMI1
)) {
6984 tcg_gen_mov_tl(cpu_cc_src
, cpu_T
[0]);
6986 /* For lzcnt, reduce the target_ulong result by the
6987 number of zeros that we expect to find at the top. */
6988 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
6989 tcg_gen_subi_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- size
);
6991 /* For tzcnt, a zero input must return the operand size:
6992 force all bits outside the operand size to 1. */
6993 target_ulong mask
= (target_ulong
)-2 << (size
- 1);
6994 tcg_gen_ori_tl(cpu_T
[0], cpu_T
[0], mask
);
6995 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
6997 /* For lzcnt/tzcnt, C and Z bits are defined and are
6998 related to the result. */
6999 gen_op_update1_cc();
7000 set_cc_op(s
, CC_OP_BMILGB
+ ot
);
7002 /* For bsr/bsf, only the Z bit is defined and it is related
7003 to the input and not the result. */
7004 tcg_gen_mov_tl(cpu_cc_dst
, cpu_T
[0]);
7005 set_cc_op(s
, CC_OP_LOGICB
+ ot
);
7007 /* For bsr, return the bit index of the first 1 bit,
7008 not the count of leading zeros. */
7009 gen_helper_clz(cpu_T
[0], cpu_T
[0]);
7010 tcg_gen_xori_tl(cpu_T
[0], cpu_T
[0], TARGET_LONG_BITS
- 1);
7012 gen_helper_ctz(cpu_T
[0], cpu_T
[0]);
7014 /* ??? The manual says that the output is undefined when the
7015 input is zero, but real hardware leaves it unchanged, and
7016 real programs appear to depend on that. */
7017 tcg_gen_movi_tl(cpu_tmp0
, 0);
7018 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_T
[0], cpu_cc_dst
, cpu_tmp0
,
7019 cpu_regs
[reg
], cpu_T
[0]);
7021 gen_op_mov_reg_T0(ot
, reg
);
7023 /************************/
7025 case 0x27: /* daa */
7028 gen_update_cc_op(s
);
7029 gen_helper_daa(cpu_env
);
7030 set_cc_op(s
, CC_OP_EFLAGS
);
7032 case 0x2f: /* das */
7035 gen_update_cc_op(s
);
7036 gen_helper_das(cpu_env
);
7037 set_cc_op(s
, CC_OP_EFLAGS
);
7039 case 0x37: /* aaa */
7042 gen_update_cc_op(s
);
7043 gen_helper_aaa(cpu_env
);
7044 set_cc_op(s
, CC_OP_EFLAGS
);
7046 case 0x3f: /* aas */
7049 gen_update_cc_op(s
);
7050 gen_helper_aas(cpu_env
);
7051 set_cc_op(s
, CC_OP_EFLAGS
);
7053 case 0xd4: /* aam */
7056 val
= cpu_ldub_code(env
, s
->pc
++);
7058 gen_exception(s
, EXCP00_DIVZ
, pc_start
- s
->cs_base
);
7060 gen_helper_aam(cpu_env
, tcg_const_i32(val
));
7061 set_cc_op(s
, CC_OP_LOGICB
);
7064 case 0xd5: /* aad */
7067 val
= cpu_ldub_code(env
, s
->pc
++);
7068 gen_helper_aad(cpu_env
, tcg_const_i32(val
));
7069 set_cc_op(s
, CC_OP_LOGICB
);
7071 /************************/
7073 case 0x90: /* nop */
7074 /* XXX: correct lock test for all insn */
7075 if (prefixes
& PREFIX_LOCK
) {
7078 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
7080 goto do_xchg_reg_eax
;
7082 if (prefixes
& PREFIX_REPZ
) {
7083 gen_update_cc_op(s
);
7084 gen_jmp_im(pc_start
- s
->cs_base
);
7085 gen_helper_pause(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7086 s
->is_jmp
= DISAS_TB_JUMP
;
7089 case 0x9b: /* fwait */
7090 if ((s
->flags
& (HF_MP_MASK
| HF_TS_MASK
)) ==
7091 (HF_MP_MASK
| HF_TS_MASK
)) {
7092 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7094 gen_update_cc_op(s
);
7095 gen_jmp_im(pc_start
- s
->cs_base
);
7096 gen_helper_fwait(cpu_env
);
7099 case 0xcc: /* int3 */
7100 gen_interrupt(s
, EXCP03_INT3
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
7102 case 0xcd: /* int N */
7103 val
= cpu_ldub_code(env
, s
->pc
++);
7104 if (s
->vm86
&& s
->iopl
!= 3) {
7105 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7107 gen_interrupt(s
, val
, pc_start
- s
->cs_base
, s
->pc
- s
->cs_base
);
7110 case 0xce: /* into */
7113 gen_update_cc_op(s
);
7114 gen_jmp_im(pc_start
- s
->cs_base
);
7115 gen_helper_into(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7118 case 0xf1: /* icebp (undocumented, exits to external debugger) */
7119 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_ICEBP
);
7121 gen_debug(s
, pc_start
- s
->cs_base
);
7125 qemu_set_log(CPU_LOG_INT
| CPU_LOG_TB_IN_ASM
);
7129 case 0xfa: /* cli */
7131 if (s
->cpl
<= s
->iopl
) {
7132 gen_helper_cli(cpu_env
);
7134 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7138 gen_helper_cli(cpu_env
);
7140 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7144 case 0xfb: /* sti */
7146 if (s
->cpl
<= s
->iopl
) {
7148 gen_helper_sti(cpu_env
);
7149 /* interruptions are enabled only the first insn after sti */
7150 /* If several instructions disable interrupts, only the
7152 if (!(s
->tb
->flags
& HF_INHIBIT_IRQ_MASK
))
7153 gen_helper_set_inhibit_irq(cpu_env
);
7154 /* give a chance to handle pending irqs */
7155 gen_jmp_im(s
->pc
- s
->cs_base
);
7158 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7164 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7168 case 0x62: /* bound */
7171 ot
= dflag
? MO_32
: MO_16
;
7172 modrm
= cpu_ldub_code(env
, s
->pc
++);
7173 reg
= (modrm
>> 3) & 7;
7174 mod
= (modrm
>> 6) & 3;
7177 gen_op_mov_TN_reg(ot
, 0, reg
);
7178 gen_lea_modrm(env
, s
, modrm
);
7179 gen_jmp_im(pc_start
- s
->cs_base
);
7180 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7182 gen_helper_boundw(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
7184 gen_helper_boundl(cpu_env
, cpu_A0
, cpu_tmp2_i32
);
7187 case 0x1c8 ... 0x1cf: /* bswap reg */
7188 reg
= (b
& 7) | REX_B(s
);
7189 #ifdef TARGET_X86_64
7191 gen_op_mov_TN_reg(MO_64
, 0, reg
);
7192 tcg_gen_bswap64_i64(cpu_T
[0], cpu_T
[0]);
7193 gen_op_mov_reg_T0(MO_64
, reg
);
7197 gen_op_mov_TN_reg(MO_32
, 0, reg
);
7198 tcg_gen_ext32u_tl(cpu_T
[0], cpu_T
[0]);
7199 tcg_gen_bswap32_tl(cpu_T
[0], cpu_T
[0]);
7200 gen_op_mov_reg_T0(MO_32
, reg
);
7203 case 0xd6: /* salc */
7206 gen_compute_eflags_c(s
, cpu_T
[0]);
7207 tcg_gen_neg_tl(cpu_T
[0], cpu_T
[0]);
7208 gen_op_mov_reg_T0(MO_8
, R_EAX
);
7210 case 0xe0: /* loopnz */
7211 case 0xe1: /* loopz */
7212 case 0xe2: /* loop */
7213 case 0xe3: /* jecxz */
7217 tval
= (int8_t)insn_get(env
, s
, MO_8
);
7218 next_eip
= s
->pc
- s
->cs_base
;
7223 l1
= gen_new_label();
7224 l2
= gen_new_label();
7225 l3
= gen_new_label();
7228 case 0: /* loopnz */
7230 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7231 gen_op_jz_ecx(s
->aflag
, l3
);
7232 gen_jcc1(s
, (JCC_Z
<< 1) | (b
^ 1), l1
);
7235 gen_op_add_reg_im(s
->aflag
, R_ECX
, -1);
7236 gen_op_jnz_ecx(s
->aflag
, l1
);
7240 gen_op_jz_ecx(s
->aflag
, l1
);
7245 gen_jmp_im(next_eip
);
7254 case 0x130: /* wrmsr */
7255 case 0x132: /* rdmsr */
7257 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7259 gen_update_cc_op(s
);
7260 gen_jmp_im(pc_start
- s
->cs_base
);
7262 gen_helper_rdmsr(cpu_env
);
7264 gen_helper_wrmsr(cpu_env
);
7268 case 0x131: /* rdtsc */
7269 gen_update_cc_op(s
);
7270 gen_jmp_im(pc_start
- s
->cs_base
);
7273 gen_helper_rdtsc(cpu_env
);
7276 gen_jmp(s
, s
->pc
- s
->cs_base
);
7279 case 0x133: /* rdpmc */
7280 gen_update_cc_op(s
);
7281 gen_jmp_im(pc_start
- s
->cs_base
);
7282 gen_helper_rdpmc(cpu_env
);
7284 case 0x134: /* sysenter */
7285 /* For Intel SYSENTER is valid on 64-bit */
7286 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7289 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7291 gen_update_cc_op(s
);
7292 gen_jmp_im(pc_start
- s
->cs_base
);
7293 gen_helper_sysenter(cpu_env
);
7297 case 0x135: /* sysexit */
7298 /* For Intel SYSEXIT is valid on 64-bit */
7299 if (CODE64(s
) && env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
)
7302 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7304 gen_update_cc_op(s
);
7305 gen_jmp_im(pc_start
- s
->cs_base
);
7306 gen_helper_sysexit(cpu_env
, tcg_const_i32(dflag
));
7310 #ifdef TARGET_X86_64
7311 case 0x105: /* syscall */
7312 /* XXX: is it usable in real mode ? */
7313 gen_update_cc_op(s
);
7314 gen_jmp_im(pc_start
- s
->cs_base
);
7315 gen_helper_syscall(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7318 case 0x107: /* sysret */
7320 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7322 gen_update_cc_op(s
);
7323 gen_jmp_im(pc_start
- s
->cs_base
);
7324 gen_helper_sysret(cpu_env
, tcg_const_i32(s
->dflag
));
7325 /* condition codes are modified only in long mode */
7327 set_cc_op(s
, CC_OP_EFLAGS
);
7333 case 0x1a2: /* cpuid */
7334 gen_update_cc_op(s
);
7335 gen_jmp_im(pc_start
- s
->cs_base
);
7336 gen_helper_cpuid(cpu_env
);
7338 case 0xf4: /* hlt */
7340 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7342 gen_update_cc_op(s
);
7343 gen_jmp_im(pc_start
- s
->cs_base
);
7344 gen_helper_hlt(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7345 s
->is_jmp
= DISAS_TB_JUMP
;
7349 modrm
= cpu_ldub_code(env
, s
->pc
++);
7350 mod
= (modrm
>> 6) & 3;
7351 op
= (modrm
>> 3) & 7;
7354 if (!s
->pe
|| s
->vm86
)
7356 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_READ
);
7357 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,ldt
.selector
));
7361 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7364 if (!s
->pe
|| s
->vm86
)
7367 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7369 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_LDTR_WRITE
);
7370 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7371 gen_jmp_im(pc_start
- s
->cs_base
);
7372 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7373 gen_helper_lldt(cpu_env
, cpu_tmp2_i32
);
7377 if (!s
->pe
|| s
->vm86
)
7379 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_READ
);
7380 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,tr
.selector
));
7384 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 1);
7387 if (!s
->pe
|| s
->vm86
)
7390 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7392 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_TR_WRITE
);
7393 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7394 gen_jmp_im(pc_start
- s
->cs_base
);
7395 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7396 gen_helper_ltr(cpu_env
, cpu_tmp2_i32
);
7401 if (!s
->pe
|| s
->vm86
)
7403 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7404 gen_update_cc_op(s
);
7406 gen_helper_verr(cpu_env
, cpu_T
[0]);
7408 gen_helper_verw(cpu_env
, cpu_T
[0]);
7410 set_cc_op(s
, CC_OP_EFLAGS
);
7417 modrm
= cpu_ldub_code(env
, s
->pc
++);
7418 mod
= (modrm
>> 6) & 3;
7419 op
= (modrm
>> 3) & 7;
7425 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_GDTR_READ
);
7426 gen_lea_modrm(env
, s
, modrm
);
7427 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.limit
));
7428 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7429 gen_add_A0_im(s
, 2);
7430 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, gdt
.base
));
7432 gen_op_andl_T0_im(0xffffff);
7433 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7438 case 0: /* monitor */
7439 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7442 gen_update_cc_op(s
);
7443 gen_jmp_im(pc_start
- s
->cs_base
);
7444 #ifdef TARGET_X86_64
7445 if (s
->aflag
== 2) {
7446 gen_op_movq_A0_reg(R_EAX
);
7450 gen_op_movl_A0_reg(R_EAX
);
7452 gen_op_andl_A0_ffff();
7454 gen_add_A0_ds_seg(s
);
7455 gen_helper_monitor(cpu_env
, cpu_A0
);
7458 if (!(s
->cpuid_ext_features
& CPUID_EXT_MONITOR
) ||
7461 gen_update_cc_op(s
);
7462 gen_jmp_im(pc_start
- s
->cs_base
);
7463 gen_helper_mwait(cpu_env
, tcg_const_i32(s
->pc
- pc_start
));
7467 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7471 gen_helper_clac(cpu_env
);
7472 gen_jmp_im(s
->pc
- s
->cs_base
);
7476 if (!(s
->cpuid_7_0_ebx_features
& CPUID_7_0_EBX_SMAP
) ||
7480 gen_helper_stac(cpu_env
);
7481 gen_jmp_im(s
->pc
- s
->cs_base
);
7488 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_IDTR_READ
);
7489 gen_lea_modrm(env
, s
, modrm
);
7490 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.limit
));
7491 gen_op_st_v(s
, MO_16
, cpu_T
[0], cpu_A0
);
7492 gen_add_A0_im(s
, 2);
7493 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, idt
.base
));
7495 gen_op_andl_T0_im(0xffffff);
7496 gen_op_st_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7502 gen_update_cc_op(s
);
7503 gen_jmp_im(pc_start
- s
->cs_base
);
7506 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7509 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7512 gen_helper_vmrun(cpu_env
, tcg_const_i32(s
->aflag
),
7513 tcg_const_i32(s
->pc
- pc_start
));
7515 s
->is_jmp
= DISAS_TB_JUMP
;
7518 case 1: /* VMMCALL */
7519 if (!(s
->flags
& HF_SVME_MASK
))
7521 gen_helper_vmmcall(cpu_env
);
7523 case 2: /* VMLOAD */
7524 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7527 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7530 gen_helper_vmload(cpu_env
, tcg_const_i32(s
->aflag
));
7533 case 3: /* VMSAVE */
7534 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7537 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7540 gen_helper_vmsave(cpu_env
, tcg_const_i32(s
->aflag
));
7544 if ((!(s
->flags
& HF_SVME_MASK
) &&
7545 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7549 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7552 gen_helper_stgi(cpu_env
);
7556 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7559 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7562 gen_helper_clgi(cpu_env
);
7565 case 6: /* SKINIT */
7566 if ((!(s
->flags
& HF_SVME_MASK
) &&
7567 !(s
->cpuid_ext3_features
& CPUID_EXT3_SKINIT
)) ||
7570 gen_helper_skinit(cpu_env
);
7572 case 7: /* INVLPGA */
7573 if (!(s
->flags
& HF_SVME_MASK
) || !s
->pe
)
7576 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7579 gen_helper_invlpga(cpu_env
, tcg_const_i32(s
->aflag
));
7585 } else if (s
->cpl
!= 0) {
7586 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7588 gen_svm_check_intercept(s
, pc_start
,
7589 op
==2 ? SVM_EXIT_GDTR_WRITE
: SVM_EXIT_IDTR_WRITE
);
7590 gen_lea_modrm(env
, s
, modrm
);
7591 gen_op_ld_v(s
, MO_16
, cpu_T
[1], cpu_A0
);
7592 gen_add_A0_im(s
, 2);
7593 gen_op_ld_v(s
, CODE64(s
) + MO_32
, cpu_T
[0], cpu_A0
);
7595 gen_op_andl_T0_im(0xffffff);
7597 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,gdt
.base
));
7598 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,gdt
.limit
));
7600 tcg_gen_st_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,idt
.base
));
7601 tcg_gen_st32_tl(cpu_T
[1], cpu_env
, offsetof(CPUX86State
,idt
.limit
));
7606 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_CR0
);
7607 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7608 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]) + 4);
7610 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,cr
[0]));
7612 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 1);
7616 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7618 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7619 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7620 gen_helper_lmsw(cpu_env
, cpu_T
[0]);
7621 gen_jmp_im(s
->pc
- s
->cs_base
);
7626 if (mod
!= 3) { /* invlpg */
7628 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7630 gen_update_cc_op(s
);
7631 gen_jmp_im(pc_start
- s
->cs_base
);
7632 gen_lea_modrm(env
, s
, modrm
);
7633 gen_helper_invlpg(cpu_env
, cpu_A0
);
7634 gen_jmp_im(s
->pc
- s
->cs_base
);
7639 case 0: /* swapgs */
7640 #ifdef TARGET_X86_64
7643 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7645 tcg_gen_ld_tl(cpu_T
[0], cpu_env
,
7646 offsetof(CPUX86State
,segs
[R_GS
].base
));
7647 tcg_gen_ld_tl(cpu_T
[1], cpu_env
,
7648 offsetof(CPUX86State
,kernelgsbase
));
7649 tcg_gen_st_tl(cpu_T
[1], cpu_env
,
7650 offsetof(CPUX86State
,segs
[R_GS
].base
));
7651 tcg_gen_st_tl(cpu_T
[0], cpu_env
,
7652 offsetof(CPUX86State
,kernelgsbase
));
7660 case 1: /* rdtscp */
7661 if (!(s
->cpuid_ext2_features
& CPUID_EXT2_RDTSCP
))
7663 gen_update_cc_op(s
);
7664 gen_jmp_im(pc_start
- s
->cs_base
);
7667 gen_helper_rdtscp(cpu_env
);
7670 gen_jmp(s
, s
->pc
- s
->cs_base
);
7682 case 0x108: /* invd */
7683 case 0x109: /* wbinvd */
7685 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7687 gen_svm_check_intercept(s
, pc_start
, (b
& 2) ? SVM_EXIT_INVD
: SVM_EXIT_WBINVD
);
7691 case 0x63: /* arpl or movslS (x86_64) */
7692 #ifdef TARGET_X86_64
7695 /* d_ot is the size of destination */
7696 d_ot
= dflag
+ MO_16
;
7698 modrm
= cpu_ldub_code(env
, s
->pc
++);
7699 reg
= ((modrm
>> 3) & 7) | rex_r
;
7700 mod
= (modrm
>> 6) & 3;
7701 rm
= (modrm
& 7) | REX_B(s
);
7704 gen_op_mov_TN_reg(MO_32
, 0, rm
);
7706 if (d_ot
== MO_64
) {
7707 tcg_gen_ext32s_tl(cpu_T
[0], cpu_T
[0]);
7709 gen_op_mov_reg_T0(d_ot
, reg
);
7711 gen_lea_modrm(env
, s
, modrm
);
7712 gen_op_ld_v(s
, MO_32
| MO_SIGN
, cpu_T
[0], cpu_A0
);
7713 gen_op_mov_reg_T0(d_ot
, reg
);
7719 TCGv t0
, t1
, t2
, a0
;
7721 if (!s
->pe
|| s
->vm86
)
7723 t0
= tcg_temp_local_new();
7724 t1
= tcg_temp_local_new();
7725 t2
= tcg_temp_local_new();
7727 modrm
= cpu_ldub_code(env
, s
->pc
++);
7728 reg
= (modrm
>> 3) & 7;
7729 mod
= (modrm
>> 6) & 3;
7732 gen_lea_modrm(env
, s
, modrm
);
7733 gen_op_ld_v(s
, ot
, t0
, cpu_A0
);
7734 a0
= tcg_temp_local_new();
7735 tcg_gen_mov_tl(a0
, cpu_A0
);
7737 gen_op_mov_v_reg(ot
, t0
, rm
);
7740 gen_op_mov_v_reg(ot
, t1
, reg
);
7741 tcg_gen_andi_tl(cpu_tmp0
, t0
, 3);
7742 tcg_gen_andi_tl(t1
, t1
, 3);
7743 tcg_gen_movi_tl(t2
, 0);
7744 label1
= gen_new_label();
7745 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_tmp0
, t1
, label1
);
7746 tcg_gen_andi_tl(t0
, t0
, ~3);
7747 tcg_gen_or_tl(t0
, t0
, t1
);
7748 tcg_gen_movi_tl(t2
, CC_Z
);
7749 gen_set_label(label1
);
7751 gen_op_st_v(s
, ot
, t0
, a0
);
7754 gen_op_mov_reg_v(ot
, rm
, t0
);
7756 gen_compute_eflags(s
);
7757 tcg_gen_andi_tl(cpu_cc_src
, cpu_cc_src
, ~CC_Z
);
7758 tcg_gen_or_tl(cpu_cc_src
, cpu_cc_src
, t2
);
7764 case 0x102: /* lar */
7765 case 0x103: /* lsl */
7769 if (!s
->pe
|| s
->vm86
)
7771 ot
= dflag
? MO_32
: MO_16
;
7772 modrm
= cpu_ldub_code(env
, s
->pc
++);
7773 reg
= ((modrm
>> 3) & 7) | rex_r
;
7774 gen_ldst_modrm(env
, s
, modrm
, MO_16
, OR_TMP0
, 0);
7775 t0
= tcg_temp_local_new();
7776 gen_update_cc_op(s
);
7778 gen_helper_lar(t0
, cpu_env
, cpu_T
[0]);
7780 gen_helper_lsl(t0
, cpu_env
, cpu_T
[0]);
7782 tcg_gen_andi_tl(cpu_tmp0
, cpu_cc_src
, CC_Z
);
7783 label1
= gen_new_label();
7784 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_tmp0
, 0, label1
);
7785 gen_op_mov_reg_v(ot
, reg
, t0
);
7786 gen_set_label(label1
);
7787 set_cc_op(s
, CC_OP_EFLAGS
);
7792 modrm
= cpu_ldub_code(env
, s
->pc
++);
7793 mod
= (modrm
>> 6) & 3;
7794 op
= (modrm
>> 3) & 7;
7796 case 0: /* prefetchnta */
7797 case 1: /* prefetchnt0 */
7798 case 2: /* prefetchnt0 */
7799 case 3: /* prefetchnt0 */
7802 gen_lea_modrm(env
, s
, modrm
);
7803 /* nothing more to do */
7805 default: /* nop (multi byte) */
7806 gen_nop_modrm(env
, s
, modrm
);
7810 case 0x119 ... 0x11f: /* nop (multi byte) */
7811 modrm
= cpu_ldub_code(env
, s
->pc
++);
7812 gen_nop_modrm(env
, s
, modrm
);
7814 case 0x120: /* mov reg, crN */
7815 case 0x122: /* mov crN, reg */
7817 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7819 modrm
= cpu_ldub_code(env
, s
->pc
++);
7820 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7821 * AMD documentation (24594.pdf) and testing of
7822 * intel 386 and 486 processors all show that the mod bits
7823 * are assumed to be 1's, regardless of actual values.
7825 rm
= (modrm
& 7) | REX_B(s
);
7826 reg
= ((modrm
>> 3) & 7) | rex_r
;
7831 if ((prefixes
& PREFIX_LOCK
) && (reg
== 0) &&
7832 (s
->cpuid_ext3_features
& CPUID_EXT3_CR8LEG
)) {
7841 gen_update_cc_op(s
);
7842 gen_jmp_im(pc_start
- s
->cs_base
);
7844 gen_op_mov_TN_reg(ot
, 0, rm
);
7845 gen_helper_write_crN(cpu_env
, tcg_const_i32(reg
),
7847 gen_jmp_im(s
->pc
- s
->cs_base
);
7850 gen_helper_read_crN(cpu_T
[0], cpu_env
, tcg_const_i32(reg
));
7851 gen_op_mov_reg_T0(ot
, rm
);
7859 case 0x121: /* mov reg, drN */
7860 case 0x123: /* mov drN, reg */
7862 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7864 modrm
= cpu_ldub_code(env
, s
->pc
++);
7865 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7866 * AMD documentation (24594.pdf) and testing of
7867 * intel 386 and 486 processors all show that the mod bits
7868 * are assumed to be 1's, regardless of actual values.
7870 rm
= (modrm
& 7) | REX_B(s
);
7871 reg
= ((modrm
>> 3) & 7) | rex_r
;
7876 /* XXX: do it dynamically with CR4.DE bit */
7877 if (reg
== 4 || reg
== 5 || reg
>= 8)
7880 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_DR0
+ reg
);
7881 gen_op_mov_TN_reg(ot
, 0, rm
);
7882 gen_helper_movl_drN_T0(cpu_env
, tcg_const_i32(reg
), cpu_T
[0]);
7883 gen_jmp_im(s
->pc
- s
->cs_base
);
7886 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_READ_DR0
+ reg
);
7887 tcg_gen_ld_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
,dr
[reg
]));
7888 gen_op_mov_reg_T0(ot
, rm
);
7892 case 0x106: /* clts */
7894 gen_exception(s
, EXCP0D_GPF
, pc_start
- s
->cs_base
);
7896 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_WRITE_CR0
);
7897 gen_helper_clts(cpu_env
);
7898 /* abort block because static cpu state changed */
7899 gen_jmp_im(s
->pc
- s
->cs_base
);
7903 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7904 case 0x1c3: /* MOVNTI reg, mem */
7905 if (!(s
->cpuid_features
& CPUID_SSE2
))
7907 ot
= s
->dflag
== 2 ? MO_64
: MO_32
;
7908 modrm
= cpu_ldub_code(env
, s
->pc
++);
7909 mod
= (modrm
>> 6) & 3;
7912 reg
= ((modrm
>> 3) & 7) | rex_r
;
7913 /* generate a generic store */
7914 gen_ldst_modrm(env
, s
, modrm
, ot
, reg
, 1);
7917 modrm
= cpu_ldub_code(env
, s
->pc
++);
7918 mod
= (modrm
>> 6) & 3;
7919 op
= (modrm
>> 3) & 7;
7921 case 0: /* fxsave */
7922 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7923 (s
->prefix
& PREFIX_LOCK
))
7925 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7926 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7929 gen_lea_modrm(env
, s
, modrm
);
7930 gen_update_cc_op(s
);
7931 gen_jmp_im(pc_start
- s
->cs_base
);
7932 gen_helper_fxsave(cpu_env
, cpu_A0
, tcg_const_i32((s
->dflag
== 2)));
7934 case 1: /* fxrstor */
7935 if (mod
== 3 || !(s
->cpuid_features
& CPUID_FXSR
) ||
7936 (s
->prefix
& PREFIX_LOCK
))
7938 if ((s
->flags
& HF_EM_MASK
) || (s
->flags
& HF_TS_MASK
)) {
7939 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7942 gen_lea_modrm(env
, s
, modrm
);
7943 gen_update_cc_op(s
);
7944 gen_jmp_im(pc_start
- s
->cs_base
);
7945 gen_helper_fxrstor(cpu_env
, cpu_A0
,
7946 tcg_const_i32((s
->dflag
== 2)));
7948 case 2: /* ldmxcsr */
7949 case 3: /* stmxcsr */
7950 if (s
->flags
& HF_TS_MASK
) {
7951 gen_exception(s
, EXCP07_PREX
, pc_start
- s
->cs_base
);
7954 if ((s
->flags
& HF_EM_MASK
) || !(s
->flags
& HF_OSFXSR_MASK
) ||
7957 gen_lea_modrm(env
, s
, modrm
);
7959 gen_op_ld_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
7960 tcg_gen_trunc_tl_i32(cpu_tmp2_i32
, cpu_T
[0]);
7961 gen_helper_ldmxcsr(cpu_env
, cpu_tmp2_i32
);
7963 tcg_gen_ld32u_tl(cpu_T
[0], cpu_env
, offsetof(CPUX86State
, mxcsr
));
7964 gen_op_st_v(s
, MO_32
, cpu_T
[0], cpu_A0
);
7967 case 5: /* lfence */
7968 case 6: /* mfence */
7969 if ((modrm
& 0xc7) != 0xc0 || !(s
->cpuid_features
& CPUID_SSE2
))
7972 case 7: /* sfence / clflush */
7973 if ((modrm
& 0xc7) == 0xc0) {
7975 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7976 if (!(s
->cpuid_features
& CPUID_SSE
))
7980 if (!(s
->cpuid_features
& CPUID_CLFLUSH
))
7982 gen_lea_modrm(env
, s
, modrm
);
7989 case 0x10d: /* 3DNow! prefetch(w) */
7990 modrm
= cpu_ldub_code(env
, s
->pc
++);
7991 mod
= (modrm
>> 6) & 3;
7994 gen_lea_modrm(env
, s
, modrm
);
7995 /* ignore for now */
7997 case 0x1aa: /* rsm */
7998 gen_svm_check_intercept(s
, pc_start
, SVM_EXIT_RSM
);
7999 if (!(s
->flags
& HF_SMM_MASK
))
8001 gen_update_cc_op(s
);
8002 gen_jmp_im(s
->pc
- s
->cs_base
);
8003 gen_helper_rsm(cpu_env
);
8006 case 0x1b8: /* SSE4.2 popcnt */
8007 if ((prefixes
& (PREFIX_REPZ
| PREFIX_LOCK
| PREFIX_REPNZ
)) !=
8010 if (!(s
->cpuid_ext_features
& CPUID_EXT_POPCNT
))
8013 modrm
= cpu_ldub_code(env
, s
->pc
++);
8014 reg
= ((modrm
>> 3) & 7) | rex_r
;
8016 if (s
->prefix
& PREFIX_DATA
)
8018 else if (s
->dflag
!= 2)
8023 gen_ldst_modrm(env
, s
, modrm
, ot
, OR_TMP0
, 0);
8024 gen_helper_popcnt(cpu_T
[0], cpu_env
, cpu_T
[0], tcg_const_i32(ot
));
8025 gen_op_mov_reg_T0(ot
, reg
);
8027 set_cc_op(s
, CC_OP_EFLAGS
);
8029 case 0x10e ... 0x10f:
8030 /* 3DNow! instructions, ignore prefixes */
8031 s
->prefix
&= ~(PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
);
8032 case 0x110 ... 0x117:
8033 case 0x128 ... 0x12f:
8034 case 0x138 ... 0x13a:
8035 case 0x150 ... 0x179:
8036 case 0x17c ... 0x17f:
8038 case 0x1c4 ... 0x1c6:
8039 case 0x1d0 ... 0x1fe:
8040 gen_sse(env
, s
, b
, pc_start
, rex_r
);
8045 /* lock generation */
8046 if (s
->prefix
& PREFIX_LOCK
)
8047 gen_helper_unlock();
8050 if (s
->prefix
& PREFIX_LOCK
)
8051 gen_helper_unlock();
8052 /* XXX: ensure that no lock was generated */
8053 gen_exception(s
, EXCP06_ILLOP
, pc_start
- s
->cs_base
);
8057 void optimize_flags_init(void)
8059 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
8060 cpu_cc_op
= tcg_global_mem_new_i32(TCG_AREG0
,
8061 offsetof(CPUX86State
, cc_op
), "cc_op");
8062 cpu_cc_dst
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_dst
),
8064 cpu_cc_src
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src
),
8066 cpu_cc_src2
= tcg_global_mem_new(TCG_AREG0
, offsetof(CPUX86State
, cc_src2
),
8069 #ifdef TARGET_X86_64
8070 cpu_regs
[R_EAX
] = tcg_global_mem_new_i64(TCG_AREG0
,
8071 offsetof(CPUX86State
, regs
[R_EAX
]), "rax");
8072 cpu_regs
[R_ECX
] = tcg_global_mem_new_i64(TCG_AREG0
,
8073 offsetof(CPUX86State
, regs
[R_ECX
]), "rcx");
8074 cpu_regs
[R_EDX
] = tcg_global_mem_new_i64(TCG_AREG0
,
8075 offsetof(CPUX86State
, regs
[R_EDX
]), "rdx");
8076 cpu_regs
[R_EBX
] = tcg_global_mem_new_i64(TCG_AREG0
,
8077 offsetof(CPUX86State
, regs
[R_EBX
]), "rbx");
8078 cpu_regs
[R_ESP
] = tcg_global_mem_new_i64(TCG_AREG0
,
8079 offsetof(CPUX86State
, regs
[R_ESP
]), "rsp");
8080 cpu_regs
[R_EBP
] = tcg_global_mem_new_i64(TCG_AREG0
,
8081 offsetof(CPUX86State
, regs
[R_EBP
]), "rbp");
8082 cpu_regs
[R_ESI
] = tcg_global_mem_new_i64(TCG_AREG0
,
8083 offsetof(CPUX86State
, regs
[R_ESI
]), "rsi");
8084 cpu_regs
[R_EDI
] = tcg_global_mem_new_i64(TCG_AREG0
,
8085 offsetof(CPUX86State
, regs
[R_EDI
]), "rdi");
8086 cpu_regs
[8] = tcg_global_mem_new_i64(TCG_AREG0
,
8087 offsetof(CPUX86State
, regs
[8]), "r8");
8088 cpu_regs
[9] = tcg_global_mem_new_i64(TCG_AREG0
,
8089 offsetof(CPUX86State
, regs
[9]), "r9");
8090 cpu_regs
[10] = tcg_global_mem_new_i64(TCG_AREG0
,
8091 offsetof(CPUX86State
, regs
[10]), "r10");
8092 cpu_regs
[11] = tcg_global_mem_new_i64(TCG_AREG0
,
8093 offsetof(CPUX86State
, regs
[11]), "r11");
8094 cpu_regs
[12] = tcg_global_mem_new_i64(TCG_AREG0
,
8095 offsetof(CPUX86State
, regs
[12]), "r12");
8096 cpu_regs
[13] = tcg_global_mem_new_i64(TCG_AREG0
,
8097 offsetof(CPUX86State
, regs
[13]), "r13");
8098 cpu_regs
[14] = tcg_global_mem_new_i64(TCG_AREG0
,
8099 offsetof(CPUX86State
, regs
[14]), "r14");
8100 cpu_regs
[15] = tcg_global_mem_new_i64(TCG_AREG0
,
8101 offsetof(CPUX86State
, regs
[15]), "r15");
8103 cpu_regs
[R_EAX
] = tcg_global_mem_new_i32(TCG_AREG0
,
8104 offsetof(CPUX86State
, regs
[R_EAX
]), "eax");
8105 cpu_regs
[R_ECX
] = tcg_global_mem_new_i32(TCG_AREG0
,
8106 offsetof(CPUX86State
, regs
[R_ECX
]), "ecx");
8107 cpu_regs
[R_EDX
] = tcg_global_mem_new_i32(TCG_AREG0
,
8108 offsetof(CPUX86State
, regs
[R_EDX
]), "edx");
8109 cpu_regs
[R_EBX
] = tcg_global_mem_new_i32(TCG_AREG0
,
8110 offsetof(CPUX86State
, regs
[R_EBX
]), "ebx");
8111 cpu_regs
[R_ESP
] = tcg_global_mem_new_i32(TCG_AREG0
,
8112 offsetof(CPUX86State
, regs
[R_ESP
]), "esp");
8113 cpu_regs
[R_EBP
] = tcg_global_mem_new_i32(TCG_AREG0
,
8114 offsetof(CPUX86State
, regs
[R_EBP
]), "ebp");
8115 cpu_regs
[R_ESI
] = tcg_global_mem_new_i32(TCG_AREG0
,
8116 offsetof(CPUX86State
, regs
[R_ESI
]), "esi");
8117 cpu_regs
[R_EDI
] = tcg_global_mem_new_i32(TCG_AREG0
,
8118 offsetof(CPUX86State
, regs
[R_EDI
]), "edi");
8122 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
8123 basic block 'tb'. If search_pc is TRUE, also generate PC
8124 information for each intermediate instruction. */
8125 static inline void gen_intermediate_code_internal(X86CPU
*cpu
,
8126 TranslationBlock
*tb
,
8129 CPUState
*cs
= CPU(cpu
);
8130 CPUX86State
*env
= &cpu
->env
;
8131 DisasContext dc1
, *dc
= &dc1
;
8132 target_ulong pc_ptr
;
8133 uint16_t *gen_opc_end
;
8137 target_ulong pc_start
;
8138 target_ulong cs_base
;
8142 /* generate intermediate code */
8144 cs_base
= tb
->cs_base
;
8147 dc
->pe
= (flags
>> HF_PE_SHIFT
) & 1;
8148 dc
->code32
= (flags
>> HF_CS32_SHIFT
) & 1;
8149 dc
->ss32
= (flags
>> HF_SS32_SHIFT
) & 1;
8150 dc
->addseg
= (flags
>> HF_ADDSEG_SHIFT
) & 1;
8152 dc
->vm86
= (flags
>> VM_SHIFT
) & 1;
8153 dc
->cpl
= (flags
>> HF_CPL_SHIFT
) & 3;
8154 dc
->iopl
= (flags
>> IOPL_SHIFT
) & 3;
8155 dc
->tf
= (flags
>> TF_SHIFT
) & 1;
8156 dc
->singlestep_enabled
= cs
->singlestep_enabled
;
8157 dc
->cc_op
= CC_OP_DYNAMIC
;
8158 dc
->cc_op_dirty
= false;
8159 dc
->cs_base
= cs_base
;
8161 dc
->popl_esp_hack
= 0;
8162 /* select memory access functions */
8164 if (flags
& HF_SOFTMMU_MASK
) {
8165 dc
->mem_index
= cpu_mmu_index(env
);
8167 dc
->cpuid_features
= env
->features
[FEAT_1_EDX
];
8168 dc
->cpuid_ext_features
= env
->features
[FEAT_1_ECX
];
8169 dc
->cpuid_ext2_features
= env
->features
[FEAT_8000_0001_EDX
];
8170 dc
->cpuid_ext3_features
= env
->features
[FEAT_8000_0001_ECX
];
8171 dc
->cpuid_7_0_ebx_features
= env
->features
[FEAT_7_0_EBX
];
8172 #ifdef TARGET_X86_64
8173 dc
->lma
= (flags
>> HF_LMA_SHIFT
) & 1;
8174 dc
->code64
= (flags
>> HF_CS64_SHIFT
) & 1;
8177 dc
->jmp_opt
= !(dc
->tf
|| cs
->singlestep_enabled
||
8178 (flags
& HF_INHIBIT_IRQ_MASK
)
8179 #ifndef CONFIG_SOFTMMU
8180 || (flags
& HF_SOFTMMU_MASK
)
8184 /* check addseg logic */
8185 if (!dc
->addseg
&& (dc
->vm86
|| !dc
->pe
|| !dc
->code32
))
8186 printf("ERROR addseg\n");
8189 cpu_T
[0] = tcg_temp_new();
8190 cpu_T
[1] = tcg_temp_new();
8191 cpu_A0
= tcg_temp_new();
8193 cpu_tmp0
= tcg_temp_new();
8194 cpu_tmp1_i64
= tcg_temp_new_i64();
8195 cpu_tmp2_i32
= tcg_temp_new_i32();
8196 cpu_tmp3_i32
= tcg_temp_new_i32();
8197 cpu_tmp4
= tcg_temp_new();
8198 cpu_ptr0
= tcg_temp_new_ptr();
8199 cpu_ptr1
= tcg_temp_new_ptr();
8200 cpu_cc_srcT
= tcg_temp_local_new();
8202 gen_opc_end
= tcg_ctx
.gen_opc_buf
+ OPC_MAX_SIZE
;
8204 dc
->is_jmp
= DISAS_NEXT
;
8208 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
8210 max_insns
= CF_COUNT_MASK
;
8214 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
8215 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
8216 if (bp
->pc
== pc_ptr
&&
8217 !((bp
->flags
& BP_CPU
) && (tb
->flags
& HF_RF_MASK
))) {
8218 gen_debug(dc
, pc_ptr
- dc
->cs_base
);
8224 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8228 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8230 tcg_ctx
.gen_opc_pc
[lj
] = pc_ptr
;
8231 gen_opc_cc_op
[lj
] = dc
->cc_op
;
8232 tcg_ctx
.gen_opc_instr_start
[lj
] = 1;
8233 tcg_ctx
.gen_opc_icount
[lj
] = num_insns
;
8235 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
))
8238 pc_ptr
= disas_insn(env
, dc
, pc_ptr
);
8240 /* stop translation if indicated */
8243 /* if single step mode, we generate only one instruction and
8244 generate an exception */
8245 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
8246 the flag and abort the translation to give the irqs a
8247 change to be happen */
8248 if (dc
->tf
|| dc
->singlestep_enabled
||
8249 (flags
& HF_INHIBIT_IRQ_MASK
)) {
8250 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8254 /* if too long translation, stop generation too */
8255 if (tcg_ctx
.gen_opc_ptr
>= gen_opc_end
||
8256 (pc_ptr
- pc_start
) >= (TARGET_PAGE_SIZE
- 32) ||
8257 num_insns
>= max_insns
) {
8258 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8263 gen_jmp_im(pc_ptr
- dc
->cs_base
);
8268 if (tb
->cflags
& CF_LAST_IO
)
8270 gen_tb_end(tb
, num_insns
);
8271 *tcg_ctx
.gen_opc_ptr
= INDEX_op_end
;
8272 /* we don't forget to fill the last values */
8274 j
= tcg_ctx
.gen_opc_ptr
- tcg_ctx
.gen_opc_buf
;
8277 tcg_ctx
.gen_opc_instr_start
[lj
++] = 0;
8281 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
8283 qemu_log("----------------\n");
8284 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
8285 #ifdef TARGET_X86_64
8290 disas_flags
= !dc
->code32
;
8291 log_target_disas(env
, pc_start
, pc_ptr
- pc_start
, disas_flags
);
8297 tb
->size
= pc_ptr
- pc_start
;
8298 tb
->icount
= num_insns
;
8302 void gen_intermediate_code(CPUX86State
*env
, TranslationBlock
*tb
)
8304 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, false);
8307 void gen_intermediate_code_pc(CPUX86State
*env
, TranslationBlock
*tb
)
8309 gen_intermediate_code_internal(x86_env_get_cpu(env
), tb
, true);
8312 void restore_state_to_opc(CPUX86State
*env
, TranslationBlock
*tb
, int pc_pos
)
8316 if (qemu_loglevel_mask(CPU_LOG_TB_OP
)) {
8318 qemu_log("RESTORE:\n");
8319 for(i
= 0;i
<= pc_pos
; i
++) {
8320 if (tcg_ctx
.gen_opc_instr_start
[i
]) {
8321 qemu_log("0x%04x: " TARGET_FMT_lx
"\n", i
,
8322 tcg_ctx
.gen_opc_pc
[i
]);
8325 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx
" cs_base=%x\n",
8326 pc_pos
, tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
,
8327 (uint32_t)tb
->cs_base
);
8330 env
->eip
= tcg_ctx
.gen_opc_pc
[pc_pos
] - tb
->cs_base
;
8331 cc_op
= gen_opc_cc_op
[pc_pos
];
8332 if (cc_op
!= CC_OP_DYNAMIC
)