?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-mips: add mips16 instruction decoding
[qemu.git] / hw / fdc.c
blob11ea439ed3f85d5eb0d764a4361868df41ec348c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "block.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37
38 /********************************************************/
39 /* debug Floppy devices */
40 //#define DEBUG_FLOPPY
41
42 #ifdef DEBUG_FLOPPY
43 #define FLOPPY_DPRINTF(fmt, ...) \
44 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define FLOPPY_DPRINTF(fmt, ...)
47 #endif
48
49 #define FLOPPY_ERROR(fmt, ...) \
50 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
58 /* Will always be a fixed parameter for us */
59 #define FD_SECTOR_LEN 512
60 #define FD_SECTOR_SC 2 /* Sector size code */
61 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
62
63 /* Floppy disk drive emulation */
64 typedef enum fdisk_type_t {
65 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
66 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
67 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
68 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
69 FDRIVE_DISK_NONE = 0x05, /* No disk */
70 } fdisk_type_t;
71
72 typedef enum fdrive_type_t {
73 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
74 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
75 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
76 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
77 } fdrive_type_t;
78
79 typedef enum fdisk_flags_t {
80 FDISK_DBL_SIDES = 0x01,
81 } fdisk_flags_t;
82
83 typedef struct fdrive_t {
84 DriveInfo *dinfo;
85 BlockDriverState *bs;
86 /* Drive status */
87 fdrive_type_t drive;
88 uint8_t perpendicular; /* 2.88 MB access mode */
89 /* Position */
90 uint8_t head;
91 uint8_t track;
92 uint8_t sect;
93 /* Media */
94 fdisk_flags_t flags;
95 uint8_t last_sect; /* Nb sector per track */
96 uint8_t max_track; /* Nb of tracks */
97 uint16_t bps; /* Bytes per sector */
98 uint8_t ro; /* Is read-only */
99 } fdrive_t;
100
101 static void fd_init (fdrive_t *drv)
102 {
103 /* Drive */
104 drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;
105 drv->drive = FDRIVE_DRV_NONE;
106 drv->perpendicular = 0;
107 /* Disk */
108 drv->last_sect = 0;
109 drv->max_track = 0;
110 }
111
112 static int _fd_sector (uint8_t head, uint8_t track,
113 uint8_t sect, uint8_t last_sect)
114 {
115 return (((track * 2) + head) * last_sect) + sect - 1;
116 }
117
118 /* Returns current position, in sectors, for given drive */
119 static int fd_sector (fdrive_t *drv)
120 {
121 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
122 }
123
124 /* Seek to a new position:
125 * returns 0 if already on right track
126 * returns 1 if track changed
127 * returns 2 if track is invalid
128 * returns 3 if sector is invalid
129 * returns 4 if seek is disabled
130 */
131 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
132 int enable_seek)
133 {
134 uint32_t sector;
135 int ret;
136
137 if (track > drv->max_track ||
138 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 2;
144 }
145 if (sect > drv->last_sect) {
146 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
147 head, track, sect, 1,
148 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
149 drv->max_track, drv->last_sect);
150 return 3;
151 }
152 sector = _fd_sector(head, track, sect, drv->last_sect);
153 ret = 0;
154 if (sector != fd_sector(drv)) {
155 #if 0
156 if (!enable_seek) {
157 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
158 head, track, sect, 1, drv->max_track, drv->last_sect);
159 return 4;
160 }
161 #endif
162 drv->head = head;
163 if (drv->track != track)
164 ret = 1;
165 drv->track = track;
166 drv->sect = sect;
167 }
168
169 return ret;
170 }
171
172 /* Set drive back to track 0 */
173 static void fd_recalibrate (fdrive_t *drv)
174 {
175 FLOPPY_DPRINTF("recalibrate\n");
176 drv->head = 0;
177 drv->track = 0;
178 drv->sect = 1;
179 }
180
181 /* Recognize floppy formats */
182 typedef struct fd_format_t {
183 fdrive_type_t drive;
184 fdisk_type_t disk;
185 uint8_t last_sect;
186 uint8_t max_track;
187 uint8_t max_head;
188 const char *str;
189 } fd_format_t;
190
191 static const fd_format_t fd_formats[] = {
192 /* First entry is default format */
193 /* 1.44 MB 3"1/2 floppy disks */
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
200 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
201 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
202 /* 2.88 MB 3"1/2 floppy disks */
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
206 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
207 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
208 /* 720 kB 3"1/2 floppy disks */
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
213 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
214 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
215 /* 1.2 MB 5"1/4 floppy disks */
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
221 /* 720 kB 5"1/4 floppy disks */
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
224 /* 360 kB 5"1/4 floppy disks */
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
227 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
229 /* 320 kB 5"1/4 floppy disks */
230 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
231 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
232 /* 360 kB must match 5"1/4 better than 3"1/2... */
233 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
234 /* end */
235 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
236 };
237
238 /* Revalidate a disk drive after a disk change */
239 static void fd_revalidate (fdrive_t *drv)
240 {
241 const fd_format_t *parse;
242 uint64_t nb_sectors, size;
243 int i, first_match, match;
244 int nb_heads, max_track, last_sect, ro;
245
246 FLOPPY_DPRINTF("revalidate\n");
247 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
248 ro = bdrv_is_read_only(drv->bs);
249 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
250 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
251 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
252 nb_heads - 1, max_track, last_sect);
253 } else {
254 bdrv_get_geometry(drv->bs, &nb_sectors);
255 match = -1;
256 first_match = -1;
257 for (i = 0;; i++) {
258 parse = &fd_formats[i];
259 if (parse->drive == FDRIVE_DRV_NONE)
260 break;
261 if (drv->drive == parse->drive ||
262 drv->drive == FDRIVE_DRV_NONE) {
263 size = (parse->max_head + 1) * parse->max_track *
264 parse->last_sect;
265 if (nb_sectors == size) {
266 match = i;
267 break;
268 }
269 if (first_match == -1)
270 first_match = i;
271 }
272 }
273 if (match == -1) {
274 if (first_match == -1)
275 match = 1;
276 else
277 match = first_match;
278 parse = &fd_formats[match];
279 }
280 nb_heads = parse->max_head + 1;
281 max_track = parse->max_track;
282 last_sect = parse->last_sect;
283 drv->drive = parse->drive;
284 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
285 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
286 }
287 if (nb_heads == 1) {
288 drv->flags &= ~FDISK_DBL_SIDES;
289 } else {
290 drv->flags |= FDISK_DBL_SIDES;
291 }
292 drv->max_track = max_track;
293 drv->last_sect = last_sect;
294 drv->ro = ro;
295 } else {
296 FLOPPY_DPRINTF("No disk in drive\n");
297 drv->last_sect = 0;
298 drv->max_track = 0;
299 drv->flags &= ~FDISK_DBL_SIDES;
300 }
301 }
302
303 /********************************************************/
304 /* Intel 82078 floppy disk controller emulation */
305
306 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
307 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
308 static int fdctrl_transfer_handler (void *opaque, int nchan,
309 int dma_pos, int dma_len);
310 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
311
312 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
313 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
314 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
315 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
316 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
317 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
318 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
319 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
320 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
321 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
322 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
323
324 enum {
325 FD_DIR_WRITE = 0,
326 FD_DIR_READ = 1,
327 FD_DIR_SCANE = 2,
328 FD_DIR_SCANL = 3,
329 FD_DIR_SCANH = 4,
330 };
331
332 enum {
333 FD_STATE_MULTI = 0x01, /* multi track flag */
334 FD_STATE_FORMAT = 0x02, /* format flag */
335 FD_STATE_SEEK = 0x04, /* seek flag */
336 };
337
338 enum {
339 FD_REG_SRA = 0x00,
340 FD_REG_SRB = 0x01,
341 FD_REG_DOR = 0x02,
342 FD_REG_TDR = 0x03,
343 FD_REG_MSR = 0x04,
344 FD_REG_DSR = 0x04,
345 FD_REG_FIFO = 0x05,
346 FD_REG_DIR = 0x07,
347 };
348
349 enum {
350 FD_CMD_READ_TRACK = 0x02,
351 FD_CMD_SPECIFY = 0x03,
352 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
353 FD_CMD_WRITE = 0x05,
354 FD_CMD_READ = 0x06,
355 FD_CMD_RECALIBRATE = 0x07,
356 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
357 FD_CMD_WRITE_DELETED = 0x09,
358 FD_CMD_READ_ID = 0x0a,
359 FD_CMD_READ_DELETED = 0x0c,
360 FD_CMD_FORMAT_TRACK = 0x0d,
361 FD_CMD_DUMPREG = 0x0e,
362 FD_CMD_SEEK = 0x0f,
363 FD_CMD_VERSION = 0x10,
364 FD_CMD_SCAN_EQUAL = 0x11,
365 FD_CMD_PERPENDICULAR_MODE = 0x12,
366 FD_CMD_CONFIGURE = 0x13,
367 FD_CMD_LOCK = 0x14,
368 FD_CMD_VERIFY = 0x16,
369 FD_CMD_POWERDOWN_MODE = 0x17,
370 FD_CMD_PART_ID = 0x18,
371 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
372 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
373 FD_CMD_SAVE = 0x2c,
374 FD_CMD_OPTION = 0x33,
375 FD_CMD_RESTORE = 0x4c,
376 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
377 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
378 FD_CMD_FORMAT_AND_WRITE = 0xcd,
379 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
380 };
381
382 enum {
383 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
384 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
385 FD_CONFIG_POLL = 0x10, /* Poll enabled */
386 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
387 FD_CONFIG_EIS = 0x40, /* No implied seeks */
388 };
389
390 enum {
391 FD_SR0_EQPMT = 0x10,
392 FD_SR0_SEEK = 0x20,
393 FD_SR0_ABNTERM = 0x40,
394 FD_SR0_INVCMD = 0x80,
395 FD_SR0_RDYCHG = 0xc0,
396 };
397
398 enum {
399 FD_SR1_EC = 0x80, /* End of cylinder */
400 };
401
402 enum {
403 FD_SR2_SNS = 0x04, /* Scan not satisfied */
404 FD_SR2_SEH = 0x08, /* Scan equal hit */
405 };
406
407 enum {
408 FD_SRA_DIR = 0x01,
409 FD_SRA_nWP = 0x02,
410 FD_SRA_nINDX = 0x04,
411 FD_SRA_HDSEL = 0x08,
412 FD_SRA_nTRK0 = 0x10,
413 FD_SRA_STEP = 0x20,
414 FD_SRA_nDRV2 = 0x40,
415 FD_SRA_INTPEND = 0x80,
416 };
417
418 enum {
419 FD_SRB_MTR0 = 0x01,
420 FD_SRB_MTR1 = 0x02,
421 FD_SRB_WGATE = 0x04,
422 FD_SRB_RDATA = 0x08,
423 FD_SRB_WDATA = 0x10,
424 FD_SRB_DR0 = 0x20,
425 };
426
427 enum {
428 #if MAX_FD == 4
429 FD_DOR_SELMASK = 0x03,
430 #else
431 FD_DOR_SELMASK = 0x01,
432 #endif
433 FD_DOR_nRESET = 0x04,
434 FD_DOR_DMAEN = 0x08,
435 FD_DOR_MOTEN0 = 0x10,
436 FD_DOR_MOTEN1 = 0x20,
437 FD_DOR_MOTEN2 = 0x40,
438 FD_DOR_MOTEN3 = 0x80,
439 };
440
441 enum {
442 #if MAX_FD == 4
443 FD_TDR_BOOTSEL = 0x0c,
444 #else
445 FD_TDR_BOOTSEL = 0x04,
446 #endif
447 };
448
449 enum {
450 FD_DSR_DRATEMASK= 0x03,
451 FD_DSR_PWRDOWN = 0x40,
452 FD_DSR_SWRESET = 0x80,
453 };
454
455 enum {
456 FD_MSR_DRV0BUSY = 0x01,
457 FD_MSR_DRV1BUSY = 0x02,
458 FD_MSR_DRV2BUSY = 0x04,
459 FD_MSR_DRV3BUSY = 0x08,
460 FD_MSR_CMDBUSY = 0x10,
461 FD_MSR_NONDMA = 0x20,
462 FD_MSR_DIO = 0x40,
463 FD_MSR_RQM = 0x80,
464 };
465
466 enum {
467 FD_DIR_DSKCHG = 0x80,
468 };
469
470 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
471 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
472 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
473
474 struct fdctrl_t {
475 /* Controller's identification */
476 uint8_t version;
477 /* HW */
478 qemu_irq irq;
479 int dma_chann;
480 /* Controller state */
481 QEMUTimer *result_timer;
482 uint8_t sra;
483 uint8_t srb;
484 uint8_t dor;
485 uint8_t dor_vmstate; /* only used as temp during vmstate */
486 uint8_t tdr;
487 uint8_t dsr;
488 uint8_t msr;
489 uint8_t cur_drv;
490 uint8_t status0;
491 uint8_t status1;
492 uint8_t status2;
493 /* Command FIFO */
494 uint8_t *fifo;
495 int32_t fifo_size;
496 uint32_t data_pos;
497 uint32_t data_len;
498 uint8_t data_state;
499 uint8_t data_dir;
500 uint8_t eot; /* last wanted sector */
501 /* States kept only to be returned back */
502 /* Timers state */
503 uint8_t timer0;
504 uint8_t timer1;
505 /* precompensation */
506 uint8_t precomp_trk;
507 uint8_t config;
508 uint8_t lock;
509 /* Power down config (also with status regB access mode */
510 uint8_t pwrd;
511 /* Sun4m quirks? */
512 int sun4m;
513 /* Floppy drives */
514 uint8_t num_floppies;
515 fdrive_t drives[MAX_FD];
516 int reset_sensei;
517 };
518
519 typedef struct fdctrl_sysbus_t {
520 SysBusDevice busdev;
521 struct fdctrl_t state;
522 } fdctrl_sysbus_t;
523
524 typedef struct fdctrl_isabus_t {
525 ISADevice busdev;
526 struct fdctrl_t state;
527 } fdctrl_isabus_t;
528
529 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
530 {
531 fdctrl_t *fdctrl = opaque;
532 uint32_t retval;
533
534 switch (reg) {
535 case FD_REG_SRA:
536 retval = fdctrl_read_statusA(fdctrl);
537 break;
538 case FD_REG_SRB:
539 retval = fdctrl_read_statusB(fdctrl);
540 break;
541 case FD_REG_DOR:
542 retval = fdctrl_read_dor(fdctrl);
543 break;
544 case FD_REG_TDR:
545 retval = fdctrl_read_tape(fdctrl);
546 break;
547 case FD_REG_MSR:
548 retval = fdctrl_read_main_status(fdctrl);
549 break;
550 case FD_REG_FIFO:
551 retval = fdctrl_read_data(fdctrl);
552 break;
553 case FD_REG_DIR:
554 retval = fdctrl_read_dir(fdctrl);
555 break;
556 default:
557 retval = (uint32_t)(-1);
558 break;
559 }
560 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
561
562 return retval;
563 }
564
565 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
566 {
567 fdctrl_t *fdctrl = opaque;
568
569 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
570
571 switch (reg) {
572 case FD_REG_DOR:
573 fdctrl_write_dor(fdctrl, value);
574 break;
575 case FD_REG_TDR:
576 fdctrl_write_tape(fdctrl, value);
577 break;
578 case FD_REG_DSR:
579 fdctrl_write_rate(fdctrl, value);
580 break;
581 case FD_REG_FIFO:
582 fdctrl_write_data(fdctrl, value);
583 break;
584 default:
585 break;
586 }
587 }
588
589 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
590 {
591 return fdctrl_read(opaque, reg & 7);
592 }
593
594 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
595 {
596 fdctrl_write(opaque, reg & 7, value);
597 }
598
599 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
600 {
601 return fdctrl_read(opaque, (uint32_t)reg);
602 }
603
604 static void fdctrl_write_mem (void *opaque,
605 target_phys_addr_t reg, uint32_t value)
606 {
607 fdctrl_write(opaque, (uint32_t)reg, value);
608 }
609
610 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
611 fdctrl_read_mem,
612 fdctrl_read_mem,
613 fdctrl_read_mem,
614 };
615
616 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
617 fdctrl_write_mem,
618 fdctrl_write_mem,
619 fdctrl_write_mem,
620 };
621
622 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
623 fdctrl_read_mem,
624 NULL,
625 NULL,
626 };
627
628 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
629 fdctrl_write_mem,
630 NULL,
631 NULL,
632 };
633
634 static const VMStateDescription vmstate_fdrive = {
635 .name = "fdrive",
636 .version_id = 1,
637 .minimum_version_id = 1,
638 .minimum_version_id_old = 1,
639 .fields = (VMStateField []) {
640 VMSTATE_UINT8(head, fdrive_t),
641 VMSTATE_UINT8(track, fdrive_t),
642 VMSTATE_UINT8(sect, fdrive_t),
643 VMSTATE_END_OF_LIST()
644 }
645 };
646
647 static void fdc_pre_save(void *opaque)
648 {
649 fdctrl_t *s = opaque;
650
651 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
652 }
653
654 static int fdc_post_load(void *opaque, int version_id)
655 {
656 fdctrl_t *s = opaque;
657
658 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
659 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
660 return 0;
661 }
662
663 static const VMStateDescription vmstate_fdc = {
664 .name = "fdctrl",
665 .version_id = 2,
666 .minimum_version_id = 2,
667 .minimum_version_id_old = 2,
668 .pre_save = fdc_pre_save,
669 .post_load = fdc_post_load,
670 .fields = (VMStateField []) {
671 /* Controller State */
672 VMSTATE_UINT8(sra, fdctrl_t),
673 VMSTATE_UINT8(srb, fdctrl_t),
674 VMSTATE_UINT8(dor_vmstate, fdctrl_t),
675 VMSTATE_UINT8(tdr, fdctrl_t),
676 VMSTATE_UINT8(dsr, fdctrl_t),
677 VMSTATE_UINT8(msr, fdctrl_t),
678 VMSTATE_UINT8(status0, fdctrl_t),
679 VMSTATE_UINT8(status1, fdctrl_t),
680 VMSTATE_UINT8(status2, fdctrl_t),
681 /* Command FIFO */
682 VMSTATE_VARRAY_INT32(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
683 VMSTATE_UINT32(data_pos, fdctrl_t),
684 VMSTATE_UINT32(data_len, fdctrl_t),
685 VMSTATE_UINT8(data_state, fdctrl_t),
686 VMSTATE_UINT8(data_dir, fdctrl_t),
687 VMSTATE_UINT8(eot, fdctrl_t),
688 /* States kept only to be returned back */
689 VMSTATE_UINT8(timer0, fdctrl_t),
690 VMSTATE_UINT8(timer1, fdctrl_t),
691 VMSTATE_UINT8(precomp_trk, fdctrl_t),
692 VMSTATE_UINT8(config, fdctrl_t),
693 VMSTATE_UINT8(lock, fdctrl_t),
694 VMSTATE_UINT8(pwrd, fdctrl_t),
695 VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
696 VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
697 vmstate_fdrive, fdrive_t),
698 VMSTATE_END_OF_LIST()
699 }
700 };
701
702 static const VMStateDescription vmstate_fdc_isa = {
703 .name = "fdc",
704 .version_id = 2,
705 .minimum_version_id = 2,
706 .minimum_version_id_old = 2,
707 .fields = (VMStateField []) {
708 /* Controller State */
709 VMSTATE_STRUCT(state, fdctrl_isabus_t, 0, vmstate_fdc, fdctrl_t),
710 VMSTATE_END_OF_LIST()
711 }
712 };
713
714 static const VMStateDescription vmstate_fdc_sysbus = {
715 .name = "fdc",
716 .version_id = 2,
717 .minimum_version_id = 2,
718 .minimum_version_id_old = 2,
719 .fields = (VMStateField []) {
720 /* Controller State */
721 VMSTATE_STRUCT(state, fdctrl_sysbus_t, 0, vmstate_fdc, fdctrl_t),
722 VMSTATE_END_OF_LIST()
723 }
724 };
725
726
727 static void fdctrl_external_reset_sysbus(DeviceState *d)
728 {
729 fdctrl_sysbus_t *sys = container_of(d, fdctrl_sysbus_t, busdev.qdev);
730 fdctrl_t *s = &sys->state;
731
732 fdctrl_reset(s, 0);
733 }
734
735 static void fdctrl_external_reset_isa(DeviceState *d)
736 {
737 fdctrl_isabus_t *isa = container_of(d, fdctrl_isabus_t, busdev.qdev);
738 fdctrl_t *s = &isa->state;
739
740 fdctrl_reset(s, 0);
741 }
742
743 static void fdctrl_handle_tc(void *opaque, int irq, int level)
744 {
745 //fdctrl_t *s = opaque;
746
747 if (level) {
748 // XXX
749 FLOPPY_DPRINTF("TC pulsed\n");
750 }
751 }
752
753 /* XXX: may change if moved to bdrv */
754 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
755 {
756 return fdctrl->drives[drive_num].drive;
757 }
758
759 /* Change IRQ state */
760 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
761 {
762 if (!(fdctrl->sra & FD_SRA_INTPEND))
763 return;
764 FLOPPY_DPRINTF("Reset interrupt\n");
765 qemu_set_irq(fdctrl->irq, 0);
766 fdctrl->sra &= ~FD_SRA_INTPEND;
767 }
768
769 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
770 {
771 /* Sparc mutation */
772 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
773 /* XXX: not sure */
774 fdctrl->msr &= ~FD_MSR_CMDBUSY;
775 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
776 fdctrl->status0 = status0;
777 return;
778 }
779 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
780 qemu_set_irq(fdctrl->irq, 1);
781 fdctrl->sra |= FD_SRA_INTPEND;
782 }
783 fdctrl->reset_sensei = 0;
784 fdctrl->status0 = status0;
785 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
786 }
787
788 /* Reset controller */
789 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
790 {
791 int i;
792
793 FLOPPY_DPRINTF("reset controller\n");
794 fdctrl_reset_irq(fdctrl);
795 /* Initialise controller */
796 fdctrl->sra = 0;
797 fdctrl->srb = 0xc0;
798 if (!fdctrl->drives[1].bs)
799 fdctrl->sra |= FD_SRA_nDRV2;
800 fdctrl->cur_drv = 0;
801 fdctrl->dor = FD_DOR_nRESET;
802 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
803 fdctrl->msr = FD_MSR_RQM;
804 /* FIFO state */
805 fdctrl->data_pos = 0;
806 fdctrl->data_len = 0;
807 fdctrl->data_state = 0;
808 fdctrl->data_dir = FD_DIR_WRITE;
809 for (i = 0; i < MAX_FD; i++)
810 fd_recalibrate(&fdctrl->drives[i]);
811 fdctrl_reset_fifo(fdctrl);
812 if (do_irq) {
813 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
814 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
815 }
816 }
817
818 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
819 {
820 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
821 }
822
823 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
824 {
825 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
826 return &fdctrl->drives[1];
827 else
828 return &fdctrl->drives[0];
829 }
830
831 #if MAX_FD == 4
832 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
833 {
834 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
835 return &fdctrl->drives[2];
836 else
837 return &fdctrl->drives[1];
838 }
839
840 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
841 {
842 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
843 return &fdctrl->drives[3];
844 else
845 return &fdctrl->drives[2];
846 }
847 #endif
848
849 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
850 {
851 switch (fdctrl->cur_drv) {
852 case 0: return drv0(fdctrl);
853 case 1: return drv1(fdctrl);
854 #if MAX_FD == 4
855 case 2: return drv2(fdctrl);
856 case 3: return drv3(fdctrl);
857 #endif
858 default: return NULL;
859 }
860 }
861
862 /* Status A register : 0x00 (read-only) */
863 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
864 {
865 uint32_t retval = fdctrl->sra;
866
867 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
868
869 return retval;
870 }
871
872 /* Status B register : 0x01 (read-only) */
873 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
874 {
875 uint32_t retval = fdctrl->srb;
876
877 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
878
879 return retval;
880 }
881
882 /* Digital output register : 0x02 */
883 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
884 {
885 uint32_t retval = fdctrl->dor;
886
887 /* Selected drive */
888 retval |= fdctrl->cur_drv;
889 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
890
891 return retval;
892 }
893
894 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
895 {
896 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
897
898 /* Motors */
899 if (value & FD_DOR_MOTEN0)
900 fdctrl->srb |= FD_SRB_MTR0;
901 else
902 fdctrl->srb &= ~FD_SRB_MTR0;
903 if (value & FD_DOR_MOTEN1)
904 fdctrl->srb |= FD_SRB_MTR1;
905 else
906 fdctrl->srb &= ~FD_SRB_MTR1;
907
908 /* Drive */
909 if (value & 1)
910 fdctrl->srb |= FD_SRB_DR0;
911 else
912 fdctrl->srb &= ~FD_SRB_DR0;
913
914 /* Reset */
915 if (!(value & FD_DOR_nRESET)) {
916 if (fdctrl->dor & FD_DOR_nRESET) {
917 FLOPPY_DPRINTF("controller enter RESET state\n");
918 }
919 } else {
920 if (!(fdctrl->dor & FD_DOR_nRESET)) {
921 FLOPPY_DPRINTF("controller out of RESET state\n");
922 fdctrl_reset(fdctrl, 1);
923 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
924 }
925 }
926 /* Selected drive */
927 fdctrl->cur_drv = value & FD_DOR_SELMASK;
928
929 fdctrl->dor = value;
930 }
931
932 /* Tape drive register : 0x03 */
933 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
934 {
935 uint32_t retval = fdctrl->tdr;
936
937 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
938
939 return retval;
940 }
941
942 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
943 {
944 /* Reset mode */
945 if (!(fdctrl->dor & FD_DOR_nRESET)) {
946 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
947 return;
948 }
949 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
950 /* Disk boot selection indicator */
951 fdctrl->tdr = value & FD_TDR_BOOTSEL;
952 /* Tape indicators: never allow */
953 }
954
955 /* Main status register : 0x04 (read) */
956 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
957 {
958 uint32_t retval = fdctrl->msr;
959
960 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
961 fdctrl->dor |= FD_DOR_nRESET;
962
963 /* Sparc mutation */
964 if (fdctrl->sun4m) {
965 retval |= FD_MSR_DIO;
966 fdctrl_reset_irq(fdctrl);
967 };
968
969 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
970
971 return retval;
972 }
973
974 /* Data select rate register : 0x04 (write) */
975 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
976 {
977 /* Reset mode */
978 if (!(fdctrl->dor & FD_DOR_nRESET)) {
979 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
980 return;
981 }
982 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
983 /* Reset: autoclear */
984 if (value & FD_DSR_SWRESET) {
985 fdctrl->dor &= ~FD_DOR_nRESET;
986 fdctrl_reset(fdctrl, 1);
987 fdctrl->dor |= FD_DOR_nRESET;
988 }
989 if (value & FD_DSR_PWRDOWN) {
990 fdctrl_reset(fdctrl, 1);
991 }
992 fdctrl->dsr = value;
993 }
994
995 static int fdctrl_media_changed(fdrive_t *drv)
996 {
997 int ret;
998
999 if (!drv->bs)
1000 return 0;
1001 ret = bdrv_media_changed(drv->bs);
1002 if (ret) {
1003 fd_revalidate(drv);
1004 }
1005 return ret;
1006 }
1007
1008 /* Digital input register : 0x07 (read-only) */
1009 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
1010 {
1011 uint32_t retval = 0;
1012
1013 if (fdctrl_media_changed(drv0(fdctrl))
1014 || fdctrl_media_changed(drv1(fdctrl))
1015 #if MAX_FD == 4
1016 || fdctrl_media_changed(drv2(fdctrl))
1017 || fdctrl_media_changed(drv3(fdctrl))
1018 #endif
1019 )
1020 retval |= FD_DIR_DSKCHG;
1021 if (retval != 0)
1022 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1023
1024 return retval;
1025 }
1026
1027 /* FIFO state control */
1028 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1029 {
1030 fdctrl->data_dir = FD_DIR_WRITE;
1031 fdctrl->data_pos = 0;
1032 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1033 }
1034
1035 /* Set FIFO status for the host to read */
1036 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1037 {
1038 fdctrl->data_dir = FD_DIR_READ;
1039 fdctrl->data_len = fifo_len;
1040 fdctrl->data_pos = 0;
1041 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1042 if (do_irq)
1043 fdctrl_raise_irq(fdctrl, 0x00);
1044 }
1045
1046 /* Set an error: unimplemented/unknown command */
1047 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1048 {
1049 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1050 fdctrl->fifo[0] = FD_SR0_INVCMD;
1051 fdctrl_set_fifo(fdctrl, 1, 0);
1052 }
1053
1054 /* Seek to next sector */
1055 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1056 {
1057 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1058 cur_drv->head, cur_drv->track, cur_drv->sect,
1059 fd_sector(cur_drv));
1060 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1061 error in fact */
1062 if (cur_drv->sect >= cur_drv->last_sect ||
1063 cur_drv->sect == fdctrl->eot) {
1064 cur_drv->sect = 1;
1065 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1066 if (cur_drv->head == 0 &&
1067 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1068 cur_drv->head = 1;
1069 } else {
1070 cur_drv->head = 0;
1071 cur_drv->track++;
1072 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1073 return 0;
1074 }
1075 } else {
1076 cur_drv->track++;
1077 return 0;
1078 }
1079 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1080 cur_drv->head, cur_drv->track,
1081 cur_drv->sect, fd_sector(cur_drv));
1082 } else {
1083 cur_drv->sect++;
1084 }
1085 return 1;
1086 }
1087
1088 /* Callback for transfer end (stop or abort) */
1089 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1090 uint8_t status1, uint8_t status2)
1091 {
1092 fdrive_t *cur_drv;
1093
1094 cur_drv = get_cur_drv(fdctrl);
1095 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1096 status0, status1, status2,
1097 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1098 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1099 fdctrl->fifo[1] = status1;
1100 fdctrl->fifo[2] = status2;
1101 fdctrl->fifo[3] = cur_drv->track;
1102 fdctrl->fifo[4] = cur_drv->head;
1103 fdctrl->fifo[5] = cur_drv->sect;
1104 fdctrl->fifo[6] = FD_SECTOR_SC;
1105 fdctrl->data_dir = FD_DIR_READ;
1106 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1107 DMA_release_DREQ(fdctrl->dma_chann);
1108 }
1109 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1110 fdctrl->msr &= ~FD_MSR_NONDMA;
1111 fdctrl_set_fifo(fdctrl, 7, 1);
1112 }
1113
1114 /* Prepare a data transfer (either DMA or FIFO) */
1115 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1116 {
1117 fdrive_t *cur_drv;
1118 uint8_t kh, kt, ks;
1119 int did_seek = 0;
1120
1121 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1122 cur_drv = get_cur_drv(fdctrl);
1123 kt = fdctrl->fifo[2];
1124 kh = fdctrl->fifo[3];
1125 ks = fdctrl->fifo[4];
1126 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1127 GET_CUR_DRV(fdctrl), kh, kt, ks,
1128 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1129 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1130 case 2:
1131 /* sect too big */
1132 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1133 fdctrl->fifo[3] = kt;
1134 fdctrl->fifo[4] = kh;
1135 fdctrl->fifo[5] = ks;
1136 return;
1137 case 3:
1138 /* track too big */
1139 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1140 fdctrl->fifo[3] = kt;
1141 fdctrl->fifo[4] = kh;
1142 fdctrl->fifo[5] = ks;
1143 return;
1144 case 4:
1145 /* No seek enabled */
1146 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1147 fdctrl->fifo[3] = kt;
1148 fdctrl->fifo[4] = kh;
1149 fdctrl->fifo[5] = ks;
1150 return;
1151 case 1:
1152 did_seek = 1;
1153 break;
1154 default:
1155 break;
1156 }
1157
1158 /* Set the FIFO state */
1159 fdctrl->data_dir = direction;
1160 fdctrl->data_pos = 0;
1161 fdctrl->msr |= FD_MSR_CMDBUSY;
1162 if (fdctrl->fifo[0] & 0x80)
1163 fdctrl->data_state |= FD_STATE_MULTI;
1164 else
1165 fdctrl->data_state &= ~FD_STATE_MULTI;
1166 if (did_seek)
1167 fdctrl->data_state |= FD_STATE_SEEK;
1168 else
1169 fdctrl->data_state &= ~FD_STATE_SEEK;
1170 if (fdctrl->fifo[5] == 00) {
1171 fdctrl->data_len = fdctrl->fifo[8];
1172 } else {
1173 int tmp;
1174 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1175 tmp = (fdctrl->fifo[6] - ks + 1);
1176 if (fdctrl->fifo[0] & 0x80)
1177 tmp += fdctrl->fifo[6];
1178 fdctrl->data_len *= tmp;
1179 }
1180 fdctrl->eot = fdctrl->fifo[6];
1181 if (fdctrl->dor & FD_DOR_DMAEN) {
1182 int dma_mode;
1183 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1184 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1185 dma_mode = (dma_mode >> 2) & 3;
1186 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1187 dma_mode, direction,
1188 (128 << fdctrl->fifo[5]) *
1189 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1190 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1191 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1192 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1193 (direction == FD_DIR_READ && dma_mode == 1)) {
1194 /* No access is allowed until DMA transfer has completed */
1195 fdctrl->msr &= ~FD_MSR_RQM;
1196 /* Now, we just have to wait for the DMA controller to
1197 * recall us...
1198 */
1199 DMA_hold_DREQ(fdctrl->dma_chann);
1200 DMA_schedule(fdctrl->dma_chann);
1201 return;
1202 } else {
1203 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1204 }
1205 }
1206 FLOPPY_DPRINTF("start non-DMA transfer\n");
1207 fdctrl->msr |= FD_MSR_NONDMA;
1208 if (direction != FD_DIR_WRITE)
1209 fdctrl->msr |= FD_MSR_DIO;
1210 /* IO based transfer: calculate len */
1211 fdctrl_raise_irq(fdctrl, 0x00);
1212
1213 return;
1214 }
1215
1216 /* Prepare a transfer of deleted data */
1217 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1218 {
1219 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1220
1221 /* We don't handle deleted data,
1222 * so we don't return *ANYTHING*
1223 */
1224 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1225 }
1226
1227 /* handlers for DMA transfers */
1228 static int fdctrl_transfer_handler (void *opaque, int nchan,
1229 int dma_pos, int dma_len)
1230 {
1231 fdctrl_t *fdctrl;
1232 fdrive_t *cur_drv;
1233 int len, start_pos, rel_pos;
1234 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1235
1236 fdctrl = opaque;
1237 if (fdctrl->msr & FD_MSR_RQM) {
1238 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1239 return 0;
1240 }
1241 cur_drv = get_cur_drv(fdctrl);
1242 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1243 fdctrl->data_dir == FD_DIR_SCANH)
1244 status2 = FD_SR2_SNS;
1245 if (dma_len > fdctrl->data_len)
1246 dma_len = fdctrl->data_len;
1247 if (cur_drv->bs == NULL) {
1248 if (fdctrl->data_dir == FD_DIR_WRITE)
1249 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1250 else
1251 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1252 len = 0;
1253 goto transfer_error;
1254 }
1255 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1256 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1257 len = dma_len - fdctrl->data_pos;
1258 if (len + rel_pos > FD_SECTOR_LEN)
1259 len = FD_SECTOR_LEN - rel_pos;
1260 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1261 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1262 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1263 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1264 fd_sector(cur_drv) * FD_SECTOR_LEN);
1265 if (fdctrl->data_dir != FD_DIR_WRITE ||
1266 len < FD_SECTOR_LEN || rel_pos != 0) {
1267 /* READ & SCAN commands and realign to a sector for WRITE */
1268 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1269 fdctrl->fifo, 1) < 0) {
1270 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1271 fd_sector(cur_drv));
1272 /* Sure, image size is too small... */
1273 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1274 }
1275 }
1276 switch (fdctrl->data_dir) {
1277 case FD_DIR_READ:
1278 /* READ commands */
1279 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1280 fdctrl->data_pos, len);
1281 break;
1282 case FD_DIR_WRITE:
1283 /* WRITE commands */
1284 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1285 fdctrl->data_pos, len);
1286 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1287 fdctrl->fifo, 1) < 0) {
1288 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1289 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1290 goto transfer_error;
1291 }
1292 break;
1293 default:
1294 /* SCAN commands */
1295 {
1296 uint8_t tmpbuf[FD_SECTOR_LEN];
1297 int ret;
1298 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1299 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1300 if (ret == 0) {
1301 status2 = FD_SR2_SEH;
1302 goto end_transfer;
1303 }
1304 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1305 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1306 status2 = 0x00;
1307 goto end_transfer;
1308 }
1309 }
1310 break;
1311 }
1312 fdctrl->data_pos += len;
1313 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1314 if (rel_pos == 0) {
1315 /* Seek to next sector */
1316 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1317 break;
1318 }
1319 }
1320 end_transfer:
1321 len = fdctrl->data_pos - start_pos;
1322 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1323 fdctrl->data_pos, len, fdctrl->data_len);
1324 if (fdctrl->data_dir == FD_DIR_SCANE ||
1325 fdctrl->data_dir == FD_DIR_SCANL ||
1326 fdctrl->data_dir == FD_DIR_SCANH)
1327 status2 = FD_SR2_SEH;
1328 if (FD_DID_SEEK(fdctrl->data_state))
1329 status0 |= FD_SR0_SEEK;
1330 fdctrl->data_len -= len;
1331 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1332 transfer_error:
1333
1334 return len;
1335 }
1336
1337 /* Data register : 0x05 */
1338 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1339 {
1340 fdrive_t *cur_drv;
1341 uint32_t retval = 0;
1342 int pos;
1343
1344 cur_drv = get_cur_drv(fdctrl);
1345 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1346 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1347 FLOPPY_ERROR("controller not ready for reading\n");
1348 return 0;
1349 }
1350 pos = fdctrl->data_pos;
1351 if (fdctrl->msr & FD_MSR_NONDMA) {
1352 pos %= FD_SECTOR_LEN;
1353 if (pos == 0) {
1354 if (fdctrl->data_pos != 0)
1355 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1356 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1357 fd_sector(cur_drv));
1358 return 0;
1359 }
1360 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1361 FLOPPY_DPRINTF("error getting sector %d\n",
1362 fd_sector(cur_drv));
1363 /* Sure, image size is too small... */
1364 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1365 }
1366 }
1367 }
1368 retval = fdctrl->fifo[pos];
1369 if (++fdctrl->data_pos == fdctrl->data_len) {
1370 fdctrl->data_pos = 0;
1371 /* Switch from transfer mode to status mode
1372 * then from status mode to command mode
1373 */
1374 if (fdctrl->msr & FD_MSR_NONDMA) {
1375 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1376 } else {
1377 fdctrl_reset_fifo(fdctrl);
1378 fdctrl_reset_irq(fdctrl);
1379 }
1380 }
1381 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1382
1383 return retval;
1384 }
1385
1386 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1387 {
1388 fdrive_t *cur_drv;
1389 uint8_t kh, kt, ks;
1390
1391 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1392 cur_drv = get_cur_drv(fdctrl);
1393 kt = fdctrl->fifo[6];
1394 kh = fdctrl->fifo[7];
1395 ks = fdctrl->fifo[8];
1396 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1397 GET_CUR_DRV(fdctrl), kh, kt, ks,
1398 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1399 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1400 case 2:
1401 /* sect too big */
1402 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1403 fdctrl->fifo[3] = kt;
1404 fdctrl->fifo[4] = kh;
1405 fdctrl->fifo[5] = ks;
1406 return;
1407 case 3:
1408 /* track too big */
1409 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1410 fdctrl->fifo[3] = kt;
1411 fdctrl->fifo[4] = kh;
1412 fdctrl->fifo[5] = ks;
1413 return;
1414 case 4:
1415 /* No seek enabled */
1416 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1417 fdctrl->fifo[3] = kt;
1418 fdctrl->fifo[4] = kh;
1419 fdctrl->fifo[5] = ks;
1420 return;
1421 case 1:
1422 fdctrl->data_state |= FD_STATE_SEEK;
1423 break;
1424 default:
1425 break;
1426 }
1427 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1428 if (cur_drv->bs == NULL ||
1429 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1430 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1431 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1432 } else {
1433 if (cur_drv->sect == cur_drv->last_sect) {
1434 fdctrl->data_state &= ~FD_STATE_FORMAT;
1435 /* Last sector done */
1436 if (FD_DID_SEEK(fdctrl->data_state))
1437 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1438 else
1439 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1440 } else {
1441 /* More to do */
1442 fdctrl->data_pos = 0;
1443 fdctrl->data_len = 4;
1444 }
1445 }
1446 }
1447
1448 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1449 {
1450 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1451 fdctrl->fifo[0] = fdctrl->lock << 4;
1452 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1453 }
1454
1455 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1456 {
1457 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1458
1459 /* Drives position */
1460 fdctrl->fifo[0] = drv0(fdctrl)->track;
1461 fdctrl->fifo[1] = drv1(fdctrl)->track;
1462 #if MAX_FD == 4
1463 fdctrl->fifo[2] = drv2(fdctrl)->track;
1464 fdctrl->fifo[3] = drv3(fdctrl)->track;
1465 #else
1466 fdctrl->fifo[2] = 0;
1467 fdctrl->fifo[3] = 0;
1468 #endif
1469 /* timers */
1470 fdctrl->fifo[4] = fdctrl->timer0;
1471 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1472 fdctrl->fifo[6] = cur_drv->last_sect;
1473 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1474 (cur_drv->perpendicular << 2);
1475 fdctrl->fifo[8] = fdctrl->config;
1476 fdctrl->fifo[9] = fdctrl->precomp_trk;
1477 fdctrl_set_fifo(fdctrl, 10, 0);
1478 }
1479
1480 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1481 {
1482 /* Controller's version */
1483 fdctrl->fifo[0] = fdctrl->version;
1484 fdctrl_set_fifo(fdctrl, 1, 1);
1485 }
1486
1487 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1488 {
1489 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1490 fdctrl_set_fifo(fdctrl, 1, 0);
1491 }
1492
1493 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1494 {
1495 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1496
1497 /* Drives position */
1498 drv0(fdctrl)->track = fdctrl->fifo[3];
1499 drv1(fdctrl)->track = fdctrl->fifo[4];
1500 #if MAX_FD == 4
1501 drv2(fdctrl)->track = fdctrl->fifo[5];
1502 drv3(fdctrl)->track = fdctrl->fifo[6];
1503 #endif
1504 /* timers */
1505 fdctrl->timer0 = fdctrl->fifo[7];
1506 fdctrl->timer1 = fdctrl->fifo[8];
1507 cur_drv->last_sect = fdctrl->fifo[9];
1508 fdctrl->lock = fdctrl->fifo[10] >> 7;
1509 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1510 fdctrl->config = fdctrl->fifo[11];
1511 fdctrl->precomp_trk = fdctrl->fifo[12];
1512 fdctrl->pwrd = fdctrl->fifo[13];
1513 fdctrl_reset_fifo(fdctrl);
1514 }
1515
1516 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1517 {
1518 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1519
1520 fdctrl->fifo[0] = 0;
1521 fdctrl->fifo[1] = 0;
1522 /* Drives position */
1523 fdctrl->fifo[2] = drv0(fdctrl)->track;
1524 fdctrl->fifo[3] = drv1(fdctrl)->track;
1525 #if MAX_FD == 4
1526 fdctrl->fifo[4] = drv2(fdctrl)->track;
1527 fdctrl->fifo[5] = drv3(fdctrl)->track;
1528 #else
1529 fdctrl->fifo[4] = 0;
1530 fdctrl->fifo[5] = 0;
1531 #endif
1532 /* timers */
1533 fdctrl->fifo[6] = fdctrl->timer0;
1534 fdctrl->fifo[7] = fdctrl->timer1;
1535 fdctrl->fifo[8] = cur_drv->last_sect;
1536 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1537 (cur_drv->perpendicular << 2);
1538 fdctrl->fifo[10] = fdctrl->config;
1539 fdctrl->fifo[11] = fdctrl->precomp_trk;
1540 fdctrl->fifo[12] = fdctrl->pwrd;
1541 fdctrl->fifo[13] = 0;
1542 fdctrl->fifo[14] = 0;
1543 fdctrl_set_fifo(fdctrl, 15, 1);
1544 }
1545
1546 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1547 {
1548 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1549
1550 /* XXX: should set main status register to busy */
1551 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1552 qemu_mod_timer(fdctrl->result_timer,
1553 qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1554 }
1555
1556 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1557 {
1558 fdrive_t *cur_drv;
1559
1560 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1561 cur_drv = get_cur_drv(fdctrl);
1562 fdctrl->data_state |= FD_STATE_FORMAT;
1563 if (fdctrl->fifo[0] & 0x80)
1564 fdctrl->data_state |= FD_STATE_MULTI;
1565 else
1566 fdctrl->data_state &= ~FD_STATE_MULTI;
1567 fdctrl->data_state &= ~FD_STATE_SEEK;
1568 cur_drv->bps =
1569 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1570 #if 0
1571 cur_drv->last_sect =
1572 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1573 fdctrl->fifo[3] / 2;
1574 #else
1575 cur_drv->last_sect = fdctrl->fifo[3];
1576 #endif
1577 /* TODO: implement format using DMA expected by the Bochs BIOS
1578 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1579 * the sector with the specified fill byte
1580 */
1581 fdctrl->data_state &= ~FD_STATE_FORMAT;
1582 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1583 }
1584
1585 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1586 {
1587 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1588 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1589 if (fdctrl->fifo[2] & 1)
1590 fdctrl->dor &= ~FD_DOR_DMAEN;
1591 else
1592 fdctrl->dor |= FD_DOR_DMAEN;
1593 /* No result back */
1594 fdctrl_reset_fifo(fdctrl);
1595 }
1596
1597 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1598 {
1599 fdrive_t *cur_drv;
1600
1601 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1602 cur_drv = get_cur_drv(fdctrl);
1603 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1604 /* 1 Byte status back */
1605 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1606 (cur_drv->track == 0 ? 0x10 : 0x00) |
1607 (cur_drv->head << 2) |
1608 GET_CUR_DRV(fdctrl) |
1609 0x28;
1610 fdctrl_set_fifo(fdctrl, 1, 0);
1611 }
1612
1613 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1614 {
1615 fdrive_t *cur_drv;
1616
1617 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1618 cur_drv = get_cur_drv(fdctrl);
1619 fd_recalibrate(cur_drv);
1620 fdctrl_reset_fifo(fdctrl);
1621 /* Raise Interrupt */
1622 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1623 }
1624
1625 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1626 {
1627 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1628
1629 if(fdctrl->reset_sensei > 0) {
1630 fdctrl->fifo[0] =
1631 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1632 fdctrl->reset_sensei--;
1633 } else {
1634 /* XXX: status0 handling is broken for read/write
1635 commands, so we do this hack. It should be suppressed
1636 ASAP */
1637 fdctrl->fifo[0] =
1638 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1639 }
1640
1641 fdctrl->fifo[1] = cur_drv->track;
1642 fdctrl_set_fifo(fdctrl, 2, 0);
1643 fdctrl_reset_irq(fdctrl);
1644 fdctrl->status0 = FD_SR0_RDYCHG;
1645 }
1646
1647 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1648 {
1649 fdrive_t *cur_drv;
1650
1651 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1652 cur_drv = get_cur_drv(fdctrl);
1653 fdctrl_reset_fifo(fdctrl);
1654 if (fdctrl->fifo[2] > cur_drv->max_track) {
1655 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1656 } else {
1657 cur_drv->track = fdctrl->fifo[2];
1658 /* Raise Interrupt */
1659 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1660 }
1661 }
1662
1663 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1664 {
1665 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1666
1667 if (fdctrl->fifo[1] & 0x80)
1668 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1669 /* No result back */
1670 fdctrl_reset_fifo(fdctrl);
1671 }
1672
1673 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1674 {
1675 fdctrl->config = fdctrl->fifo[2];
1676 fdctrl->precomp_trk = fdctrl->fifo[3];
1677 /* No result back */
1678 fdctrl_reset_fifo(fdctrl);
1679 }
1680
1681 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1682 {
1683 fdctrl->pwrd = fdctrl->fifo[1];
1684 fdctrl->fifo[0] = fdctrl->fifo[1];
1685 fdctrl_set_fifo(fdctrl, 1, 1);
1686 }
1687
1688 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1689 {
1690 /* No result back */
1691 fdctrl_reset_fifo(fdctrl);
1692 }
1693
1694 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1695 {
1696 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1697
1698 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1699 /* Command parameters done */
1700 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1701 fdctrl->fifo[0] = fdctrl->fifo[1];
1702 fdctrl->fifo[2] = 0;
1703 fdctrl->fifo[3] = 0;
1704 fdctrl_set_fifo(fdctrl, 4, 1);
1705 } else {
1706 fdctrl_reset_fifo(fdctrl);
1707 }
1708 } else if (fdctrl->data_len > 7) {
1709 /* ERROR */
1710 fdctrl->fifo[0] = 0x80 |
1711 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1712 fdctrl_set_fifo(fdctrl, 1, 1);
1713 }
1714 }
1715
1716 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1717 {
1718 fdrive_t *cur_drv;
1719
1720 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1721 cur_drv = get_cur_drv(fdctrl);
1722 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1723 cur_drv->track = cur_drv->max_track - 1;
1724 } else {
1725 cur_drv->track += fdctrl->fifo[2];
1726 }
1727 fdctrl_reset_fifo(fdctrl);
1728 /* Raise Interrupt */
1729 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1730 }
1731
1732 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1733 {
1734 fdrive_t *cur_drv;
1735
1736 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1737 cur_drv = get_cur_drv(fdctrl);
1738 if (fdctrl->fifo[2] > cur_drv->track) {
1739 cur_drv->track = 0;
1740 } else {
1741 cur_drv->track -= fdctrl->fifo[2];
1742 }
1743 fdctrl_reset_fifo(fdctrl);
1744 /* Raise Interrupt */
1745 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1746 }
1747
1748 static const struct {
1749 uint8_t value;
1750 uint8_t mask;
1751 const char* name;
1752 int parameters;
1753 void (*handler)(fdctrl_t *fdctrl, int direction);
1754 int direction;
1755 } handlers[] = {
1756 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1757 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1758 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1759 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1760 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1761 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1762 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1763 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1764 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1765 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1766 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1767 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1768 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1769 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1770 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1771 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1772 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1773 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1774 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1775 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1776 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1777 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1778 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1779 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1780 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1781 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1782 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1783 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1784 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1785 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1786 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1787 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1788 };
1789 /* Associate command to an index in the 'handlers' array */
1790 static uint8_t command_to_handler[256];
1791
1792 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1793 {
1794 fdrive_t *cur_drv;
1795 int pos;
1796
1797 /* Reset mode */
1798 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1799 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1800 return;
1801 }
1802 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1803 FLOPPY_ERROR("controller not ready for writing\n");
1804 return;
1805 }
1806 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1807 /* Is it write command time ? */
1808 if (fdctrl->msr & FD_MSR_NONDMA) {
1809 /* FIFO data write */
1810 pos = fdctrl->data_pos++;
1811 pos %= FD_SECTOR_LEN;
1812 fdctrl->fifo[pos] = value;
1813 if (pos == FD_SECTOR_LEN - 1 ||
1814 fdctrl->data_pos == fdctrl->data_len) {
1815 cur_drv = get_cur_drv(fdctrl);
1816 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1817 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1818 return;
1819 }
1820 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1821 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1822 fd_sector(cur_drv));
1823 return;
1824 }
1825 }
1826 /* Switch from transfer mode to status mode
1827 * then from status mode to command mode
1828 */
1829 if (fdctrl->data_pos == fdctrl->data_len)
1830 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1831 return;
1832 }
1833 if (fdctrl->data_pos == 0) {
1834 /* Command */
1835 pos = command_to_handler[value & 0xff];
1836 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1837 fdctrl->data_len = handlers[pos].parameters + 1;
1838 }
1839
1840 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1841 fdctrl->fifo[fdctrl->data_pos++] = value;
1842 if (fdctrl->data_pos == fdctrl->data_len) {
1843 /* We now have all parameters
1844 * and will be able to treat the command
1845 */
1846 if (fdctrl->data_state & FD_STATE_FORMAT) {
1847 fdctrl_format_sector(fdctrl);
1848 return;
1849 }
1850
1851 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1852 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1853 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1854 }
1855 }
1856
1857 static void fdctrl_result_timer(void *opaque)
1858 {
1859 fdctrl_t *fdctrl = opaque;
1860 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1861
1862 /* Pretend we are spinning.
1863 * This is needed for Coherent, which uses READ ID to check for
1864 * sector interleaving.
1865 */
1866 if (cur_drv->last_sect != 0) {
1867 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1868 }
1869 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1870 }
1871
1872 /* Init functions */
1873 static void fdctrl_connect_drives(fdctrl_t *fdctrl)
1874 {
1875 unsigned int i;
1876
1877 for (i = 0; i < MAX_FD; i++) {
1878 fd_init(&fdctrl->drives[i]);
1879 fd_revalidate(&fdctrl->drives[i]);
1880 }
1881 }
1882
1883 fdctrl_t *fdctrl_init_isa(DriveInfo **fds)
1884 {
1885 ISADevice *dev;
1886
1887 dev = isa_create("isa-fdc");
1888 qdev_prop_set_drive(&dev->qdev, "driveA", fds[0]);
1889 qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);
1890 if (qdev_init(&dev->qdev) < 0)
1891 return NULL;
1892 return &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
1893 }
1894
1895 fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1896 target_phys_addr_t mmio_base,
1897 DriveInfo **fds)
1898 {
1899 fdctrl_t *fdctrl;
1900 DeviceState *dev;
1901 fdctrl_sysbus_t *sys;
1902
1903 dev = qdev_create(NULL, "sysbus-fdc");
1904 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1905 fdctrl = &sys->state;
1906 fdctrl->dma_chann = dma_chann; /* FIXME */
1907 qdev_prop_set_drive(dev, "driveA", fds[0]);
1908 qdev_prop_set_drive(dev, "driveB", fds[1]);
1909 qdev_init_nofail(dev);
1910 sysbus_connect_irq(&sys->busdev, 0, irq);
1911 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1912
1913 return fdctrl;
1914 }
1915
1916 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1917 DriveInfo **fds, qemu_irq *fdc_tc)
1918 {
1919 DeviceState *dev;
1920 fdctrl_sysbus_t *sys;
1921 fdctrl_t *fdctrl;
1922
1923 dev = qdev_create(NULL, "SUNW,fdtwo");
1924 qdev_prop_set_drive(dev, "drive", fds[0]);
1925 qdev_init_nofail(dev);
1926 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1927 fdctrl = &sys->state;
1928 sysbus_connect_irq(&sys->busdev, 0, irq);
1929 sysbus_mmio_map(&sys->busdev, 0, io_base);
1930 *fdc_tc = qdev_get_gpio_in(dev, 0);
1931
1932 return fdctrl;
1933 }
1934
1935 static int fdctrl_init_common(fdctrl_t *fdctrl)
1936 {
1937 int i, j;
1938 static int command_tables_inited = 0;
1939
1940 /* Fill 'command_to_handler' lookup table */
1941 if (!command_tables_inited) {
1942 command_tables_inited = 1;
1943 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1944 for (j = 0; j < sizeof(command_to_handler); j++) {
1945 if ((j & handlers[i].mask) == handlers[i].value) {
1946 command_to_handler[j] = i;
1947 }
1948 }
1949 }
1950 }
1951
1952 FLOPPY_DPRINTF("init controller\n");
1953 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1954 fdctrl->fifo_size = 512;
1955 fdctrl->result_timer = qemu_new_timer(vm_clock,
1956 fdctrl_result_timer, fdctrl);
1957
1958 fdctrl->version = 0x90; /* Intel 82078 controller */
1959 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1960 fdctrl->num_floppies = MAX_FD;
1961
1962 if (fdctrl->dma_chann != -1)
1963 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1964 fdctrl_connect_drives(fdctrl);
1965
1966 return 0;
1967 }
1968
1969 static int isabus_fdc_init1(ISADevice *dev)
1970 {
1971 fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
1972 fdctrl_t *fdctrl = &isa->state;
1973 int iobase = 0x3f0;
1974 int isairq = 6;
1975 int dma_chann = 2;
1976 int ret;
1977
1978 register_ioport_read(iobase + 0x01, 5, 1,
1979 &fdctrl_read_port, fdctrl);
1980 register_ioport_read(iobase + 0x07, 1, 1,
1981 &fdctrl_read_port, fdctrl);
1982 register_ioport_write(iobase + 0x01, 5, 1,
1983 &fdctrl_write_port, fdctrl);
1984 register_ioport_write(iobase + 0x07, 1, 1,
1985 &fdctrl_write_port, fdctrl);
1986 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1987 fdctrl->dma_chann = dma_chann;
1988
1989 ret = fdctrl_init_common(fdctrl);
1990
1991 return ret;
1992 }
1993
1994 static int sysbus_fdc_init1(SysBusDevice *dev)
1995 {
1996 fdctrl_sysbus_t *sys = DO_UPCAST(fdctrl_sysbus_t, busdev, dev);
1997 fdctrl_t *fdctrl = &sys->state;
1998 int io;
1999 int ret;
2000
2001 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
2002 sysbus_init_mmio(dev, 0x08, io);
2003 sysbus_init_irq(dev, &fdctrl->irq);
2004 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2005 fdctrl->dma_chann = -1;
2006
2007 ret = fdctrl_init_common(fdctrl);
2008
2009 return ret;
2010 }
2011
2012 static int sun4m_fdc_init1(SysBusDevice *dev)
2013 {
2014 fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
2015 int io;
2016
2017 io = cpu_register_io_memory(fdctrl_mem_read_strict,
2018 fdctrl_mem_write_strict, fdctrl);
2019 sysbus_init_mmio(dev, 0x08, io);
2020 sysbus_init_irq(dev, &fdctrl->irq);
2021 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
2022
2023 fdctrl->sun4m = 1;
2024 return fdctrl_init_common(fdctrl);
2025 }
2026
2027 static ISADeviceInfo isa_fdc_info = {
2028 .init = isabus_fdc_init1,
2029 .qdev.name = "isa-fdc",
2030 .qdev.size = sizeof(fdctrl_isabus_t),
2031 .qdev.no_user = 1,
2032 .qdev.vmsd = &vmstate_fdc_isa,
2033 .qdev.reset = fdctrl_external_reset_isa,
2034 .qdev.props = (Property[]) {
2035 DEFINE_PROP_DRIVE("driveA", fdctrl_isabus_t, state.drives[0].dinfo),
2036 DEFINE_PROP_DRIVE("driveB", fdctrl_isabus_t, state.drives[1].dinfo),
2037 DEFINE_PROP_END_OF_LIST(),
2038 },
2039 };
2040
2041 static SysBusDeviceInfo sysbus_fdc_info = {
2042 .init = sysbus_fdc_init1,
2043 .qdev.name = "sysbus-fdc",
2044 .qdev.size = sizeof(fdctrl_sysbus_t),
2045 .qdev.vmsd = &vmstate_fdc_sysbus,
2046 .qdev.reset = fdctrl_external_reset_sysbus,
2047 .qdev.props = (Property[]) {
2048 DEFINE_PROP_DRIVE("driveA", fdctrl_sysbus_t, state.drives[0].dinfo),
2049 DEFINE_PROP_DRIVE("driveB", fdctrl_sysbus_t, state.drives[1].dinfo),
2050 DEFINE_PROP_END_OF_LIST(),
2051 },
2052 };
2053
2054 static SysBusDeviceInfo sun4m_fdc_info = {
2055 .init = sun4m_fdc_init1,
2056 .qdev.name = "SUNW,fdtwo",
2057 .qdev.size = sizeof(fdctrl_sysbus_t),
2058 .qdev.vmsd = &vmstate_fdc_sysbus,
2059 .qdev.reset = fdctrl_external_reset_sysbus,
2060 .qdev.props = (Property[]) {
2061 DEFINE_PROP_DRIVE("drive", fdctrl_sysbus_t, state.drives[0].dinfo),
2062 DEFINE_PROP_END_OF_LIST(),
2063 },
2064 };
2065
2066 static void fdc_register_devices(void)
2067 {
2068 isa_qdev_register(&isa_fdc_info);
2069 sysbus_register_withprop(&sysbus_fdc_info);
2070 sysbus_register_withprop(&sun4m_fdc_info);
2071 }
2072
2073 device_init(fdc_register_devices)
QEmu