hw/ppc_chrp.c

   1 /*
   2  * QEMU PPC CHRP/PMAC hardware System Emulator
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 #define BIOS_FILENAME "ppc_rom.bin"
  27 #define NVRAM_SIZE        0x2000
  28
  29 /* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
  30    NVRAM (not implemented).  */
  31
  32 static int dbdma_mem_index;
  33 static int cuda_mem_index;
  34
  35 /* DBDMA: currently no op - should suffice right now */
  36
  37 static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
  38 {
  39 }
  40
  41 static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
  42 {
  43 }
  44
  45 static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
  46 {
  47 }
  48
  49 static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
  50 {
  51     return 0;
  52 }
  53
  54 static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
  55 {
  56     return 0;
  57 }
  58
  59 static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
  60 {
  61     return 0;
  62 }
  63
  64 static CPUWriteMemoryFunc *dbdma_write[] = {
  65     &dbdma_writeb,
  66     &dbdma_writew,
  67     &dbdma_writel,
  68 };
  69
  70 static CPUReadMemoryFunc *dbdma_read[] = {
  71     &dbdma_readb,
  72     &dbdma_readw,
  73     &dbdma_readl,
  74 };
  75
  76 static void macio_map(PCIDevice *pci_dev, int region_num,
  77                       uint32_t addr, uint32_t size, int type)
  78 {
  79     cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
  80     cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
  81 }
  82
  83 static void macio_init(void)
  84 {
  85     PCIDevice *d;
  86
  87     d = pci_register_device("macio", sizeof(PCIDevice),
  88                             0, -1,
  89                             NULL, NULL);
  90     /* Note: this code is strongly inspirated from the corresponding code
  91        in PearPC */
  92     d->config[0x00] = 0x6b; // vendor_id
  93     d->config[0x01] = 0x10;
  94     d->config[0x02] = 0x17;
  95     d->config[0x03] = 0x00;
  96
  97     d->config[0x0a] = 0x00; // class_sub = pci2pci
  98     d->config[0x0b] = 0xff; // class_base = bridge
  99     d->config[0x0e] = 0x00; // header_type
 100
 101     d->config[0x3d] = 0x01; // interrupt on pin 1
 102
 103     dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
 104
 105     pci_register_io_region(d, 0, 0x80000,
 106                            PCI_ADDRESS_SPACE_MEM, macio_map);
 107 }
 108
 109 /* PowerPC PREP hardware initialisation */
 110 void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
 111                    DisplayState *ds, const char **fd_filename, int snapshot,
 112                    const char *kernel_filename, const char *kernel_cmdline,
 113                    const char *initrd_filename)
 114 {
 115     char buf[1024];
 116     m48t59_t *nvram;
 117     int PPC_io_memory;
 118     int ret, linux_boot, i, fd;
 119     unsigned long bios_offset;
 120
 121     linux_boot = (kernel_filename != NULL);
 122
 123     /* allocate RAM */
 124     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 125
 126     /* allocate and load BIOS */
 127     bios_offset = ram_size + vga_ram_size;
 128     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 129     ret = load_image(buf, phys_ram_base + bios_offset);
 130     if (ret != BIOS_SIZE) {
 131         fprintf(stderr, "qemu: could not load PPC PREP bios '%s'\n", buf);
 132         exit(1);
 133     }
 134     cpu_register_physical_memory((uint32_t)(-BIOS_SIZE),
 135                                  BIOS_SIZE, bios_offset | IO_MEM_ROM);
 136     cpu_single_env->nip = 0xfffffffc;
 137
 138     /* Register CPU as a 74x/75x */
 139     cpu_ppc_register(cpu_single_env, 0x00080000);
 140     /* Set time-base frequency to 100 Mhz */
 141     cpu_ppc_tb_init(cpu_single_env, 100UL * 1000UL * 1000UL);
 142
 143     isa_mem_base = 0xc0000000;
 144     pci_pmac_init();
 145
 146     /* Register 64 KB of ISA IO space */
 147     PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
 148     cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory);
 149     //    cpu_register_physical_memory(0xfe000000, 0xfe010000, PPC_io_memory);
 150
 151     /* init basic PC hardware */
 152     vga_initialize(ds, phys_ram_base + ram_size, ram_size,
 153                    vga_ram_size, 1);
 154     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 155     //    pic_init(openpic);
 156     pic_init();
 157     //    pit = pit_init(0x40, 0);
 158
 159     /* XXX: use Mac Serial port */
 160     fd = serial_open_device();
 161     serial_init(0x3f8, 4, fd);
 162
 163     for(i = 0; i < nb_nics; i++) {
 164         pci_ne2000_init(&nd_table[i]);
 165     }
 166
 167     pci_ide_init(bs_table);
 168
 169     /* cuda also initialize ADB */
 170     cuda_mem_index = cuda_init();
 171
 172     adb_kbd_init(&adb_bus);
 173     adb_mouse_init(&adb_bus);
 174
 175     macio_init();
 176
 177     nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
 178
 179     PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
 180                          0, 0,
 181                          0,
 182                          0,
 183                          0, 0,
 184                          /* XXX: need an option to load a NVRAM image */
 185                          0
 186                          );
 187
 188     /* Special port to get debug messages from Open-Firmware */
 189     register_ioport_write(0xFF00, 0x04, 1, &PREP_debug_write, NULL);
 190     register_ioport_write(0xFF00, 0x04, 2, &PREP_debug_write, NULL);
 191
 192     pci_ppc_bios_init();
 193 }