3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 typedef struct DisasContext
{
44 const XtensaConfig
*config
;
49 int singlestep_enabled
;
53 bool sar_m32_allocated
;
57 static TCGv_ptr cpu_env
;
58 static TCGv_i32 cpu_pc
;
59 static TCGv_i32 cpu_R
[16];
60 static TCGv_i32 cpu_SR
[256];
61 static TCGv_i32 cpu_UR
[256];
63 #include "gen-icount.h"
65 static const char * const sregnames
[256] = {
69 static const char * const uregnames
[256] = {
70 [THREADPTR
] = "THREADPTR",
75 void xtensa_translate_init(void)
77 static const char * const regnames
[] = {
78 "ar0", "ar1", "ar2", "ar3",
79 "ar4", "ar5", "ar6", "ar7",
80 "ar8", "ar9", "ar10", "ar11",
81 "ar12", "ar13", "ar14", "ar15",
85 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
86 cpu_pc
= tcg_global_mem_new_i32(TCG_AREG0
,
87 offsetof(CPUState
, pc
), "pc");
89 for (i
= 0; i
< 16; i
++) {
90 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
91 offsetof(CPUState
, regs
[i
]),
95 for (i
= 0; i
< 256; ++i
) {
97 cpu_SR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
98 offsetof(CPUState
, sregs
[i
]),
103 for (i
= 0; i
< 256; ++i
) {
105 cpu_UR
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
106 offsetof(CPUState
, uregs
[i
]),
114 static inline bool option_enabled(DisasContext
*dc
, int opt
)
116 return xtensa_option_enabled(dc
->config
, opt
);
119 static void init_sar_tracker(DisasContext
*dc
)
121 dc
->sar_5bit
= false;
122 dc
->sar_m32_5bit
= false;
123 dc
->sar_m32_allocated
= false;
126 static void reset_sar_tracker(DisasContext
*dc
)
128 if (dc
->sar_m32_allocated
) {
129 tcg_temp_free(dc
->sar_m32
);
133 static void gen_right_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
135 tcg_gen_andi_i32(cpu_SR
[SAR
], sa
, 0x1f);
136 if (dc
->sar_m32_5bit
) {
137 tcg_gen_discard_i32(dc
->sar_m32
);
140 dc
->sar_m32_5bit
= false;
143 static void gen_left_shift_sar(DisasContext
*dc
, TCGv_i32 sa
)
145 TCGv_i32 tmp
= tcg_const_i32(32);
146 if (!dc
->sar_m32_allocated
) {
147 dc
->sar_m32
= tcg_temp_local_new_i32();
148 dc
->sar_m32_allocated
= true;
150 tcg_gen_andi_i32(dc
->sar_m32
, sa
, 0x1f);
151 tcg_gen_sub_i32(cpu_SR
[SAR
], tmp
, dc
->sar_m32
);
152 dc
->sar_5bit
= false;
153 dc
->sar_m32_5bit
= true;
157 static void gen_exception(int excp
)
159 TCGv_i32 tmp
= tcg_const_i32(excp
);
160 gen_helper_exception(tmp
);
164 static void gen_jump_slot(DisasContext
*dc
, TCGv dest
, int slot
)
166 tcg_gen_mov_i32(cpu_pc
, dest
);
167 if (dc
->singlestep_enabled
) {
168 gen_exception(EXCP_DEBUG
);
171 tcg_gen_goto_tb(slot
);
172 tcg_gen_exit_tb((tcg_target_long
)dc
->tb
+ slot
);
177 dc
->is_jmp
= DISAS_UPDATE
;
180 static void gen_jump(DisasContext
*dc
, TCGv dest
)
182 gen_jump_slot(dc
, dest
, -1);
185 static void gen_jumpi(DisasContext
*dc
, uint32_t dest
, int slot
)
187 TCGv_i32 tmp
= tcg_const_i32(dest
);
188 if (((dc
->pc
^ dest
) & TARGET_PAGE_MASK
) != 0) {
191 gen_jump_slot(dc
, tmp
, slot
);
195 static void gen_brcond(DisasContext
*dc
, TCGCond cond
,
196 TCGv_i32 t0
, TCGv_i32 t1
, uint32_t offset
)
198 int label
= gen_new_label();
200 tcg_gen_brcond_i32(cond
, t0
, t1
, label
);
201 gen_jumpi(dc
, dc
->next_pc
, 0);
202 gen_set_label(label
);
203 gen_jumpi(dc
, dc
->pc
+ offset
, 1);
206 static void gen_brcondi(DisasContext
*dc
, TCGCond cond
,
207 TCGv_i32 t0
, uint32_t t1
, uint32_t offset
)
209 TCGv_i32 tmp
= tcg_const_i32(t1
);
210 gen_brcond(dc
, cond
, t0
, tmp
, offset
);
214 static void gen_rsr(DisasContext
*dc
, TCGv_i32 d
, uint32_t sr
)
216 static void (* const rsr_handler
[256])(DisasContext
*dc
,
217 TCGv_i32 d
, uint32_t sr
) = {
221 if (rsr_handler
[sr
]) {
222 rsr_handler
[sr
](dc
, d
, sr
);
224 tcg_gen_mov_i32(d
, cpu_SR
[sr
]);
227 qemu_log("RSR %d not implemented, ", sr
);
231 static void gen_wsr_sar(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
233 tcg_gen_andi_i32(cpu_SR
[sr
], s
, 0x3f);
234 if (dc
->sar_m32_5bit
) {
235 tcg_gen_discard_i32(dc
->sar_m32
);
237 dc
->sar_5bit
= false;
238 dc
->sar_m32_5bit
= false;
241 static void gen_wsr(DisasContext
*dc
, uint32_t sr
, TCGv_i32 s
)
243 static void (* const wsr_handler
[256])(DisasContext
*dc
,
244 uint32_t sr
, TCGv_i32 v
) = {
249 if (wsr_handler
[sr
]) {
250 wsr_handler
[sr
](dc
, sr
, s
);
252 tcg_gen_mov_i32(cpu_SR
[sr
], s
);
255 qemu_log("WSR %d not implemented, ", sr
);
259 static void disas_xtensa_insn(DisasContext
*dc
)
261 #define HAS_OPTION(opt) do { \
262 if (!option_enabled(dc, opt)) { \
263 qemu_log("Option %d is not enabled %s:%d\n", \
264 (opt), __FILE__, __LINE__); \
265 goto invalid_opcode; \
269 #ifdef TARGET_WORDS_BIGENDIAN
270 #define OP0 (((b0) & 0xf0) >> 4)
271 #define OP1 (((b2) & 0xf0) >> 4)
272 #define OP2 ((b2) & 0xf)
273 #define RRR_R ((b1) & 0xf)
274 #define RRR_S (((b1) & 0xf0) >> 4)
275 #define RRR_T ((b0) & 0xf)
277 #define OP0 (((b0) & 0xf))
278 #define OP1 (((b2) & 0xf))
279 #define OP2 (((b2) & 0xf0) >> 4)
280 #define RRR_R (((b1) & 0xf0) >> 4)
281 #define RRR_S (((b1) & 0xf))
282 #define RRR_T (((b0) & 0xf0) >> 4)
292 #define RRI8_IMM8 (b2)
293 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
295 #ifdef TARGET_WORDS_BIGENDIAN
296 #define RI16_IMM16 (((b1) << 8) | (b2))
298 #define RI16_IMM16 (((b2) << 8) | (b1))
301 #ifdef TARGET_WORDS_BIGENDIAN
302 #define CALL_N (((b0) & 0xc) >> 2)
303 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
305 #define CALL_N (((b0) & 0x30) >> 4)
306 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
308 #define CALL_OFFSET_SE \
309 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
311 #define CALLX_N CALL_N
312 #ifdef TARGET_WORDS_BIGENDIAN
313 #define CALLX_M ((b0) & 0x3)
315 #define CALLX_M (((b0) & 0xc0) >> 6)
317 #define CALLX_S RRR_S
319 #define BRI12_M CALLX_M
320 #define BRI12_S RRR_S
321 #ifdef TARGET_WORDS_BIGENDIAN
322 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
324 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
326 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
328 #define BRI8_M BRI12_M
329 #define BRI8_R RRI8_R
330 #define BRI8_S RRI8_S
331 #define BRI8_IMM8 RRI8_IMM8
332 #define BRI8_IMM8_SE RRI8_IMM8_SE
336 uint8_t b0
= ldub_code(dc
->pc
);
337 uint8_t b1
= ldub_code(dc
->pc
+ 1);
338 uint8_t b2
= ldub_code(dc
->pc
+ 2);
340 static const uint32_t B4CONST
[] = {
341 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
344 static const uint32_t B4CONSTU
[] = {
345 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
349 dc
->next_pc
= dc
->pc
+ 2;
350 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY
);
352 dc
->next_pc
= dc
->pc
+ 3;
361 if ((RRR_R
& 0xc) == 0x8) {
362 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
378 gen_jump(dc
, cpu_R
[CALLX_S
]);
382 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
394 TCGv_i32 tmp
= tcg_temp_new_i32();
395 tcg_gen_mov_i32(tmp
, cpu_R
[CALLX_S
]);
396 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
405 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
413 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
426 tcg_gen_and_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
430 tcg_gen_or_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
434 tcg_gen_xor_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
440 gen_right_shift_sar(dc
, cpu_R
[RRR_S
]);
444 gen_left_shift_sar(dc
, cpu_R
[RRR_S
]);
449 TCGv_i32 tmp
= tcg_temp_new_i32();
450 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
451 gen_right_shift_sar(dc
, tmp
);
458 TCGv_i32 tmp
= tcg_temp_new_i32();
459 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], 3);
460 gen_left_shift_sar(dc
, tmp
);
467 TCGv_i32 tmp
= tcg_const_i32(
468 RRR_S
| ((RRR_T
& 1) << 4));
469 gen_right_shift_sar(dc
, tmp
);
481 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
485 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
486 gen_helper_nsa(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
490 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
491 gen_helper_nsau(cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
494 default: /*reserved*/
505 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
510 int label
= gen_new_label();
511 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
513 TCG_COND_GE
, cpu_R
[RRR_R
], 0, label
);
514 tcg_gen_neg_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
515 gen_set_label(label
);
519 default: /*reserved*/
528 tcg_gen_add_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
535 TCGv_i32 tmp
= tcg_temp_new_i32();
536 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 8);
537 tcg_gen_add_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
543 tcg_gen_sub_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], cpu_R
[RRR_T
]);
550 TCGv_i32 tmp
= tcg_temp_new_i32();
551 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], OP2
- 12);
552 tcg_gen_sub_i32(cpu_R
[RRR_R
], tmp
, cpu_R
[RRR_T
]);
563 tcg_gen_shli_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
],
564 32 - (RRR_T
| ((OP2
& 1) << 4)));
569 tcg_gen_sari_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
],
570 RRR_S
| ((OP2
& 1) << 4));
574 tcg_gen_shri_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], RRR_S
);
579 TCGv_i32 tmp
= tcg_temp_new_i32();
580 tcg_gen_mov_i32(tmp
, cpu_R
[RRR_T
]);
581 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
582 gen_wsr(dc
, RSR_SR
, tmp
);
588 * Note: 64 bit ops are used here solely because SAR values
591 #define gen_shift_reg(cmd, reg) do { \
592 TCGv_i64 tmp = tcg_temp_new_i64(); \
593 tcg_gen_extu_i32_i64(tmp, reg); \
594 tcg_gen_##cmd##_i64(v, v, tmp); \
595 tcg_gen_trunc_i64_i32(cpu_R[RRR_R], v); \
596 tcg_temp_free_i64(v); \
597 tcg_temp_free_i64(tmp); \
600 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
604 TCGv_i64 v
= tcg_temp_new_i64();
605 tcg_gen_concat_i32_i64(v
, cpu_R
[RRR_T
], cpu_R
[RRR_S
]);
612 tcg_gen_shr_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
614 TCGv_i64 v
= tcg_temp_new_i64();
615 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_T
]);
621 if (dc
->sar_m32_5bit
) {
622 tcg_gen_shl_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
], dc
->sar_m32
);
624 TCGv_i64 v
= tcg_temp_new_i64();
625 TCGv_i32 s
= tcg_const_i32(32);
626 tcg_gen_sub_i32(s
, s
, cpu_SR
[SAR
]);
627 tcg_gen_andi_i32(s
, s
, 0x3f);
628 tcg_gen_extu_i32_i64(v
, cpu_R
[RRR_S
]);
629 gen_shift_reg(shl
, s
);
636 tcg_gen_sar_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
], cpu_SR
[SAR
]);
638 TCGv_i64 v
= tcg_temp_new_i64();
639 tcg_gen_ext_i32_i64(v
, cpu_R
[RRR_T
]);
647 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
649 TCGv_i32 v1
= tcg_temp_new_i32();
650 TCGv_i32 v2
= tcg_temp_new_i32();
651 tcg_gen_ext16u_i32(v1
, cpu_R
[RRR_S
]);
652 tcg_gen_ext16u_i32(v2
, cpu_R
[RRR_T
]);
653 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
660 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL
);
662 TCGv_i32 v1
= tcg_temp_new_i32();
663 TCGv_i32 v2
= tcg_temp_new_i32();
664 tcg_gen_ext16s_i32(v1
, cpu_R
[RRR_S
]);
665 tcg_gen_ext16s_i32(v2
, cpu_R
[RRR_T
]);
666 tcg_gen_mul_i32(cpu_R
[RRR_R
], v1
, v2
);
672 default: /*reserved*/
683 gen_rsr(dc
, cpu_R
[RRR_T
], RSR_SR
);
687 gen_wsr(dc
, RSR_SR
, cpu_R
[RRR_T
]);
691 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
693 int shift
= 24 - RRR_T
;
696 tcg_gen_ext8s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
697 } else if (shift
== 16) {
698 tcg_gen_ext16s_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
700 TCGv_i32 tmp
= tcg_temp_new_i32();
701 tcg_gen_shli_i32(tmp
, cpu_R
[RRR_S
], shift
);
702 tcg_gen_sari_i32(cpu_R
[RRR_R
], tmp
, shift
);
709 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
711 TCGv_i32 tmp1
= tcg_temp_new_i32();
712 TCGv_i32 tmp2
= tcg_temp_new_i32();
713 int label
= gen_new_label();
715 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 24 - RRR_T
);
716 tcg_gen_xor_i32(tmp2
, tmp1
, cpu_R
[RRR_S
]);
717 tcg_gen_andi_i32(tmp2
, tmp2
, 0xffffffff << (RRR_T
+ 7));
718 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
719 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp2
, 0, label
);
721 tcg_gen_sari_i32(tmp1
, cpu_R
[RRR_S
], 31);
722 tcg_gen_xori_i32(cpu_R
[RRR_R
], tmp1
,
723 0xffffffff >> (25 - RRR_T
));
725 gen_set_label(label
);
736 HAS_OPTION(XTENSA_OPTION_MISC_OP
);
738 static const TCGCond cond
[] = {
744 int label
= gen_new_label();
746 if (RRR_R
!= RRR_T
) {
747 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
748 tcg_gen_brcond_i32(cond
[OP2
- 4],
749 cpu_R
[RRR_S
], cpu_R
[RRR_T
], label
);
750 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_T
]);
752 tcg_gen_brcond_i32(cond
[OP2
- 4],
753 cpu_R
[RRR_T
], cpu_R
[RRR_S
], label
);
754 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
756 gen_set_label(label
);
765 static const TCGCond cond
[] = {
771 int label
= gen_new_label();
772 tcg_gen_brcondi_i32(cond
[OP2
- 8], cpu_R
[RRR_T
], 0, label
);
773 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_R
[RRR_S
]);
774 gen_set_label(label
);
779 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
783 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
788 int st
= (RRR_S
<< 4) + RRR_T
;
790 tcg_gen_mov_i32(cpu_R
[RRR_R
], cpu_UR
[st
]);
792 qemu_log("RUR %d not implemented, ", st
);
799 if (uregnames
[RSR_SR
]) {
800 tcg_gen_mov_i32(cpu_UR
[RSR_SR
], cpu_R
[RRR_T
]);
802 qemu_log("WUR %d not implemented, ", RSR_SR
);
813 int shiftimm
= RRR_S
| (OP1
<< 4);
814 int maskimm
= (1 << (OP2
+ 1)) - 1;
816 TCGv_i32 tmp
= tcg_temp_new_i32();
817 tcg_gen_shri_i32(tmp
, cpu_R
[RRR_T
], shiftimm
);
818 tcg_gen_andi_i32(cpu_R
[RRR_R
], tmp
, maskimm
);
830 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
837 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
841 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR
);
844 default: /*reserved*/
851 TCGv_i32 tmp
= tcg_const_i32(
852 (0xfffc0000 | (RI16_IMM16
<< 2)) +
853 ((dc
->pc
+ 3) & ~3));
857 tcg_gen_qemu_ld32u(cpu_R
[RRR_T
], tmp
, 0);
866 HAS_OPTION(XTENSA_OPTION_COPROCESSOR
);
870 HAS_OPTION(XTENSA_OPTION_MAC16
);
876 tcg_gen_movi_i32(cpu_R
[0], dc
->next_pc
);
877 gen_jumpi(dc
, (dc
->pc
& ~3) + (CALL_OFFSET_SE
<< 2) + 4, 0);
883 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
891 gen_jumpi(dc
, dc
->pc
+ 4 + CALL_OFFSET_SE
, 0);
896 static const TCGCond cond
[] = {
897 TCG_COND_EQ
, /*BEQZ*/
898 TCG_COND_NE
, /*BNEZ*/
899 TCG_COND_LT
, /*BLTZ*/
900 TCG_COND_GE
, /*BGEZ*/
903 gen_brcondi(dc
, cond
[BRI12_M
& 3], cpu_R
[BRI12_S
], 0,
910 static const TCGCond cond
[] = {
911 TCG_COND_EQ
, /*BEQI*/
912 TCG_COND_NE
, /*BNEI*/
913 TCG_COND_LT
, /*BLTI*/
914 TCG_COND_GE
, /*BGEI*/
917 gen_brcondi(dc
, cond
[BRI8_M
& 3],
918 cpu_R
[BRI8_S
], B4CONST
[BRI8_R
], 4 + BRI8_IMM8_SE
);
925 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER
);
931 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
935 HAS_OPTION(XTENSA_OPTION_BOOLEAN
);
947 default: /*reserved*/
955 gen_brcondi(dc
, BRI8_M
== 2 ? TCG_COND_LTU
: TCG_COND_GEU
,
956 cpu_R
[BRI8_S
], B4CONSTU
[BRI8_R
], 4 + BRI8_IMM8_SE
);
966 TCGCond eq_ne
= (RRI8_R
& 8) ? TCG_COND_NE
: TCG_COND_EQ
;
968 switch (RRI8_R
& 7) {
969 case 0: /*BNONE*/ /*BANY*/
971 TCGv_i32 tmp
= tcg_temp_new_i32();
972 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
973 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
978 case 1: /*BEQ*/ /*BNE*/
979 case 2: /*BLT*/ /*BGE*/
980 case 3: /*BLTU*/ /*BGEU*/
982 static const TCGCond cond
[] = {
990 gen_brcond(dc
, cond
[RRI8_R
], cpu_R
[RRI8_S
], cpu_R
[RRI8_T
],
995 case 4: /*BALL*/ /*BNALL*/
997 TCGv_i32 tmp
= tcg_temp_new_i32();
998 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], cpu_R
[RRI8_T
]);
999 gen_brcond(dc
, eq_ne
, tmp
, cpu_R
[RRI8_T
],
1005 case 5: /*BBC*/ /*BBS*/
1007 TCGv_i32 bit
= tcg_const_i32(1);
1008 TCGv_i32 tmp
= tcg_temp_new_i32();
1009 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_T
], 0x1f);
1010 tcg_gen_shl_i32(bit
, bit
, tmp
);
1011 tcg_gen_and_i32(tmp
, cpu_R
[RRI8_S
], bit
);
1012 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
1018 case 6: /*BBCI*/ /*BBSI*/
1021 TCGv_i32 tmp
= tcg_temp_new_i32();
1022 tcg_gen_andi_i32(tmp
, cpu_R
[RRI8_S
],
1023 1 << (((RRI8_R
& 1) << 4) | RRI8_T
));
1024 gen_brcondi(dc
, eq_ne
, tmp
, 0, 4 + RRI8_IMM8_SE
);
1033 #define gen_narrow_load_store(type) do { \
1034 TCGv_i32 addr = tcg_temp_new_i32(); \
1035 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
1036 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
1037 tcg_temp_free(addr); \
1041 gen_narrow_load_store(ld32u
);
1045 gen_narrow_load_store(st32
);
1047 #undef gen_narrow_load_store
1050 tcg_gen_add_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], cpu_R
[RRRN_T
]);
1053 case 11: /*ADDI.Nn*/
1054 tcg_gen_addi_i32(cpu_R
[RRRN_R
], cpu_R
[RRRN_S
], RRRN_T
? RRRN_T
: -1);
1058 if (RRRN_T
< 8) { /*MOVI.Nn*/
1059 tcg_gen_movi_i32(cpu_R
[RRRN_S
],
1060 RRRN_R
| (RRRN_T
<< 4) |
1061 ((RRRN_T
& 6) == 6 ? 0xffffff80 : 0));
1062 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
1063 TCGCond eq_ne
= (RRRN_T
& 4) ? TCG_COND_NE
: TCG_COND_EQ
;
1065 gen_brcondi(dc
, eq_ne
, cpu_R
[RRRN_S
], 0,
1066 4 + (RRRN_R
| ((RRRN_T
& 3) << 4)));
1073 tcg_gen_mov_i32(cpu_R
[RRRN_T
], cpu_R
[RRRN_S
]);
1079 gen_jump(dc
, cpu_R
[0]);
1085 case 2: /*BREAK.Nn*/
1094 default: /*reserved*/
1099 default: /*reserved*/
1104 default: /*reserved*/
1108 dc
->pc
= dc
->next_pc
;
1112 qemu_log("INVALID(pc = %08x)\n", dc
->pc
);
1113 dc
->pc
= dc
->next_pc
;
1117 static void check_breakpoint(CPUState
*env
, DisasContext
*dc
)
1121 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1122 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1123 if (bp
->pc
== dc
->pc
) {
1124 tcg_gen_movi_i32(cpu_pc
, dc
->pc
);
1125 gen_exception(EXCP_DEBUG
);
1126 dc
->is_jmp
= DISAS_UPDATE
;
1132 static void gen_intermediate_code_internal(
1133 CPUState
*env
, TranslationBlock
*tb
, int search_pc
)
1138 uint16_t *gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1139 int max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1140 uint32_t pc_start
= tb
->pc
;
1141 uint32_t next_page_start
=
1142 (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1144 if (max_insns
== 0) {
1145 max_insns
= CF_COUNT_MASK
;
1148 dc
.config
= env
->config
;
1149 dc
.singlestep_enabled
= env
->singlestep_enabled
;
1152 dc
.is_jmp
= DISAS_NEXT
;
1154 init_sar_tracker(&dc
);
1159 check_breakpoint(env
, &dc
);
1162 j
= gen_opc_ptr
- gen_opc_buf
;
1166 gen_opc_instr_start
[lj
++] = 0;
1169 gen_opc_pc
[lj
] = dc
.pc
;
1170 gen_opc_instr_start
[lj
] = 1;
1171 gen_opc_icount
[lj
] = insn_count
;
1174 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
))) {
1175 tcg_gen_debug_insn_start(dc
.pc
);
1178 disas_xtensa_insn(&dc
);
1180 if (env
->singlestep_enabled
) {
1181 tcg_gen_movi_i32(cpu_pc
, dc
.pc
);
1182 gen_exception(EXCP_DEBUG
);
1185 } while (dc
.is_jmp
== DISAS_NEXT
&&
1186 insn_count
< max_insns
&&
1187 dc
.pc
< next_page_start
&&
1188 gen_opc_ptr
< gen_opc_end
);
1190 reset_sar_tracker(&dc
);
1192 if (dc
.is_jmp
== DISAS_NEXT
) {
1193 gen_jumpi(&dc
, dc
.pc
, 0);
1195 gen_icount_end(tb
, insn_count
);
1196 *gen_opc_ptr
= INDEX_op_end
;
1199 tb
->size
= dc
.pc
- pc_start
;
1200 tb
->icount
= insn_count
;
1204 void gen_intermediate_code(CPUState
*env
, TranslationBlock
*tb
)
1206 gen_intermediate_code_internal(env
, tb
, 0);
1209 void gen_intermediate_code_pc(CPUState
*env
, TranslationBlock
*tb
)
1211 gen_intermediate_code_internal(env
, tb
, 1);
1214 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
1219 cpu_fprintf(f
, "PC=%08x\n\n", env
->pc
);
1221 for (i
= j
= 0; i
< 256; ++i
) {
1223 cpu_fprintf(f
, "%s=%08x%c", sregnames
[i
], env
->sregs
[i
],
1224 (j
++ % 4) == 3 ? '\n' : ' ');
1228 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1230 for (i
= j
= 0; i
< 256; ++i
) {
1232 cpu_fprintf(f
, "%s=%08x%c", uregnames
[i
], env
->uregs
[i
],
1233 (j
++ % 4) == 3 ? '\n' : ' ');
1237 cpu_fprintf(f
, (j
% 4) == 0 ? "\n" : "\n\n");
1239 for (i
= 0; i
< 16; ++i
) {
1240 cpu_fprintf(f
, "A%02d=%08x%c", i
, env
->regs
[i
],
1241 (i
% 4) == 3 ? '\n' : ' ');
1245 void restore_state_to_opc(CPUState
*env
, TranslationBlock
*tb
, int pc_pos
)
1247 env
->pc
= gen_opc_pc
[pc_pos
];