4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
33 #include "qmp-commands.h"
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
39 # define PCI_DPRINTF(format, ...) do { } while (0)
42 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
43 static char *pcibus_get_dev_path(DeviceState
*dev
);
44 static char *pcibus_get_fw_dev_path(DeviceState
*dev
);
45 static int pcibus_reset(BusState
*qbus
);
47 struct BusInfo pci_bus_info
= {
49 .size
= sizeof(PCIBus
),
50 .print_dev
= pcibus_dev_print
,
51 .get_dev_path
= pcibus_get_dev_path
,
52 .get_fw_dev_path
= pcibus_get_fw_dev_path
,
53 .reset
= pcibus_reset
,
54 .props
= (Property
[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice
, romfile
),
57 DEFINE_PROP_UINT32("rombar", PCIDevice
, rom_bar
, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice
, cap_present
,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR
, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice
, cap_present
,
61 QEMU_PCI_CAP_SERR_BITNR
, true),
62 DEFINE_PROP_END_OF_LIST()
66 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
);
67 static void pci_update_mappings(PCIDevice
*d
);
68 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
69 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
);
70 static void pci_del_option_rom(PCIDevice
*pdev
);
72 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
73 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
78 QLIST_ENTRY(PCIHostBus
) next
;
80 static QLIST_HEAD(, PCIHostBus
) host_buses
;
82 static const VMStateDescription vmstate_pcibus
= {
85 .minimum_version_id
= 1,
86 .minimum_version_id_old
= 1,
87 .fields
= (VMStateField
[]) {
88 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
89 VMSTATE_VARRAY_INT32(irq_count
, PCIBus
, nirq
, 0, vmstate_info_int32
, int32_t),
93 static int pci_bar(PCIDevice
*d
, int reg
)
97 if (reg
!= PCI_ROM_SLOT
)
98 return PCI_BASE_ADDRESS_0
+ reg
* 4;
100 type
= d
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
101 return type
== PCI_HEADER_TYPE_BRIDGE
? PCI_ROM_ADDRESS1
: PCI_ROM_ADDRESS
;
104 static inline int pci_irq_state(PCIDevice
*d
, int irq_num
)
106 return (d
->irq_state
>> irq_num
) & 0x1;
109 static inline void pci_set_irq_state(PCIDevice
*d
, int irq_num
, int level
)
111 d
->irq_state
&= ~(0x1 << irq_num
);
112 d
->irq_state
|= level
<< irq_num
;
115 static void pci_change_irq_level(PCIDevice
*pci_dev
, int irq_num
, int change
)
120 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
123 pci_dev
= bus
->parent_dev
;
125 bus
->irq_count
[irq_num
] += change
;
126 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
129 int pci_bus_get_irq_level(PCIBus
*bus
, int irq_num
)
131 assert(irq_num
>= 0);
132 assert(irq_num
< bus
->nirq
);
133 return !!bus
->irq_count
[irq_num
];
136 /* Update interrupt status bit in config space on interrupt
138 static void pci_update_irq_status(PCIDevice
*dev
)
140 if (dev
->irq_state
) {
141 dev
->config
[PCI_STATUS
] |= PCI_STATUS_INTERRUPT
;
143 dev
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
147 void pci_device_deassert_intx(PCIDevice
*dev
)
150 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
151 qemu_set_irq(dev
->irq
[i
], 0);
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
159 void pci_device_reset(PCIDevice
*dev
)
163 qdev_reset_all(&dev
->qdev
);
166 pci_update_irq_status(dev
);
167 pci_device_deassert_intx(dev
);
168 /* Clear all writable bits */
169 pci_word_test_and_clear_mask(dev
->config
+ PCI_COMMAND
,
170 pci_get_word(dev
->wmask
+ PCI_COMMAND
) |
171 pci_get_word(dev
->w1cmask
+ PCI_COMMAND
));
172 pci_word_test_and_clear_mask(dev
->config
+ PCI_STATUS
,
173 pci_get_word(dev
->wmask
+ PCI_STATUS
) |
174 pci_get_word(dev
->w1cmask
+ PCI_STATUS
));
175 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
176 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
177 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
178 PCIIORegion
*region
= &dev
->io_regions
[r
];
183 if (!(region
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
184 region
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
185 pci_set_quad(dev
->config
+ pci_bar(dev
, r
), region
->type
);
187 pci_set_long(dev
->config
+ pci_bar(dev
, r
), region
->type
);
190 pci_update_mappings(dev
);
194 * Trigger pci bus reset under a given bus.
195 * To be called on RST# assert.
197 void pci_bus_reset(PCIBus
*bus
)
201 for (i
= 0; i
< bus
->nirq
; i
++) {
202 bus
->irq_count
[i
] = 0;
204 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
205 if (bus
->devices
[i
]) {
206 pci_device_reset(bus
->devices
[i
]);
211 static int pcibus_reset(BusState
*qbus
)
213 pci_bus_reset(DO_UPCAST(PCIBus
, qbus
, qbus
));
215 /* topology traverse is done by pci_bus_reset().
216 Tell qbus/qdev walker not to traverse the tree */
220 static void pci_host_bus_register(int domain
, PCIBus
*bus
)
222 struct PCIHostBus
*host
;
223 host
= g_malloc0(sizeof(*host
));
224 host
->domain
= domain
;
226 QLIST_INSERT_HEAD(&host_buses
, host
, next
);
229 PCIBus
*pci_find_root_bus(int domain
)
231 struct PCIHostBus
*host
;
233 QLIST_FOREACH(host
, &host_buses
, next
) {
234 if (host
->domain
== domain
) {
242 int pci_find_domain(const PCIBus
*bus
)
245 struct PCIHostBus
*host
;
247 /* obtain root bus */
248 while ((d
= bus
->parent_dev
) != NULL
) {
252 QLIST_FOREACH(host
, &host_buses
, next
) {
253 if (host
->bus
== bus
) {
258 abort(); /* should not be reached */
262 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
264 MemoryRegion
*address_space_mem
,
265 MemoryRegion
*address_space_io
,
268 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
269 assert(PCI_FUNC(devfn_min
) == 0);
270 bus
->devfn_min
= devfn_min
;
271 bus
->address_space_mem
= address_space_mem
;
272 bus
->address_space_io
= address_space_io
;
275 QLIST_INIT(&bus
->child
);
276 pci_host_bus_register(0, bus
); /* for now only pci domain 0 is supported */
278 vmstate_register(NULL
, -1, &vmstate_pcibus
, bus
);
281 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
,
282 MemoryRegion
*address_space_mem
,
283 MemoryRegion
*address_space_io
,
288 bus
= g_malloc0(sizeof(*bus
));
289 bus
->qbus
.qdev_allocated
= 1;
290 pci_bus_new_inplace(bus
, parent
, name
, address_space_mem
,
291 address_space_io
, devfn_min
);
295 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
296 void *irq_opaque
, int nirq
)
298 bus
->set_irq
= set_irq
;
299 bus
->map_irq
= map_irq
;
300 bus
->irq_opaque
= irq_opaque
;
302 bus
->irq_count
= g_malloc0(nirq
* sizeof(bus
->irq_count
[0]));
305 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
, DeviceState
*qdev
)
307 bus
->qbus
.allow_hotplug
= 1;
308 bus
->hotplug
= hotplug
;
309 bus
->hotplug_qdev
= qdev
;
312 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
313 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
315 MemoryRegion
*address_space_mem
,
316 MemoryRegion
*address_space_io
,
317 uint8_t devfn_min
, int nirq
)
321 bus
= pci_bus_new(parent
, name
, address_space_mem
,
322 address_space_io
, devfn_min
);
323 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
327 int pci_bus_num(PCIBus
*s
)
330 return 0; /* pci host bridge */
331 return s
->parent_dev
->config
[PCI_SECONDARY_BUS
];
334 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
336 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
340 assert(size
== pci_config_size(s
));
341 config
= g_malloc(size
);
343 qemu_get_buffer(f
, config
, size
);
344 for (i
= 0; i
< size
; ++i
) {
345 if ((config
[i
] ^ s
->config
[i
]) &
346 s
->cmask
[i
] & ~s
->wmask
[i
] & ~s
->w1cmask
[i
]) {
351 memcpy(s
->config
, config
, size
);
353 pci_update_mappings(s
);
359 /* just put buffer */
360 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
362 const uint8_t **v
= pv
;
363 assert(size
== pci_config_size(container_of(pv
, PCIDevice
, config
)));
364 qemu_put_buffer(f
, *v
, size
);
367 static VMStateInfo vmstate_info_pci_config
= {
368 .name
= "pci config",
369 .get
= get_pci_config_device
,
370 .put
= put_pci_config_device
,
373 static int get_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
375 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
376 uint32_t irq_state
[PCI_NUM_PINS
];
378 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
379 irq_state
[i
] = qemu_get_be32(f
);
380 if (irq_state
[i
] != 0x1 && irq_state
[i
] != 0) {
381 fprintf(stderr
, "irq state %d: must be 0 or 1.\n",
387 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
388 pci_set_irq_state(s
, i
, irq_state
[i
]);
394 static void put_pci_irq_state(QEMUFile
*f
, void *pv
, size_t size
)
397 PCIDevice
*s
= container_of(pv
, PCIDevice
, irq_state
);
399 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
400 qemu_put_be32(f
, pci_irq_state(s
, i
));
404 static VMStateInfo vmstate_info_pci_irq_state
= {
405 .name
= "pci irq state",
406 .get
= get_pci_irq_state
,
407 .put
= put_pci_irq_state
,
410 const VMStateDescription vmstate_pci_device
= {
413 .minimum_version_id
= 1,
414 .minimum_version_id_old
= 1,
415 .fields
= (VMStateField
[]) {
416 VMSTATE_INT32_LE(version_id
, PCIDevice
),
417 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
418 vmstate_info_pci_config
,
419 PCI_CONFIG_SPACE_SIZE
),
420 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
421 vmstate_info_pci_irq_state
,
422 PCI_NUM_PINS
* sizeof(int32_t)),
423 VMSTATE_END_OF_LIST()
427 const VMStateDescription vmstate_pcie_device
= {
430 .minimum_version_id
= 1,
431 .minimum_version_id_old
= 1,
432 .fields
= (VMStateField
[]) {
433 VMSTATE_INT32_LE(version_id
, PCIDevice
),
434 VMSTATE_BUFFER_UNSAFE_INFO(config
, PCIDevice
, 0,
435 vmstate_info_pci_config
,
436 PCIE_CONFIG_SPACE_SIZE
),
437 VMSTATE_BUFFER_UNSAFE_INFO(irq_state
, PCIDevice
, 2,
438 vmstate_info_pci_irq_state
,
439 PCI_NUM_PINS
* sizeof(int32_t)),
440 VMSTATE_END_OF_LIST()
444 static inline const VMStateDescription
*pci_get_vmstate(PCIDevice
*s
)
446 return pci_is_express(s
) ? &vmstate_pcie_device
: &vmstate_pci_device
;
449 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
451 /* Clear interrupt status bit: it is implicit
452 * in irq_state which we are saving.
453 * This makes us compatible with old devices
454 * which never set or clear this bit. */
455 s
->config
[PCI_STATUS
] &= ~PCI_STATUS_INTERRUPT
;
456 vmstate_save_state(f
, pci_get_vmstate(s
), s
);
457 /* Restore the interrupt status bit. */
458 pci_update_irq_status(s
);
461 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
464 ret
= vmstate_load_state(f
, pci_get_vmstate(s
), s
, s
->version_id
);
465 /* Restore the interrupt status bit. */
466 pci_update_irq_status(s
);
470 static void pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
472 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
473 pci_default_sub_vendor_id
);
474 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
475 pci_default_sub_device_id
);
479 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
480 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
482 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
,
483 unsigned int *slotp
, unsigned int *funcp
)
488 unsigned long dom
= 0, bus
= 0;
489 unsigned int slot
= 0;
490 unsigned int func
= 0;
493 val
= strtoul(p
, &e
, 16);
499 val
= strtoul(p
, &e
, 16);
506 val
= strtoul(p
, &e
, 16);
519 val
= strtoul(p
, &e
, 16);
526 /* if funcp == NULL func is 0 */
527 if (dom
> 0xffff || bus
> 0xff || slot
> 0x1f || func
> 7)
541 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
544 /* strip legacy tag */
545 if (!strncmp(addr
, "pci_addr=", 9)) {
548 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
, NULL
)) {
549 monitor_printf(mon
, "Invalid pci address\n");
555 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
562 return pci_find_bus_nr(pci_find_root_bus(0), 0);
565 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
, NULL
) < 0) {
569 *devfnp
= PCI_DEVFN(slot
, 0);
570 return pci_find_bus_nr(pci_find_root_bus(dom
), bus
);
573 static void pci_init_cmask(PCIDevice
*dev
)
575 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
576 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
577 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
578 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
579 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
580 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
581 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
582 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
585 static void pci_init_wmask(PCIDevice
*dev
)
587 int config_size
= pci_config_size(dev
);
589 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
590 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
591 pci_set_word(dev
->wmask
+ PCI_COMMAND
,
592 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
593 PCI_COMMAND_INTX_DISABLE
);
594 if (dev
->cap_present
& QEMU_PCI_CAP_SERR
) {
595 pci_word_test_and_set_mask(dev
->wmask
+ PCI_COMMAND
, PCI_COMMAND_SERR
);
598 memset(dev
->wmask
+ PCI_CONFIG_HEADER_SIZE
, 0xff,
599 config_size
- PCI_CONFIG_HEADER_SIZE
);
602 static void pci_init_w1cmask(PCIDevice
*dev
)
605 * Note: It's okay to set w1cmask even for readonly bits as
606 * long as their value is hardwired to 0.
608 pci_set_word(dev
->w1cmask
+ PCI_STATUS
,
609 PCI_STATUS_PARITY
| PCI_STATUS_SIG_TARGET_ABORT
|
610 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_REC_MASTER_ABORT
|
611 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_DETECTED_PARITY
);
614 static void pci_init_mask_bridge(PCIDevice
*d
)
616 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
617 PCI_SEC_LETENCY_TIMER */
618 memset(d
->wmask
+ PCI_PRIMARY_BUS
, 0xff, 4);
621 d
->wmask
[PCI_IO_BASE
] = PCI_IO_RANGE_MASK
& 0xff;
622 d
->wmask
[PCI_IO_LIMIT
] = PCI_IO_RANGE_MASK
& 0xff;
623 pci_set_word(d
->wmask
+ PCI_MEMORY_BASE
,
624 PCI_MEMORY_RANGE_MASK
& 0xffff);
625 pci_set_word(d
->wmask
+ PCI_MEMORY_LIMIT
,
626 PCI_MEMORY_RANGE_MASK
& 0xffff);
627 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_BASE
,
628 PCI_PREF_RANGE_MASK
& 0xffff);
629 pci_set_word(d
->wmask
+ PCI_PREF_MEMORY_LIMIT
,
630 PCI_PREF_RANGE_MASK
& 0xffff);
632 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
633 memset(d
->wmask
+ PCI_PREF_BASE_UPPER32
, 0xff, 8);
635 /* Supported memory and i/o types */
636 d
->config
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_16
;
637 d
->config
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_16
;
638 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_BASE
,
639 PCI_PREF_RANGE_TYPE_64
);
640 pci_word_test_and_set_mask(d
->config
+ PCI_PREF_MEMORY_LIMIT
,
641 PCI_PREF_RANGE_TYPE_64
);
643 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
644 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
645 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
646 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
647 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
648 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
649 pci_set_word(d
->wmask
+ PCI_BRIDGE_CONTROL
,
650 PCI_BRIDGE_CTL_PARITY
|
651 PCI_BRIDGE_CTL_SERR
|
654 PCI_BRIDGE_CTL_VGA_16BIT
|
655 PCI_BRIDGE_CTL_MASTER_ABORT
|
656 PCI_BRIDGE_CTL_BUS_RESET
|
657 PCI_BRIDGE_CTL_FAST_BACK
|
658 PCI_BRIDGE_CTL_DISCARD
|
659 PCI_BRIDGE_CTL_SEC_DISCARD
|
660 PCI_BRIDGE_CTL_DISCARD_SERR
);
661 /* Below does not do anything as we never set this bit, put here for
663 pci_set_word(d
->w1cmask
+ PCI_BRIDGE_CONTROL
,
664 PCI_BRIDGE_CTL_DISCARD_STATUS
);
665 d
->cmask
[PCI_IO_BASE
] |= PCI_IO_RANGE_TYPE_MASK
;
666 d
->cmask
[PCI_IO_LIMIT
] |= PCI_IO_RANGE_TYPE_MASK
;
667 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_BASE
,
668 PCI_PREF_RANGE_TYPE_MASK
);
669 pci_word_test_and_set_mask(d
->cmask
+ PCI_PREF_MEMORY_LIMIT
,
670 PCI_PREF_RANGE_TYPE_MASK
);
673 static int pci_init_multifunction(PCIBus
*bus
, PCIDevice
*dev
)
675 uint8_t slot
= PCI_SLOT(dev
->devfn
);
678 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
679 dev
->config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
683 * multifunction bit is interpreted in two ways as follows.
684 * - all functions must set the bit to 1.
686 * - function 0 must set the bit, but the rest function (> 0)
687 * is allowed to leave the bit to 0.
688 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
690 * So OS (at least Linux) checks the bit of only function 0,
691 * and doesn't see the bit of function > 0.
693 * The below check allows both interpretation.
695 if (PCI_FUNC(dev
->devfn
)) {
696 PCIDevice
*f0
= bus
->devices
[PCI_DEVFN(slot
, 0)];
697 if (f0
&& !(f0
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
)) {
698 /* function 0 should set multifunction bit */
699 error_report("PCI: single function device can't be populated "
700 "in function %x.%x", slot
, PCI_FUNC(dev
->devfn
));
706 if (dev
->cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
709 /* function 0 indicates single function, so function > 0 must be NULL */
710 for (func
= 1; func
< PCI_FUNC_MAX
; ++func
) {
711 if (bus
->devices
[PCI_DEVFN(slot
, func
)]) {
712 error_report("PCI: %x.0 indicates single function, "
713 "but %x.%x is already populated.",
721 static void pci_config_alloc(PCIDevice
*pci_dev
)
723 int config_size
= pci_config_size(pci_dev
);
725 pci_dev
->config
= g_malloc0(config_size
);
726 pci_dev
->cmask
= g_malloc0(config_size
);
727 pci_dev
->wmask
= g_malloc0(config_size
);
728 pci_dev
->w1cmask
= g_malloc0(config_size
);
729 pci_dev
->used
= g_malloc0(config_size
);
732 static void pci_config_free(PCIDevice
*pci_dev
)
734 g_free(pci_dev
->config
);
735 g_free(pci_dev
->cmask
);
736 g_free(pci_dev
->wmask
);
737 g_free(pci_dev
->w1cmask
);
738 g_free(pci_dev
->used
);
741 /* -1 for devfn means auto assign */
742 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
743 const char *name
, int devfn
)
745 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
746 PCIConfigReadFunc
*config_read
= pc
->config_read
;
747 PCIConfigWriteFunc
*config_write
= pc
->config_write
;
750 for(devfn
= bus
->devfn_min
; devfn
< ARRAY_SIZE(bus
->devices
);
751 devfn
+= PCI_FUNC_MAX
) {
752 if (!bus
->devices
[devfn
])
755 error_report("PCI: no slot/function available for %s, all in use", name
);
758 } else if (bus
->devices
[devfn
]) {
759 error_report("PCI: slot %d function %d not available for %s, in use by %s",
760 PCI_SLOT(devfn
), PCI_FUNC(devfn
), name
, bus
->devices
[devfn
]->name
);
764 pci_dev
->devfn
= devfn
;
765 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
766 pci_dev
->irq_state
= 0;
767 pci_config_alloc(pci_dev
);
769 pci_config_set_vendor_id(pci_dev
->config
, pc
->vendor_id
);
770 pci_config_set_device_id(pci_dev
->config
, pc
->device_id
);
771 pci_config_set_revision(pci_dev
->config
, pc
->revision
);
772 pci_config_set_class(pci_dev
->config
, pc
->class_id
);
774 if (!pc
->is_bridge
) {
775 if (pc
->subsystem_vendor_id
|| pc
->subsystem_id
) {
776 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_VENDOR_ID
,
777 pc
->subsystem_vendor_id
);
778 pci_set_word(pci_dev
->config
+ PCI_SUBSYSTEM_ID
,
781 pci_set_default_subsystem_id(pci_dev
);
784 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
785 assert(!pc
->subsystem_vendor_id
);
786 assert(!pc
->subsystem_id
);
788 pci_init_cmask(pci_dev
);
789 pci_init_wmask(pci_dev
);
790 pci_init_w1cmask(pci_dev
);
792 pci_init_mask_bridge(pci_dev
);
794 if (pci_init_multifunction(bus
, pci_dev
)) {
795 pci_config_free(pci_dev
);
800 config_read
= pci_default_read_config
;
802 config_write
= pci_default_write_config
;
803 pci_dev
->config_read
= config_read
;
804 pci_dev
->config_write
= config_write
;
805 bus
->devices
[devfn
] = pci_dev
;
806 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, PCI_NUM_PINS
);
807 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
811 static void do_pci_unregister_device(PCIDevice
*pci_dev
)
813 qemu_free_irqs(pci_dev
->irq
);
814 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
815 pci_config_free(pci_dev
);
818 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
823 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
824 r
= &pci_dev
->io_regions
[i
];
825 if (!r
->size
|| r
->addr
== PCI_BAR_UNMAPPED
)
827 memory_region_del_subregion(r
->address_space
, r
->memory
);
831 static int pci_unregister_device(DeviceState
*dev
)
833 PCIDevice
*pci_dev
= PCI_DEVICE(dev
);
834 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
838 ret
= pc
->exit(pci_dev
);
842 pci_unregister_io_regions(pci_dev
);
843 pci_del_option_rom(pci_dev
);
844 do_pci_unregister_device(pci_dev
);
848 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
849 uint8_t type
, MemoryRegion
*memory
)
854 pcibus_t size
= memory_region_size(memory
);
856 assert(region_num
>= 0);
857 assert(region_num
< PCI_NUM_REGIONS
);
858 if (size
& (size
-1)) {
859 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
860 "type=0x%x, size=0x%"FMT_PCIBUS
"\n", type
, size
);
864 r
= &pci_dev
->io_regions
[region_num
];
865 r
->addr
= PCI_BAR_UNMAPPED
;
871 addr
= pci_bar(pci_dev
, region_num
);
872 if (region_num
== PCI_ROM_SLOT
) {
873 /* ROM enable bit is writable */
874 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
876 pci_set_long(pci_dev
->config
+ addr
, type
);
877 if (!(r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) &&
878 r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
879 pci_set_quad(pci_dev
->wmask
+ addr
, wmask
);
880 pci_set_quad(pci_dev
->cmask
+ addr
, ~0ULL);
882 pci_set_long(pci_dev
->wmask
+ addr
, wmask
& 0xffffffff);
883 pci_set_long(pci_dev
->cmask
+ addr
, 0xffffffff);
885 pci_dev
->io_regions
[region_num
].memory
= memory
;
886 pci_dev
->io_regions
[region_num
].address_space
887 = type
& PCI_BASE_ADDRESS_SPACE_IO
888 ? pci_dev
->bus
->address_space_io
889 : pci_dev
->bus
->address_space_mem
;
892 pcibus_t
pci_get_bar_addr(PCIDevice
*pci_dev
, int region_num
)
894 return pci_dev
->io_regions
[region_num
].addr
;
897 static pcibus_t
pci_bar_address(PCIDevice
*d
,
898 int reg
, uint8_t type
, pcibus_t size
)
900 pcibus_t new_addr
, last_addr
;
901 int bar
= pci_bar(d
, reg
);
902 uint16_t cmd
= pci_get_word(d
->config
+ PCI_COMMAND
);
904 if (type
& PCI_BASE_ADDRESS_SPACE_IO
) {
905 if (!(cmd
& PCI_COMMAND_IO
)) {
906 return PCI_BAR_UNMAPPED
;
908 new_addr
= pci_get_long(d
->config
+ bar
) & ~(size
- 1);
909 last_addr
= new_addr
+ size
- 1;
910 /* NOTE: we have only 64K ioports on PC */
911 if (last_addr
<= new_addr
|| new_addr
== 0 || last_addr
> UINT16_MAX
) {
912 return PCI_BAR_UNMAPPED
;
917 if (!(cmd
& PCI_COMMAND_MEMORY
)) {
918 return PCI_BAR_UNMAPPED
;
920 if (type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) {
921 new_addr
= pci_get_quad(d
->config
+ bar
);
923 new_addr
= pci_get_long(d
->config
+ bar
);
925 /* the ROM slot has a specific enable bit */
926 if (reg
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
)) {
927 return PCI_BAR_UNMAPPED
;
929 new_addr
&= ~(size
- 1);
930 last_addr
= new_addr
+ size
- 1;
931 /* NOTE: we do not support wrapping */
932 /* XXX: as we cannot support really dynamic
933 mappings, we handle specific values as invalid
935 if (last_addr
<= new_addr
|| new_addr
== 0 ||
936 last_addr
== PCI_BAR_UNMAPPED
) {
937 return PCI_BAR_UNMAPPED
;
940 /* Now pcibus_t is 64bit.
941 * Check if 32 bit BAR wraps around explicitly.
942 * Without this, PC ide doesn't work well.
943 * TODO: remove this work around.
945 if (!(type
& PCI_BASE_ADDRESS_MEM_TYPE_64
) && last_addr
>= UINT32_MAX
) {
946 return PCI_BAR_UNMAPPED
;
950 * OS is allowed to set BAR beyond its addressable
951 * bits. For example, 32 bit OS can set 64bit bar
952 * to >4G. Check it. TODO: we might need to support
953 * it in the future for e.g. PAE.
955 if (last_addr
>= TARGET_PHYS_ADDR_MAX
) {
956 return PCI_BAR_UNMAPPED
;
962 static void pci_update_mappings(PCIDevice
*d
)
968 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
969 r
= &d
->io_regions
[i
];
971 /* this region isn't registered */
975 new_addr
= pci_bar_address(d
, i
, r
->type
, r
->size
);
977 /* This bar isn't changed */
978 if (new_addr
== r
->addr
)
981 /* now do the real mapping */
982 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
983 memory_region_del_subregion(r
->address_space
, r
->memory
);
986 if (r
->addr
!= PCI_BAR_UNMAPPED
) {
987 memory_region_add_subregion_overlap(r
->address_space
,
988 r
->addr
, r
->memory
, 1);
993 static inline int pci_irq_disabled(PCIDevice
*d
)
995 return pci_get_word(d
->config
+ PCI_COMMAND
) & PCI_COMMAND_INTX_DISABLE
;
998 /* Called after interrupt disabled field update in config space,
999 * assert/deassert interrupts if necessary.
1000 * Gets original interrupt disable bit value (before update). */
1001 static void pci_update_irq_disabled(PCIDevice
*d
, int was_irq_disabled
)
1003 int i
, disabled
= pci_irq_disabled(d
);
1004 if (disabled
== was_irq_disabled
)
1006 for (i
= 0; i
< PCI_NUM_PINS
; ++i
) {
1007 int state
= pci_irq_state(d
, i
);
1008 pci_change_irq_level(d
, i
, disabled
? -state
: state
);
1012 uint32_t pci_default_read_config(PCIDevice
*d
,
1013 uint32_t address
, int len
)
1017 memcpy(&val
, d
->config
+ address
, len
);
1018 return le32_to_cpu(val
);
1021 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
1023 int i
, was_irq_disabled
= pci_irq_disabled(d
);
1025 for (i
= 0; i
< l
; val
>>= 8, ++i
) {
1026 uint8_t wmask
= d
->wmask
[addr
+ i
];
1027 uint8_t w1cmask
= d
->w1cmask
[addr
+ i
];
1028 assert(!(wmask
& w1cmask
));
1029 d
->config
[addr
+ i
] = (d
->config
[addr
+ i
] & ~wmask
) | (val
& wmask
);
1030 d
->config
[addr
+ i
] &= ~(val
& w1cmask
); /* W1C: Write 1 to Clear */
1032 if (ranges_overlap(addr
, l
, PCI_BASE_ADDRESS_0
, 24) ||
1033 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS
, 4) ||
1034 ranges_overlap(addr
, l
, PCI_ROM_ADDRESS1
, 4) ||
1035 range_covers_byte(addr
, l
, PCI_COMMAND
))
1036 pci_update_mappings(d
);
1038 if (range_covers_byte(addr
, l
, PCI_COMMAND
))
1039 pci_update_irq_disabled(d
, was_irq_disabled
);
1042 /***********************************************************/
1043 /* generic PCI irq support */
1045 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1046 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
1048 PCIDevice
*pci_dev
= opaque
;
1051 change
= level
- pci_irq_state(pci_dev
, irq_num
);
1055 pci_set_irq_state(pci_dev
, irq_num
, level
);
1056 pci_update_irq_status(pci_dev
);
1057 if (pci_irq_disabled(pci_dev
))
1059 pci_change_irq_level(pci_dev
, irq_num
, change
);
1062 /***********************************************************/
1063 /* monitor info on PCI */
1068 const char *fw_name
;
1069 uint16_t fw_ign_bits
;
1072 static const pci_class_desc pci_class_descriptions
[] =
1074 { 0x0001, "VGA controller", "display"},
1075 { 0x0100, "SCSI controller", "scsi"},
1076 { 0x0101, "IDE controller", "ide"},
1077 { 0x0102, "Floppy controller", "fdc"},
1078 { 0x0103, "IPI controller", "ipi"},
1079 { 0x0104, "RAID controller", "raid"},
1080 { 0x0106, "SATA controller"},
1081 { 0x0107, "SAS controller"},
1082 { 0x0180, "Storage controller"},
1083 { 0x0200, "Ethernet controller", "ethernet"},
1084 { 0x0201, "Token Ring controller", "token-ring"},
1085 { 0x0202, "FDDI controller", "fddi"},
1086 { 0x0203, "ATM controller", "atm"},
1087 { 0x0280, "Network controller"},
1088 { 0x0300, "VGA controller", "display", 0x00ff},
1089 { 0x0301, "XGA controller"},
1090 { 0x0302, "3D controller"},
1091 { 0x0380, "Display controller"},
1092 { 0x0400, "Video controller", "video"},
1093 { 0x0401, "Audio controller", "sound"},
1095 { 0x0403, "Audio controller", "sound"},
1096 { 0x0480, "Multimedia controller"},
1097 { 0x0500, "RAM controller", "memory"},
1098 { 0x0501, "Flash controller", "flash"},
1099 { 0x0580, "Memory controller"},
1100 { 0x0600, "Host bridge", "host"},
1101 { 0x0601, "ISA bridge", "isa"},
1102 { 0x0602, "EISA bridge", "eisa"},
1103 { 0x0603, "MC bridge", "mca"},
1104 { 0x0604, "PCI bridge", "pci"},
1105 { 0x0605, "PCMCIA bridge", "pcmcia"},
1106 { 0x0606, "NUBUS bridge", "nubus"},
1107 { 0x0607, "CARDBUS bridge", "cardbus"},
1108 { 0x0608, "RACEWAY bridge"},
1109 { 0x0680, "Bridge"},
1110 { 0x0700, "Serial port", "serial"},
1111 { 0x0701, "Parallel port", "parallel"},
1112 { 0x0800, "Interrupt controller", "interrupt-controller"},
1113 { 0x0801, "DMA controller", "dma-controller"},
1114 { 0x0802, "Timer", "timer"},
1115 { 0x0803, "RTC", "rtc"},
1116 { 0x0900, "Keyboard", "keyboard"},
1117 { 0x0901, "Pen", "pen"},
1118 { 0x0902, "Mouse", "mouse"},
1119 { 0x0A00, "Dock station", "dock", 0x00ff},
1120 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1121 { 0x0c00, "Fireware contorller", "fireware"},
1122 { 0x0c01, "Access bus controller", "access-bus"},
1123 { 0x0c02, "SSA controller", "ssa"},
1124 { 0x0c03, "USB controller", "usb"},
1125 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1129 static void pci_for_each_device_under_bus(PCIBus
*bus
,
1130 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1135 for(devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1136 d
= bus
->devices
[devfn
];
1143 void pci_for_each_device(PCIBus
*bus
, int bus_num
,
1144 void (*fn
)(PCIBus
*b
, PCIDevice
*d
))
1146 bus
= pci_find_bus_nr(bus
, bus_num
);
1149 pci_for_each_device_under_bus(bus
, fn
);
1153 static const pci_class_desc
*get_class_desc(int class)
1155 const pci_class_desc
*desc
;
1157 desc
= pci_class_descriptions
;
1158 while (desc
->desc
&& class != desc
->class) {
1165 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
);
1167 static PciMemoryRegionList
*qmp_query_pci_regions(const PCIDevice
*dev
)
1169 PciMemoryRegionList
*head
= NULL
, *cur_item
= NULL
;
1172 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1173 const PCIIORegion
*r
= &dev
->io_regions
[i
];
1174 PciMemoryRegionList
*region
;
1180 region
= g_malloc0(sizeof(*region
));
1181 region
->value
= g_malloc0(sizeof(*region
->value
));
1183 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
1184 region
->value
->type
= g_strdup("io");
1186 region
->value
->type
= g_strdup("memory");
1187 region
->value
->has_prefetch
= true;
1188 region
->value
->prefetch
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_PREFETCH
);
1189 region
->value
->has_mem_type_64
= true;
1190 region
->value
->mem_type_64
= !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
1193 region
->value
->bar
= i
;
1194 region
->value
->address
= r
->addr
;
1195 region
->value
->size
= r
->size
;
1197 /* XXX: waiting for the qapi to support GSList */
1199 head
= cur_item
= region
;
1201 cur_item
->next
= region
;
1209 static PciBridgeInfo
*qmp_query_pci_bridge(PCIDevice
*dev
, PCIBus
*bus
,
1212 PciBridgeInfo
*info
;
1214 info
= g_malloc0(sizeof(*info
));
1216 info
->bus
.number
= dev
->config
[PCI_PRIMARY_BUS
];
1217 info
->bus
.secondary
= dev
->config
[PCI_SECONDARY_BUS
];
1218 info
->bus
.subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
1220 info
->bus
.io_range
= g_malloc0(sizeof(*info
->bus
.io_range
));
1221 info
->bus
.io_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1222 info
->bus
.io_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
1224 info
->bus
.memory_range
= g_malloc0(sizeof(*info
->bus
.memory_range
));
1225 info
->bus
.memory_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1226 info
->bus
.memory_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
1228 info
->bus
.prefetchable_range
= g_malloc0(sizeof(*info
->bus
.prefetchable_range
));
1229 info
->bus
.prefetchable_range
->base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1230 info
->bus
.prefetchable_range
->limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
1232 if (dev
->config
[PCI_SECONDARY_BUS
] != 0) {
1233 PCIBus
*child_bus
= pci_find_bus_nr(bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1235 info
->has_devices
= true;
1236 info
->devices
= qmp_query_pci_devices(child_bus
, dev
->config
[PCI_SECONDARY_BUS
]);
1243 static PciDeviceInfo
*qmp_query_pci_device(PCIDevice
*dev
, PCIBus
*bus
,
1246 const pci_class_desc
*desc
;
1247 PciDeviceInfo
*info
;
1251 info
= g_malloc0(sizeof(*info
));
1252 info
->bus
= bus_num
;
1253 info
->slot
= PCI_SLOT(dev
->devfn
);
1254 info
->function
= PCI_FUNC(dev
->devfn
);
1256 class = pci_get_word(dev
->config
+ PCI_CLASS_DEVICE
);
1257 info
->class_info
.class = class;
1258 desc
= get_class_desc(class);
1260 info
->class_info
.has_desc
= true;
1261 info
->class_info
.desc
= g_strdup(desc
->desc
);
1264 info
->id
.vendor
= pci_get_word(dev
->config
+ PCI_VENDOR_ID
);
1265 info
->id
.device
= pci_get_word(dev
->config
+ PCI_DEVICE_ID
);
1266 info
->regions
= qmp_query_pci_regions(dev
);
1267 info
->qdev_id
= g_strdup(dev
->qdev
.id
? dev
->qdev
.id
: "");
1269 if (dev
->config
[PCI_INTERRUPT_PIN
] != 0) {
1270 info
->has_irq
= true;
1271 info
->irq
= dev
->config
[PCI_INTERRUPT_LINE
];
1274 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
1275 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
1276 info
->has_pci_bridge
= true;
1277 info
->pci_bridge
= qmp_query_pci_bridge(dev
, bus
, bus_num
);
1283 static PciDeviceInfoList
*qmp_query_pci_devices(PCIBus
*bus
, int bus_num
)
1285 PciDeviceInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1289 for (devfn
= 0; devfn
< ARRAY_SIZE(bus
->devices
); devfn
++) {
1290 dev
= bus
->devices
[devfn
];
1292 info
= g_malloc0(sizeof(*info
));
1293 info
->value
= qmp_query_pci_device(dev
, bus
, bus_num
);
1295 /* XXX: waiting for the qapi to support GSList */
1297 head
= cur_item
= info
;
1299 cur_item
->next
= info
;
1308 static PciInfo
*qmp_query_pci_bus(PCIBus
*bus
, int bus_num
)
1310 PciInfo
*info
= NULL
;
1312 bus
= pci_find_bus_nr(bus
, bus_num
);
1314 info
= g_malloc0(sizeof(*info
));
1315 info
->bus
= bus_num
;
1316 info
->devices
= qmp_query_pci_devices(bus
, bus_num
);
1322 PciInfoList
*qmp_query_pci(Error
**errp
)
1324 PciInfoList
*info
, *head
= NULL
, *cur_item
= NULL
;
1325 struct PCIHostBus
*host
;
1327 QLIST_FOREACH(host
, &host_buses
, next
) {
1328 info
= g_malloc0(sizeof(*info
));
1329 info
->value
= qmp_query_pci_bus(host
->bus
, 0);
1331 /* XXX: waiting for the qapi to support GSList */
1333 head
= cur_item
= info
;
1335 cur_item
->next
= info
;
1343 static const char * const pci_nic_models
[] = {
1355 static const char * const pci_nic_names
[] = {
1367 /* Initialize a PCI NIC. */
1368 /* FIXME callers should check for failure, but don't */
1369 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
1370 const char *default_devaddr
)
1372 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
1379 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
1383 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
1385 error_report("Invalid PCI device address %s for device %s",
1386 devaddr
, pci_nic_names
[i
]);
1390 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
1391 dev
= &pci_dev
->qdev
;
1392 qdev_set_nic_properties(dev
, nd
);
1393 if (qdev_init(dev
) < 0)
1398 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
1399 const char *default_devaddr
)
1403 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
1406 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
1412 /* Whether a given bus number is in range of the secondary
1413 * bus of the given bridge device. */
1414 static bool pci_secondary_bus_in_range(PCIDevice
*dev
, int bus_num
)
1416 return !(pci_get_word(dev
->config
+ PCI_BRIDGE_CONTROL
) &
1417 PCI_BRIDGE_CTL_BUS_RESET
) /* Don't walk the bus if it's reset. */ &&
1418 dev
->config
[PCI_SECONDARY_BUS
] < bus_num
&&
1419 bus_num
<= dev
->config
[PCI_SUBORDINATE_BUS
];
1422 static PCIBus
*pci_find_bus_nr(PCIBus
*bus
, int bus_num
)
1430 if (pci_bus_num(bus
) == bus_num
) {
1434 /* Consider all bus numbers in range for the host pci bridge. */
1435 if (bus
->parent_dev
&&
1436 !pci_secondary_bus_in_range(bus
->parent_dev
, bus_num
)) {
1441 for (; bus
; bus
= sec
) {
1442 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
1443 assert(sec
->parent_dev
);
1444 if (sec
->parent_dev
->config
[PCI_SECONDARY_BUS
] == bus_num
) {
1447 if (pci_secondary_bus_in_range(sec
->parent_dev
, bus_num
)) {
1456 PCIDevice
*pci_find_device(PCIBus
*bus
, int bus_num
, uint8_t devfn
)
1458 bus
= pci_find_bus_nr(bus
, bus_num
);
1463 return bus
->devices
[devfn
];
1466 static int pci_qdev_init(DeviceState
*qdev
)
1468 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
1469 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(pci_dev
);
1472 bool is_default_rom
;
1474 /* initialize cap_present for pci_is_express() and pci_config_size() */
1475 if (pc
->is_express
) {
1476 pci_dev
->cap_present
|= QEMU_PCI_CAP_EXPRESS
;
1479 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
1480 pci_dev
= do_pci_register_device(pci_dev
, bus
,
1481 object_get_typename(OBJECT(qdev
)),
1483 if (pci_dev
== NULL
)
1485 if (qdev
->hotplugged
&& pc
->no_hotplug
) {
1486 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(pci_dev
)));
1487 do_pci_unregister_device(pci_dev
);
1491 rc
= pc
->init(pci_dev
);
1493 do_pci_unregister_device(pci_dev
);
1499 is_default_rom
= false;
1500 if (pci_dev
->romfile
== NULL
&& pc
->romfile
!= NULL
) {
1501 pci_dev
->romfile
= g_strdup(pc
->romfile
);
1502 is_default_rom
= true;
1504 pci_add_option_rom(pci_dev
, is_default_rom
);
1507 /* Let buses differentiate between hotplug and when device is
1508 * enabled during qemu machine creation. */
1509 rc
= bus
->hotplug(bus
->hotplug_qdev
, pci_dev
,
1510 qdev
->hotplugged
? PCI_HOTPLUG_ENABLED
:
1511 PCI_COLDPLUG_ENABLED
);
1513 int r
= pci_unregister_device(&pci_dev
->qdev
);
1521 static int pci_unplug_device(DeviceState
*qdev
)
1523 PCIDevice
*dev
= PCI_DEVICE(qdev
);
1524 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1526 if (pc
->no_hotplug
) {
1527 qerror_report(QERR_DEVICE_NO_HOTPLUG
, object_get_typename(OBJECT(dev
)));
1530 return dev
->bus
->hotplug(dev
->bus
->hotplug_qdev
, dev
,
1531 PCI_HOTPLUG_DISABLED
);
1534 PCIDevice
*pci_create_multifunction(PCIBus
*bus
, int devfn
, bool multifunction
,
1539 dev
= qdev_create(&bus
->qbus
, name
);
1540 qdev_prop_set_int32(dev
, "addr", devfn
);
1541 qdev_prop_set_bit(dev
, "multifunction", multifunction
);
1542 return PCI_DEVICE(dev
);
1545 PCIDevice
*pci_create_simple_multifunction(PCIBus
*bus
, int devfn
,
1549 PCIDevice
*dev
= pci_create_multifunction(bus
, devfn
, multifunction
, name
);
1550 qdev_init_nofail(&dev
->qdev
);
1554 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1556 return pci_create_multifunction(bus
, devfn
, false, name
);
1559 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1561 return pci_create_simple_multifunction(bus
, devfn
, false, name
);
1564 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1566 int config_size
= pci_config_size(pdev
);
1567 int offset
= PCI_CONFIG_HEADER_SIZE
;
1569 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< config_size
; ++i
)
1572 else if (i
- offset
+ 1 == size
)
1577 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1582 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1585 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1586 prev
= next
+ PCI_CAP_LIST_NEXT
)
1587 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1595 static uint8_t pci_find_capability_at_offset(PCIDevice
*pdev
, uint8_t offset
)
1597 uint8_t next
, prev
, found
= 0;
1599 if (!(pdev
->used
[offset
])) {
1603 assert(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
);
1605 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1606 prev
= next
+ PCI_CAP_LIST_NEXT
) {
1607 if (next
<= offset
&& next
> found
) {
1614 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1615 This is needed for an option rom which is used for more than one device. */
1616 static void pci_patch_ids(PCIDevice
*pdev
, uint8_t *ptr
, int size
)
1620 uint16_t rom_vendor_id
;
1621 uint16_t rom_device_id
;
1623 uint16_t pcir_offset
;
1626 /* Words in rom data are little endian (like in PCI configuration),
1627 so they can be read / written with pci_get_word / pci_set_word. */
1629 /* Only a valid rom will be patched. */
1630 rom_magic
= pci_get_word(ptr
);
1631 if (rom_magic
!= 0xaa55) {
1632 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic
);
1635 pcir_offset
= pci_get_word(ptr
+ 0x18);
1636 if (pcir_offset
+ 8 >= size
|| memcmp(ptr
+ pcir_offset
, "PCIR", 4)) {
1637 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset
);
1641 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1642 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1643 rom_vendor_id
= pci_get_word(ptr
+ pcir_offset
+ 4);
1644 rom_device_id
= pci_get_word(ptr
+ pcir_offset
+ 6);
1646 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev
->romfile
,
1647 vendor_id
, device_id
, rom_vendor_id
, rom_device_id
);
1651 if (vendor_id
!= rom_vendor_id
) {
1652 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1653 checksum
+= (uint8_t)rom_vendor_id
+ (uint8_t)(rom_vendor_id
>> 8);
1654 checksum
-= (uint8_t)vendor_id
+ (uint8_t)(vendor_id
>> 8);
1655 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1657 pci_set_word(ptr
+ pcir_offset
+ 4, vendor_id
);
1660 if (device_id
!= rom_device_id
) {
1661 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1662 checksum
+= (uint8_t)rom_device_id
+ (uint8_t)(rom_device_id
>> 8);
1663 checksum
-= (uint8_t)device_id
+ (uint8_t)(device_id
>> 8);
1664 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr
[6], checksum
);
1666 pci_set_word(ptr
+ pcir_offset
+ 6, device_id
);
1670 /* Add an option rom for the device */
1671 static int pci_add_option_rom(PCIDevice
*pdev
, bool is_default_rom
)
1677 const VMStateDescription
*vmsd
;
1681 if (strlen(pdev
->romfile
) == 0)
1684 if (!pdev
->rom_bar
) {
1686 * Load rom via fw_cfg instead of creating a rom bar,
1687 * for 0.11 compatibility.
1689 int class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1690 if (class == 0x0300) {
1691 rom_add_vga(pdev
->romfile
);
1693 rom_add_option(pdev
->romfile
, -1);
1698 path
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, pdev
->romfile
);
1700 path
= g_strdup(pdev
->romfile
);
1703 size
= get_image_size(path
);
1705 error_report("%s: failed to find romfile \"%s\"",
1706 __FUNCTION__
, pdev
->romfile
);
1710 if (size
& (size
- 1)) {
1711 size
= 1 << qemu_fls(size
);
1714 vmsd
= qdev_get_vmsd(DEVICE(pdev
));
1717 snprintf(name
, sizeof(name
), "%s.rom", vmsd
->name
);
1719 snprintf(name
, sizeof(name
), "%s.rom", object_get_typename(OBJECT(pdev
)));
1721 pdev
->has_rom
= true;
1722 memory_region_init_ram(&pdev
->rom
, name
, size
);
1723 vmstate_register_ram(&pdev
->rom
, &pdev
->qdev
);
1724 ptr
= memory_region_get_ram_ptr(&pdev
->rom
);
1725 load_image(path
, ptr
);
1728 if (is_default_rom
) {
1729 /* Only the default rom images will be patched (if needed). */
1730 pci_patch_ids(pdev
, ptr
, size
);
1733 qemu_put_ram_ptr(ptr
);
1735 pci_register_bar(pdev
, PCI_ROM_SLOT
, 0, &pdev
->rom
);
1740 static void pci_del_option_rom(PCIDevice
*pdev
)
1745 vmstate_unregister_ram(&pdev
->rom
, &pdev
->qdev
);
1746 memory_region_destroy(&pdev
->rom
);
1747 pdev
->has_rom
= false;
1752 * Reserve space and add capability to the linked list in pci config space
1755 * Find and reserve space and add capability to the linked list
1756 * in pci config space */
1757 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
,
1758 uint8_t offset
, uint8_t size
)
1761 int i
, overlapping_cap
;
1764 offset
= pci_find_space(pdev
, size
);
1769 /* Verify that capabilities don't overlap. Note: device assignment
1770 * depends on this check to verify that the device is not broken.
1771 * Should never trigger for emulated devices, but it's helpful
1772 * for debugging these. */
1773 for (i
= offset
; i
< offset
+ size
; i
++) {
1774 overlapping_cap
= pci_find_capability_at_offset(pdev
, i
);
1775 if (overlapping_cap
) {
1776 fprintf(stderr
, "ERROR: %04x:%02x:%02x.%x "
1777 "Attempt to add PCI capability %x at offset "
1778 "%x overlaps existing capability %x at offset %x\n",
1779 pci_find_domain(pdev
->bus
), pci_bus_num(pdev
->bus
),
1780 PCI_SLOT(pdev
->devfn
), PCI_FUNC(pdev
->devfn
),
1781 cap_id
, offset
, overlapping_cap
, i
);
1787 config
= pdev
->config
+ offset
;
1788 config
[PCI_CAP_LIST_ID
] = cap_id
;
1789 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1790 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1791 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1792 memset(pdev
->used
+ offset
, 0xFF, size
);
1793 /* Make capability read-only by default */
1794 memset(pdev
->wmask
+ offset
, 0, size
);
1795 /* Check capability by default */
1796 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1800 /* Unlink capability from the pci config space. */
1801 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1803 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1806 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1807 /* Make capability writable again */
1808 memset(pdev
->wmask
+ offset
, 0xff, size
);
1809 memset(pdev
->w1cmask
+ offset
, 0, size
);
1810 /* Clear cmask as device-specific registers can't be checked */
1811 memset(pdev
->cmask
+ offset
, 0, size
);
1812 memset(pdev
->used
+ offset
, 0, size
);
1814 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1815 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1818 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1820 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1823 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1825 PCIDevice
*d
= (PCIDevice
*)dev
;
1826 const pci_class_desc
*desc
;
1831 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1832 desc
= pci_class_descriptions
;
1833 while (desc
->desc
&& class != desc
->class)
1836 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1838 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1841 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1842 "pci id %04x:%04x (sub %04x:%04x)\n",
1843 indent
, "", ctxt
, pci_bus_num(d
->bus
),
1844 PCI_SLOT(d
->devfn
), PCI_FUNC(d
->devfn
),
1845 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1846 pci_get_word(d
->config
+ PCI_DEVICE_ID
),
1847 pci_get_word(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
),
1848 pci_get_word(d
->config
+ PCI_SUBSYSTEM_ID
));
1849 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1850 r
= &d
->io_regions
[i
];
1853 monitor_printf(mon
, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1854 " [0x%"FMT_PCIBUS
"]\n",
1856 i
, r
->type
& PCI_BASE_ADDRESS_SPACE_IO
? "i/o" : "mem",
1857 r
->addr
, r
->addr
+ r
->size
- 1);
1861 static char *pci_dev_fw_name(DeviceState
*dev
, char *buf
, int len
)
1863 PCIDevice
*d
= (PCIDevice
*)dev
;
1864 const char *name
= NULL
;
1865 const pci_class_desc
*desc
= pci_class_descriptions
;
1866 int class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
1868 while (desc
->desc
&&
1869 (class & ~desc
->fw_ign_bits
) !=
1870 (desc
->class & ~desc
->fw_ign_bits
)) {
1875 name
= desc
->fw_name
;
1879 pstrcpy(buf
, len
, name
);
1881 snprintf(buf
, len
, "pci%04x,%04x",
1882 pci_get_word(d
->config
+ PCI_VENDOR_ID
),
1883 pci_get_word(d
->config
+ PCI_DEVICE_ID
));
1889 static char *pcibus_get_fw_dev_path(DeviceState
*dev
)
1891 PCIDevice
*d
= (PCIDevice
*)dev
;
1892 char path
[50], name
[33];
1895 off
= snprintf(path
, sizeof(path
), "%s@%x",
1896 pci_dev_fw_name(dev
, name
, sizeof name
),
1897 PCI_SLOT(d
->devfn
));
1898 if (PCI_FUNC(d
->devfn
))
1899 snprintf(path
+ off
, sizeof(path
) + off
, ",%x", PCI_FUNC(d
->devfn
));
1900 return strdup(path
);
1903 static char *pcibus_get_dev_path(DeviceState
*dev
)
1905 PCIDevice
*d
= container_of(dev
, PCIDevice
, qdev
);
1908 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
1909 * 00 is added here to make this format compatible with
1910 * domain:Bus:Slot.Func for systems without nested PCI bridges.
1911 * Slot.Function list specifies the slot and function numbers for all
1912 * devices on the path from root to the specific device. */
1913 char domain
[] = "DDDD:00";
1914 char slot
[] = ":SS.F";
1915 int domain_len
= sizeof domain
- 1 /* For '\0' */;
1916 int slot_len
= sizeof slot
- 1 /* For '\0' */;
1921 /* Calculate # of slots on path between device and root. */;
1923 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
1927 path_len
= domain_len
+ slot_len
* slot_depth
;
1929 /* Allocate memory, fill in the terminating null byte. */
1930 path
= g_malloc(path_len
+ 1 /* For '\0' */);
1931 path
[path_len
] = '\0';
1933 /* First field is the domain. */
1934 s
= snprintf(domain
, sizeof domain
, "%04x:00", pci_find_domain(d
->bus
));
1935 assert(s
== domain_len
);
1936 memcpy(path
, domain
, domain_len
);
1938 /* Fill in slot numbers. We walk up from device to root, so need to print
1939 * them in the reverse order, last to first. */
1940 p
= path
+ path_len
;
1941 for (t
= d
; t
; t
= t
->bus
->parent_dev
) {
1943 s
= snprintf(slot
, sizeof slot
, ":%02x.%x",
1944 PCI_SLOT(t
->devfn
), PCI_FUNC(t
->devfn
));
1945 assert(s
== slot_len
);
1946 memcpy(p
, slot
, slot_len
);
1952 static int pci_qdev_find_recursive(PCIBus
*bus
,
1953 const char *id
, PCIDevice
**pdev
)
1955 DeviceState
*qdev
= qdev_find_recursive(&bus
->qbus
, id
);
1960 /* roughly check if given qdev is pci device */
1961 if (object_dynamic_cast(OBJECT(qdev
), TYPE_PCI_DEVICE
)) {
1962 *pdev
= PCI_DEVICE(qdev
);
1968 int pci_qdev_find_device(const char *id
, PCIDevice
**pdev
)
1970 struct PCIHostBus
*host
;
1973 QLIST_FOREACH(host
, &host_buses
, next
) {
1974 int tmp
= pci_qdev_find_recursive(host
->bus
, id
, pdev
);
1979 if (tmp
!= -ENODEV
) {
1987 MemoryRegion
*pci_address_space(PCIDevice
*dev
)
1989 return dev
->bus
->address_space_mem
;
1992 MemoryRegion
*pci_address_space_io(PCIDevice
*dev
)
1994 return dev
->bus
->address_space_io
;
1997 static void pci_device_class_init(ObjectClass
*klass
, void *data
)
1999 DeviceClass
*k
= DEVICE_CLASS(klass
);
2000 k
->init
= pci_qdev_init
;
2001 k
->unplug
= pci_unplug_device
;
2002 k
->exit
= pci_unregister_device
;
2003 k
->bus_info
= &pci_bus_info
;
2006 static TypeInfo pci_device_type_info
= {
2007 .name
= TYPE_PCI_DEVICE
,
2008 .parent
= TYPE_DEVICE
,
2009 .instance_size
= sizeof(PCIDevice
),
2011 .class_size
= sizeof(PCIDeviceClass
),
2012 .class_init
= pci_device_class_init
,
2015 static void pci_register_types(void)
2017 type_register_static(&pci_device_type_info
);
2020 type_init(pci_register_types
)