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xen_platform: SUSE xenlinux unplug for emulated PCI
[qemu.git] / target-i386 / cpu.c
blobd95514c7dd43b41c21fec57b442773fe73aacda6
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/cutils.h"
21
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/cpus.h"
26 #include "kvm_i386.h"
27
28 #include "qemu/error-report.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #if defined(CONFIG_KVM)
39 #include <linux/kvm_para.h>
40 #endif
41
42 #include "sysemu/sysemu.h"
43 #include "hw/qdev-properties.h"
44 #include "hw/i386/topology.h"
45 #ifndef CONFIG_USER_ONLY
46 #include "exec/address-spaces.h"
47 #include "hw/hw.h"
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
50 #endif
51
52
53 /* Cache topology CPUID constants: */
54
55 /* CPUID Leaf 2 Descriptors */
56
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
60 #define CPUID_2_L3_16MB_16WAY_64B 0x4d
61
62
63 /* CPUID Leaf 4 constants: */
64
65 /* EAX: */
66 #define CPUID_4_TYPE_DCACHE 1
67 #define CPUID_4_TYPE_ICACHE 2
68 #define CPUID_4_TYPE_UNIFIED 3
69
70 #define CPUID_4_LEVEL(l) ((l) << 5)
71
72 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73 #define CPUID_4_FULLY_ASSOC (1 << 9)
74
75 /* EDX: */
76 #define CPUID_4_NO_INVD_SHARING (1 << 0)
77 #define CPUID_4_INCLUSIVE (1 << 1)
78 #define CPUID_4_COMPLEX_IDX (1 << 2)
79
80 #define ASSOC_FULL 0xFF
81
82 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97 /* Definitions of the hardcoded cache entries we expose: */
98
99 /* L1 data cache: */
100 #define L1D_LINE_SIZE 64
101 #define L1D_ASSOCIATIVITY 8
102 #define L1D_SETS 64
103 #define L1D_PARTITIONS 1
104 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107 #define L1D_LINES_PER_TAG 1
108 #define L1D_SIZE_KB_AMD 64
109 #define L1D_ASSOCIATIVITY_AMD 2
110
111 /* L1 instruction cache: */
112 #define L1I_LINE_SIZE 64
113 #define L1I_ASSOCIATIVITY 8
114 #define L1I_SETS 64
115 #define L1I_PARTITIONS 1
116 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119 #define L1I_LINES_PER_TAG 1
120 #define L1I_SIZE_KB_AMD 64
121 #define L1I_ASSOCIATIVITY_AMD 2
122
123 /* Level 2 unified cache: */
124 #define L2_LINE_SIZE 64
125 #define L2_ASSOCIATIVITY 16
126 #define L2_SETS 4096
127 #define L2_PARTITIONS 1
128 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132 #define L2_LINES_PER_TAG 1
133 #define L2_SIZE_KB_AMD 512
134
135 /* Level 3 unified cache: */
136 #define L3_SIZE_KB 0 /* disabled */
137 #define L3_ASSOCIATIVITY 0 /* disabled */
138 #define L3_LINES_PER_TAG 0 /* disabled */
139 #define L3_LINE_SIZE 0 /* disabled */
140 #define L3_N_LINE_SIZE 64
141 #define L3_N_ASSOCIATIVITY 16
142 #define L3_N_SETS 16384
143 #define L3_N_PARTITIONS 1
144 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145 #define L3_N_LINES_PER_TAG 1
146 #define L3_N_SIZE_KB_AMD 16384
147
148 /* TLB definitions: */
149
150 #define L1_DTLB_2M_ASSOC 1
151 #define L1_DTLB_2M_ENTRIES 255
152 #define L1_DTLB_4K_ASSOC 1
153 #define L1_DTLB_4K_ENTRIES 255
154
155 #define L1_ITLB_2M_ASSOC 1
156 #define L1_ITLB_2M_ENTRIES 255
157 #define L1_ITLB_4K_ASSOC 1
158 #define L1_ITLB_4K_ENTRIES 255
159
160 #define L2_DTLB_2M_ASSOC 0 /* disabled */
161 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
162 #define L2_DTLB_4K_ASSOC 4
163 #define L2_DTLB_4K_ENTRIES 512
164
165 #define L2_ITLB_2M_ASSOC 0 /* disabled */
166 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
167 #define L2_ITLB_4K_ASSOC 4
168 #define L2_ITLB_4K_ENTRIES 512
169
170
171
172 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174 {
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182 }
183
184 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
216
217 #ifdef TARGET_X86_64
218 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219 #else
220 #define TCG_EXT2_X86_64_FEATURES 0
221 #endif
222
223 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229 #define TCG_EXT4_FEATURES 0
230 #define TCG_SVM_FEATURES 0
231 #define TCG_KVM_FEATURES 0
232 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
237 /* missing:
238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
240 CPUID_7_0_EBX_RDSEED */
241 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
242 #define TCG_APM_FEATURES 0
243 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
244 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
245 /* missing:
246 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
247
248 typedef struct FeatureWordInfo {
249 /* feature flags names are taken from "Intel Processor Identification and
250 * the CPUID Instruction" and AMD's "CPUID Specification".
251 * In cases of disagreement between feature naming conventions,
252 * aliases may be added.
253 */
254 const char *feat_names[32];
255 uint32_t cpuid_eax; /* Input EAX for CPUID */
256 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
257 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
258 int cpuid_reg; /* output register (R_* constant) */
259 uint32_t tcg_features; /* Feature flags supported by TCG */
260 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
261 uint32_t migratable_flags; /* Feature flags known to be migratable */
262 } FeatureWordInfo;
263
264 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
265 [FEAT_1_EDX] = {
266 .feat_names = {
267 "fpu", "vme", "de", "pse",
268 "tsc", "msr", "pae", "mce",
269 "cx8", "apic", NULL, "sep",
270 "mtrr", "pge", "mca", "cmov",
271 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
272 NULL, "ds" /* Intel dts */, "acpi", "mmx",
273 "fxsr", "sse", "sse2", "ss",
274 "ht" /* Intel htt */, "tm", "ia64", "pbe",
275 },
276 .cpuid_eax = 1, .cpuid_reg = R_EDX,
277 .tcg_features = TCG_FEATURES,
278 },
279 [FEAT_1_ECX] = {
280 .feat_names = {
281 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
282 "ds-cpl", "vmx", "smx", "est",
283 "tm2", "ssse3", "cid", NULL,
284 "fma", "cx16", "xtpr", "pdcm",
285 NULL, "pcid", "dca", "sse4.1",
286 "sse4.2", "x2apic", "movbe", "popcnt",
287 "tsc-deadline", "aes", "xsave", "osxsave",
288 "avx", "f16c", "rdrand", "hypervisor",
289 },
290 .cpuid_eax = 1, .cpuid_reg = R_ECX,
291 .tcg_features = TCG_EXT_FEATURES,
292 },
293 /* Feature names that are already defined on feature_name[] but
294 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
295 * names on feat_names below. They are copied automatically
296 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
297 */
298 [FEAT_8000_0001_EDX] = {
299 .feat_names = {
300 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
301 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
302 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
303 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
304 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
305 "nx", NULL, "mmxext", NULL /* mmx */,
306 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
307 NULL, "lm", "3dnowext", "3dnow",
308 },
309 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
310 .tcg_features = TCG_EXT2_FEATURES,
311 },
312 [FEAT_8000_0001_ECX] = {
313 .feat_names = {
314 "lahf-lm", "cmp-legacy", "svm", "extapic",
315 "cr8legacy", "abm", "sse4a", "misalignsse",
316 "3dnowprefetch", "osvw", "ibs", "xop",
317 "skinit", "wdt", NULL, "lwp",
318 "fma4", "tce", NULL, "nodeid-msr",
319 NULL, "tbm", "topoext", "perfctr-core",
320 "perfctr-nb", NULL, NULL, NULL,
321 NULL, NULL, NULL, NULL,
322 },
323 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
324 .tcg_features = TCG_EXT3_FEATURES,
325 },
326 [FEAT_C000_0001_EDX] = {
327 .feat_names = {
328 NULL, NULL, "xstore", "xstore-en",
329 NULL, NULL, "xcrypt", "xcrypt-en",
330 "ace2", "ace2-en", "phe", "phe-en",
331 "pmm", "pmm-en", NULL, NULL,
332 NULL, NULL, NULL, NULL,
333 NULL, NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 },
337 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
338 .tcg_features = TCG_EXT4_FEATURES,
339 },
340 [FEAT_KVM] = {
341 .feat_names = {
342 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
343 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
344 NULL, NULL, NULL, NULL,
345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 "kvmclock-stable-bit", NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 },
351 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
352 .tcg_features = TCG_KVM_FEATURES,
353 },
354 [FEAT_HYPERV_EAX] = {
355 .feat_names = {
356 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
357 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
358 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
359 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
360 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
361 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
362 NULL, NULL, NULL, NULL,
363 NULL, NULL, NULL, NULL,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 },
368 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
369 },
370 [FEAT_HYPERV_EBX] = {
371 .feat_names = {
372 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
373 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
374 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
375 NULL /* hv_create_port */, NULL /* hv_connect_port */,
376 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
377 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
378 NULL, NULL,
379 NULL, NULL, NULL, NULL,
380 NULL, NULL, NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL,
383 },
384 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
385 },
386 [FEAT_HYPERV_EDX] = {
387 .feat_names = {
388 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
389 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
390 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
391 NULL, NULL,
392 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
393 NULL, NULL, NULL, NULL,
394 NULL, NULL, NULL, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 },
399 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
400 },
401 [FEAT_SVM] = {
402 .feat_names = {
403 "npt", "lbrv", "svm-lock", "nrip-save",
404 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
405 NULL, NULL, "pause-filter", NULL,
406 "pfthreshold", NULL, NULL, NULL,
407 NULL, NULL, NULL, NULL,
408 NULL, NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 NULL, NULL, NULL, NULL,
411 },
412 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
413 .tcg_features = TCG_SVM_FEATURES,
414 },
415 [FEAT_7_0_EBX] = {
416 .feat_names = {
417 "fsgsbase", "tsc-adjust", NULL, "bmi1",
418 "hle", "avx2", NULL, "smep",
419 "bmi2", "erms", "invpcid", "rtm",
420 NULL, NULL, "mpx", NULL,
421 "avx512f", "avx512dq", "rdseed", "adx",
422 "smap", "avx512ifma", "pcommit", "clflushopt",
423 "clwb", NULL, "avx512pf", "avx512er",
424 "avx512cd", NULL, "avx512bw", "avx512vl",
425 },
426 .cpuid_eax = 7,
427 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
428 .cpuid_reg = R_EBX,
429 .tcg_features = TCG_7_0_EBX_FEATURES,
430 },
431 [FEAT_7_0_ECX] = {
432 .feat_names = {
433 NULL, "avx512vbmi", "umip", "pku",
434 "ospke", NULL, NULL, NULL,
435 NULL, NULL, NULL, NULL,
436 NULL, NULL, NULL, NULL,
437 NULL, NULL, NULL, NULL,
438 NULL, NULL, "rdpid", NULL,
439 NULL, NULL, NULL, NULL,
440 NULL, NULL, NULL, NULL,
441 },
442 .cpuid_eax = 7,
443 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
444 .cpuid_reg = R_ECX,
445 .tcg_features = TCG_7_0_ECX_FEATURES,
446 },
447 [FEAT_8000_0007_EDX] = {
448 .feat_names = {
449 NULL, NULL, NULL, NULL,
450 NULL, NULL, NULL, NULL,
451 "invtsc", NULL, NULL, NULL,
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 },
458 .cpuid_eax = 0x80000007,
459 .cpuid_reg = R_EDX,
460 .tcg_features = TCG_APM_FEATURES,
461 .unmigratable_flags = CPUID_APM_INVTSC,
462 },
463 [FEAT_XSAVE] = {
464 .feat_names = {
465 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
466 NULL, NULL, NULL, NULL,
467 NULL, NULL, NULL, NULL,
468 NULL, NULL, NULL, NULL,
469 NULL, NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 },
474 .cpuid_eax = 0xd,
475 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
476 .cpuid_reg = R_EAX,
477 .tcg_features = TCG_XSAVE_FEATURES,
478 },
479 [FEAT_6_EAX] = {
480 .feat_names = {
481 NULL, NULL, "arat", NULL,
482 NULL, NULL, NULL, NULL,
483 NULL, NULL, NULL, NULL,
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 },
490 .cpuid_eax = 6, .cpuid_reg = R_EAX,
491 .tcg_features = TCG_6_EAX_FEATURES,
492 },
493 [FEAT_XSAVE_COMP_LO] = {
494 .cpuid_eax = 0xD,
495 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
496 .cpuid_reg = R_EAX,
497 .tcg_features = ~0U,
498 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
499 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
500 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
501 XSTATE_PKRU_MASK,
502 },
503 [FEAT_XSAVE_COMP_HI] = {
504 .cpuid_eax = 0xD,
505 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
506 .cpuid_reg = R_EDX,
507 .tcg_features = ~0U,
508 },
509 };
510
511 typedef struct X86RegisterInfo32 {
512 /* Name of register */
513 const char *name;
514 /* QAPI enum value register */
515 X86CPURegister32 qapi_enum;
516 } X86RegisterInfo32;
517
518 #define REGISTER(reg) \
519 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
520 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
521 REGISTER(EAX),
522 REGISTER(ECX),
523 REGISTER(EDX),
524 REGISTER(EBX),
525 REGISTER(ESP),
526 REGISTER(EBP),
527 REGISTER(ESI),
528 REGISTER(EDI),
529 };
530 #undef REGISTER
531
532 typedef struct ExtSaveArea {
533 uint32_t feature, bits;
534 uint32_t offset, size;
535 } ExtSaveArea;
536
537 static const ExtSaveArea x86_ext_save_areas[] = {
538 [XSTATE_FP_BIT] = {
539 /* x87 FP state component is always enabled if XSAVE is supported */
540 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
541 /* x87 state is in the legacy region of the XSAVE area */
542 .offset = 0,
543 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
544 },
545 [XSTATE_SSE_BIT] = {
546 /* SSE state component is always enabled if XSAVE is supported */
547 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
548 /* SSE state is in the legacy region of the XSAVE area */
549 .offset = 0,
550 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
551 },
552 [XSTATE_YMM_BIT] =
553 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
554 .offset = offsetof(X86XSaveArea, avx_state),
555 .size = sizeof(XSaveAVX) },
556 [XSTATE_BNDREGS_BIT] =
557 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
558 .offset = offsetof(X86XSaveArea, bndreg_state),
559 .size = sizeof(XSaveBNDREG) },
560 [XSTATE_BNDCSR_BIT] =
561 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
562 .offset = offsetof(X86XSaveArea, bndcsr_state),
563 .size = sizeof(XSaveBNDCSR) },
564 [XSTATE_OPMASK_BIT] =
565 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
566 .offset = offsetof(X86XSaveArea, opmask_state),
567 .size = sizeof(XSaveOpmask) },
568 [XSTATE_ZMM_Hi256_BIT] =
569 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
570 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
571 .size = sizeof(XSaveZMM_Hi256) },
572 [XSTATE_Hi16_ZMM_BIT] =
573 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
574 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
575 .size = sizeof(XSaveHi16_ZMM) },
576 [XSTATE_PKRU_BIT] =
577 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
578 .offset = offsetof(X86XSaveArea, pkru_state),
579 .size = sizeof(XSavePKRU) },
580 };
581
582 static uint32_t xsave_area_size(uint64_t mask)
583 {
584 int i;
585 uint64_t ret = 0;
586
587 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
588 const ExtSaveArea *esa = &x86_ext_save_areas[i];
589 if ((mask >> i) & 1) {
590 ret = MAX(ret, esa->offset + esa->size);
591 }
592 }
593 return ret;
594 }
595
596 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
597 {
598 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
599 cpu->env.features[FEAT_XSAVE_COMP_LO];
600 }
601
602 const char *get_register_name_32(unsigned int reg)
603 {
604 if (reg >= CPU_NB_REGS32) {
605 return NULL;
606 }
607 return x86_reg_info_32[reg].name;
608 }
609
610 /*
611 * Returns the set of feature flags that are supported and migratable by
612 * QEMU, for a given FeatureWord.
613 */
614 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
615 {
616 FeatureWordInfo *wi = &feature_word_info[w];
617 uint32_t r = 0;
618 int i;
619
620 for (i = 0; i < 32; i++) {
621 uint32_t f = 1U << i;
622
623 /* If the feature name is known, it is implicitly considered migratable,
624 * unless it is explicitly set in unmigratable_flags */
625 if ((wi->migratable_flags & f) ||
626 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
627 r |= f;
628 }
629 }
630 return r;
631 }
632
633 void host_cpuid(uint32_t function, uint32_t count,
634 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
635 {
636 uint32_t vec[4];
637
638 #ifdef __x86_64__
639 asm volatile("cpuid"
640 : "=a"(vec[0]), "=b"(vec[1]),
641 "=c"(vec[2]), "=d"(vec[3])
642 : "0"(function), "c"(count) : "cc");
643 #elif defined(__i386__)
644 asm volatile("pusha \n\t"
645 "cpuid \n\t"
646 "mov %%eax, 0(%2) \n\t"
647 "mov %%ebx, 4(%2) \n\t"
648 "mov %%ecx, 8(%2) \n\t"
649 "mov %%edx, 12(%2) \n\t"
650 "popa"
651 : : "a"(function), "c"(count), "S"(vec)
652 : "memory", "cc");
653 #else
654 abort();
655 #endif
656
657 if (eax)
658 *eax = vec[0];
659 if (ebx)
660 *ebx = vec[1];
661 if (ecx)
662 *ecx = vec[2];
663 if (edx)
664 *edx = vec[3];
665 }
666
667 /* CPU class name definitions: */
668
669 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
670 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
671
672 /* Return type name for a given CPU model name
673 * Caller is responsible for freeing the returned string.
674 */
675 static char *x86_cpu_type_name(const char *model_name)
676 {
677 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
678 }
679
680 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
681 {
682 ObjectClass *oc;
683 char *typename;
684
685 if (cpu_model == NULL) {
686 return NULL;
687 }
688
689 typename = x86_cpu_type_name(cpu_model);
690 oc = object_class_by_name(typename);
691 g_free(typename);
692 return oc;
693 }
694
695 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
696 {
697 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
698 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
699 return g_strndup(class_name,
700 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
701 }
702
703 struct X86CPUDefinition {
704 const char *name;
705 uint32_t level;
706 uint32_t xlevel;
707 /* vendor is zero-terminated, 12 character ASCII string */
708 char vendor[CPUID_VENDOR_SZ + 1];
709 int family;
710 int model;
711 int stepping;
712 FeatureWordArray features;
713 char model_id[48];
714 };
715
716 static X86CPUDefinition builtin_x86_defs[] = {
717 {
718 .name = "qemu64",
719 .level = 0xd,
720 .vendor = CPUID_VENDOR_AMD,
721 .family = 6,
722 .model = 6,
723 .stepping = 3,
724 .features[FEAT_1_EDX] =
725 PPRO_FEATURES |
726 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
727 CPUID_PSE36,
728 .features[FEAT_1_ECX] =
729 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
730 .features[FEAT_8000_0001_EDX] =
731 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
732 .features[FEAT_8000_0001_ECX] =
733 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
734 .xlevel = 0x8000000A,
735 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
736 },
737 {
738 .name = "phenom",
739 .level = 5,
740 .vendor = CPUID_VENDOR_AMD,
741 .family = 16,
742 .model = 2,
743 .stepping = 3,
744 /* Missing: CPUID_HT */
745 .features[FEAT_1_EDX] =
746 PPRO_FEATURES |
747 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
748 CPUID_PSE36 | CPUID_VME,
749 .features[FEAT_1_ECX] =
750 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
751 CPUID_EXT_POPCNT,
752 .features[FEAT_8000_0001_EDX] =
753 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
754 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
755 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
756 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
757 CPUID_EXT3_CR8LEG,
758 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
759 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
760 .features[FEAT_8000_0001_ECX] =
761 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
762 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
763 /* Missing: CPUID_SVM_LBRV */
764 .features[FEAT_SVM] =
765 CPUID_SVM_NPT,
766 .xlevel = 0x8000001A,
767 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
768 },
769 {
770 .name = "core2duo",
771 .level = 10,
772 .vendor = CPUID_VENDOR_INTEL,
773 .family = 6,
774 .model = 15,
775 .stepping = 11,
776 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
777 .features[FEAT_1_EDX] =
778 PPRO_FEATURES |
779 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
780 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
781 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
782 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
783 .features[FEAT_1_ECX] =
784 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
785 CPUID_EXT_CX16,
786 .features[FEAT_8000_0001_EDX] =
787 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
788 .features[FEAT_8000_0001_ECX] =
789 CPUID_EXT3_LAHF_LM,
790 .xlevel = 0x80000008,
791 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
792 },
793 {
794 .name = "kvm64",
795 .level = 0xd,
796 .vendor = CPUID_VENDOR_INTEL,
797 .family = 15,
798 .model = 6,
799 .stepping = 1,
800 /* Missing: CPUID_HT */
801 .features[FEAT_1_EDX] =
802 PPRO_FEATURES | CPUID_VME |
803 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
804 CPUID_PSE36,
805 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
806 .features[FEAT_1_ECX] =
807 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
808 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
809 .features[FEAT_8000_0001_EDX] =
810 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
811 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
812 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
813 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
814 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
815 .features[FEAT_8000_0001_ECX] =
816 0,
817 .xlevel = 0x80000008,
818 .model_id = "Common KVM processor"
819 },
820 {
821 .name = "qemu32",
822 .level = 4,
823 .vendor = CPUID_VENDOR_INTEL,
824 .family = 6,
825 .model = 6,
826 .stepping = 3,
827 .features[FEAT_1_EDX] =
828 PPRO_FEATURES,
829 .features[FEAT_1_ECX] =
830 CPUID_EXT_SSE3,
831 .xlevel = 0x80000004,
832 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
833 },
834 {
835 .name = "kvm32",
836 .level = 5,
837 .vendor = CPUID_VENDOR_INTEL,
838 .family = 15,
839 .model = 6,
840 .stepping = 1,
841 .features[FEAT_1_EDX] =
842 PPRO_FEATURES | CPUID_VME |
843 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
844 .features[FEAT_1_ECX] =
845 CPUID_EXT_SSE3,
846 .features[FEAT_8000_0001_ECX] =
847 0,
848 .xlevel = 0x80000008,
849 .model_id = "Common 32-bit KVM processor"
850 },
851 {
852 .name = "coreduo",
853 .level = 10,
854 .vendor = CPUID_VENDOR_INTEL,
855 .family = 6,
856 .model = 14,
857 .stepping = 8,
858 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
859 .features[FEAT_1_EDX] =
860 PPRO_FEATURES | CPUID_VME |
861 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
862 CPUID_SS,
863 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
864 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
865 .features[FEAT_1_ECX] =
866 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
867 .features[FEAT_8000_0001_EDX] =
868 CPUID_EXT2_NX,
869 .xlevel = 0x80000008,
870 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
871 },
872 {
873 .name = "486",
874 .level = 1,
875 .vendor = CPUID_VENDOR_INTEL,
876 .family = 4,
877 .model = 8,
878 .stepping = 0,
879 .features[FEAT_1_EDX] =
880 I486_FEATURES,
881 .xlevel = 0,
882 },
883 {
884 .name = "pentium",
885 .level = 1,
886 .vendor = CPUID_VENDOR_INTEL,
887 .family = 5,
888 .model = 4,
889 .stepping = 3,
890 .features[FEAT_1_EDX] =
891 PENTIUM_FEATURES,
892 .xlevel = 0,
893 },
894 {
895 .name = "pentium2",
896 .level = 2,
897 .vendor = CPUID_VENDOR_INTEL,
898 .family = 6,
899 .model = 5,
900 .stepping = 2,
901 .features[FEAT_1_EDX] =
902 PENTIUM2_FEATURES,
903 .xlevel = 0,
904 },
905 {
906 .name = "pentium3",
907 .level = 3,
908 .vendor = CPUID_VENDOR_INTEL,
909 .family = 6,
910 .model = 7,
911 .stepping = 3,
912 .features[FEAT_1_EDX] =
913 PENTIUM3_FEATURES,
914 .xlevel = 0,
915 },
916 {
917 .name = "athlon",
918 .level = 2,
919 .vendor = CPUID_VENDOR_AMD,
920 .family = 6,
921 .model = 2,
922 .stepping = 3,
923 .features[FEAT_1_EDX] =
924 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
925 CPUID_MCA,
926 .features[FEAT_8000_0001_EDX] =
927 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
928 .xlevel = 0x80000008,
929 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
930 },
931 {
932 .name = "n270",
933 .level = 10,
934 .vendor = CPUID_VENDOR_INTEL,
935 .family = 6,
936 .model = 28,
937 .stepping = 2,
938 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
939 .features[FEAT_1_EDX] =
940 PPRO_FEATURES |
941 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
942 CPUID_ACPI | CPUID_SS,
943 /* Some CPUs got no CPUID_SEP */
944 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
945 * CPUID_EXT_XTPR */
946 .features[FEAT_1_ECX] =
947 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
948 CPUID_EXT_MOVBE,
949 .features[FEAT_8000_0001_EDX] =
950 CPUID_EXT2_NX,
951 .features[FEAT_8000_0001_ECX] =
952 CPUID_EXT3_LAHF_LM,
953 .xlevel = 0x80000008,
954 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
955 },
956 {
957 .name = "Conroe",
958 .level = 10,
959 .vendor = CPUID_VENDOR_INTEL,
960 .family = 6,
961 .model = 15,
962 .stepping = 3,
963 .features[FEAT_1_EDX] =
964 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
965 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
966 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
967 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
968 CPUID_DE | CPUID_FP87,
969 .features[FEAT_1_ECX] =
970 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
971 .features[FEAT_8000_0001_EDX] =
972 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
973 .features[FEAT_8000_0001_ECX] =
974 CPUID_EXT3_LAHF_LM,
975 .xlevel = 0x80000008,
976 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
977 },
978 {
979 .name = "Penryn",
980 .level = 10,
981 .vendor = CPUID_VENDOR_INTEL,
982 .family = 6,
983 .model = 23,
984 .stepping = 3,
985 .features[FEAT_1_EDX] =
986 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
987 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
988 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
989 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
990 CPUID_DE | CPUID_FP87,
991 .features[FEAT_1_ECX] =
992 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
993 CPUID_EXT_SSE3,
994 .features[FEAT_8000_0001_EDX] =
995 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
996 .features[FEAT_8000_0001_ECX] =
997 CPUID_EXT3_LAHF_LM,
998 .xlevel = 0x80000008,
999 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1000 },
1001 {
1002 .name = "Nehalem",
1003 .level = 11,
1004 .vendor = CPUID_VENDOR_INTEL,
1005 .family = 6,
1006 .model = 26,
1007 .stepping = 3,
1008 .features[FEAT_1_EDX] =
1009 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1010 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1011 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1012 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1013 CPUID_DE | CPUID_FP87,
1014 .features[FEAT_1_ECX] =
1015 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1016 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1017 .features[FEAT_8000_0001_EDX] =
1018 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1019 .features[FEAT_8000_0001_ECX] =
1020 CPUID_EXT3_LAHF_LM,
1021 .xlevel = 0x80000008,
1022 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1023 },
1024 {
1025 .name = "Westmere",
1026 .level = 11,
1027 .vendor = CPUID_VENDOR_INTEL,
1028 .family = 6,
1029 .model = 44,
1030 .stepping = 1,
1031 .features[FEAT_1_EDX] =
1032 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1033 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1034 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1035 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1036 CPUID_DE | CPUID_FP87,
1037 .features[FEAT_1_ECX] =
1038 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1039 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1040 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1041 .features[FEAT_8000_0001_EDX] =
1042 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1043 .features[FEAT_8000_0001_ECX] =
1044 CPUID_EXT3_LAHF_LM,
1045 .features[FEAT_6_EAX] =
1046 CPUID_6_EAX_ARAT,
1047 .xlevel = 0x80000008,
1048 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1049 },
1050 {
1051 .name = "SandyBridge",
1052 .level = 0xd,
1053 .vendor = CPUID_VENDOR_INTEL,
1054 .family = 6,
1055 .model = 42,
1056 .stepping = 1,
1057 .features[FEAT_1_EDX] =
1058 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1059 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1060 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1061 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1062 CPUID_DE | CPUID_FP87,
1063 .features[FEAT_1_ECX] =
1064 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1065 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1066 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1067 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1068 CPUID_EXT_SSE3,
1069 .features[FEAT_8000_0001_EDX] =
1070 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1071 CPUID_EXT2_SYSCALL,
1072 .features[FEAT_8000_0001_ECX] =
1073 CPUID_EXT3_LAHF_LM,
1074 .features[FEAT_XSAVE] =
1075 CPUID_XSAVE_XSAVEOPT,
1076 .features[FEAT_6_EAX] =
1077 CPUID_6_EAX_ARAT,
1078 .xlevel = 0x80000008,
1079 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1080 },
1081 {
1082 .name = "IvyBridge",
1083 .level = 0xd,
1084 .vendor = CPUID_VENDOR_INTEL,
1085 .family = 6,
1086 .model = 58,
1087 .stepping = 9,
1088 .features[FEAT_1_EDX] =
1089 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1090 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1091 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1092 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1093 CPUID_DE | CPUID_FP87,
1094 .features[FEAT_1_ECX] =
1095 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1096 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1097 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1098 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1099 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1100 .features[FEAT_7_0_EBX] =
1101 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1102 CPUID_7_0_EBX_ERMS,
1103 .features[FEAT_8000_0001_EDX] =
1104 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1105 CPUID_EXT2_SYSCALL,
1106 .features[FEAT_8000_0001_ECX] =
1107 CPUID_EXT3_LAHF_LM,
1108 .features[FEAT_XSAVE] =
1109 CPUID_XSAVE_XSAVEOPT,
1110 .features[FEAT_6_EAX] =
1111 CPUID_6_EAX_ARAT,
1112 .xlevel = 0x80000008,
1113 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1114 },
1115 {
1116 .name = "Haswell-noTSX",
1117 .level = 0xd,
1118 .vendor = CPUID_VENDOR_INTEL,
1119 .family = 6,
1120 .model = 60,
1121 .stepping = 1,
1122 .features[FEAT_1_EDX] =
1123 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1124 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1125 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1126 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1127 CPUID_DE | CPUID_FP87,
1128 .features[FEAT_1_ECX] =
1129 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1130 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1131 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1132 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1133 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1134 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1135 .features[FEAT_8000_0001_EDX] =
1136 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1137 CPUID_EXT2_SYSCALL,
1138 .features[FEAT_8000_0001_ECX] =
1139 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1140 .features[FEAT_7_0_EBX] =
1141 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1142 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1143 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1144 .features[FEAT_XSAVE] =
1145 CPUID_XSAVE_XSAVEOPT,
1146 .features[FEAT_6_EAX] =
1147 CPUID_6_EAX_ARAT,
1148 .xlevel = 0x80000008,
1149 .model_id = "Intel Core Processor (Haswell, no TSX)",
1150 }, {
1151 .name = "Haswell",
1152 .level = 0xd,
1153 .vendor = CPUID_VENDOR_INTEL,
1154 .family = 6,
1155 .model = 60,
1156 .stepping = 1,
1157 .features[FEAT_1_EDX] =
1158 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1159 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1160 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1161 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1162 CPUID_DE | CPUID_FP87,
1163 .features[FEAT_1_ECX] =
1164 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1165 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1166 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1167 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1168 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1169 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1170 .features[FEAT_8000_0001_EDX] =
1171 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1172 CPUID_EXT2_SYSCALL,
1173 .features[FEAT_8000_0001_ECX] =
1174 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1175 .features[FEAT_7_0_EBX] =
1176 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1177 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1178 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1179 CPUID_7_0_EBX_RTM,
1180 .features[FEAT_XSAVE] =
1181 CPUID_XSAVE_XSAVEOPT,
1182 .features[FEAT_6_EAX] =
1183 CPUID_6_EAX_ARAT,
1184 .xlevel = 0x80000008,
1185 .model_id = "Intel Core Processor (Haswell)",
1186 },
1187 {
1188 .name = "Broadwell-noTSX",
1189 .level = 0xd,
1190 .vendor = CPUID_VENDOR_INTEL,
1191 .family = 6,
1192 .model = 61,
1193 .stepping = 2,
1194 .features[FEAT_1_EDX] =
1195 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1196 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1197 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1198 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1199 CPUID_DE | CPUID_FP87,
1200 .features[FEAT_1_ECX] =
1201 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1202 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1203 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1204 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1205 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1206 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1207 .features[FEAT_8000_0001_EDX] =
1208 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1209 CPUID_EXT2_SYSCALL,
1210 .features[FEAT_8000_0001_ECX] =
1211 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1212 .features[FEAT_7_0_EBX] =
1213 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1214 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1215 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1216 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1217 CPUID_7_0_EBX_SMAP,
1218 .features[FEAT_XSAVE] =
1219 CPUID_XSAVE_XSAVEOPT,
1220 .features[FEAT_6_EAX] =
1221 CPUID_6_EAX_ARAT,
1222 .xlevel = 0x80000008,
1223 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1224 },
1225 {
1226 .name = "Broadwell",
1227 .level = 0xd,
1228 .vendor = CPUID_VENDOR_INTEL,
1229 .family = 6,
1230 .model = 61,
1231 .stepping = 2,
1232 .features[FEAT_1_EDX] =
1233 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1234 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1235 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1236 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1237 CPUID_DE | CPUID_FP87,
1238 .features[FEAT_1_ECX] =
1239 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1240 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1241 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1242 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1243 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1244 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1245 .features[FEAT_8000_0001_EDX] =
1246 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1247 CPUID_EXT2_SYSCALL,
1248 .features[FEAT_8000_0001_ECX] =
1249 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1250 .features[FEAT_7_0_EBX] =
1251 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1252 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1253 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1254 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1255 CPUID_7_0_EBX_SMAP,
1256 .features[FEAT_XSAVE] =
1257 CPUID_XSAVE_XSAVEOPT,
1258 .features[FEAT_6_EAX] =
1259 CPUID_6_EAX_ARAT,
1260 .xlevel = 0x80000008,
1261 .model_id = "Intel Core Processor (Broadwell)",
1262 },
1263 {
1264 .name = "Skylake-Client",
1265 .level = 0xd,
1266 .vendor = CPUID_VENDOR_INTEL,
1267 .family = 6,
1268 .model = 94,
1269 .stepping = 3,
1270 .features[FEAT_1_EDX] =
1271 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1272 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1273 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1274 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1275 CPUID_DE | CPUID_FP87,
1276 .features[FEAT_1_ECX] =
1277 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1278 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1279 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1280 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1281 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1282 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1283 .features[FEAT_8000_0001_EDX] =
1284 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1285 CPUID_EXT2_SYSCALL,
1286 .features[FEAT_8000_0001_ECX] =
1287 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1288 .features[FEAT_7_0_EBX] =
1289 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1290 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1291 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1292 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1293 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1294 /* Missing: XSAVES (not supported by some Linux versions,
1295 * including v4.1 to v4.6).
1296 * KVM doesn't yet expose any XSAVES state save component,
1297 * and the only one defined in Skylake (processor tracing)
1298 * probably will block migration anyway.
1299 */
1300 .features[FEAT_XSAVE] =
1301 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1302 CPUID_XSAVE_XGETBV1,
1303 .features[FEAT_6_EAX] =
1304 CPUID_6_EAX_ARAT,
1305 .xlevel = 0x80000008,
1306 .model_id = "Intel Core Processor (Skylake)",
1307 },
1308 {
1309 .name = "Opteron_G1",
1310 .level = 5,
1311 .vendor = CPUID_VENDOR_AMD,
1312 .family = 15,
1313 .model = 6,
1314 .stepping = 1,
1315 .features[FEAT_1_EDX] =
1316 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1317 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1318 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1319 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1320 CPUID_DE | CPUID_FP87,
1321 .features[FEAT_1_ECX] =
1322 CPUID_EXT_SSE3,
1323 .features[FEAT_8000_0001_EDX] =
1324 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1325 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1326 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1327 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1328 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1329 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1330 .xlevel = 0x80000008,
1331 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1332 },
1333 {
1334 .name = "Opteron_G2",
1335 .level = 5,
1336 .vendor = CPUID_VENDOR_AMD,
1337 .family = 15,
1338 .model = 6,
1339 .stepping = 1,
1340 .features[FEAT_1_EDX] =
1341 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1342 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1343 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1344 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1345 CPUID_DE | CPUID_FP87,
1346 .features[FEAT_1_ECX] =
1347 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1348 /* Missing: CPUID_EXT2_RDTSCP */
1349 .features[FEAT_8000_0001_EDX] =
1350 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
1351 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1352 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1353 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1354 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1355 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1356 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1357 .features[FEAT_8000_0001_ECX] =
1358 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1359 .xlevel = 0x80000008,
1360 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1361 },
1362 {
1363 .name = "Opteron_G3",
1364 .level = 5,
1365 .vendor = CPUID_VENDOR_AMD,
1366 .family = 16,
1367 .model = 2,
1368 .stepping = 3,
1369 .features[FEAT_1_EDX] =
1370 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1371 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1372 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1373 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1374 CPUID_DE | CPUID_FP87,
1375 .features[FEAT_1_ECX] =
1376 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1377 CPUID_EXT_SSE3,
1378 /* Missing: CPUID_EXT2_RDTSCP */
1379 .features[FEAT_8000_0001_EDX] =
1380 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
1381 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1382 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1383 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1384 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1385 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1386 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1387 .features[FEAT_8000_0001_ECX] =
1388 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1389 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1390 .xlevel = 0x80000008,
1391 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1392 },
1393 {
1394 .name = "Opteron_G4",
1395 .level = 0xd,
1396 .vendor = CPUID_VENDOR_AMD,
1397 .family = 21,
1398 .model = 1,
1399 .stepping = 2,
1400 .features[FEAT_1_EDX] =
1401 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1402 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1403 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1404 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1405 CPUID_DE | CPUID_FP87,
1406 .features[FEAT_1_ECX] =
1407 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1408 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1409 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1410 CPUID_EXT_SSE3,
1411 /* Missing: CPUID_EXT2_RDTSCP */
1412 .features[FEAT_8000_0001_EDX] =
1413 CPUID_EXT2_LM |
1414 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1415 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1416 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1417 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1418 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1419 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1420 .features[FEAT_8000_0001_ECX] =
1421 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1422 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1423 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1424 CPUID_EXT3_LAHF_LM,
1425 /* no xsaveopt! */
1426 .xlevel = 0x8000001A,
1427 .model_id = "AMD Opteron 62xx class CPU",
1428 },
1429 {
1430 .name = "Opteron_G5",
1431 .level = 0xd,
1432 .vendor = CPUID_VENDOR_AMD,
1433 .family = 21,
1434 .model = 2,
1435 .stepping = 0,
1436 .features[FEAT_1_EDX] =
1437 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1438 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1439 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1440 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1441 CPUID_DE | CPUID_FP87,
1442 .features[FEAT_1_ECX] =
1443 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1444 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1445 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1446 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1447 /* Missing: CPUID_EXT2_RDTSCP */
1448 .features[FEAT_8000_0001_EDX] =
1449 CPUID_EXT2_LM |
1450 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1451 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1452 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1453 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1454 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1455 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1456 .features[FEAT_8000_0001_ECX] =
1457 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1458 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1459 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1460 CPUID_EXT3_LAHF_LM,
1461 /* no xsaveopt! */
1462 .xlevel = 0x8000001A,
1463 .model_id = "AMD Opteron 63xx class CPU",
1464 },
1465 };
1466
1467 typedef struct PropValue {
1468 const char *prop, *value;
1469 } PropValue;
1470
1471 /* KVM-specific features that are automatically added/removed
1472 * from all CPU models when KVM is enabled.
1473 */
1474 static PropValue kvm_default_props[] = {
1475 { "kvmclock", "on" },
1476 { "kvm-nopiodelay", "on" },
1477 { "kvm-asyncpf", "on" },
1478 { "kvm-steal-time", "on" },
1479 { "kvm-pv-eoi", "on" },
1480 { "kvmclock-stable-bit", "on" },
1481 { "x2apic", "on" },
1482 { "acpi", "off" },
1483 { "monitor", "off" },
1484 { "svm", "off" },
1485 { NULL, NULL },
1486 };
1487
1488 /* TCG-specific defaults that override all CPU models when using TCG
1489 */
1490 static PropValue tcg_default_props[] = {
1491 { "vme", "off" },
1492 { NULL, NULL },
1493 };
1494
1495
1496 void x86_cpu_change_kvm_default(const char *prop, const char *value)
1497 {
1498 PropValue *pv;
1499 for (pv = kvm_default_props; pv->prop; pv++) {
1500 if (!strcmp(pv->prop, prop)) {
1501 pv->value = value;
1502 break;
1503 }
1504 }
1505
1506 /* It is valid to call this function only for properties that
1507 * are already present in the kvm_default_props table.
1508 */
1509 assert(pv->prop);
1510 }
1511
1512 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1513 bool migratable_only);
1514
1515 #ifdef CONFIG_KVM
1516
1517 static bool lmce_supported(void)
1518 {
1519 uint64_t mce_cap;
1520
1521 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1522 return false;
1523 }
1524
1525 return !!(mce_cap & MCG_LMCE_P);
1526 }
1527
1528 static int cpu_x86_fill_model_id(char *str)
1529 {
1530 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1531 int i;
1532
1533 for (i = 0; i < 3; i++) {
1534 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1535 memcpy(str + i * 16 + 0, &eax, 4);
1536 memcpy(str + i * 16 + 4, &ebx, 4);
1537 memcpy(str + i * 16 + 8, &ecx, 4);
1538 memcpy(str + i * 16 + 12, &edx, 4);
1539 }
1540 return 0;
1541 }
1542
1543 static X86CPUDefinition host_cpudef;
1544
1545 static Property host_x86_cpu_properties[] = {
1546 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
1547 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
1548 DEFINE_PROP_END_OF_LIST()
1549 };
1550
1551 /* class_init for the "host" CPU model
1552 *
1553 * This function may be called before KVM is initialized.
1554 */
1555 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1556 {
1557 DeviceClass *dc = DEVICE_CLASS(oc);
1558 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1559 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1560
1561 xcc->kvm_required = true;
1562
1563 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1564 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1565
1566 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1567 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1568 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1569 host_cpudef.stepping = eax & 0x0F;
1570
1571 cpu_x86_fill_model_id(host_cpudef.model_id);
1572
1573 xcc->cpu_def = &host_cpudef;
1574 xcc->model_description =
1575 "KVM processor with all supported host features "
1576 "(only available in KVM mode)";
1577
1578 /* level, xlevel, xlevel2, and the feature words are initialized on
1579 * instance_init, because they require KVM to be initialized.
1580 */
1581
1582 dc->props = host_x86_cpu_properties;
1583 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1584 dc->cannot_destroy_with_object_finalize_yet = true;
1585 }
1586
1587 static void host_x86_cpu_initfn(Object *obj)
1588 {
1589 X86CPU *cpu = X86_CPU(obj);
1590 CPUX86State *env = &cpu->env;
1591 KVMState *s = kvm_state;
1592
1593 /* We can't fill the features array here because we don't know yet if
1594 * "migratable" is true or false.
1595 */
1596 cpu->host_features = true;
1597
1598 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
1599 if (kvm_enabled()) {
1600 env->cpuid_min_level =
1601 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1602 env->cpuid_min_xlevel =
1603 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1604 env->cpuid_min_xlevel2 =
1605 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1606
1607 if (lmce_supported()) {
1608 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1609 }
1610 }
1611
1612 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1613 }
1614
1615 static const TypeInfo host_x86_cpu_type_info = {
1616 .name = X86_CPU_TYPE_NAME("host"),
1617 .parent = TYPE_X86_CPU,
1618 .instance_init = host_x86_cpu_initfn,
1619 .class_init = host_x86_cpu_class_init,
1620 };
1621
1622 #endif
1623
1624 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1625 {
1626 FeatureWordInfo *f = &feature_word_info[w];
1627 int i;
1628
1629 for (i = 0; i < 32; ++i) {
1630 if ((1UL << i) & mask) {
1631 const char *reg = get_register_name_32(f->cpuid_reg);
1632 assert(reg);
1633 fprintf(stderr, "warning: %s doesn't support requested feature: "
1634 "CPUID.%02XH:%s%s%s [bit %d]\n",
1635 kvm_enabled() ? "host" : "TCG",
1636 f->cpuid_eax, reg,
1637 f->feat_names[i] ? "." : "",
1638 f->feat_names[i] ? f->feat_names[i] : "", i);
1639 }
1640 }
1641 }
1642
1643 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1644 const char *name, void *opaque,
1645 Error **errp)
1646 {
1647 X86CPU *cpu = X86_CPU(obj);
1648 CPUX86State *env = &cpu->env;
1649 int64_t value;
1650
1651 value = (env->cpuid_version >> 8) & 0xf;
1652 if (value == 0xf) {
1653 value += (env->cpuid_version >> 20) & 0xff;
1654 }
1655 visit_type_int(v, name, &value, errp);
1656 }
1657
1658 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1659 const char *name, void *opaque,
1660 Error **errp)
1661 {
1662 X86CPU *cpu = X86_CPU(obj);
1663 CPUX86State *env = &cpu->env;
1664 const int64_t min = 0;
1665 const int64_t max = 0xff + 0xf;
1666 Error *local_err = NULL;
1667 int64_t value;
1668
1669 visit_type_int(v, name, &value, &local_err);
1670 if (local_err) {
1671 error_propagate(errp, local_err);
1672 return;
1673 }
1674 if (value < min || value > max) {
1675 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1676 name ? name : "null", value, min, max);
1677 return;
1678 }
1679
1680 env->cpuid_version &= ~0xff00f00;
1681 if (value > 0x0f) {
1682 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1683 } else {
1684 env->cpuid_version |= value << 8;
1685 }
1686 }
1687
1688 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1689 const char *name, void *opaque,
1690 Error **errp)
1691 {
1692 X86CPU *cpu = X86_CPU(obj);
1693 CPUX86State *env = &cpu->env;
1694 int64_t value;
1695
1696 value = (env->cpuid_version >> 4) & 0xf;
1697 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1698 visit_type_int(v, name, &value, errp);
1699 }
1700
1701 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1702 const char *name, void *opaque,
1703 Error **errp)
1704 {
1705 X86CPU *cpu = X86_CPU(obj);
1706 CPUX86State *env = &cpu->env;
1707 const int64_t min = 0;
1708 const int64_t max = 0xff;
1709 Error *local_err = NULL;
1710 int64_t value;
1711
1712 visit_type_int(v, name, &value, &local_err);
1713 if (local_err) {
1714 error_propagate(errp, local_err);
1715 return;
1716 }
1717 if (value < min || value > max) {
1718 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1719 name ? name : "null", value, min, max);
1720 return;
1721 }
1722
1723 env->cpuid_version &= ~0xf00f0;
1724 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1725 }
1726
1727 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1728 const char *name, void *opaque,
1729 Error **errp)
1730 {
1731 X86CPU *cpu = X86_CPU(obj);
1732 CPUX86State *env = &cpu->env;
1733 int64_t value;
1734
1735 value = env->cpuid_version & 0xf;
1736 visit_type_int(v, name, &value, errp);
1737 }
1738
1739 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1740 const char *name, void *opaque,
1741 Error **errp)
1742 {
1743 X86CPU *cpu = X86_CPU(obj);
1744 CPUX86State *env = &cpu->env;
1745 const int64_t min = 0;
1746 const int64_t max = 0xf;
1747 Error *local_err = NULL;
1748 int64_t value;
1749
1750 visit_type_int(v, name, &value, &local_err);
1751 if (local_err) {
1752 error_propagate(errp, local_err);
1753 return;
1754 }
1755 if (value < min || value > max) {
1756 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1757 name ? name : "null", value, min, max);
1758 return;
1759 }
1760
1761 env->cpuid_version &= ~0xf;
1762 env->cpuid_version |= value & 0xf;
1763 }
1764
1765 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1766 {
1767 X86CPU *cpu = X86_CPU(obj);
1768 CPUX86State *env = &cpu->env;
1769 char *value;
1770
1771 value = g_malloc(CPUID_VENDOR_SZ + 1);
1772 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1773 env->cpuid_vendor3);
1774 return value;
1775 }
1776
1777 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1778 Error **errp)
1779 {
1780 X86CPU *cpu = X86_CPU(obj);
1781 CPUX86State *env = &cpu->env;
1782 int i;
1783
1784 if (strlen(value) != CPUID_VENDOR_SZ) {
1785 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
1786 return;
1787 }
1788
1789 env->cpuid_vendor1 = 0;
1790 env->cpuid_vendor2 = 0;
1791 env->cpuid_vendor3 = 0;
1792 for (i = 0; i < 4; i++) {
1793 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1794 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1795 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1796 }
1797 }
1798
1799 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1800 {
1801 X86CPU *cpu = X86_CPU(obj);
1802 CPUX86State *env = &cpu->env;
1803 char *value;
1804 int i;
1805
1806 value = g_malloc(48 + 1);
1807 for (i = 0; i < 48; i++) {
1808 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1809 }
1810 value[48] = '\0';
1811 return value;
1812 }
1813
1814 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1815 Error **errp)
1816 {
1817 X86CPU *cpu = X86_CPU(obj);
1818 CPUX86State *env = &cpu->env;
1819 int c, len, i;
1820
1821 if (model_id == NULL) {
1822 model_id = "";
1823 }
1824 len = strlen(model_id);
1825 memset(env->cpuid_model, 0, 48);
1826 for (i = 0; i < 48; i++) {
1827 if (i >= len) {
1828 c = '\0';
1829 } else {
1830 c = (uint8_t)model_id[i];
1831 }
1832 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1833 }
1834 }
1835
1836 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1837 void *opaque, Error **errp)
1838 {
1839 X86CPU *cpu = X86_CPU(obj);
1840 int64_t value;
1841
1842 value = cpu->env.tsc_khz * 1000;
1843 visit_type_int(v, name, &value, errp);
1844 }
1845
1846 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1847 void *opaque, Error **errp)
1848 {
1849 X86CPU *cpu = X86_CPU(obj);
1850 const int64_t min = 0;
1851 const int64_t max = INT64_MAX;
1852 Error *local_err = NULL;
1853 int64_t value;
1854
1855 visit_type_int(v, name, &value, &local_err);
1856 if (local_err) {
1857 error_propagate(errp, local_err);
1858 return;
1859 }
1860 if (value < min || value > max) {
1861 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1862 name ? name : "null", value, min, max);
1863 return;
1864 }
1865
1866 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
1867 }
1868
1869 /* Generic getter for "feature-words" and "filtered-features" properties */
1870 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1871 const char *name, void *opaque,
1872 Error **errp)
1873 {
1874 uint32_t *array = (uint32_t *)opaque;
1875 FeatureWord w;
1876 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1877 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1878 X86CPUFeatureWordInfoList *list = NULL;
1879
1880 for (w = 0; w < FEATURE_WORDS; w++) {
1881 FeatureWordInfo *wi = &feature_word_info[w];
1882 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1883 qwi->cpuid_input_eax = wi->cpuid_eax;
1884 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1885 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1886 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1887 qwi->features = array[w];
1888
1889 /* List will be in reverse order, but order shouldn't matter */
1890 list_entries[w].next = list;
1891 list_entries[w].value = &word_infos[w];
1892 list = &list_entries[w];
1893 }
1894
1895 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
1896 }
1897
1898 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1899 void *opaque, Error **errp)
1900 {
1901 X86CPU *cpu = X86_CPU(obj);
1902 int64_t value = cpu->hyperv_spinlock_attempts;
1903
1904 visit_type_int(v, name, &value, errp);
1905 }
1906
1907 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1908 void *opaque, Error **errp)
1909 {
1910 const int64_t min = 0xFFF;
1911 const int64_t max = UINT_MAX;
1912 X86CPU *cpu = X86_CPU(obj);
1913 Error *err = NULL;
1914 int64_t value;
1915
1916 visit_type_int(v, name, &value, &err);
1917 if (err) {
1918 error_propagate(errp, err);
1919 return;
1920 }
1921
1922 if (value < min || value > max) {
1923 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1924 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1925 object_get_typename(obj), name ? name : "null",
1926 value, min, max);
1927 return;
1928 }
1929 cpu->hyperv_spinlock_attempts = value;
1930 }
1931
1932 static PropertyInfo qdev_prop_spinlocks = {
1933 .name = "int",
1934 .get = x86_get_hv_spinlocks,
1935 .set = x86_set_hv_spinlocks,
1936 };
1937
1938 /* Convert all '_' in a feature string option name to '-', to make feature
1939 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1940 */
1941 static inline void feat2prop(char *s)
1942 {
1943 while ((s = strchr(s, '_'))) {
1944 *s = '-';
1945 }
1946 }
1947
1948 /* Return the feature property name for a feature flag bit */
1949 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
1950 {
1951 /* XSAVE components are automatically enabled by other features,
1952 * so return the original feature name instead
1953 */
1954 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
1955 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
1956
1957 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
1958 x86_ext_save_areas[comp].bits) {
1959 w = x86_ext_save_areas[comp].feature;
1960 bitnr = ctz32(x86_ext_save_areas[comp].bits);
1961 }
1962 }
1963
1964 assert(bitnr < 32);
1965 assert(w < FEATURE_WORDS);
1966 return feature_word_info[w].feat_names[bitnr];
1967 }
1968
1969 /* Compatibily hack to maintain legacy +-feat semantic,
1970 * where +-feat overwrites any feature set by
1971 * feat=on|feat even if the later is parsed after +-feat
1972 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1973 */
1974 static GList *plus_features, *minus_features;
1975
1976 /* Parse "+feature,-feature,feature=foo" CPU feature string
1977 */
1978 static void x86_cpu_parse_featurestr(const char *typename, char *features,
1979 Error **errp)
1980 {
1981 char *featurestr; /* Single 'key=value" string being parsed */
1982 Error *local_err = NULL;
1983 static bool cpu_globals_initialized;
1984
1985 if (cpu_globals_initialized) {
1986 return;
1987 }
1988 cpu_globals_initialized = true;
1989
1990 if (!features) {
1991 return;
1992 }
1993
1994 for (featurestr = strtok(features, ",");
1995 featurestr && !local_err;
1996 featurestr = strtok(NULL, ",")) {
1997 const char *name;
1998 const char *val = NULL;
1999 char *eq = NULL;
2000 char num[32];
2001 GlobalProperty *prop;
2002
2003 /* Compatibility syntax: */
2004 if (featurestr[0] == '+') {
2005 plus_features = g_list_append(plus_features,
2006 g_strdup(featurestr + 1));
2007 continue;
2008 } else if (featurestr[0] == '-') {
2009 minus_features = g_list_append(minus_features,
2010 g_strdup(featurestr + 1));
2011 continue;
2012 }
2013
2014 eq = strchr(featurestr, '=');
2015 if (eq) {
2016 *eq++ = 0;
2017 val = eq;
2018 } else {
2019 val = "on";
2020 }
2021
2022 feat2prop(featurestr);
2023 name = featurestr;
2024
2025 /* Special case: */
2026 if (!strcmp(name, "tsc-freq")) {
2027 int64_t tsc_freq;
2028 char *err;
2029
2030 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2031 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2032 if (tsc_freq < 0 || *err) {
2033 error_setg(errp, "bad numerical value %s", val);
2034 return;
2035 }
2036 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2037 val = num;
2038 name = "tsc-frequency";
2039 }
2040
2041 prop = g_new0(typeof(*prop), 1);
2042 prop->driver = typename;
2043 prop->property = g_strdup(name);
2044 prop->value = g_strdup(val);
2045 prop->errp = &error_fatal;
2046 qdev_prop_register_global(prop);
2047 }
2048
2049 if (local_err) {
2050 error_propagate(errp, local_err);
2051 }
2052 }
2053
2054 static void x86_cpu_load_features(X86CPU *cpu, Error **errp);
2055 static int x86_cpu_filter_features(X86CPU *cpu);
2056
2057 /* Check for missing features that may prevent the CPU class from
2058 * running using the current machine and accelerator.
2059 */
2060 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2061 strList **missing_feats)
2062 {
2063 X86CPU *xc;
2064 FeatureWord w;
2065 Error *err = NULL;
2066 strList **next = missing_feats;
2067
2068 if (xcc->kvm_required && !kvm_enabled()) {
2069 strList *new = g_new0(strList, 1);
2070 new->value = g_strdup("kvm");;
2071 *missing_feats = new;
2072 return;
2073 }
2074
2075 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2076
2077 x86_cpu_load_features(xc, &err);
2078 if (err) {
2079 /* Errors at x86_cpu_load_features should never happen,
2080 * but in case it does, just report the model as not
2081 * runnable at all using the "type" property.
2082 */
2083 strList *new = g_new0(strList, 1);
2084 new->value = g_strdup("type");
2085 *next = new;
2086 next = &new->next;
2087 }
2088
2089 x86_cpu_filter_features(xc);
2090
2091 for (w = 0; w < FEATURE_WORDS; w++) {
2092 uint32_t filtered = xc->filtered_features[w];
2093 int i;
2094 for (i = 0; i < 32; i++) {
2095 if (filtered & (1UL << i)) {
2096 strList *new = g_new0(strList, 1);
2097 new->value = g_strdup(x86_cpu_feature_name(w, i));
2098 *next = new;
2099 next = &new->next;
2100 }
2101 }
2102 }
2103
2104 object_unref(OBJECT(xc));
2105 }
2106
2107 /* Print all cpuid feature names in featureset
2108 */
2109 static void listflags(FILE *f, fprintf_function print, const char **featureset)
2110 {
2111 int bit;
2112 bool first = true;
2113
2114 for (bit = 0; bit < 32; bit++) {
2115 if (featureset[bit]) {
2116 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2117 first = false;
2118 }
2119 }
2120 }
2121
2122 /* Sort alphabetically by type name, listing kvm_required models last. */
2123 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2124 {
2125 ObjectClass *class_a = (ObjectClass *)a;
2126 ObjectClass *class_b = (ObjectClass *)b;
2127 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2128 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2129 const char *name_a, *name_b;
2130
2131 if (cc_a->kvm_required != cc_b->kvm_required) {
2132 /* kvm_required items go last */
2133 return cc_a->kvm_required ? 1 : -1;
2134 } else {
2135 name_a = object_class_get_name(class_a);
2136 name_b = object_class_get_name(class_b);
2137 return strcmp(name_a, name_b);
2138 }
2139 }
2140
2141 static GSList *get_sorted_cpu_model_list(void)
2142 {
2143 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2144 list = g_slist_sort(list, x86_cpu_list_compare);
2145 return list;
2146 }
2147
2148 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2149 {
2150 ObjectClass *oc = data;
2151 X86CPUClass *cc = X86_CPU_CLASS(oc);
2152 CPUListState *s = user_data;
2153 char *name = x86_cpu_class_get_model_name(cc);
2154 const char *desc = cc->model_description;
2155 if (!desc) {
2156 desc = cc->cpu_def->model_id;
2157 }
2158
2159 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2160 name, desc);
2161 g_free(name);
2162 }
2163
2164 /* list available CPU models and flags */
2165 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2166 {
2167 int i;
2168 CPUListState s = {
2169 .file = f,
2170 .cpu_fprintf = cpu_fprintf,
2171 };
2172 GSList *list;
2173
2174 (*cpu_fprintf)(f, "Available CPUs:\n");
2175 list = get_sorted_cpu_model_list();
2176 g_slist_foreach(list, x86_cpu_list_entry, &s);
2177 g_slist_free(list);
2178
2179 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
2180 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2181 FeatureWordInfo *fw = &feature_word_info[i];
2182
2183 (*cpu_fprintf)(f, " ");
2184 listflags(f, cpu_fprintf, fw->feat_names);
2185 (*cpu_fprintf)(f, "\n");
2186 }
2187 }
2188
2189 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2190 {
2191 ObjectClass *oc = data;
2192 X86CPUClass *cc = X86_CPU_CLASS(oc);
2193 CpuDefinitionInfoList **cpu_list = user_data;
2194 CpuDefinitionInfoList *entry;
2195 CpuDefinitionInfo *info;
2196
2197 info = g_malloc0(sizeof(*info));
2198 info->name = x86_cpu_class_get_model_name(cc);
2199 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2200 info->has_unavailable_features = true;
2201
2202 entry = g_malloc0(sizeof(*entry));
2203 entry->value = info;
2204 entry->next = *cpu_list;
2205 *cpu_list = entry;
2206 }
2207
2208 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2209 {
2210 CpuDefinitionInfoList *cpu_list = NULL;
2211 GSList *list = get_sorted_cpu_model_list();
2212 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2213 g_slist_free(list);
2214 return cpu_list;
2215 }
2216
2217 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2218 bool migratable_only)
2219 {
2220 FeatureWordInfo *wi = &feature_word_info[w];
2221 uint32_t r;
2222
2223 if (kvm_enabled()) {
2224 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2225 wi->cpuid_ecx,
2226 wi->cpuid_reg);
2227 } else if (tcg_enabled()) {
2228 r = wi->tcg_features;
2229 } else {
2230 return ~0;
2231 }
2232 if (migratable_only) {
2233 r &= x86_cpu_get_migratable_flags(w);
2234 }
2235 return r;
2236 }
2237
2238 /*
2239 * Filters CPU feature words based on host availability of each feature.
2240 *
2241 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2242 */
2243 static int x86_cpu_filter_features(X86CPU *cpu)
2244 {
2245 CPUX86State *env = &cpu->env;
2246 FeatureWord w;
2247 int rv = 0;
2248
2249 for (w = 0; w < FEATURE_WORDS; w++) {
2250 uint32_t host_feat =
2251 x86_cpu_get_supported_feature_word(w, false);
2252 uint32_t requested_features = env->features[w];
2253 env->features[w] &= host_feat;
2254 cpu->filtered_features[w] = requested_features & ~env->features[w];
2255 if (cpu->filtered_features[w]) {
2256 rv = 1;
2257 }
2258 }
2259
2260 return rv;
2261 }
2262
2263 static void x86_cpu_report_filtered_features(X86CPU *cpu)
2264 {
2265 FeatureWord w;
2266
2267 for (w = 0; w < FEATURE_WORDS; w++) {
2268 report_unavailable_features(w, cpu->filtered_features[w]);
2269 }
2270 }
2271
2272 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2273 {
2274 PropValue *pv;
2275 for (pv = props; pv->prop; pv++) {
2276 if (!pv->value) {
2277 continue;
2278 }
2279 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2280 &error_abort);
2281 }
2282 }
2283
2284 /* Load data from X86CPUDefinition
2285 */
2286 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
2287 {
2288 CPUX86State *env = &cpu->env;
2289 const char *vendor;
2290 char host_vendor[CPUID_VENDOR_SZ + 1];
2291 FeatureWord w;
2292
2293 /* CPU models only set _minimum_ values for level/xlevel: */
2294 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2295 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2296
2297 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2298 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2299 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2300 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
2301 for (w = 0; w < FEATURE_WORDS; w++) {
2302 env->features[w] = def->features[w];
2303 }
2304
2305 /* Special cases not set in the X86CPUDefinition structs: */
2306 if (kvm_enabled()) {
2307 if (!kvm_irqchip_in_kernel()) {
2308 x86_cpu_change_kvm_default("x2apic", "off");
2309 }
2310
2311 x86_cpu_apply_props(cpu, kvm_default_props);
2312 } else if (tcg_enabled()) {
2313 x86_cpu_apply_props(cpu, tcg_default_props);
2314 }
2315
2316 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
2317
2318 /* sysenter isn't supported in compatibility mode on AMD,
2319 * syscall isn't supported in compatibility mode on Intel.
2320 * Normally we advertise the actual CPU vendor, but you can
2321 * override this using the 'vendor' property if you want to use
2322 * KVM's sysenter/syscall emulation in compatibility mode and
2323 * when doing cross vendor migration
2324 */
2325 vendor = def->vendor;
2326 if (kvm_enabled()) {
2327 uint32_t ebx = 0, ecx = 0, edx = 0;
2328 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2329 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2330 vendor = host_vendor;
2331 }
2332
2333 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2334
2335 }
2336
2337 X86CPU *cpu_x86_init(const char *cpu_model)
2338 {
2339 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
2340 }
2341
2342 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2343 {
2344 X86CPUDefinition *cpudef = data;
2345 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2346
2347 xcc->cpu_def = cpudef;
2348 }
2349
2350 static void x86_register_cpudef_type(X86CPUDefinition *def)
2351 {
2352 char *typename = x86_cpu_type_name(def->name);
2353 TypeInfo ti = {
2354 .name = typename,
2355 .parent = TYPE_X86_CPU,
2356 .class_init = x86_cpu_cpudef_class_init,
2357 .class_data = def,
2358 };
2359
2360 type_register(&ti);
2361 g_free(typename);
2362 }
2363
2364 #if !defined(CONFIG_USER_ONLY)
2365
2366 void cpu_clear_apic_feature(CPUX86State *env)
2367 {
2368 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2369 }
2370
2371 #endif /* !CONFIG_USER_ONLY */
2372
2373 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2374 uint32_t *eax, uint32_t *ebx,
2375 uint32_t *ecx, uint32_t *edx)
2376 {
2377 X86CPU *cpu = x86_env_get_cpu(env);
2378 CPUState *cs = CPU(cpu);
2379 uint32_t pkg_offset;
2380
2381 /* test if maximum index reached */
2382 if (index & 0x80000000) {
2383 if (index > env->cpuid_xlevel) {
2384 if (env->cpuid_xlevel2 > 0) {
2385 /* Handle the Centaur's CPUID instruction. */
2386 if (index > env->cpuid_xlevel2) {
2387 index = env->cpuid_xlevel2;
2388 } else if (index < 0xC0000000) {
2389 index = env->cpuid_xlevel;
2390 }
2391 } else {
2392 /* Intel documentation states that invalid EAX input will
2393 * return the same information as EAX=cpuid_level
2394 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2395 */
2396 index = env->cpuid_level;
2397 }
2398 }
2399 } else {
2400 if (index > env->cpuid_level)
2401 index = env->cpuid_level;
2402 }
2403
2404 switch(index) {
2405 case 0:
2406 *eax = env->cpuid_level;
2407 *ebx = env->cpuid_vendor1;
2408 *edx = env->cpuid_vendor2;
2409 *ecx = env->cpuid_vendor3;
2410 break;
2411 case 1:
2412 *eax = env->cpuid_version;
2413 *ebx = (cpu->apic_id << 24) |
2414 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2415 *ecx = env->features[FEAT_1_ECX];
2416 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2417 *ecx |= CPUID_EXT_OSXSAVE;
2418 }
2419 *edx = env->features[FEAT_1_EDX];
2420 if (cs->nr_cores * cs->nr_threads > 1) {
2421 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2422 *edx |= CPUID_HT;
2423 }
2424 break;
2425 case 2:
2426 /* cache info: needed for Pentium Pro compatibility */
2427 if (cpu->cache_info_passthrough) {
2428 host_cpuid(index, 0, eax, ebx, ecx, edx);
2429 break;
2430 }
2431 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2432 *ebx = 0;
2433 if (!cpu->enable_l3_cache) {
2434 *ecx = 0;
2435 } else {
2436 *ecx = L3_N_DESCRIPTOR;
2437 }
2438 *edx = (L1D_DESCRIPTOR << 16) | \
2439 (L1I_DESCRIPTOR << 8) | \
2440 (L2_DESCRIPTOR);
2441 break;
2442 case 4:
2443 /* cache info: needed for Core compatibility */
2444 if (cpu->cache_info_passthrough) {
2445 host_cpuid(index, count, eax, ebx, ecx, edx);
2446 *eax &= ~0xFC000000;
2447 } else {
2448 *eax = 0;
2449 switch (count) {
2450 case 0: /* L1 dcache info */
2451 *eax |= CPUID_4_TYPE_DCACHE | \
2452 CPUID_4_LEVEL(1) | \
2453 CPUID_4_SELF_INIT_LEVEL;
2454 *ebx = (L1D_LINE_SIZE - 1) | \
2455 ((L1D_PARTITIONS - 1) << 12) | \
2456 ((L1D_ASSOCIATIVITY - 1) << 22);
2457 *ecx = L1D_SETS - 1;
2458 *edx = CPUID_4_NO_INVD_SHARING;
2459 break;
2460 case 1: /* L1 icache info */
2461 *eax |= CPUID_4_TYPE_ICACHE | \
2462 CPUID_4_LEVEL(1) | \
2463 CPUID_4_SELF_INIT_LEVEL;
2464 *ebx = (L1I_LINE_SIZE - 1) | \
2465 ((L1I_PARTITIONS - 1) << 12) | \
2466 ((L1I_ASSOCIATIVITY - 1) << 22);
2467 *ecx = L1I_SETS - 1;
2468 *edx = CPUID_4_NO_INVD_SHARING;
2469 break;
2470 case 2: /* L2 cache info */
2471 *eax |= CPUID_4_TYPE_UNIFIED | \
2472 CPUID_4_LEVEL(2) | \
2473 CPUID_4_SELF_INIT_LEVEL;
2474 if (cs->nr_threads > 1) {
2475 *eax |= (cs->nr_threads - 1) << 14;
2476 }
2477 *ebx = (L2_LINE_SIZE - 1) | \
2478 ((L2_PARTITIONS - 1) << 12) | \
2479 ((L2_ASSOCIATIVITY - 1) << 22);
2480 *ecx = L2_SETS - 1;
2481 *edx = CPUID_4_NO_INVD_SHARING;
2482 break;
2483 case 3: /* L3 cache info */
2484 if (!cpu->enable_l3_cache) {
2485 *eax = 0;
2486 *ebx = 0;
2487 *ecx = 0;
2488 *edx = 0;
2489 break;
2490 }
2491 *eax |= CPUID_4_TYPE_UNIFIED | \
2492 CPUID_4_LEVEL(3) | \
2493 CPUID_4_SELF_INIT_LEVEL;
2494 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2495 *eax |= ((1 << pkg_offset) - 1) << 14;
2496 *ebx = (L3_N_LINE_SIZE - 1) | \
2497 ((L3_N_PARTITIONS - 1) << 12) | \
2498 ((L3_N_ASSOCIATIVITY - 1) << 22);
2499 *ecx = L3_N_SETS - 1;
2500 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2501 break;
2502 default: /* end of info */
2503 *eax = 0;
2504 *ebx = 0;
2505 *ecx = 0;
2506 *edx = 0;
2507 break;
2508 }
2509 }
2510
2511 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2512 if ((*eax & 31) && cs->nr_cores > 1) {
2513 *eax |= (cs->nr_cores - 1) << 26;
2514 }
2515 break;
2516 case 5:
2517 /* mwait info: needed for Core compatibility */
2518 *eax = 0; /* Smallest monitor-line size in bytes */
2519 *ebx = 0; /* Largest monitor-line size in bytes */
2520 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2521 *edx = 0;
2522 break;
2523 case 6:
2524 /* Thermal and Power Leaf */
2525 *eax = env->features[FEAT_6_EAX];
2526 *ebx = 0;
2527 *ecx = 0;
2528 *edx = 0;
2529 break;
2530 case 7:
2531 /* Structured Extended Feature Flags Enumeration Leaf */
2532 if (count == 0) {
2533 *eax = 0; /* Maximum ECX value for sub-leaves */
2534 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2535 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
2536 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2537 *ecx |= CPUID_7_0_ECX_OSPKE;
2538 }
2539 *edx = 0; /* Reserved */
2540 } else {
2541 *eax = 0;
2542 *ebx = 0;
2543 *ecx = 0;
2544 *edx = 0;
2545 }
2546 break;
2547 case 9:
2548 /* Direct Cache Access Information Leaf */
2549 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2550 *ebx = 0;
2551 *ecx = 0;
2552 *edx = 0;
2553 break;
2554 case 0xA:
2555 /* Architectural Performance Monitoring Leaf */
2556 if (kvm_enabled() && cpu->enable_pmu) {
2557 KVMState *s = cs->kvm_state;
2558
2559 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2560 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2561 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2562 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2563 } else {
2564 *eax = 0;
2565 *ebx = 0;
2566 *ecx = 0;
2567 *edx = 0;
2568 }
2569 break;
2570 case 0xB:
2571 /* Extended Topology Enumeration Leaf */
2572 if (!cpu->enable_cpuid_0xb) {
2573 *eax = *ebx = *ecx = *edx = 0;
2574 break;
2575 }
2576
2577 *ecx = count & 0xff;
2578 *edx = cpu->apic_id;
2579
2580 switch (count) {
2581 case 0:
2582 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2583 *ebx = cs->nr_threads;
2584 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2585 break;
2586 case 1:
2587 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2588 *ebx = cs->nr_cores * cs->nr_threads;
2589 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2590 break;
2591 default:
2592 *eax = 0;
2593 *ebx = 0;
2594 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2595 }
2596
2597 assert(!(*eax & ~0x1f));
2598 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2599 break;
2600 case 0xD: {
2601 /* Processor Extended State */
2602 *eax = 0;
2603 *ebx = 0;
2604 *ecx = 0;
2605 *edx = 0;
2606 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
2607 break;
2608 }
2609
2610 if (count == 0) {
2611 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2612 *eax = env->features[FEAT_XSAVE_COMP_LO];
2613 *edx = env->features[FEAT_XSAVE_COMP_HI];
2614 *ebx = *ecx;
2615 } else if (count == 1) {
2616 *eax = env->features[FEAT_XSAVE];
2617 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2618 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2619 const ExtSaveArea *esa = &x86_ext_save_areas[count];
2620 *eax = esa->size;
2621 *ebx = esa->offset;
2622 }
2623 }
2624 break;
2625 }
2626 case 0x80000000:
2627 *eax = env->cpuid_xlevel;
2628 *ebx = env->cpuid_vendor1;
2629 *edx = env->cpuid_vendor2;
2630 *ecx = env->cpuid_vendor3;
2631 break;
2632 case 0x80000001:
2633 *eax = env->cpuid_version;
2634 *ebx = 0;
2635 *ecx = env->features[FEAT_8000_0001_ECX];
2636 *edx = env->features[FEAT_8000_0001_EDX];
2637
2638 /* The Linux kernel checks for the CMPLegacy bit and
2639 * discards multiple thread information if it is set.
2640 * So don't set it here for Intel to make Linux guests happy.
2641 */
2642 if (cs->nr_cores * cs->nr_threads > 1) {
2643 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2644 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2645 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
2646 *ecx |= 1 << 1; /* CmpLegacy bit */
2647 }
2648 }
2649 break;
2650 case 0x80000002:
2651 case 0x80000003:
2652 case 0x80000004:
2653 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2654 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2655 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2656 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2657 break;
2658 case 0x80000005:
2659 /* cache info (L1 cache) */
2660 if (cpu->cache_info_passthrough) {
2661 host_cpuid(index, 0, eax, ebx, ecx, edx);
2662 break;
2663 }
2664 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2665 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2666 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2667 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2668 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2669 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2670 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2671 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2672 break;
2673 case 0x80000006:
2674 /* cache info (L2 cache) */
2675 if (cpu->cache_info_passthrough) {
2676 host_cpuid(index, 0, eax, ebx, ecx, edx);
2677 break;
2678 }
2679 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2680 (L2_DTLB_2M_ENTRIES << 16) | \
2681 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2682 (L2_ITLB_2M_ENTRIES);
2683 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2684 (L2_DTLB_4K_ENTRIES << 16) | \
2685 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2686 (L2_ITLB_4K_ENTRIES);
2687 *ecx = (L2_SIZE_KB_AMD << 16) | \
2688 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2689 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2690 if (!cpu->enable_l3_cache) {
2691 *edx = ((L3_SIZE_KB / 512) << 18) | \
2692 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2693 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2694 } else {
2695 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2696 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2697 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2698 }
2699 break;
2700 case 0x80000007:
2701 *eax = 0;
2702 *ebx = 0;
2703 *ecx = 0;
2704 *edx = env->features[FEAT_8000_0007_EDX];
2705 break;
2706 case 0x80000008:
2707 /* virtual & phys address size in low 2 bytes. */
2708 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2709 /* 64 bit processor, 48 bits virtual, configurable
2710 * physical bits.
2711 */
2712 *eax = 0x00003000 + cpu->phys_bits;
2713 } else {
2714 *eax = cpu->phys_bits;
2715 }
2716 *ebx = 0;
2717 *ecx = 0;
2718 *edx = 0;
2719 if (cs->nr_cores * cs->nr_threads > 1) {
2720 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2721 }
2722 break;
2723 case 0x8000000A:
2724 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2725 *eax = 0x00000001; /* SVM Revision */
2726 *ebx = 0x00000010; /* nr of ASIDs */
2727 *ecx = 0;
2728 *edx = env->features[FEAT_SVM]; /* optional features */
2729 } else {
2730 *eax = 0;
2731 *ebx = 0;
2732 *ecx = 0;
2733 *edx = 0;
2734 }
2735 break;
2736 case 0xC0000000:
2737 *eax = env->cpuid_xlevel2;
2738 *ebx = 0;
2739 *ecx = 0;
2740 *edx = 0;
2741 break;
2742 case 0xC0000001:
2743 /* Support for VIA CPU's CPUID instruction */
2744 *eax = env->cpuid_version;
2745 *ebx = 0;
2746 *ecx = 0;
2747 *edx = env->features[FEAT_C000_0001_EDX];
2748 break;
2749 case 0xC0000002:
2750 case 0xC0000003:
2751 case 0xC0000004:
2752 /* Reserved for the future, and now filled with zero */
2753 *eax = 0;
2754 *ebx = 0;
2755 *ecx = 0;
2756 *edx = 0;
2757 break;
2758 default:
2759 /* reserved values: zero */
2760 *eax = 0;
2761 *ebx = 0;
2762 *ecx = 0;
2763 *edx = 0;
2764 break;
2765 }
2766 }
2767
2768 /* CPUClass::reset() */
2769 static void x86_cpu_reset(CPUState *s)
2770 {
2771 X86CPU *cpu = X86_CPU(s);
2772 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2773 CPUX86State *env = &cpu->env;
2774 target_ulong cr4;
2775 uint64_t xcr0;
2776 int i;
2777
2778 xcc->parent_reset(s);
2779
2780 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
2781
2782 tlb_flush(s, 1);
2783
2784 env->old_exception = -1;
2785
2786 /* init to reset state */
2787
2788 env->hflags2 |= HF2_GIF_MASK;
2789
2790 cpu_x86_update_cr0(env, 0x60000010);
2791 env->a20_mask = ~0x0;
2792 env->smbase = 0x30000;
2793
2794 env->idt.limit = 0xffff;
2795 env->gdt.limit = 0xffff;
2796 env->ldt.limit = 0xffff;
2797 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2798 env->tr.limit = 0xffff;
2799 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2800
2801 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2802 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2803 DESC_R_MASK | DESC_A_MASK);
2804 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2805 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2806 DESC_A_MASK);
2807 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2808 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2809 DESC_A_MASK);
2810 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2811 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2812 DESC_A_MASK);
2813 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2814 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2815 DESC_A_MASK);
2816 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2817 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2818 DESC_A_MASK);
2819
2820 env->eip = 0xfff0;
2821 env->regs[R_EDX] = env->cpuid_version;
2822
2823 env->eflags = 0x2;
2824
2825 /* FPU init */
2826 for (i = 0; i < 8; i++) {
2827 env->fptags[i] = 1;
2828 }
2829 cpu_set_fpuc(env, 0x37f);
2830
2831 env->mxcsr = 0x1f80;
2832 /* All units are in INIT state. */
2833 env->xstate_bv = 0;
2834
2835 env->pat = 0x0007040600070406ULL;
2836 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2837
2838 memset(env->dr, 0, sizeof(env->dr));
2839 env->dr[6] = DR6_FIXED_1;
2840 env->dr[7] = DR7_FIXED_1;
2841 cpu_breakpoint_remove_all(s, BP_CPU);
2842 cpu_watchpoint_remove_all(s, BP_CPU);
2843
2844 cr4 = 0;
2845 xcr0 = XSTATE_FP_MASK;
2846
2847 #ifdef CONFIG_USER_ONLY
2848 /* Enable all the features for user-mode. */
2849 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
2850 xcr0 |= XSTATE_SSE_MASK;
2851 }
2852 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2853 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2854 if (env->features[esa->feature] & esa->bits) {
2855 xcr0 |= 1ull << i;
2856 }
2857 }
2858
2859 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2860 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2861 }
2862 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2863 cr4 |= CR4_FSGSBASE_MASK;
2864 }
2865 #endif
2866
2867 env->xcr0 = xcr0;
2868 cpu_x86_update_cr4(env, cr4);
2869
2870 /*
2871 * SDM 11.11.5 requires:
2872 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2873 * - IA32_MTRR_PHYSMASKn.V = 0
2874 * All other bits are undefined. For simplification, zero it all.
2875 */
2876 env->mtrr_deftype = 0;
2877 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2878 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2879
2880 #if !defined(CONFIG_USER_ONLY)
2881 /* We hard-wire the BSP to the first CPU. */
2882 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
2883
2884 s->halted = !cpu_is_bsp(cpu);
2885
2886 if (kvm_enabled()) {
2887 kvm_arch_reset_vcpu(cpu);
2888 }
2889 #endif
2890 }
2891
2892 #ifndef CONFIG_USER_ONLY
2893 bool cpu_is_bsp(X86CPU *cpu)
2894 {
2895 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2896 }
2897
2898 /* TODO: remove me, when reset over QOM tree is implemented */
2899 static void x86_cpu_machine_reset_cb(void *opaque)
2900 {
2901 X86CPU *cpu = opaque;
2902 cpu_reset(CPU(cpu));
2903 }
2904 #endif
2905
2906 static void mce_init(X86CPU *cpu)
2907 {
2908 CPUX86State *cenv = &cpu->env;
2909 unsigned int bank;
2910
2911 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2912 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2913 (CPUID_MCE | CPUID_MCA)) {
2914 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2915 (cpu->enable_lmce ? MCG_LMCE_P : 0);
2916 cenv->mcg_ctl = ~(uint64_t)0;
2917 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2918 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2919 }
2920 }
2921 }
2922
2923 #ifndef CONFIG_USER_ONLY
2924 APICCommonClass *apic_get_class(void)
2925 {
2926 const char *apic_type = "apic";
2927
2928 if (kvm_apic_in_kernel()) {
2929 apic_type = "kvm-apic";
2930 } else if (xen_enabled()) {
2931 apic_type = "xen-apic";
2932 }
2933
2934 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
2935 }
2936
2937 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2938 {
2939 APICCommonState *apic;
2940 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
2941
2942 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
2943
2944 object_property_add_child(OBJECT(cpu), "lapic",
2945 OBJECT(cpu->apic_state), &error_abort);
2946 object_unref(OBJECT(cpu->apic_state));
2947
2948 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
2949 /* TODO: convert to link<> */
2950 apic = APIC_COMMON(cpu->apic_state);
2951 apic->cpu = cpu;
2952 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
2953 }
2954
2955 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2956 {
2957 APICCommonState *apic;
2958 static bool apic_mmio_map_once;
2959
2960 if (cpu->apic_state == NULL) {
2961 return;
2962 }
2963 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2964 errp);
2965
2966 /* Map APIC MMIO area */
2967 apic = APIC_COMMON(cpu->apic_state);
2968 if (!apic_mmio_map_once) {
2969 memory_region_add_subregion_overlap(get_system_memory(),
2970 apic->apicbase &
2971 MSR_IA32_APICBASE_BASE,
2972 &apic->io_memory,
2973 0x1000);
2974 apic_mmio_map_once = true;
2975 }
2976 }
2977
2978 static void x86_cpu_machine_done(Notifier *n, void *unused)
2979 {
2980 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2981 MemoryRegion *smram =
2982 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2983
2984 if (smram) {
2985 cpu->smram = g_new(MemoryRegion, 1);
2986 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2987 smram, 0, 1ull << 32);
2988 memory_region_set_enabled(cpu->smram, false);
2989 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2990 }
2991 }
2992 #else
2993 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2994 {
2995 }
2996 #endif
2997
2998 /* Note: Only safe for use on x86(-64) hosts */
2999 static uint32_t x86_host_phys_bits(void)
3000 {
3001 uint32_t eax;
3002 uint32_t host_phys_bits;
3003
3004 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3005 if (eax >= 0x80000008) {
3006 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3007 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3008 * at 23:16 that can specify a maximum physical address bits for
3009 * the guest that can override this value; but I've not seen
3010 * anything with that set.
3011 */
3012 host_phys_bits = eax & 0xff;
3013 } else {
3014 /* It's an odd 64 bit machine that doesn't have the leaf for
3015 * physical address bits; fall back to 36 that's most older
3016 * Intel.
3017 */
3018 host_phys_bits = 36;
3019 }
3020
3021 return host_phys_bits;
3022 }
3023
3024 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3025 {
3026 if (*min < value) {
3027 *min = value;
3028 }
3029 }
3030
3031 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3032 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3033 {
3034 CPUX86State *env = &cpu->env;
3035 FeatureWordInfo *fi = &feature_word_info[w];
3036 uint32_t eax = fi->cpuid_eax;
3037 uint32_t region = eax & 0xF0000000;
3038
3039 if (!env->features[w]) {
3040 return;
3041 }
3042
3043 switch (region) {
3044 case 0x00000000:
3045 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3046 break;
3047 case 0x80000000:
3048 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3049 break;
3050 case 0xC0000000:
3051 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3052 break;
3053 }
3054 }
3055
3056 /* Calculate XSAVE components based on the configured CPU feature flags */
3057 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3058 {
3059 CPUX86State *env = &cpu->env;
3060 int i;
3061 uint64_t mask;
3062
3063 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3064 return;
3065 }
3066
3067 mask = 0;
3068 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3069 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3070 if (env->features[esa->feature] & esa->bits) {
3071 mask |= (1ULL << i);
3072 }
3073 }
3074
3075 env->features[FEAT_XSAVE_COMP_LO] = mask;
3076 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
3077 }
3078
3079 /* Load CPUID data based on configured features */
3080 static void x86_cpu_load_features(X86CPU *cpu, Error **errp)
3081 {
3082 CPUX86State *env = &cpu->env;
3083 FeatureWord w;
3084 GList *l;
3085 Error *local_err = NULL;
3086
3087 /*TODO: cpu->host_features incorrectly overwrites features
3088 * set using "feat=on|off". Once we fix this, we can convert
3089 * plus_features & minus_features to global properties
3090 * inside x86_cpu_parse_featurestr() too.
3091 */
3092 if (cpu->host_features) {
3093 for (w = 0; w < FEATURE_WORDS; w++) {
3094 env->features[w] =
3095 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3096 }
3097 }
3098
3099 for (l = plus_features; l; l = l->next) {
3100 const char *prop = l->data;
3101 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3102 if (local_err) {
3103 goto out;
3104 }
3105 }
3106
3107 for (l = minus_features; l; l = l->next) {
3108 const char *prop = l->data;
3109 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3110 if (local_err) {
3111 goto out;
3112 }
3113 }
3114
3115 if (!kvm_enabled() || !cpu->expose_kvm) {
3116 env->features[FEAT_KVM] = 0;
3117 }
3118
3119 x86_cpu_enable_xsave_components(cpu);
3120
3121 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3122 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3123 if (cpu->full_cpuid_auto_level) {
3124 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3125 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3126 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3127 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3128 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3129 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3130 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3131 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3132 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3133 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
3134 /* SVM requires CPUID[0x8000000A] */
3135 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3136 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3137 }
3138 }
3139
3140 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3141 if (env->cpuid_level == UINT32_MAX) {
3142 env->cpuid_level = env->cpuid_min_level;
3143 }
3144 if (env->cpuid_xlevel == UINT32_MAX) {
3145 env->cpuid_xlevel = env->cpuid_min_xlevel;
3146 }
3147 if (env->cpuid_xlevel2 == UINT32_MAX) {
3148 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
3149 }
3150
3151 out:
3152 if (local_err != NULL) {
3153 error_propagate(errp, local_err);
3154 }
3155 }
3156
3157 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3158 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3159 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3160 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3161 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3162 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3163 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3164 {
3165 CPUState *cs = CPU(dev);
3166 X86CPU *cpu = X86_CPU(dev);
3167 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3168 CPUX86State *env = &cpu->env;
3169 Error *local_err = NULL;
3170 static bool ht_warned;
3171
3172 if (xcc->kvm_required && !kvm_enabled()) {
3173 char *name = x86_cpu_class_get_model_name(xcc);
3174 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3175 g_free(name);
3176 goto out;
3177 }
3178
3179 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3180 error_setg(errp, "apic-id property was not initialized properly");
3181 return;
3182 }
3183
3184 x86_cpu_load_features(cpu, &local_err);
3185 if (local_err) {
3186 goto out;
3187 }
3188
3189 if (x86_cpu_filter_features(cpu) &&
3190 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3191 x86_cpu_report_filtered_features(cpu);
3192 if (cpu->enforce_cpuid) {
3193 error_setg(&local_err,
3194 kvm_enabled() ?
3195 "Host doesn't support requested features" :
3196 "TCG doesn't support requested features");
3197 goto out;
3198 }
3199 }
3200
3201 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3202 * CPUID[1].EDX.
3203 */
3204 if (IS_AMD_CPU(env)) {
3205 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3206 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
3207 & CPUID_EXT2_AMD_ALIASES);
3208 }
3209
3210 /* For 64bit systems think about the number of physical bits to present.
3211 * ideally this should be the same as the host; anything other than matching
3212 * the host can cause incorrect guest behaviour.
3213 * QEMU used to pick the magic value of 40 bits that corresponds to
3214 * consumer AMD devices but nothing else.
3215 */
3216 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
3217 if (kvm_enabled()) {
3218 uint32_t host_phys_bits = x86_host_phys_bits();
3219 static bool warned;
3220
3221 if (cpu->host_phys_bits) {
3222 /* The user asked for us to use the host physical bits */
3223 cpu->phys_bits = host_phys_bits;
3224 }
3225
3226 /* Print a warning if the user set it to a value that's not the
3227 * host value.
3228 */
3229 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3230 !warned) {
3231 error_report("Warning: Host physical bits (%u)"
3232 " does not match phys-bits property (%u)",
3233 host_phys_bits, cpu->phys_bits);
3234 warned = true;
3235 }
3236
3237 if (cpu->phys_bits &&
3238 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3239 cpu->phys_bits < 32)) {
3240 error_setg(errp, "phys-bits should be between 32 and %u "
3241 " (but is %u)",
3242 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3243 return;
3244 }
3245 } else {
3246 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
3247 error_setg(errp, "TCG only supports phys-bits=%u",
3248 TCG_PHYS_ADDR_BITS);
3249 return;
3250 }
3251 }
3252 /* 0 means it was not explicitly set by the user (or by machine
3253 * compat_props or by the host code above). In this case, the default
3254 * is the value used by TCG (40).
3255 */
3256 if (cpu->phys_bits == 0) {
3257 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3258 }
3259 } else {
3260 /* For 32 bit systems don't use the user set value, but keep
3261 * phys_bits consistent with what we tell the guest.
3262 */
3263 if (cpu->phys_bits != 0) {
3264 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3265 return;
3266 }
3267
3268 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3269 cpu->phys_bits = 36;
3270 } else {
3271 cpu->phys_bits = 32;
3272 }
3273 }
3274 cpu_exec_init(cs, &error_abort);
3275
3276 if (tcg_enabled()) {
3277 tcg_x86_init();
3278 }
3279
3280 #ifndef CONFIG_USER_ONLY
3281 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
3282
3283 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
3284 x86_cpu_apic_create(cpu, &local_err);
3285 if (local_err != NULL) {
3286 goto out;
3287 }
3288 }
3289 #endif
3290
3291 mce_init(cpu);
3292
3293 #ifndef CONFIG_USER_ONLY
3294 if (tcg_enabled()) {
3295 AddressSpace *newas = g_new(AddressSpace, 1);
3296
3297 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
3298 cpu->cpu_as_root = g_new(MemoryRegion, 1);
3299
3300 /* Outer container... */
3301 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
3302 memory_region_set_enabled(cpu->cpu_as_root, true);
3303
3304 /* ... with two regions inside: normal system memory with low
3305 * priority, and...
3306 */
3307 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3308 get_system_memory(), 0, ~0ull);
3309 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3310 memory_region_set_enabled(cpu->cpu_as_mem, true);
3311 address_space_init(newas, cpu->cpu_as_root, "CPU");
3312 cs->num_ases = 1;
3313 cpu_address_space_init(cs, newas, 0);
3314
3315 /* ... SMRAM with higher priority, linked from /machine/smram. */
3316 cpu->machine_done.notify = x86_cpu_machine_done;
3317 qemu_add_machine_init_done_notifier(&cpu->machine_done);
3318 }
3319 #endif
3320
3321 qemu_init_vcpu(cs);
3322
3323 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3324 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3325 * based on inputs (sockets,cores,threads), it is still better to gives
3326 * users a warning.
3327 *
3328 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3329 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3330 */
3331 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3332 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3333 " -smp options properly.");
3334 ht_warned = true;
3335 }
3336
3337 x86_cpu_apic_realize(cpu, &local_err);
3338 if (local_err != NULL) {
3339 goto out;
3340 }
3341 cpu_reset(cs);
3342
3343 xcc->parent_realize(dev, &local_err);
3344
3345 out:
3346 if (local_err != NULL) {
3347 error_propagate(errp, local_err);
3348 return;
3349 }
3350 }
3351
3352 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3353 {
3354 X86CPU *cpu = X86_CPU(dev);
3355
3356 #ifndef CONFIG_USER_ONLY
3357 cpu_remove_sync(CPU(dev));
3358 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3359 #endif
3360
3361 if (cpu->apic_state) {
3362 object_unparent(OBJECT(cpu->apic_state));
3363 cpu->apic_state = NULL;
3364 }
3365 }
3366
3367 typedef struct BitProperty {
3368 uint32_t *ptr;
3369 uint32_t mask;
3370 } BitProperty;
3371
3372 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3373 void *opaque, Error **errp)
3374 {
3375 BitProperty *fp = opaque;
3376 bool value = (*fp->ptr & fp->mask) == fp->mask;
3377 visit_type_bool(v, name, &value, errp);
3378 }
3379
3380 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3381 void *opaque, Error **errp)
3382 {
3383 DeviceState *dev = DEVICE(obj);
3384 BitProperty *fp = opaque;
3385 Error *local_err = NULL;
3386 bool value;
3387
3388 if (dev->realized) {
3389 qdev_prop_set_after_realize(dev, name, errp);
3390 return;
3391 }
3392
3393 visit_type_bool(v, name, &value, &local_err);
3394 if (local_err) {
3395 error_propagate(errp, local_err);
3396 return;
3397 }
3398
3399 if (value) {
3400 *fp->ptr |= fp->mask;
3401 } else {
3402 *fp->ptr &= ~fp->mask;
3403 }
3404 }
3405
3406 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3407 void *opaque)
3408 {
3409 BitProperty *prop = opaque;
3410 g_free(prop);
3411 }
3412
3413 /* Register a boolean property to get/set a single bit in a uint32_t field.
3414 *
3415 * The same property name can be registered multiple times to make it affect
3416 * multiple bits in the same FeatureWord. In that case, the getter will return
3417 * true only if all bits are set.
3418 */
3419 static void x86_cpu_register_bit_prop(X86CPU *cpu,
3420 const char *prop_name,
3421 uint32_t *field,
3422 int bitnr)
3423 {
3424 BitProperty *fp;
3425 ObjectProperty *op;
3426 uint32_t mask = (1UL << bitnr);
3427
3428 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3429 if (op) {
3430 fp = op->opaque;
3431 assert(fp->ptr == field);
3432 fp->mask |= mask;
3433 } else {
3434 fp = g_new0(BitProperty, 1);
3435 fp->ptr = field;
3436 fp->mask = mask;
3437 object_property_add(OBJECT(cpu), prop_name, "bool",
3438 x86_cpu_get_bit_prop,
3439 x86_cpu_set_bit_prop,
3440 x86_cpu_release_bit_prop, fp, &error_abort);
3441 }
3442 }
3443
3444 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3445 FeatureWord w,
3446 int bitnr)
3447 {
3448 FeatureWordInfo *fi = &feature_word_info[w];
3449 const char *name = fi->feat_names[bitnr];
3450
3451 if (!name) {
3452 return;
3453 }
3454
3455 /* Property names should use "-" instead of "_".
3456 * Old names containing underscores are registered as aliases
3457 * using object_property_add_alias()
3458 */
3459 assert(!strchr(name, '_'));
3460 /* aliases don't use "|" delimiters anymore, they are registered
3461 * manually using object_property_add_alias() */
3462 assert(!strchr(name, '|'));
3463 x86_cpu_register_bit_prop(cpu, name, &cpu->env.features[w], bitnr);
3464 }
3465
3466 static void x86_cpu_initfn(Object *obj)
3467 {
3468 CPUState *cs = CPU(obj);
3469 X86CPU *cpu = X86_CPU(obj);
3470 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
3471 CPUX86State *env = &cpu->env;
3472 FeatureWord w;
3473
3474 cs->env_ptr = env;
3475
3476 object_property_add(obj, "family", "int",
3477 x86_cpuid_version_get_family,
3478 x86_cpuid_version_set_family, NULL, NULL, NULL);
3479 object_property_add(obj, "model", "int",
3480 x86_cpuid_version_get_model,
3481 x86_cpuid_version_set_model, NULL, NULL, NULL);
3482 object_property_add(obj, "stepping", "int",
3483 x86_cpuid_version_get_stepping,
3484 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
3485 object_property_add_str(obj, "vendor",
3486 x86_cpuid_get_vendor,
3487 x86_cpuid_set_vendor, NULL);
3488 object_property_add_str(obj, "model-id",
3489 x86_cpuid_get_model_id,
3490 x86_cpuid_set_model_id, NULL);
3491 object_property_add(obj, "tsc-frequency", "int",
3492 x86_cpuid_get_tsc_freq,
3493 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
3494 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3495 x86_cpu_get_feature_words,
3496 NULL, NULL, (void *)env->features, NULL);
3497 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3498 x86_cpu_get_feature_words,
3499 NULL, NULL, (void *)cpu->filtered_features, NULL);
3500
3501 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
3502
3503 for (w = 0; w < FEATURE_WORDS; w++) {
3504 int bitnr;
3505
3506 for (bitnr = 0; bitnr < 32; bitnr++) {
3507 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3508 }
3509 }
3510
3511 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3512 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3513 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3514 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3515 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3516 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3517 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3518
3519 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3520 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3521 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3522 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3523 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3524 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3525 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3526 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3527 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3528 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3529 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3530 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3531 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3532 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3533 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3534 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3535 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3536 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3537 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3538 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3539 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3540
3541 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3542 }
3543
3544 static int64_t x86_cpu_get_arch_id(CPUState *cs)
3545 {
3546 X86CPU *cpu = X86_CPU(cs);
3547
3548 return cpu->apic_id;
3549 }
3550
3551 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3552 {
3553 X86CPU *cpu = X86_CPU(cs);
3554
3555 return cpu->env.cr[0] & CR0_PG_MASK;
3556 }
3557
3558 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3559 {
3560 X86CPU *cpu = X86_CPU(cs);
3561
3562 cpu->env.eip = value;
3563 }
3564
3565 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3566 {
3567 X86CPU *cpu = X86_CPU(cs);
3568
3569 cpu->env.eip = tb->pc - tb->cs_base;
3570 }
3571
3572 static bool x86_cpu_has_work(CPUState *cs)
3573 {
3574 X86CPU *cpu = X86_CPU(cs);
3575 CPUX86State *env = &cpu->env;
3576
3577 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3578 CPU_INTERRUPT_POLL)) &&
3579 (env->eflags & IF_MASK)) ||
3580 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3581 CPU_INTERRUPT_INIT |
3582 CPU_INTERRUPT_SIPI |
3583 CPU_INTERRUPT_MCE)) ||
3584 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3585 !(env->hflags & HF_SMM_MASK));
3586 }
3587
3588 static Property x86_cpu_properties[] = {
3589 #ifdef CONFIG_USER_ONLY
3590 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3591 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
3592 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3593 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3594 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
3595 #else
3596 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
3597 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3598 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3599 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
3600 #endif
3601 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
3602 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
3603 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
3604 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
3605 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
3606 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
3607 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
3608 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
3609 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
3610 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
3611 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
3612 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
3613 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
3614 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
3615 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
3616 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
3617 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
3618 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3619 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3620 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3621 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3622 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3623 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3624 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
3625 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
3626 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
3627 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
3628 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
3629 DEFINE_PROP_END_OF_LIST()
3630 };
3631
3632 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3633 {
3634 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3635 CPUClass *cc = CPU_CLASS(oc);
3636 DeviceClass *dc = DEVICE_CLASS(oc);
3637
3638 xcc->parent_realize = dc->realize;
3639 dc->realize = x86_cpu_realizefn;
3640 dc->unrealize = x86_cpu_unrealizefn;
3641 dc->props = x86_cpu_properties;
3642
3643 xcc->parent_reset = cc->reset;
3644 cc->reset = x86_cpu_reset;
3645 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
3646
3647 cc->class_by_name = x86_cpu_class_by_name;
3648 cc->parse_features = x86_cpu_parse_featurestr;
3649 cc->has_work = x86_cpu_has_work;
3650 cc->do_interrupt = x86_cpu_do_interrupt;
3651 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
3652 cc->dump_state = x86_cpu_dump_state;
3653 cc->set_pc = x86_cpu_set_pc;
3654 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
3655 cc->gdb_read_register = x86_cpu_gdb_read_register;
3656 cc->gdb_write_register = x86_cpu_gdb_write_register;
3657 cc->get_arch_id = x86_cpu_get_arch_id;
3658 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
3659 #ifdef CONFIG_USER_ONLY
3660 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3661 #else
3662 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
3663 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
3664 cc->write_elf64_note = x86_cpu_write_elf64_note;
3665 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3666 cc->write_elf32_note = x86_cpu_write_elf32_note;
3667 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
3668 cc->vmsd = &vmstate_x86_cpu;
3669 #endif
3670 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
3671 #ifndef CONFIG_USER_ONLY
3672 cc->debug_excp_handler = breakpoint_handler;
3673 #endif
3674 cc->cpu_exec_enter = x86_cpu_exec_enter;
3675 cc->cpu_exec_exit = x86_cpu_exec_exit;
3676
3677 dc->cannot_instantiate_with_device_add_yet = false;
3678 }
3679
3680 static const TypeInfo x86_cpu_type_info = {
3681 .name = TYPE_X86_CPU,
3682 .parent = TYPE_CPU,
3683 .instance_size = sizeof(X86CPU),
3684 .instance_init = x86_cpu_initfn,
3685 .abstract = true,
3686 .class_size = sizeof(X86CPUClass),
3687 .class_init = x86_cpu_common_class_init,
3688 };
3689
3690 static void x86_cpu_register_types(void)
3691 {
3692 int i;
3693
3694 type_register_static(&x86_cpu_type_info);
3695 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3696 x86_register_cpudef_type(&builtin_x86_defs[i]);
3697 }
3698 #ifdef CONFIG_KVM
3699 type_register_static(&host_x86_cpu_type_info);
3700 #endif
3701 }
3702
3703 type_init(x86_cpu_register_types)
QEmu