2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
34 #include "hw/fw-path-provider.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/cpus.h"
39 #include "sysemu/hw_accel.h"
41 #include "migration/misc.h"
42 #include "migration/global_state.h"
43 #include "migration/register.h"
44 #include "mmu-hash64.h"
45 #include "mmu-book3s-v3.h"
46 #include "cpu-models.h"
49 #include "hw/boards.h"
50 #include "hw/ppc/ppc.h"
51 #include "hw/loader.h"
53 #include "hw/ppc/fdt.h"
54 #include "hw/ppc/spapr.h"
55 #include "hw/ppc/spapr_vio.h"
56 #include "hw/pci-host/spapr.h"
57 #include "hw/pci/msi.h"
59 #include "hw/pci/pci.h"
60 #include "hw/scsi/scsi.h"
61 #include "hw/virtio/virtio-scsi.h"
62 #include "hw/virtio/vhost-scsi-common.h"
64 #include "exec/address-spaces.h"
65 #include "exec/ram_addr.h"
67 #include "qemu/config-file.h"
68 #include "qemu/error-report.h"
71 #include "hw/intc/intc.h"
73 #include "hw/compat.h"
74 #include "qemu/cutils.h"
75 #include "hw/ppc/spapr_cpu_core.h"
76 #include "hw/mem/memory-device.h"
80 /* SLOF memory layout:
82 * SLOF raw image loaded at 0, copies its romfs right below the flat
83 * device-tree, then position SLOF itself 31M below that
85 * So we set FW_OVERHEAD to 40MB which should account for all of that
88 * We load our kernel at 4M, leaving space for SLOF initial image
90 #define FDT_MAX_SIZE 0x100000
91 #define RTAS_MAX_SIZE 0x10000
92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
93 #define FW_MAX_SIZE 0x400000
94 #define FW_FILE_NAME "slof.bin"
95 #define FW_OVERHEAD 0x2800000
96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
98 #define MIN_RMA_SLOF 128UL
100 #define PHANDLE_XICP 0x00001111
102 /* These two functions implement the VCPU id numbering: one to compute them
103 * all and one to identify thread 0 of a VCORE. Any change to the first one
104 * is likely to have an impact on the second one, so let's keep them close.
106 static int spapr_vcpu_id(sPAPRMachineState
*spapr
, int cpu_index
)
110 (cpu_index
/ smp_threads
) * spapr
->vsmt
+ cpu_index
% smp_threads
;
112 static bool spapr_is_thread0_in_vcore(sPAPRMachineState
*spapr
,
116 return spapr_get_vcpu_id(cpu
) % spapr
->vsmt
== 0;
119 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque
)
121 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
122 * and newer QEMUs don't even have them. In both cases, we don't want
123 * to send anything on the wire.
128 static const VMStateDescription pre_2_10_vmstate_dummy_icp
= {
129 .name
= "icp/server",
131 .minimum_version_id
= 1,
132 .needed
= pre_2_10_vmstate_dummy_icp_needed
,
133 .fields
= (VMStateField
[]) {
134 VMSTATE_UNUSED(4), /* uint32_t xirr */
135 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
136 VMSTATE_UNUSED(1), /* uint8_t mfrr */
137 VMSTATE_END_OF_LIST()
141 static void pre_2_10_vmstate_register_dummy_icp(int i
)
143 vmstate_register(NULL
, i
, &pre_2_10_vmstate_dummy_icp
,
144 (void *)(uintptr_t) i
);
147 static void pre_2_10_vmstate_unregister_dummy_icp(int i
)
149 vmstate_unregister(NULL
, &pre_2_10_vmstate_dummy_icp
,
150 (void *)(uintptr_t) i
);
153 int spapr_max_server_number(sPAPRMachineState
*spapr
)
156 return DIV_ROUND_UP(max_cpus
* spapr
->vsmt
, smp_threads
);
159 static int spapr_fixup_cpu_smt_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
,
163 uint32_t servers_prop
[smt_threads
];
164 uint32_t gservers_prop
[smt_threads
* 2];
165 int index
= spapr_get_vcpu_id(cpu
);
167 if (cpu
->compat_pvr
) {
168 ret
= fdt_setprop_cell(fdt
, offset
, "cpu-version", cpu
->compat_pvr
);
174 /* Build interrupt servers and gservers properties */
175 for (i
= 0; i
< smt_threads
; i
++) {
176 servers_prop
[i
] = cpu_to_be32(index
+ i
);
177 /* Hack, direct the group queues back to cpu 0 */
178 gservers_prop
[i
*2] = cpu_to_be32(index
+ i
);
179 gservers_prop
[i
*2 + 1] = 0;
181 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
182 servers_prop
, sizeof(servers_prop
));
186 ret
= fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-gserver#s",
187 gservers_prop
, sizeof(gservers_prop
));
192 static int spapr_fixup_cpu_numa_dt(void *fdt
, int offset
, PowerPCCPU
*cpu
)
194 int index
= spapr_get_vcpu_id(cpu
);
195 uint32_t associativity
[] = {cpu_to_be32(0x5),
199 cpu_to_be32(cpu
->node_id
),
202 /* Advertise NUMA via ibm,associativity */
203 return fdt_setprop(fdt
, offset
, "ibm,associativity", associativity
,
204 sizeof(associativity
));
207 /* Populate the "ibm,pa-features" property */
208 static void spapr_populate_pa_features(sPAPRMachineState
*spapr
,
210 void *fdt
, int offset
,
213 uint8_t pa_features_206
[] = { 6, 0,
214 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
215 uint8_t pa_features_207
[] = { 24, 0,
216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
217 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
218 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
219 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
220 uint8_t pa_features_300
[] = { 66, 0,
221 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
222 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
223 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
225 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
227 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
228 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
229 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
230 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
231 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
232 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
233 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
234 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
235 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
236 /* 42: PM, 44: PC RA, 46: SC vec'd */
237 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
238 /* 48: SIMD, 50: QP BFP, 52: String */
239 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
240 /* 54: DecFP, 56: DecI, 58: SHA */
241 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
242 /* 60: NM atomic, 62: RNG */
243 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
245 uint8_t *pa_features
= NULL
;
248 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_06
, 0, cpu
->compat_pvr
)) {
249 pa_features
= pa_features_206
;
250 pa_size
= sizeof(pa_features_206
);
252 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_2_07
, 0, cpu
->compat_pvr
)) {
253 pa_features
= pa_features_207
;
254 pa_size
= sizeof(pa_features_207
);
256 if (ppc_check_compat(cpu
, CPU_POWERPC_LOGICAL_3_00
, 0, cpu
->compat_pvr
)) {
257 pa_features
= pa_features_300
;
258 pa_size
= sizeof(pa_features_300
);
264 if (ppc_hash64_has(cpu
, PPC_HASH64_CI_LARGEPAGE
)) {
266 * Note: we keep CI large pages off by default because a 64K capable
267 * guest provisioned with large pages might otherwise try to map a qemu
268 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
269 * even if that qemu runs on a 4k host.
270 * We dd this bit back here if we are confident this is not an issue
272 pa_features
[3] |= 0x20;
274 if ((spapr_get_cap(spapr
, SPAPR_CAP_HTM
) != 0) && pa_size
> 24) {
275 pa_features
[24] |= 0x80; /* Transactional memory support */
277 if (legacy_guest
&& pa_size
> 40) {
278 /* Workaround for broken kernels that attempt (guest) radix
279 * mode when they can't handle it, if they see the radix bit set
280 * in pa-features. So hide it from them. */
281 pa_features
[40 + 2] &= ~0x80; /* Radix MMU */
284 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features", pa_features
, pa_size
)));
287 static int spapr_fixup_cpu_dt(void *fdt
, sPAPRMachineState
*spapr
)
289 int ret
= 0, offset
, cpus_offset
;
292 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
295 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
296 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
297 int index
= spapr_get_vcpu_id(cpu
);
298 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
300 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
304 snprintf(cpu_model
, 32, "%s@%x", dc
->fw_name
, index
);
306 cpus_offset
= fdt_path_offset(fdt
, "/cpus");
307 if (cpus_offset
< 0) {
308 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
309 if (cpus_offset
< 0) {
313 offset
= fdt_subnode_offset(fdt
, cpus_offset
, cpu_model
);
315 offset
= fdt_add_subnode(fdt
, cpus_offset
, cpu_model
);
321 ret
= fdt_setprop(fdt
, offset
, "ibm,pft-size",
322 pft_size_prop
, sizeof(pft_size_prop
));
327 if (nb_numa_nodes
> 1) {
328 ret
= spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
);
334 ret
= spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
);
339 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
,
340 spapr
->cas_legacy_guest_workaround
);
345 static hwaddr
spapr_node0_size(MachineState
*machine
)
349 for (i
= 0; i
< nb_numa_nodes
; ++i
) {
350 if (numa_info
[i
].node_mem
) {
351 return MIN(pow2floor(numa_info
[i
].node_mem
),
356 return machine
->ram_size
;
359 static void add_str(GString
*s
, const gchar
*s1
)
361 g_string_append_len(s
, s1
, strlen(s1
) + 1);
364 static int spapr_populate_memory_node(void *fdt
, int nodeid
, hwaddr start
,
367 uint32_t associativity
[] = {
368 cpu_to_be32(0x4), /* length */
369 cpu_to_be32(0x0), cpu_to_be32(0x0),
370 cpu_to_be32(0x0), cpu_to_be32(nodeid
)
373 uint64_t mem_reg_property
[2];
376 mem_reg_property
[0] = cpu_to_be64(start
);
377 mem_reg_property
[1] = cpu_to_be64(size
);
379 sprintf(mem_name
, "memory@" TARGET_FMT_lx
, start
);
380 off
= fdt_add_subnode(fdt
, 0, mem_name
);
382 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
383 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
384 sizeof(mem_reg_property
))));
385 _FDT((fdt_setprop(fdt
, off
, "ibm,associativity", associativity
,
386 sizeof(associativity
))));
390 static int spapr_populate_memory(sPAPRMachineState
*spapr
, void *fdt
)
392 MachineState
*machine
= MACHINE(spapr
);
393 hwaddr mem_start
, node_size
;
394 int i
, nb_nodes
= nb_numa_nodes
;
395 NodeInfo
*nodes
= numa_info
;
398 /* No NUMA nodes, assume there is just one node with whole RAM */
399 if (!nb_numa_nodes
) {
401 ramnode
.node_mem
= machine
->ram_size
;
405 for (i
= 0, mem_start
= 0; i
< nb_nodes
; ++i
) {
406 if (!nodes
[i
].node_mem
) {
409 if (mem_start
>= machine
->ram_size
) {
412 node_size
= nodes
[i
].node_mem
;
413 if (node_size
> machine
->ram_size
- mem_start
) {
414 node_size
= machine
->ram_size
- mem_start
;
418 /* spapr_machine_init() checks for rma_size <= node0_size
420 spapr_populate_memory_node(fdt
, i
, 0, spapr
->rma_size
);
421 mem_start
+= spapr
->rma_size
;
422 node_size
-= spapr
->rma_size
;
424 for ( ; node_size
; ) {
425 hwaddr sizetmp
= pow2floor(node_size
);
427 /* mem_start != 0 here */
428 if (ctzl(mem_start
) < ctzl(sizetmp
)) {
429 sizetmp
= 1ULL << ctzl(mem_start
);
432 spapr_populate_memory_node(fdt
, i
, mem_start
, sizetmp
);
433 node_size
-= sizetmp
;
434 mem_start
+= sizetmp
;
441 static void spapr_populate_cpu_dt(CPUState
*cs
, void *fdt
, int offset
,
442 sPAPRMachineState
*spapr
)
444 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
445 CPUPPCState
*env
= &cpu
->env
;
446 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
447 int index
= spapr_get_vcpu_id(cpu
);
448 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
449 0xffffffff, 0xffffffff};
450 uint32_t tbfreq
= kvm_enabled() ? kvmppc_get_tbfreq()
451 : SPAPR_TIMEBASE_FREQ
;
452 uint32_t cpufreq
= kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
453 uint32_t page_sizes_prop
[64];
454 size_t page_sizes_prop_size
;
455 uint32_t vcpus_per_socket
= smp_threads
* smp_cores
;
456 uint32_t pft_size_prop
[] = {0, cpu_to_be32(spapr
->htab_shift
)};
457 int compat_smt
= MIN(smp_threads
, ppc_compat_max_vthreads(cpu
));
458 sPAPRDRConnector
*drc
;
460 uint32_t radix_AP_encodings
[PPC_PAGE_SIZES_MAX_SZ
];
463 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
, index
);
465 drc_index
= spapr_drc_index(drc
);
466 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,my-drc-index", drc_index
)));
469 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", index
)));
470 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
472 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
473 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
474 env
->dcache_line_size
)));
475 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
476 env
->dcache_line_size
)));
477 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
478 env
->icache_line_size
)));
479 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
480 env
->icache_line_size
)));
482 if (pcc
->l1_dcache_size
) {
483 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
484 pcc
->l1_dcache_size
)));
486 warn_report("Unknown L1 dcache size for cpu");
488 if (pcc
->l1_icache_size
) {
489 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
490 pcc
->l1_icache_size
)));
492 warn_report("Unknown L1 icache size for cpu");
495 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
496 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
497 _FDT((fdt_setprop_cell(fdt
, offset
, "slb-size", cpu
->hash64_opts
->slb_size
)));
498 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
499 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
500 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
502 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
503 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
506 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
507 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
508 segs
, sizeof(segs
))));
511 /* Advertise VSX (vector extensions) if available
512 * 1 == VMX / Altivec available
515 * Only CPUs for which we create core types in spapr_cpu_core.c
516 * are possible, and all of those have VMX */
517 if (spapr_get_cap(spapr
, SPAPR_CAP_VSX
) != 0) {
518 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 2)));
520 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", 1)));
523 /* Advertise DFP (Decimal Floating Point) if available
524 * 0 / no property == no DFP
525 * 1 == DFP available */
526 if (spapr_get_cap(spapr
, SPAPR_CAP_DFP
) != 0) {
527 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
530 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
531 sizeof(page_sizes_prop
));
532 if (page_sizes_prop_size
) {
533 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
534 page_sizes_prop
, page_sizes_prop_size
)));
537 spapr_populate_pa_features(spapr
, cpu
, fdt
, offset
, false);
539 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id",
540 cs
->cpu_index
/ vcpus_per_socket
)));
542 _FDT((fdt_setprop(fdt
, offset
, "ibm,pft-size",
543 pft_size_prop
, sizeof(pft_size_prop
))));
545 if (nb_numa_nodes
> 1) {
546 _FDT(spapr_fixup_cpu_numa_dt(fdt
, offset
, cpu
));
549 _FDT(spapr_fixup_cpu_smt_dt(fdt
, offset
, cpu
, compat_smt
));
551 if (pcc
->radix_page_info
) {
552 for (i
= 0; i
< pcc
->radix_page_info
->count
; i
++) {
553 radix_AP_encodings
[i
] =
554 cpu_to_be32(pcc
->radix_page_info
->entries
[i
]);
556 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-radix-AP-encodings",
558 pcc
->radix_page_info
->count
*
559 sizeof(radix_AP_encodings
[0]))));
563 static void spapr_populate_cpus_dt_node(void *fdt
, sPAPRMachineState
*spapr
)
572 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
574 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
575 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
578 * We walk the CPUs in reverse order to ensure that CPU DT nodes
579 * created by fdt_add_subnode() end up in the right order in FDT
580 * for the guest kernel the enumerate the CPUs correctly.
582 * The CPU list cannot be traversed in reverse order, so we need
588 rev
= g_renew(CPUState
*, rev
, n_cpus
+ 1);
592 for (i
= n_cpus
- 1; i
>= 0; i
--) {
593 CPUState
*cs
= rev
[i
];
594 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
595 int index
= spapr_get_vcpu_id(cpu
);
596 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
599 if (!spapr_is_thread0_in_vcore(spapr
, cpu
)) {
603 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, index
);
604 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
607 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
613 static int spapr_rng_populate_dt(void *fdt
)
618 node
= qemu_fdt_add_subnode(fdt
, "/ibm,platform-facilities");
622 ret
= fdt_setprop_string(fdt
, node
, "device_type",
623 "ibm,platform-facilities");
624 ret
|= fdt_setprop_cell(fdt
, node
, "#address-cells", 0x1);
625 ret
|= fdt_setprop_cell(fdt
, node
, "#size-cells", 0x0);
627 node
= fdt_add_subnode(fdt
, node
, "ibm,random-v1");
631 ret
|= fdt_setprop_string(fdt
, node
, "compatible", "ibm,random");
636 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList
*list
, ram_addr_t addr
)
638 MemoryDeviceInfoList
*info
;
640 for (info
= list
; info
; info
= info
->next
) {
641 MemoryDeviceInfo
*value
= info
->value
;
643 if (value
&& value
->type
== MEMORY_DEVICE_INFO_KIND_DIMM
) {
644 PCDIMMDeviceInfo
*pcdimm_info
= value
->u
.dimm
.data
;
646 if (addr
>= pcdimm_info
->addr
&&
647 addr
< (pcdimm_info
->addr
+ pcdimm_info
->size
)) {
648 return pcdimm_info
->node
;
656 struct sPAPRDrconfCellV2
{
664 typedef struct DrconfCellQueue
{
665 struct sPAPRDrconfCellV2 cell
;
666 QSIMPLEQ_ENTRY(DrconfCellQueue
) entry
;
669 static DrconfCellQueue
*
670 spapr_get_drconf_cell(uint32_t seq_lmbs
, uint64_t base_addr
,
671 uint32_t drc_index
, uint32_t aa_index
,
674 DrconfCellQueue
*elem
;
676 elem
= g_malloc0(sizeof(*elem
));
677 elem
->cell
.seq_lmbs
= cpu_to_be32(seq_lmbs
);
678 elem
->cell
.base_addr
= cpu_to_be64(base_addr
);
679 elem
->cell
.drc_index
= cpu_to_be32(drc_index
);
680 elem
->cell
.aa_index
= cpu_to_be32(aa_index
);
681 elem
->cell
.flags
= cpu_to_be32(flags
);
686 /* ibm,dynamic-memory-v2 */
687 static int spapr_populate_drmem_v2(sPAPRMachineState
*spapr
, void *fdt
,
688 int offset
, MemoryDeviceInfoList
*dimms
)
690 MachineState
*machine
= MACHINE(spapr
);
691 uint8_t *int_buf
, *cur_index
, buf_len
;
693 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
694 uint64_t addr
, cur_addr
, size
;
695 uint32_t nr_boot_lmbs
= (machine
->device_memory
->base
/ lmb_size
);
696 uint64_t mem_end
= machine
->device_memory
->base
+
697 memory_region_size(&machine
->device_memory
->mr
);
698 uint32_t node
, nr_entries
= 0;
699 sPAPRDRConnector
*drc
;
700 DrconfCellQueue
*elem
, *next
;
701 MemoryDeviceInfoList
*info
;
702 QSIMPLEQ_HEAD(, DrconfCellQueue
) drconf_queue
703 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue
);
705 /* Entry to cover RAM and the gap area */
706 elem
= spapr_get_drconf_cell(nr_boot_lmbs
, 0, 0, -1,
707 SPAPR_LMB_FLAGS_RESERVED
|
708 SPAPR_LMB_FLAGS_DRC_INVALID
);
709 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
712 cur_addr
= machine
->device_memory
->base
;
713 for (info
= dimms
; info
; info
= info
->next
) {
714 PCDIMMDeviceInfo
*di
= info
->value
->u
.dimm
.data
;
720 /* Entry for hot-pluggable area */
721 if (cur_addr
< addr
) {
722 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
724 elem
= spapr_get_drconf_cell((addr
- cur_addr
) / lmb_size
,
725 cur_addr
, spapr_drc_index(drc
), -1, 0);
726 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
731 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, addr
/ lmb_size
);
733 elem
= spapr_get_drconf_cell(size
/ lmb_size
, addr
,
734 spapr_drc_index(drc
), node
,
735 SPAPR_LMB_FLAGS_ASSIGNED
);
736 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
738 cur_addr
= addr
+ size
;
741 /* Entry for remaining hotpluggable area */
742 if (cur_addr
< mem_end
) {
743 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, cur_addr
/ lmb_size
);
745 elem
= spapr_get_drconf_cell((mem_end
- cur_addr
) / lmb_size
,
746 cur_addr
, spapr_drc_index(drc
), -1, 0);
747 QSIMPLEQ_INSERT_TAIL(&drconf_queue
, elem
, entry
);
751 buf_len
= nr_entries
* sizeof(struct sPAPRDrconfCellV2
) + sizeof(uint32_t);
752 int_buf
= cur_index
= g_malloc0(buf_len
);
753 *(uint32_t *)int_buf
= cpu_to_be32(nr_entries
);
754 cur_index
+= sizeof(nr_entries
);
756 QSIMPLEQ_FOREACH_SAFE(elem
, &drconf_queue
, entry
, next
) {
757 memcpy(cur_index
, &elem
->cell
, sizeof(elem
->cell
));
758 cur_index
+= sizeof(elem
->cell
);
759 QSIMPLEQ_REMOVE(&drconf_queue
, elem
, DrconfCellQueue
, entry
);
763 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory-v2", int_buf
, buf_len
);
771 /* ibm,dynamic-memory */
772 static int spapr_populate_drmem_v1(sPAPRMachineState
*spapr
, void *fdt
,
773 int offset
, MemoryDeviceInfoList
*dimms
)
775 MachineState
*machine
= MACHINE(spapr
);
777 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
778 uint32_t device_lmb_start
= machine
->device_memory
->base
/ lmb_size
;
779 uint32_t nr_lmbs
= (machine
->device_memory
->base
+
780 memory_region_size(&machine
->device_memory
->mr
)) /
782 uint32_t *int_buf
, *cur_index
, buf_len
;
785 * Allocate enough buffer size to fit in ibm,dynamic-memory
787 buf_len
= (nr_lmbs
* SPAPR_DR_LMB_LIST_ENTRY_SIZE
+ 1) * sizeof(uint32_t);
788 cur_index
= int_buf
= g_malloc0(buf_len
);
789 int_buf
[0] = cpu_to_be32(nr_lmbs
);
791 for (i
= 0; i
< nr_lmbs
; i
++) {
792 uint64_t addr
= i
* lmb_size
;
793 uint32_t *dynamic_memory
= cur_index
;
795 if (i
>= device_lmb_start
) {
796 sPAPRDRConnector
*drc
;
798 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
, i
);
801 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
802 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
803 dynamic_memory
[2] = cpu_to_be32(spapr_drc_index(drc
));
804 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
805 dynamic_memory
[4] = cpu_to_be32(spapr_pc_dimm_node(dimms
, addr
));
806 if (memory_region_present(get_system_memory(), addr
)) {
807 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED
);
809 dynamic_memory
[5] = cpu_to_be32(0);
813 * LMB information for RMA, boot time RAM and gap b/n RAM and
814 * device memory region -- all these are marked as reserved
815 * and as having no valid DRC.
817 dynamic_memory
[0] = cpu_to_be32(addr
>> 32);
818 dynamic_memory
[1] = cpu_to_be32(addr
& 0xffffffff);
819 dynamic_memory
[2] = cpu_to_be32(0);
820 dynamic_memory
[3] = cpu_to_be32(0); /* reserved */
821 dynamic_memory
[4] = cpu_to_be32(-1);
822 dynamic_memory
[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED
|
823 SPAPR_LMB_FLAGS_DRC_INVALID
);
826 cur_index
+= SPAPR_DR_LMB_LIST_ENTRY_SIZE
;
828 ret
= fdt_setprop(fdt
, offset
, "ibm,dynamic-memory", int_buf
, buf_len
);
837 * Adds ibm,dynamic-reconfiguration-memory node.
838 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
839 * of this device tree node.
841 static int spapr_populate_drconf_memory(sPAPRMachineState
*spapr
, void *fdt
)
843 MachineState
*machine
= MACHINE(spapr
);
845 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
846 uint32_t prop_lmb_size
[] = {0, cpu_to_be32(lmb_size
)};
847 uint32_t *int_buf
, *cur_index
, buf_len
;
848 int nr_nodes
= nb_numa_nodes
? nb_numa_nodes
: 1;
849 MemoryDeviceInfoList
*dimms
= NULL
;
852 * Don't create the node if there is no device memory
854 if (machine
->ram_size
== machine
->maxram_size
) {
858 offset
= fdt_add_subnode(fdt
, 0, "ibm,dynamic-reconfiguration-memory");
860 ret
= fdt_setprop(fdt
, offset
, "ibm,lmb-size", prop_lmb_size
,
861 sizeof(prop_lmb_size
));
866 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-flags-mask", 0xff);
871 ret
= fdt_setprop_cell(fdt
, offset
, "ibm,memory-preservation-time", 0x0);
876 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */
877 dimms
= qmp_memory_device_list();
878 if (spapr_ovec_test(spapr
->ov5_cas
, OV5_DRMEM_V2
)) {
879 ret
= spapr_populate_drmem_v2(spapr
, fdt
, offset
, dimms
);
881 ret
= spapr_populate_drmem_v1(spapr
, fdt
, offset
, dimms
);
883 qapi_free_MemoryDeviceInfoList(dimms
);
889 /* ibm,associativity-lookup-arrays */
890 buf_len
= (nr_nodes
* 4 + 2) * sizeof(uint32_t);
891 cur_index
= int_buf
= g_malloc0(buf_len
);
892 int_buf
[0] = cpu_to_be32(nr_nodes
);
893 int_buf
[1] = cpu_to_be32(4); /* Number of entries per associativity list */
895 for (i
= 0; i
< nr_nodes
; i
++) {
896 uint32_t associativity
[] = {
902 memcpy(cur_index
, associativity
, sizeof(associativity
));
905 ret
= fdt_setprop(fdt
, offset
, "ibm,associativity-lookup-arrays", int_buf
,
906 (cur_index
- int_buf
) * sizeof(uint32_t));
912 static int spapr_dt_cas_updates(sPAPRMachineState
*spapr
, void *fdt
,
913 sPAPROptionVector
*ov5_updates
)
915 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
918 /* Generate ibm,dynamic-reconfiguration-memory node if required */
919 if (spapr_ovec_test(ov5_updates
, OV5_DRCONF_MEMORY
)) {
920 g_assert(smc
->dr_lmb_enabled
);
921 ret
= spapr_populate_drconf_memory(spapr
, fdt
);
927 offset
= fdt_path_offset(fdt
, "/chosen");
929 offset
= fdt_add_subnode(fdt
, 0, "chosen");
934 ret
= spapr_ovec_populate_dt(fdt
, offset
, spapr
->ov5_cas
,
935 "ibm,architecture-vec-5");
941 static bool spapr_hotplugged_dev_before_cas(void)
943 Object
*drc_container
, *obj
;
944 ObjectProperty
*prop
;
945 ObjectPropertyIterator iter
;
947 drc_container
= container_get(object_get_root(), "/dr-connector");
948 object_property_iter_init(&iter
, drc_container
);
949 while ((prop
= object_property_iter_next(&iter
))) {
950 if (!strstart(prop
->type
, "link<", NULL
)) {
953 obj
= object_property_get_link(drc_container
, prop
->name
, NULL
);
954 if (spapr_drc_needed(obj
)) {
961 int spapr_h_cas_compose_response(sPAPRMachineState
*spapr
,
962 target_ulong addr
, target_ulong size
,
963 sPAPROptionVector
*ov5_updates
)
965 void *fdt
, *fdt_skel
;
966 sPAPRDeviceTreeUpdateHeader hdr
= { .version_id
= 1 };
968 if (spapr_hotplugged_dev_before_cas()) {
972 if (size
< sizeof(hdr
) || size
> FW_MAX_SIZE
) {
973 error_report("SLOF provided an unexpected CAS buffer size "
974 TARGET_FMT_lu
" (min: %zu, max: %u)",
975 size
, sizeof(hdr
), FW_MAX_SIZE
);
981 /* Create skeleton */
982 fdt_skel
= g_malloc0(size
);
983 _FDT((fdt_create(fdt_skel
, size
)));
984 _FDT((fdt_finish_reservemap(fdt_skel
)));
985 _FDT((fdt_begin_node(fdt_skel
, "")));
986 _FDT((fdt_end_node(fdt_skel
)));
987 _FDT((fdt_finish(fdt_skel
)));
988 fdt
= g_malloc0(size
);
989 _FDT((fdt_open_into(fdt_skel
, fdt
, size
)));
992 /* Fixup cpu nodes */
993 _FDT((spapr_fixup_cpu_dt(fdt
, spapr
)));
995 if (spapr_dt_cas_updates(spapr
, fdt
, ov5_updates
)) {
999 /* Pack resulting tree */
1000 _FDT((fdt_pack(fdt
)));
1002 if (fdt_totalsize(fdt
) + sizeof(hdr
) > size
) {
1003 trace_spapr_cas_failed(size
);
1007 cpu_physical_memory_write(addr
, &hdr
, sizeof(hdr
));
1008 cpu_physical_memory_write(addr
+ sizeof(hdr
), fdt
, fdt_totalsize(fdt
));
1009 trace_spapr_cas_continue(fdt_totalsize(fdt
) + sizeof(hdr
));
1015 static void spapr_dt_rtas(sPAPRMachineState
*spapr
, void *fdt
)
1018 GString
*hypertas
= g_string_sized_new(256);
1019 GString
*qemu_hypertas
= g_string_sized_new(256);
1020 uint32_t refpoints
[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
1021 uint64_t max_device_addr
= MACHINE(spapr
)->device_memory
->base
+
1022 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
1023 uint32_t lrdr_capacity
[] = {
1024 cpu_to_be32(max_device_addr
>> 32),
1025 cpu_to_be32(max_device_addr
& 0xffffffff),
1026 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE
),
1027 cpu_to_be32(max_cpus
/ smp_threads
),
1029 uint32_t maxdomains
[] = {
1034 cpu_to_be32(nb_numa_nodes
? nb_numa_nodes
: 1),
1037 _FDT(rtas
= fdt_add_subnode(fdt
, 0, "rtas"));
1040 add_str(hypertas
, "hcall-pft");
1041 add_str(hypertas
, "hcall-term");
1042 add_str(hypertas
, "hcall-dabr");
1043 add_str(hypertas
, "hcall-interrupt");
1044 add_str(hypertas
, "hcall-tce");
1045 add_str(hypertas
, "hcall-vio");
1046 add_str(hypertas
, "hcall-splpar");
1047 add_str(hypertas
, "hcall-bulk");
1048 add_str(hypertas
, "hcall-set-mode");
1049 add_str(hypertas
, "hcall-sprg0");
1050 add_str(hypertas
, "hcall-copy");
1051 add_str(hypertas
, "hcall-debug");
1052 add_str(qemu_hypertas
, "hcall-memop1");
1054 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
1055 add_str(hypertas
, "hcall-multi-tce");
1058 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
1059 add_str(hypertas
, "hcall-hpt-resize");
1062 _FDT(fdt_setprop(fdt
, rtas
, "ibm,hypertas-functions",
1063 hypertas
->str
, hypertas
->len
));
1064 g_string_free(hypertas
, TRUE
);
1065 _FDT(fdt_setprop(fdt
, rtas
, "qemu,hypertas-functions",
1066 qemu_hypertas
->str
, qemu_hypertas
->len
));
1067 g_string_free(qemu_hypertas
, TRUE
);
1069 _FDT(fdt_setprop(fdt
, rtas
, "ibm,associativity-reference-points",
1070 refpoints
, sizeof(refpoints
)));
1072 _FDT(fdt_setprop(fdt
, rtas
, "ibm,max-associativity-domains",
1073 maxdomains
, sizeof(maxdomains
)));
1075 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-error-log-max",
1076 RTAS_ERROR_LOG_MAX
));
1077 _FDT(fdt_setprop_cell(fdt
, rtas
, "rtas-event-scan-rate",
1078 RTAS_EVENT_SCAN_RATE
));
1080 g_assert(msi_nonbroken
);
1081 _FDT(fdt_setprop(fdt
, rtas
, "ibm,change-msix-capable", NULL
, 0));
1084 * According to PAPR, rtas ibm,os-term does not guarantee a return
1085 * back to the guest cpu.
1087 * While an additional ibm,extended-os-term property indicates
1088 * that rtas call return will always occur. Set this property.
1090 _FDT(fdt_setprop(fdt
, rtas
, "ibm,extended-os-term", NULL
, 0));
1092 _FDT(fdt_setprop(fdt
, rtas
, "ibm,lrdr-capacity",
1093 lrdr_capacity
, sizeof(lrdr_capacity
)));
1095 spapr_dt_rtas_tokens(fdt
, rtas
);
1099 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU
1100 * and the XIVE features that the guest may request and thus the valid
1101 * values for bytes 23..26 of option vector 5:
1103 static void spapr_dt_ov5_platform_support(sPAPRMachineState
*spapr
, void *fdt
,
1106 PowerPCCPU
*first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1109 23, spapr
->irq
->ov5
, /* Xive mode. */
1110 24, 0x00, /* Hash/Radix, filled in below. */
1111 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
1112 26, 0x40, /* Radix options: GTSE == yes. */
1115 if (!ppc_check_compat(first_ppc_cpu
, CPU_POWERPC_LOGICAL_3_00
, 0,
1116 first_ppc_cpu
->compat_pvr
)) {
1118 * If we're in a pre POWER9 compat mode then the guest should
1119 * do hash and use the legacy interrupt mode
1121 val
[1] = 0x00; /* XICS */
1122 val
[3] = 0x00; /* Hash */
1123 } else if (kvm_enabled()) {
1124 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
1125 val
[3] = 0x80; /* OV5_MMU_BOTH */
1126 } else if (kvmppc_has_cap_mmu_radix()) {
1127 val
[3] = 0x40; /* OV5_MMU_RADIX_300 */
1129 val
[3] = 0x00; /* Hash */
1132 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
1135 _FDT(fdt_setprop(fdt
, chosen
, "ibm,arch-vec-5-platform-support",
1139 static void spapr_dt_chosen(sPAPRMachineState
*spapr
, void *fdt
)
1141 MachineState
*machine
= MACHINE(spapr
);
1143 const char *boot_device
= machine
->boot_order
;
1144 char *stdout_path
= spapr_vio_stdout_path(spapr
->vio_bus
);
1146 char *bootlist
= get_boot_devices_list(&cb
);
1148 _FDT(chosen
= fdt_add_subnode(fdt
, 0, "chosen"));
1150 _FDT(fdt_setprop_string(fdt
, chosen
, "bootargs", machine
->kernel_cmdline
));
1151 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-start",
1152 spapr
->initrd_base
));
1153 _FDT(fdt_setprop_cell(fdt
, chosen
, "linux,initrd-end",
1154 spapr
->initrd_base
+ spapr
->initrd_size
));
1156 if (spapr
->kernel_size
) {
1157 uint64_t kprop
[2] = { cpu_to_be64(KERNEL_LOAD_ADDR
),
1158 cpu_to_be64(spapr
->kernel_size
) };
1160 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel",
1161 &kprop
, sizeof(kprop
)));
1162 if (spapr
->kernel_le
) {
1163 _FDT(fdt_setprop(fdt
, chosen
, "qemu,boot-kernel-le", NULL
, 0));
1167 _FDT((fdt_setprop_cell(fdt
, chosen
, "qemu,boot-menu", boot_menu
)));
1169 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-width", graphic_width
));
1170 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-height", graphic_height
));
1171 _FDT(fdt_setprop_cell(fdt
, chosen
, "qemu,graphic-depth", graphic_depth
));
1173 if (cb
&& bootlist
) {
1176 for (i
= 0; i
< cb
; i
++) {
1177 if (bootlist
[i
] == '\n') {
1181 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-list", bootlist
));
1184 if (boot_device
&& strlen(boot_device
)) {
1185 _FDT(fdt_setprop_string(fdt
, chosen
, "qemu,boot-device", boot_device
));
1188 if (!spapr
->has_graphics
&& stdout_path
) {
1190 * "linux,stdout-path" and "stdout" properties are deprecated by linux
1191 * kernel. New platforms should only use the "stdout-path" property. Set
1192 * the new property and continue using older property to remain
1193 * compatible with the existing firmware.
1195 _FDT(fdt_setprop_string(fdt
, chosen
, "linux,stdout-path", stdout_path
));
1196 _FDT(fdt_setprop_string(fdt
, chosen
, "stdout-path", stdout_path
));
1199 spapr_dt_ov5_platform_support(spapr
, fdt
, chosen
);
1201 g_free(stdout_path
);
1205 static void spapr_dt_hypervisor(sPAPRMachineState
*spapr
, void *fdt
)
1207 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1208 * KVM to work under pHyp with some guest co-operation */
1210 uint8_t hypercall
[16];
1212 _FDT(hypervisor
= fdt_add_subnode(fdt
, 0, "hypervisor"));
1213 /* indicate KVM hypercall interface */
1214 _FDT(fdt_setprop_string(fdt
, hypervisor
, "compatible", "linux,kvm"));
1215 if (kvmppc_has_cap_fixup_hcalls()) {
1217 * Older KVM versions with older guest kernels were broken
1218 * with the magic page, don't allow the guest to map it.
1220 if (!kvmppc_get_hypercall(first_cpu
->env_ptr
, hypercall
,
1221 sizeof(hypercall
))) {
1222 _FDT(fdt_setprop(fdt
, hypervisor
, "hcall-instructions",
1223 hypercall
, sizeof(hypercall
)));
1228 static void *spapr_build_fdt(sPAPRMachineState
*spapr
,
1232 MachineState
*machine
= MACHINE(spapr
);
1233 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
1234 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
1240 fdt
= g_malloc0(FDT_MAX_SIZE
);
1241 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
1244 _FDT(fdt_setprop_string(fdt
, 0, "device_type", "chrp"));
1245 _FDT(fdt_setprop_string(fdt
, 0, "model", "IBM pSeries (emulated by qemu)"));
1246 _FDT(fdt_setprop_string(fdt
, 0, "compatible", "qemu,pseries"));
1249 * Add info to guest to indentify which host is it being run on
1250 * and what is the uuid of the guest
1252 if (kvmppc_get_host_model(&buf
)) {
1253 _FDT(fdt_setprop_string(fdt
, 0, "host-model", buf
));
1256 if (kvmppc_get_host_serial(&buf
)) {
1257 _FDT(fdt_setprop_string(fdt
, 0, "host-serial", buf
));
1261 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
1263 _FDT(fdt_setprop_string(fdt
, 0, "vm,uuid", buf
));
1264 if (qemu_uuid_set
) {
1265 _FDT(fdt_setprop_string(fdt
, 0, "system-id", buf
));
1269 if (qemu_get_vm_name()) {
1270 _FDT(fdt_setprop_string(fdt
, 0, "ibm,partition-name",
1271 qemu_get_vm_name()));
1274 _FDT(fdt_setprop_cell(fdt
, 0, "#address-cells", 2));
1275 _FDT(fdt_setprop_cell(fdt
, 0, "#size-cells", 2));
1277 /* /interrupt controller */
1278 spapr
->irq
->dt_populate(spapr
, spapr_max_server_number(spapr
), fdt
,
1281 ret
= spapr_populate_memory(spapr
, fdt
);
1283 error_report("couldn't setup memory nodes in fdt");
1288 spapr_dt_vdevice(spapr
->vio_bus
, fdt
);
1290 if (object_resolve_path_type("", TYPE_SPAPR_RNG
, NULL
)) {
1291 ret
= spapr_rng_populate_dt(fdt
);
1293 error_report("could not set up rng device in the fdt");
1298 QLIST_FOREACH(phb
, &spapr
->phbs
, list
) {
1299 ret
= spapr_populate_pci_dt(phb
, PHANDLE_XICP
, fdt
,
1300 spapr
->irq
->nr_msis
);
1302 error_report("couldn't setup PCI devices in fdt");
1308 spapr_populate_cpus_dt_node(fdt
, spapr
);
1310 if (smc
->dr_lmb_enabled
) {
1311 _FDT(spapr_drc_populate_dt(fdt
, 0, NULL
, SPAPR_DR_CONNECTOR_TYPE_LMB
));
1314 if (mc
->has_hotpluggable_cpus
) {
1315 int offset
= fdt_path_offset(fdt
, "/cpus");
1316 ret
= spapr_drc_populate_dt(fdt
, offset
, NULL
,
1317 SPAPR_DR_CONNECTOR_TYPE_CPU
);
1319 error_report("Couldn't set up CPU DR device tree properties");
1324 /* /event-sources */
1325 spapr_dt_events(spapr
, fdt
);
1328 spapr_dt_rtas(spapr
, fdt
);
1331 spapr_dt_chosen(spapr
, fdt
);
1334 if (kvm_enabled()) {
1335 spapr_dt_hypervisor(spapr
, fdt
);
1338 /* Build memory reserve map */
1339 if (spapr
->kernel_size
) {
1340 _FDT((fdt_add_mem_rsv(fdt
, KERNEL_LOAD_ADDR
, spapr
->kernel_size
)));
1342 if (spapr
->initrd_size
) {
1343 _FDT((fdt_add_mem_rsv(fdt
, spapr
->initrd_base
, spapr
->initrd_size
)));
1346 /* ibm,client-architecture-support updates */
1347 ret
= spapr_dt_cas_updates(spapr
, fdt
, spapr
->ov5_cas
);
1349 error_report("couldn't setup CAS properties fdt");
1356 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
1358 return (addr
& 0x0fffffff) + KERNEL_LOAD_ADDR
;
1361 static void emulate_spapr_hypercall(PPCVirtualHypervisor
*vhyp
,
1364 CPUPPCState
*env
= &cpu
->env
;
1366 /* The TCG path should also be holding the BQL at this point */
1367 g_assert(qemu_mutex_iothread_locked());
1370 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1371 env
->gpr
[3] = H_PRIVILEGE
;
1373 env
->gpr
[3] = spapr_hypercall(cpu
, env
->gpr
[3], &env
->gpr
[4]);
1377 static uint64_t spapr_get_patbe(PPCVirtualHypervisor
*vhyp
)
1379 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1381 return spapr
->patb_entry
;
1384 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1385 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1386 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1387 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1388 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1391 * Get the fd to access the kernel htab, re-opening it if necessary
1393 static int get_htab_fd(sPAPRMachineState
*spapr
)
1395 Error
*local_err
= NULL
;
1397 if (spapr
->htab_fd
>= 0) {
1398 return spapr
->htab_fd
;
1401 spapr
->htab_fd
= kvmppc_get_htab_fd(false, 0, &local_err
);
1402 if (spapr
->htab_fd
< 0) {
1403 error_report_err(local_err
);
1406 return spapr
->htab_fd
;
1409 void close_htab_fd(sPAPRMachineState
*spapr
)
1411 if (spapr
->htab_fd
>= 0) {
1412 close(spapr
->htab_fd
);
1414 spapr
->htab_fd
= -1;
1417 static hwaddr
spapr_hpt_mask(PPCVirtualHypervisor
*vhyp
)
1419 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1421 return HTAB_SIZE(spapr
) / HASH_PTEG_SIZE_64
- 1;
1424 static target_ulong
spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor
*vhyp
)
1426 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1428 assert(kvm_enabled());
1434 return (target_ulong
)(uintptr_t)spapr
->htab
| (spapr
->htab_shift
- 18);
1437 static const ppc_hash_pte64_t
*spapr_map_hptes(PPCVirtualHypervisor
*vhyp
,
1440 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1441 hwaddr pte_offset
= ptex
* HASH_PTE_SIZE_64
;
1445 * HTAB is controlled by KVM. Fetch into temporary buffer
1447 ppc_hash_pte64_t
*hptes
= g_malloc(n
* HASH_PTE_SIZE_64
);
1448 kvmppc_read_hptes(hptes
, ptex
, n
);
1453 * HTAB is controlled by QEMU. Just point to the internally
1456 return (const ppc_hash_pte64_t
*)(spapr
->htab
+ pte_offset
);
1459 static void spapr_unmap_hptes(PPCVirtualHypervisor
*vhyp
,
1460 const ppc_hash_pte64_t
*hptes
,
1463 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1466 g_free((void *)hptes
);
1469 /* Nothing to do for qemu managed HPT */
1472 static void spapr_store_hpte(PPCVirtualHypervisor
*vhyp
, hwaddr ptex
,
1473 uint64_t pte0
, uint64_t pte1
)
1475 sPAPRMachineState
*spapr
= SPAPR_MACHINE(vhyp
);
1476 hwaddr offset
= ptex
* HASH_PTE_SIZE_64
;
1479 kvmppc_write_hpte(ptex
, pte0
, pte1
);
1481 stq_p(spapr
->htab
+ offset
, pte0
);
1482 stq_p(spapr
->htab
+ offset
+ HASH_PTE_SIZE_64
/ 2, pte1
);
1486 int spapr_hpt_shift_for_ramsize(uint64_t ramsize
)
1490 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1491 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1492 * that's much more than is needed for Linux guests */
1493 shift
= ctz64(pow2ceil(ramsize
)) - 7;
1494 shift
= MAX(shift
, 18); /* Minimum architected size */
1495 shift
= MIN(shift
, 46); /* Maximum architected size */
1499 void spapr_free_hpt(sPAPRMachineState
*spapr
)
1501 g_free(spapr
->htab
);
1503 spapr
->htab_shift
= 0;
1504 close_htab_fd(spapr
);
1507 void spapr_reallocate_hpt(sPAPRMachineState
*spapr
, int shift
,
1512 /* Clean up any HPT info from a previous boot */
1513 spapr_free_hpt(spapr
);
1515 rc
= kvmppc_reset_htab(shift
);
1517 /* kernel-side HPT needed, but couldn't allocate one */
1518 error_setg_errno(errp
, errno
,
1519 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1521 /* This is almost certainly fatal, but if the caller really
1522 * wants to carry on with shift == 0, it's welcome to try */
1523 } else if (rc
> 0) {
1524 /* kernel-side HPT allocated */
1527 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1531 spapr
->htab_shift
= shift
;
1534 /* kernel-side HPT not needed, allocate in userspace instead */
1535 size_t size
= 1ULL << shift
;
1538 spapr
->htab
= qemu_memalign(size
, size
);
1540 error_setg_errno(errp
, errno
,
1541 "Could not allocate HPT of order %d", shift
);
1545 memset(spapr
->htab
, 0, size
);
1546 spapr
->htab_shift
= shift
;
1548 for (i
= 0; i
< size
/ HASH_PTE_SIZE_64
; i
++) {
1549 DIRTY_HPTE(HPTE(spapr
->htab
, i
));
1552 /* We're setting up a hash table, so that means we're not radix */
1553 spapr
->patb_entry
= 0;
1556 void spapr_setup_hpt_and_vrma(sPAPRMachineState
*spapr
)
1560 if ((spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DISABLED
)
1561 || (spapr
->cas_reboot
1562 && !spapr_ovec_test(spapr
->ov5_cas
, OV5_HPT_RESIZE
))) {
1563 hpt_shift
= spapr_hpt_shift_for_ramsize(MACHINE(spapr
)->maxram_size
);
1565 uint64_t current_ram_size
;
1567 current_ram_size
= MACHINE(spapr
)->ram_size
+ get_plugged_memory_size();
1568 hpt_shift
= spapr_hpt_shift_for_ramsize(current_ram_size
);
1570 spapr_reallocate_hpt(spapr
, hpt_shift
, &error_fatal
);
1572 if (spapr
->vrma_adjust
) {
1573 spapr
->rma_size
= kvmppc_rma_size(spapr_node0_size(MACHINE(spapr
)),
1578 static int spapr_reset_drcs(Object
*child
, void *opaque
)
1580 sPAPRDRConnector
*drc
=
1581 (sPAPRDRConnector
*) object_dynamic_cast(child
,
1582 TYPE_SPAPR_DR_CONNECTOR
);
1585 spapr_drc_reset(drc
);
1591 static void spapr_machine_reset(void)
1593 MachineState
*machine
= MACHINE(qdev_get_machine());
1594 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
1595 PowerPCCPU
*first_ppc_cpu
;
1596 uint32_t rtas_limit
;
1597 hwaddr rtas_addr
, fdt_addr
;
1601 spapr_caps_apply(spapr
);
1603 first_ppc_cpu
= POWERPC_CPU(first_cpu
);
1604 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1605 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
1606 spapr
->max_compat_pvr
)) {
1607 /* If using KVM with radix mode available, VCPUs can be started
1608 * without a HPT because KVM will start them in radix mode.
1609 * Set the GR bit in PATB so that we know there is no HPT. */
1610 spapr
->patb_entry
= PATBE1_GR
;
1612 spapr_setup_hpt_and_vrma(spapr
);
1615 /* if this reset wasn't generated by CAS, we should reset our
1616 * negotiated options and start from scratch */
1617 if (!spapr
->cas_reboot
) {
1618 spapr_ovec_cleanup(spapr
->ov5_cas
);
1619 spapr
->ov5_cas
= spapr_ovec_new();
1621 ppc_set_compat(first_ppc_cpu
, spapr
->max_compat_pvr
, &error_fatal
);
1624 if (!SPAPR_MACHINE_GET_CLASS(spapr
)->legacy_irq_allocation
) {
1625 spapr_irq_msi_reset(spapr
);
1628 qemu_devices_reset();
1631 * This is fixing some of the default configuration of the XIVE
1632 * devices. To be called after the reset of the machine devices.
1634 spapr_irq_reset(spapr
, &error_fatal
);
1636 /* DRC reset may cause a device to be unplugged. This will cause troubles
1637 * if this device is used by another device (eg, a running vhost backend
1638 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1639 * situations, we reset DRCs after all devices have been reset.
1641 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs
, NULL
);
1643 spapr_clear_pending_events(spapr
);
1646 * We place the device tree and RTAS just below either the top of the RMA,
1647 * or just below 2GB, whichever is lowere, so that it can be
1648 * processed with 32-bit real mode code if necessary
1650 rtas_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
);
1651 rtas_addr
= rtas_limit
- RTAS_MAX_SIZE
;
1652 fdt_addr
= rtas_addr
- FDT_MAX_SIZE
;
1654 fdt
= spapr_build_fdt(spapr
, rtas_addr
, spapr
->rtas_size
);
1656 spapr_load_rtas(spapr
, fdt
, rtas_addr
);
1660 /* Should only fail if we've built a corrupted tree */
1663 if (fdt_totalsize(fdt
) > FDT_MAX_SIZE
) {
1664 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1665 fdt_totalsize(fdt
), FDT_MAX_SIZE
);
1670 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
1671 cpu_physical_memory_write(fdt_addr
, fdt
, fdt_totalsize(fdt
));
1674 /* Set up the entry state */
1675 spapr_cpu_set_entry_state(first_ppc_cpu
, SPAPR_ENTRY_POINT
, fdt_addr
);
1676 first_ppc_cpu
->env
.gpr
[5] = 0;
1678 spapr
->cas_reboot
= false;
1681 static void spapr_create_nvram(sPAPRMachineState
*spapr
)
1683 DeviceState
*dev
= qdev_create(&spapr
->vio_bus
->bus
, "spapr-nvram");
1684 DriveInfo
*dinfo
= drive_get(IF_PFLASH
, 0, 0);
1687 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
1691 qdev_init_nofail(dev
);
1693 spapr
->nvram
= (struct sPAPRNVRAM
*)dev
;
1696 static void spapr_rtc_create(sPAPRMachineState
*spapr
)
1698 object_initialize(&spapr
->rtc
, sizeof(spapr
->rtc
), TYPE_SPAPR_RTC
);
1699 object_property_add_child(OBJECT(spapr
), "rtc", OBJECT(&spapr
->rtc
),
1701 object_property_set_bool(OBJECT(&spapr
->rtc
), true, "realized",
1703 object_property_add_alias(OBJECT(spapr
), "rtc-time", OBJECT(&spapr
->rtc
),
1704 "date", &error_fatal
);
1707 /* Returns whether we want to use VGA or not */
1708 static bool spapr_vga_init(PCIBus
*pci_bus
, Error
**errp
)
1710 switch (vga_interface_type
) {
1717 return pci_vga_init(pci_bus
) != NULL
;
1720 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1725 static int spapr_pre_load(void *opaque
)
1729 rc
= spapr_caps_pre_load(opaque
);
1737 static int spapr_post_load(void *opaque
, int version_id
)
1739 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1742 err
= spapr_caps_post_migration(spapr
);
1747 /* In earlier versions, there was no separate qdev for the PAPR
1748 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1749 * So when migrating from those versions, poke the incoming offset
1750 * value into the RTC device */
1751 if (version_id
< 3) {
1752 err
= spapr_rtc_import_offset(&spapr
->rtc
, spapr
->rtc_offset
);
1755 if (kvm_enabled() && spapr
->patb_entry
) {
1756 PowerPCCPU
*cpu
= POWERPC_CPU(first_cpu
);
1757 bool radix
= !!(spapr
->patb_entry
& PATBE1_GR
);
1758 bool gtse
= !!(cpu
->env
.spr
[SPR_LPCR
] & LPCR_GTSE
);
1760 err
= kvmppc_configure_v3_mmu(cpu
, radix
, gtse
, spapr
->patb_entry
);
1762 error_report("Process table config unsupported by the host");
1767 err
= spapr_irq_post_load(spapr
, version_id
);
1775 static int spapr_pre_save(void *opaque
)
1779 rc
= spapr_caps_pre_save(opaque
);
1787 static bool version_before_3(void *opaque
, int version_id
)
1789 return version_id
< 3;
1792 static bool spapr_pending_events_needed(void *opaque
)
1794 sPAPRMachineState
*spapr
= (sPAPRMachineState
*)opaque
;
1795 return !QTAILQ_EMPTY(&spapr
->pending_events
);
1798 static const VMStateDescription vmstate_spapr_event_entry
= {
1799 .name
= "spapr_event_log_entry",
1801 .minimum_version_id
= 1,
1802 .fields
= (VMStateField
[]) {
1803 VMSTATE_UINT32(summary
, sPAPREventLogEntry
),
1804 VMSTATE_UINT32(extended_length
, sPAPREventLogEntry
),
1805 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log
, sPAPREventLogEntry
, 0,
1806 NULL
, extended_length
),
1807 VMSTATE_END_OF_LIST()
1811 static const VMStateDescription vmstate_spapr_pending_events
= {
1812 .name
= "spapr_pending_events",
1814 .minimum_version_id
= 1,
1815 .needed
= spapr_pending_events_needed
,
1816 .fields
= (VMStateField
[]) {
1817 VMSTATE_QTAILQ_V(pending_events
, sPAPRMachineState
, 1,
1818 vmstate_spapr_event_entry
, sPAPREventLogEntry
, next
),
1819 VMSTATE_END_OF_LIST()
1823 static bool spapr_ov5_cas_needed(void *opaque
)
1825 sPAPRMachineState
*spapr
= opaque
;
1826 sPAPROptionVector
*ov5_mask
= spapr_ovec_new();
1827 sPAPROptionVector
*ov5_legacy
= spapr_ovec_new();
1828 sPAPROptionVector
*ov5_removed
= spapr_ovec_new();
1831 /* Prior to the introduction of sPAPROptionVector, we had two option
1832 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1833 * Both of these options encode machine topology into the device-tree
1834 * in such a way that the now-booted OS should still be able to interact
1835 * appropriately with QEMU regardless of what options were actually
1836 * negotiatied on the source side.
1838 * As such, we can avoid migrating the CAS-negotiated options if these
1839 * are the only options available on the current machine/platform.
1840 * Since these are the only options available for pseries-2.7 and
1841 * earlier, this allows us to maintain old->new/new->old migration
1844 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1845 * via default pseries-2.8 machines and explicit command-line parameters.
1846 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1847 * of the actual CAS-negotiated values to continue working properly. For
1848 * example, availability of memory unplug depends on knowing whether
1849 * OV5_HP_EVT was negotiated via CAS.
1851 * Thus, for any cases where the set of available CAS-negotiatable
1852 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1853 * include the CAS-negotiated options in the migration stream, unless
1854 * if they affect boot time behaviour only.
1856 spapr_ovec_set(ov5_mask
, OV5_FORM1_AFFINITY
);
1857 spapr_ovec_set(ov5_mask
, OV5_DRCONF_MEMORY
);
1858 spapr_ovec_set(ov5_mask
, OV5_DRMEM_V2
);
1860 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1861 * the mask itself since in the future it's possible "legacy" bits may be
1862 * removed via machine options, which could generate a false positive
1863 * that breaks migration.
1865 spapr_ovec_intersect(ov5_legacy
, spapr
->ov5
, ov5_mask
);
1866 cas_needed
= spapr_ovec_diff(ov5_removed
, spapr
->ov5
, ov5_legacy
);
1868 spapr_ovec_cleanup(ov5_mask
);
1869 spapr_ovec_cleanup(ov5_legacy
);
1870 spapr_ovec_cleanup(ov5_removed
);
1875 static const VMStateDescription vmstate_spapr_ov5_cas
= {
1876 .name
= "spapr_option_vector_ov5_cas",
1878 .minimum_version_id
= 1,
1879 .needed
= spapr_ov5_cas_needed
,
1880 .fields
= (VMStateField
[]) {
1881 VMSTATE_STRUCT_POINTER_V(ov5_cas
, sPAPRMachineState
, 1,
1882 vmstate_spapr_ovec
, sPAPROptionVector
),
1883 VMSTATE_END_OF_LIST()
1887 static bool spapr_patb_entry_needed(void *opaque
)
1889 sPAPRMachineState
*spapr
= opaque
;
1891 return !!spapr
->patb_entry
;
1894 static const VMStateDescription vmstate_spapr_patb_entry
= {
1895 .name
= "spapr_patb_entry",
1897 .minimum_version_id
= 1,
1898 .needed
= spapr_patb_entry_needed
,
1899 .fields
= (VMStateField
[]) {
1900 VMSTATE_UINT64(patb_entry
, sPAPRMachineState
),
1901 VMSTATE_END_OF_LIST()
1905 static bool spapr_irq_map_needed(void *opaque
)
1907 sPAPRMachineState
*spapr
= opaque
;
1909 return spapr
->irq_map
&& !bitmap_empty(spapr
->irq_map
, spapr
->irq_map_nr
);
1912 static const VMStateDescription vmstate_spapr_irq_map
= {
1913 .name
= "spapr_irq_map",
1915 .minimum_version_id
= 1,
1916 .needed
= spapr_irq_map_needed
,
1917 .fields
= (VMStateField
[]) {
1918 VMSTATE_BITMAP(irq_map
, sPAPRMachineState
, 0, irq_map_nr
),
1919 VMSTATE_END_OF_LIST()
1923 static const VMStateDescription vmstate_spapr
= {
1926 .minimum_version_id
= 1,
1927 .pre_load
= spapr_pre_load
,
1928 .post_load
= spapr_post_load
,
1929 .pre_save
= spapr_pre_save
,
1930 .fields
= (VMStateField
[]) {
1931 /* used to be @next_irq */
1932 VMSTATE_UNUSED_BUFFER(version_before_3
, 0, 4),
1935 VMSTATE_UINT64_TEST(rtc_offset
, sPAPRMachineState
, version_before_3
),
1937 VMSTATE_PPC_TIMEBASE_V(tb
, sPAPRMachineState
, 2),
1938 VMSTATE_END_OF_LIST()
1940 .subsections
= (const VMStateDescription
*[]) {
1941 &vmstate_spapr_ov5_cas
,
1942 &vmstate_spapr_patb_entry
,
1943 &vmstate_spapr_pending_events
,
1944 &vmstate_spapr_cap_htm
,
1945 &vmstate_spapr_cap_vsx
,
1946 &vmstate_spapr_cap_dfp
,
1947 &vmstate_spapr_cap_cfpc
,
1948 &vmstate_spapr_cap_sbbc
,
1949 &vmstate_spapr_cap_ibs
,
1950 &vmstate_spapr_irq_map
,
1951 &vmstate_spapr_cap_nested_kvm_hv
,
1956 static int htab_save_setup(QEMUFile
*f
, void *opaque
)
1958 sPAPRMachineState
*spapr
= opaque
;
1960 /* "Iteration" header */
1961 if (!spapr
->htab_shift
) {
1962 qemu_put_be32(f
, -1);
1964 qemu_put_be32(f
, spapr
->htab_shift
);
1968 spapr
->htab_save_index
= 0;
1969 spapr
->htab_first_pass
= true;
1971 if (spapr
->htab_shift
) {
1972 assert(kvm_enabled());
1980 static void htab_save_chunk(QEMUFile
*f
, sPAPRMachineState
*spapr
,
1981 int chunkstart
, int n_valid
, int n_invalid
)
1983 qemu_put_be32(f
, chunkstart
);
1984 qemu_put_be16(f
, n_valid
);
1985 qemu_put_be16(f
, n_invalid
);
1986 qemu_put_buffer(f
, HPTE(spapr
->htab
, chunkstart
),
1987 HASH_PTE_SIZE_64
* n_valid
);
1990 static void htab_save_end_marker(QEMUFile
*f
)
1992 qemu_put_be32(f
, 0);
1993 qemu_put_be16(f
, 0);
1994 qemu_put_be16(f
, 0);
1997 static void htab_save_first_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
2000 bool has_timeout
= max_ns
!= -1;
2001 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2002 int index
= spapr
->htab_save_index
;
2003 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2005 assert(spapr
->htab_first_pass
);
2010 /* Consume invalid HPTEs */
2011 while ((index
< htabslots
)
2012 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2013 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2017 /* Consume valid HPTEs */
2019 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2020 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2021 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2025 if (index
> chunkstart
) {
2026 int n_valid
= index
- chunkstart
;
2028 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, 0);
2031 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2035 } while ((index
< htabslots
) && !qemu_file_rate_limit(f
));
2037 if (index
>= htabslots
) {
2038 assert(index
== htabslots
);
2040 spapr
->htab_first_pass
= false;
2042 spapr
->htab_save_index
= index
;
2045 static int htab_save_later_pass(QEMUFile
*f
, sPAPRMachineState
*spapr
,
2048 bool final
= max_ns
< 0;
2049 int htabslots
= HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
;
2050 int examined
= 0, sent
= 0;
2051 int index
= spapr
->htab_save_index
;
2052 int64_t starttime
= qemu_clock_get_ns(QEMU_CLOCK_REALTIME
);
2054 assert(!spapr
->htab_first_pass
);
2057 int chunkstart
, invalidstart
;
2059 /* Consume non-dirty HPTEs */
2060 while ((index
< htabslots
)
2061 && !HPTE_DIRTY(HPTE(spapr
->htab
, index
))) {
2067 /* Consume valid dirty HPTEs */
2068 while ((index
< htabslots
) && (index
- chunkstart
< USHRT_MAX
)
2069 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2070 && HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2071 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2076 invalidstart
= index
;
2077 /* Consume invalid dirty HPTEs */
2078 while ((index
< htabslots
) && (index
- invalidstart
< USHRT_MAX
)
2079 && HPTE_DIRTY(HPTE(spapr
->htab
, index
))
2080 && !HPTE_VALID(HPTE(spapr
->htab
, index
))) {
2081 CLEAN_HPTE(HPTE(spapr
->htab
, index
));
2086 if (index
> chunkstart
) {
2087 int n_valid
= invalidstart
- chunkstart
;
2088 int n_invalid
= index
- invalidstart
;
2090 htab_save_chunk(f
, spapr
, chunkstart
, n_valid
, n_invalid
);
2091 sent
+= index
- chunkstart
;
2093 if (!final
&& (qemu_clock_get_ns(QEMU_CLOCK_REALTIME
) - starttime
) > max_ns
) {
2098 if (examined
>= htabslots
) {
2102 if (index
>= htabslots
) {
2103 assert(index
== htabslots
);
2106 } while ((examined
< htabslots
) && (!qemu_file_rate_limit(f
) || final
));
2108 if (index
>= htabslots
) {
2109 assert(index
== htabslots
);
2113 spapr
->htab_save_index
= index
;
2115 return (examined
>= htabslots
) && (sent
== 0) ? 1 : 0;
2118 #define MAX_ITERATION_NS 5000000 /* 5 ms */
2119 #define MAX_KVM_BUF_SIZE 2048
2121 static int htab_save_iterate(QEMUFile
*f
, void *opaque
)
2123 sPAPRMachineState
*spapr
= opaque
;
2127 /* Iteration header */
2128 if (!spapr
->htab_shift
) {
2129 qemu_put_be32(f
, -1);
2132 qemu_put_be32(f
, 0);
2136 assert(kvm_enabled());
2138 fd
= get_htab_fd(spapr
);
2143 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, MAX_ITERATION_NS
);
2147 } else if (spapr
->htab_first_pass
) {
2148 htab_save_first_pass(f
, spapr
, MAX_ITERATION_NS
);
2150 rc
= htab_save_later_pass(f
, spapr
, MAX_ITERATION_NS
);
2153 htab_save_end_marker(f
);
2158 static int htab_save_complete(QEMUFile
*f
, void *opaque
)
2160 sPAPRMachineState
*spapr
= opaque
;
2163 /* Iteration header */
2164 if (!spapr
->htab_shift
) {
2165 qemu_put_be32(f
, -1);
2168 qemu_put_be32(f
, 0);
2174 assert(kvm_enabled());
2176 fd
= get_htab_fd(spapr
);
2181 rc
= kvmppc_save_htab(f
, fd
, MAX_KVM_BUF_SIZE
, -1);
2186 if (spapr
->htab_first_pass
) {
2187 htab_save_first_pass(f
, spapr
, -1);
2189 htab_save_later_pass(f
, spapr
, -1);
2193 htab_save_end_marker(f
);
2198 static int htab_load(QEMUFile
*f
, void *opaque
, int version_id
)
2200 sPAPRMachineState
*spapr
= opaque
;
2201 uint32_t section_hdr
;
2203 Error
*local_err
= NULL
;
2205 if (version_id
< 1 || version_id
> 1) {
2206 error_report("htab_load() bad version");
2210 section_hdr
= qemu_get_be32(f
);
2212 if (section_hdr
== -1) {
2213 spapr_free_hpt(spapr
);
2218 /* First section gives the htab size */
2219 spapr_reallocate_hpt(spapr
, section_hdr
, &local_err
);
2221 error_report_err(local_err
);
2228 assert(kvm_enabled());
2230 fd
= kvmppc_get_htab_fd(true, 0, &local_err
);
2232 error_report_err(local_err
);
2239 uint16_t n_valid
, n_invalid
;
2241 index
= qemu_get_be32(f
);
2242 n_valid
= qemu_get_be16(f
);
2243 n_invalid
= qemu_get_be16(f
);
2245 if ((index
== 0) && (n_valid
== 0) && (n_invalid
== 0)) {
2250 if ((index
+ n_valid
+ n_invalid
) >
2251 (HTAB_SIZE(spapr
) / HASH_PTE_SIZE_64
)) {
2252 /* Bad index in stream */
2254 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2255 index
, n_valid
, n_invalid
, spapr
->htab_shift
);
2261 qemu_get_buffer(f
, HPTE(spapr
->htab
, index
),
2262 HASH_PTE_SIZE_64
* n_valid
);
2265 memset(HPTE(spapr
->htab
, index
+ n_valid
), 0,
2266 HASH_PTE_SIZE_64
* n_invalid
);
2273 rc
= kvmppc_load_htab_chunk(f
, fd
, index
, n_valid
, n_invalid
);
2288 static void htab_save_cleanup(void *opaque
)
2290 sPAPRMachineState
*spapr
= opaque
;
2292 close_htab_fd(spapr
);
2295 static SaveVMHandlers savevm_htab_handlers
= {
2296 .save_setup
= htab_save_setup
,
2297 .save_live_iterate
= htab_save_iterate
,
2298 .save_live_complete_precopy
= htab_save_complete
,
2299 .save_cleanup
= htab_save_cleanup
,
2300 .load_state
= htab_load
,
2303 static void spapr_boot_set(void *opaque
, const char *boot_device
,
2306 MachineState
*machine
= MACHINE(opaque
);
2307 machine
->boot_order
= g_strdup(boot_device
);
2310 static void spapr_create_lmb_dr_connectors(sPAPRMachineState
*spapr
)
2312 MachineState
*machine
= MACHINE(spapr
);
2313 uint64_t lmb_size
= SPAPR_MEMORY_BLOCK_SIZE
;
2314 uint32_t nr_lmbs
= (machine
->maxram_size
- machine
->ram_size
)/lmb_size
;
2317 for (i
= 0; i
< nr_lmbs
; i
++) {
2320 addr
= i
* lmb_size
+ machine
->device_memory
->base
;
2321 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_LMB
,
2327 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2328 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2329 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2331 static void spapr_validate_node_memory(MachineState
*machine
, Error
**errp
)
2335 if (machine
->ram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2336 error_setg(errp
, "Memory size 0x" RAM_ADDR_FMT
2337 " is not aligned to %" PRIu64
" MiB",
2339 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2343 if (machine
->maxram_size
% SPAPR_MEMORY_BLOCK_SIZE
) {
2344 error_setg(errp
, "Maximum memory size 0x" RAM_ADDR_FMT
2345 " is not aligned to %" PRIu64
" MiB",
2347 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2351 for (i
= 0; i
< nb_numa_nodes
; i
++) {
2352 if (numa_info
[i
].node_mem
% SPAPR_MEMORY_BLOCK_SIZE
) {
2354 "Node %d memory size 0x%" PRIx64
2355 " is not aligned to %" PRIu64
" MiB",
2356 i
, numa_info
[i
].node_mem
,
2357 SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
2363 /* find cpu slot in machine->possible_cpus by core_id */
2364 static CPUArchId
*spapr_find_cpu_slot(MachineState
*ms
, uint32_t id
, int *idx
)
2366 int index
= id
/ smp_threads
;
2368 if (index
>= ms
->possible_cpus
->len
) {
2374 return &ms
->possible_cpus
->cpus
[index
];
2377 static void spapr_set_vsmt_mode(sPAPRMachineState
*spapr
, Error
**errp
)
2379 Error
*local_err
= NULL
;
2380 bool vsmt_user
= !!spapr
->vsmt
;
2381 int kvm_smt
= kvmppc_smt_threads();
2384 if (!kvm_enabled() && (smp_threads
> 1)) {
2385 error_setg(&local_err
, "TCG cannot support more than 1 thread/core "
2386 "on a pseries machine");
2389 if (!is_power_of_2(smp_threads
)) {
2390 error_setg(&local_err
, "Cannot support %d threads/core on a pseries "
2391 "machine because it must be a power of 2", smp_threads
);
2395 /* Detemine the VSMT mode to use: */
2397 if (spapr
->vsmt
< smp_threads
) {
2398 error_setg(&local_err
, "Cannot support VSMT mode %d"
2399 " because it must be >= threads/core (%d)",
2400 spapr
->vsmt
, smp_threads
);
2403 /* In this case, spapr->vsmt has been set by the command line */
2406 * Default VSMT value is tricky, because we need it to be as
2407 * consistent as possible (for migration), but this requires
2408 * changing it for at least some existing cases. We pick 8 as
2409 * the value that we'd get with KVM on POWER8, the
2410 * overwhelmingly common case in production systems.
2412 spapr
->vsmt
= MAX(8, smp_threads
);
2415 /* KVM: If necessary, set the SMT mode: */
2416 if (kvm_enabled() && (spapr
->vsmt
!= kvm_smt
)) {
2417 ret
= kvmppc_set_smt_threads(spapr
->vsmt
);
2419 /* Looks like KVM isn't able to change VSMT mode */
2420 error_setg(&local_err
,
2421 "Failed to set KVM's VSMT mode to %d (errno %d)",
2423 /* We can live with that if the default one is big enough
2424 * for the number of threads, and a submultiple of the one
2425 * we want. In this case we'll waste some vcpu ids, but
2426 * behaviour will be correct */
2427 if ((kvm_smt
>= smp_threads
) && ((spapr
->vsmt
% kvm_smt
) == 0)) {
2428 warn_report_err(local_err
);
2433 error_append_hint(&local_err
,
2434 "On PPC, a VM with %d threads/core"
2435 " on a host with %d threads/core"
2436 " requires the use of VSMT mode %d.\n",
2437 smp_threads
, kvm_smt
, spapr
->vsmt
);
2439 kvmppc_hint_smt_possible(&local_err
);
2444 /* else TCG: nothing to do currently */
2446 error_propagate(errp
, local_err
);
2449 static void spapr_init_cpus(sPAPRMachineState
*spapr
)
2451 MachineState
*machine
= MACHINE(spapr
);
2452 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2453 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2454 const char *type
= spapr_get_cpu_core_type(machine
->cpu_type
);
2455 const CPUArchIdList
*possible_cpus
;
2456 int boot_cores_nr
= smp_cpus
/ smp_threads
;
2459 possible_cpus
= mc
->possible_cpu_arch_ids(machine
);
2460 if (mc
->has_hotpluggable_cpus
) {
2461 if (smp_cpus
% smp_threads
) {
2462 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2463 smp_cpus
, smp_threads
);
2466 if (max_cpus
% smp_threads
) {
2467 error_report("max_cpus (%u) must be multiple of threads (%u)",
2468 max_cpus
, smp_threads
);
2472 if (max_cpus
!= smp_cpus
) {
2473 error_report("This machine version does not support CPU hotplug");
2476 boot_cores_nr
= possible_cpus
->len
;
2479 if (smc
->pre_2_10_has_unused_icps
) {
2482 for (i
= 0; i
< spapr_max_server_number(spapr
); i
++) {
2483 /* Dummy entries get deregistered when real ICPState objects
2484 * are registered during CPU core hotplug.
2486 pre_2_10_vmstate_register_dummy_icp(i
);
2490 for (i
= 0; i
< possible_cpus
->len
; i
++) {
2491 int core_id
= i
* smp_threads
;
2493 if (mc
->has_hotpluggable_cpus
) {
2494 spapr_dr_connector_new(OBJECT(spapr
), TYPE_SPAPR_DRC_CPU
,
2495 spapr_vcpu_id(spapr
, core_id
));
2498 if (i
< boot_cores_nr
) {
2499 Object
*core
= object_new(type
);
2500 int nr_threads
= smp_threads
;
2502 /* Handle the partially filled core for older machine types */
2503 if ((i
+ 1) * smp_threads
>= smp_cpus
) {
2504 nr_threads
= smp_cpus
- i
* smp_threads
;
2507 object_property_set_int(core
, nr_threads
, "nr-threads",
2509 object_property_set_int(core
, core_id
, CPU_CORE_PROP_CORE_ID
,
2511 object_property_set_bool(core
, true, "realized", &error_fatal
);
2518 /* pSeries LPAR / sPAPR hardware init */
2519 static void spapr_machine_init(MachineState
*machine
)
2521 sPAPRMachineState
*spapr
= SPAPR_MACHINE(machine
);
2522 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(machine
);
2523 const char *kernel_filename
= machine
->kernel_filename
;
2524 const char *initrd_filename
= machine
->initrd_filename
;
2527 MemoryRegion
*sysmem
= get_system_memory();
2528 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
2529 hwaddr node0_size
= spapr_node0_size(machine
);
2530 long load_limit
, fw_size
;
2532 Error
*resize_hpt_err
= NULL
;
2534 msi_nonbroken
= true;
2536 QLIST_INIT(&spapr
->phbs
);
2537 QTAILQ_INIT(&spapr
->pending_dimm_unplugs
);
2539 /* Determine capabilities to run with */
2540 spapr_caps_init(spapr
);
2542 kvmppc_check_papr_resize_hpt(&resize_hpt_err
);
2543 if (spapr
->resize_hpt
== SPAPR_RESIZE_HPT_DEFAULT
) {
2545 * If the user explicitly requested a mode we should either
2546 * supply it, or fail completely (which we do below). But if
2547 * it's not set explicitly, we reset our mode to something
2550 if (resize_hpt_err
) {
2551 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
2552 error_free(resize_hpt_err
);
2553 resize_hpt_err
= NULL
;
2555 spapr
->resize_hpt
= smc
->resize_hpt_default
;
2559 assert(spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DEFAULT
);
2561 if ((spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) && resize_hpt_err
) {
2563 * User requested HPT resize, but this host can't supply it. Bail out
2565 error_report_err(resize_hpt_err
);
2569 spapr
->rma_size
= node0_size
;
2571 /* With KVM, we don't actually know whether KVM supports an
2572 * unbounded RMA (PR KVM) or is limited by the hash table size
2573 * (HV KVM using VRMA), so we always assume the latter
2575 * In that case, we also limit the initial allocations for RTAS
2576 * etc... to 256M since we have no way to know what the VRMA size
2577 * is going to be as it depends on the size of the hash table
2578 * which isn't determined yet.
2580 if (kvm_enabled()) {
2581 spapr
->vrma_adjust
= 1;
2582 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x10000000);
2585 /* Actually we don't support unbounded RMA anymore since we added
2586 * proper emulation of HV mode. The max we can get is 16G which
2587 * also happens to be what we configure for PAPR mode so make sure
2588 * we don't do anything bigger than that
2590 spapr
->rma_size
= MIN(spapr
->rma_size
, 0x400000000ull
);
2592 if (spapr
->rma_size
> node0_size
) {
2593 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx
")",
2598 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2599 load_limit
= MIN(spapr
->rma_size
, RTAS_MAX_ADDR
) - FW_OVERHEAD
;
2602 * VSMT must be set in order to be able to compute VCPU ids, ie to
2603 * call spapr_max_server_number() or spapr_vcpu_id().
2605 spapr_set_vsmt_mode(spapr
, &error_fatal
);
2607 /* Set up Interrupt Controller before we create the VCPUs */
2608 spapr_irq_init(spapr
, &error_fatal
);
2610 /* Set up containers for ibm,client-architecture-support negotiated options
2612 spapr
->ov5
= spapr_ovec_new();
2613 spapr
->ov5_cas
= spapr_ovec_new();
2615 if (smc
->dr_lmb_enabled
) {
2616 spapr_ovec_set(spapr
->ov5
, OV5_DRCONF_MEMORY
);
2617 spapr_validate_node_memory(machine
, &error_fatal
);
2620 spapr_ovec_set(spapr
->ov5
, OV5_FORM1_AFFINITY
);
2622 /* advertise support for dedicated HP event source to guests */
2623 if (spapr
->use_hotplug_event_source
) {
2624 spapr_ovec_set(spapr
->ov5
, OV5_HP_EVT
);
2627 /* advertise support for HPT resizing */
2628 if (spapr
->resize_hpt
!= SPAPR_RESIZE_HPT_DISABLED
) {
2629 spapr_ovec_set(spapr
->ov5
, OV5_HPT_RESIZE
);
2632 /* advertise support for ibm,dyamic-memory-v2 */
2633 spapr_ovec_set(spapr
->ov5
, OV5_DRMEM_V2
);
2635 /* advertise XIVE on POWER9 machines */
2636 if (spapr
->irq
->ov5
& SPAPR_OV5_XIVE_EXPLOIT
) {
2637 if (ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
,
2638 0, spapr
->max_compat_pvr
)) {
2639 spapr_ovec_set(spapr
->ov5
, OV5_XIVE_EXPLOIT
);
2641 error_report("XIVE-only machines require a POWER9 CPU");
2647 spapr_init_cpus(spapr
);
2649 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) &&
2650 ppc_type_check_compat(machine
->cpu_type
, CPU_POWERPC_LOGICAL_3_00
, 0,
2651 spapr
->max_compat_pvr
)) {
2652 /* KVM and TCG always allow GTSE with radix... */
2653 spapr_ovec_set(spapr
->ov5
, OV5_MMU_RADIX_GTSE
);
2655 /* ... but not with hash (currently). */
2657 if (kvm_enabled()) {
2658 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2659 kvmppc_enable_logical_ci_hcalls();
2660 kvmppc_enable_set_mode_hcall();
2662 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2663 kvmppc_enable_clear_ref_mod_hcalls();
2667 memory_region_allocate_system_memory(ram
, NULL
, "ppc_spapr.ram",
2669 memory_region_add_subregion(sysmem
, 0, ram
);
2671 /* always allocate the device memory information */
2672 machine
->device_memory
= g_malloc0(sizeof(*machine
->device_memory
));
2674 /* initialize hotplug memory address space */
2675 if (machine
->ram_size
< machine
->maxram_size
) {
2676 ram_addr_t device_mem_size
= machine
->maxram_size
- machine
->ram_size
;
2678 * Limit the number of hotpluggable memory slots to half the number
2679 * slots that KVM supports, leaving the other half for PCI and other
2680 * devices. However ensure that number of slots doesn't drop below 32.
2682 int max_memslots
= kvm_enabled() ? kvm_get_max_memslots() / 2 :
2683 SPAPR_MAX_RAM_SLOTS
;
2685 if (max_memslots
< SPAPR_MAX_RAM_SLOTS
) {
2686 max_memslots
= SPAPR_MAX_RAM_SLOTS
;
2688 if (machine
->ram_slots
> max_memslots
) {
2689 error_report("Specified number of memory slots %"
2690 PRIu64
" exceeds max supported %d",
2691 machine
->ram_slots
, max_memslots
);
2695 machine
->device_memory
->base
= ROUND_UP(machine
->ram_size
,
2696 SPAPR_DEVICE_MEM_ALIGN
);
2697 memory_region_init(&machine
->device_memory
->mr
, OBJECT(spapr
),
2698 "device-memory", device_mem_size
);
2699 memory_region_add_subregion(sysmem
, machine
->device_memory
->base
,
2700 &machine
->device_memory
->mr
);
2703 if (smc
->dr_lmb_enabled
) {
2704 spapr_create_lmb_dr_connectors(spapr
);
2707 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, "spapr-rtas.bin");
2709 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2712 spapr
->rtas_size
= get_image_size(filename
);
2713 if (spapr
->rtas_size
< 0) {
2714 error_report("Could not get size of LPAR rtas '%s'", filename
);
2717 spapr
->rtas_blob
= g_malloc(spapr
->rtas_size
);
2718 if (load_image_size(filename
, spapr
->rtas_blob
, spapr
->rtas_size
) < 0) {
2719 error_report("Could not load LPAR rtas '%s'", filename
);
2722 if (spapr
->rtas_size
> RTAS_MAX_SIZE
) {
2723 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2724 (size_t)spapr
->rtas_size
, RTAS_MAX_SIZE
);
2729 /* Set up RTAS event infrastructure */
2730 spapr_events_init(spapr
);
2732 /* Set up the RTC RTAS interfaces */
2733 spapr_rtc_create(spapr
);
2735 /* Set up VIO bus */
2736 spapr
->vio_bus
= spapr_vio_bus_init();
2738 for (i
= 0; i
< serial_max_hds(); i
++) {
2740 spapr_vty_create(spapr
->vio_bus
, serial_hd(i
));
2744 /* We always have at least the nvram device on VIO */
2745 spapr_create_nvram(spapr
);
2748 spapr_pci_rtas_init();
2750 phb
= spapr_create_phb(spapr
, 0);
2752 for (i
= 0; i
< nb_nics
; i
++) {
2753 NICInfo
*nd
= &nd_table
[i
];
2756 nd
->model
= g_strdup("spapr-vlan");
2759 if (g_str_equal(nd
->model
, "spapr-vlan") ||
2760 g_str_equal(nd
->model
, "ibmveth")) {
2761 spapr_vlan_create(spapr
->vio_bus
, nd
);
2763 pci_nic_init_nofail(&nd_table
[i
], phb
->bus
, nd
->model
, NULL
);
2767 for (i
= 0; i
<= drive_get_max_bus(IF_SCSI
); i
++) {
2768 spapr_vscsi_create(spapr
->vio_bus
);
2772 if (spapr_vga_init(phb
->bus
, &error_fatal
)) {
2773 spapr
->has_graphics
= true;
2774 machine
->usb
|= defaults_enabled() && !machine
->usb_disabled
;
2778 if (smc
->use_ohci_by_default
) {
2779 pci_create_simple(phb
->bus
, -1, "pci-ohci");
2781 pci_create_simple(phb
->bus
, -1, "nec-usb-xhci");
2784 if (spapr
->has_graphics
) {
2785 USBBus
*usb_bus
= usb_bus_find(-1);
2787 usb_create_simple(usb_bus
, "usb-kbd");
2788 usb_create_simple(usb_bus
, "usb-mouse");
2792 if (spapr
->rma_size
< (MIN_RMA_SLOF
* MiB
)) {
2794 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2799 if (kernel_filename
) {
2800 uint64_t lowaddr
= 0;
2802 spapr
->kernel_size
= load_elf(kernel_filename
, translate_kernel_address
,
2803 NULL
, NULL
, &lowaddr
, NULL
, 1,
2804 PPC_ELF_MACHINE
, 0, 0);
2805 if (spapr
->kernel_size
== ELF_LOAD_WRONG_ENDIAN
) {
2806 spapr
->kernel_size
= load_elf(kernel_filename
,
2807 translate_kernel_address
, NULL
, NULL
,
2808 &lowaddr
, NULL
, 0, PPC_ELF_MACHINE
,
2810 spapr
->kernel_le
= spapr
->kernel_size
> 0;
2812 if (spapr
->kernel_size
< 0) {
2813 error_report("error loading %s: %s", kernel_filename
,
2814 load_elf_strerror(spapr
->kernel_size
));
2819 if (initrd_filename
) {
2820 /* Try to locate the initrd in the gap between the kernel
2821 * and the firmware. Add a bit of space just in case
2823 spapr
->initrd_base
= (KERNEL_LOAD_ADDR
+ spapr
->kernel_size
2824 + 0x1ffff) & ~0xffff;
2825 spapr
->initrd_size
= load_image_targphys(initrd_filename
,
2828 - spapr
->initrd_base
);
2829 if (spapr
->initrd_size
< 0) {
2830 error_report("could not load initial ram disk '%s'",
2837 if (bios_name
== NULL
) {
2838 bios_name
= FW_FILE_NAME
;
2840 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
2842 error_report("Could not find LPAR firmware '%s'", bios_name
);
2845 fw_size
= load_image_targphys(filename
, 0, FW_MAX_SIZE
);
2847 error_report("Could not load LPAR firmware '%s'", filename
);
2852 /* FIXME: Should register things through the MachineState's qdev
2853 * interface, this is a legacy from the sPAPREnvironment structure
2854 * which predated MachineState but had a similar function */
2855 vmstate_register(NULL
, 0, &vmstate_spapr
, spapr
);
2856 register_savevm_live(NULL
, "spapr/htab", -1, 1,
2857 &savevm_htab_handlers
, spapr
);
2859 qemu_register_boot_set(spapr_boot_set
, spapr
);
2861 if (kvm_enabled()) {
2862 /* to stop and start vmclock */
2863 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change
,
2866 kvmppc_spapr_enable_inkernel_multitce();
2870 static int spapr_kvm_type(const char *vm_type
)
2876 if (!strcmp(vm_type
, "HV")) {
2880 if (!strcmp(vm_type
, "PR")) {
2884 error_report("Unknown kvm-type specified '%s'", vm_type
);
2889 * Implementation of an interface to adjust firmware path
2890 * for the bootindex property handling.
2892 static char *spapr_get_fw_dev_path(FWPathProvider
*p
, BusState
*bus
,
2895 #define CAST(type, obj, name) \
2896 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2897 SCSIDevice
*d
= CAST(SCSIDevice
, dev
, TYPE_SCSI_DEVICE
);
2898 sPAPRPHBState
*phb
= CAST(sPAPRPHBState
, dev
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
2899 VHostSCSICommon
*vsc
= CAST(VHostSCSICommon
, dev
, TYPE_VHOST_SCSI_COMMON
);
2902 void *spapr
= CAST(void, bus
->parent
, "spapr-vscsi");
2903 VirtIOSCSI
*virtio
= CAST(VirtIOSCSI
, bus
->parent
, TYPE_VIRTIO_SCSI
);
2904 USBDevice
*usb
= CAST(USBDevice
, bus
->parent
, TYPE_USB_DEVICE
);
2908 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2909 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2910 * in the top 16 bits of the 64-bit LUN
2912 unsigned id
= 0x8000 | (d
->id
<< 8) | d
->lun
;
2913 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2914 (uint64_t)id
<< 48);
2915 } else if (virtio
) {
2917 * We use SRP luns of the form 01000000 | (target << 8) | lun
2918 * in the top 32 bits of the 64-bit LUN
2919 * Note: the quote above is from SLOF and it is wrong,
2920 * the actual binding is:
2921 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2923 unsigned id
= 0x1000000 | (d
->id
<< 16) | d
->lun
;
2924 if (d
->lun
>= 256) {
2925 /* Use the LUN "flat space addressing method" */
2928 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2929 (uint64_t)id
<< 32);
2932 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2933 * in the top 32 bits of the 64-bit LUN
2935 unsigned usb_port
= atoi(usb
->port
->path
);
2936 unsigned id
= 0x1000000 | (usb_port
<< 16) | d
->lun
;
2937 return g_strdup_printf("%s@%"PRIX64
, qdev_fw_name(dev
),
2938 (uint64_t)id
<< 32);
2943 * SLOF probes the USB devices, and if it recognizes that the device is a
2944 * storage device, it changes its name to "storage" instead of "usb-host",
2945 * and additionally adds a child node for the SCSI LUN, so the correct
2946 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2948 if (strcmp("usb-host", qdev_fw_name(dev
)) == 0) {
2949 USBDevice
*usbdev
= CAST(USBDevice
, dev
, TYPE_USB_DEVICE
);
2950 if (usb_host_dev_is_scsi_storage(usbdev
)) {
2951 return g_strdup_printf("storage@%s/disk", usbdev
->port
->path
);
2956 /* Replace "pci" with "pci@800000020000000" */
2957 return g_strdup_printf("pci@%"PRIX64
, phb
->buid
);
2961 /* Same logic as virtio above */
2962 unsigned id
= 0x1000000 | (vsc
->target
<< 16) | vsc
->lun
;
2963 return g_strdup_printf("disk@%"PRIX64
, (uint64_t)id
<< 32);
2966 if (g_str_equal("pci-bridge", qdev_fw_name(dev
))) {
2967 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2968 PCIDevice
*pcidev
= CAST(PCIDevice
, dev
, TYPE_PCI_DEVICE
);
2969 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev
->devfn
));
2975 static char *spapr_get_kvm_type(Object
*obj
, Error
**errp
)
2977 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2979 return g_strdup(spapr
->kvm_type
);
2982 static void spapr_set_kvm_type(Object
*obj
, const char *value
, Error
**errp
)
2984 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2986 g_free(spapr
->kvm_type
);
2987 spapr
->kvm_type
= g_strdup(value
);
2990 static bool spapr_get_modern_hotplug_events(Object
*obj
, Error
**errp
)
2992 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
2994 return spapr
->use_hotplug_event_source
;
2997 static void spapr_set_modern_hotplug_events(Object
*obj
, bool value
,
3000 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3002 spapr
->use_hotplug_event_source
= value
;
3005 static bool spapr_get_msix_emulation(Object
*obj
, Error
**errp
)
3010 static char *spapr_get_resize_hpt(Object
*obj
, Error
**errp
)
3012 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3014 switch (spapr
->resize_hpt
) {
3015 case SPAPR_RESIZE_HPT_DEFAULT
:
3016 return g_strdup("default");
3017 case SPAPR_RESIZE_HPT_DISABLED
:
3018 return g_strdup("disabled");
3019 case SPAPR_RESIZE_HPT_ENABLED
:
3020 return g_strdup("enabled");
3021 case SPAPR_RESIZE_HPT_REQUIRED
:
3022 return g_strdup("required");
3024 g_assert_not_reached();
3027 static void spapr_set_resize_hpt(Object
*obj
, const char *value
, Error
**errp
)
3029 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3031 if (strcmp(value
, "default") == 0) {
3032 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DEFAULT
;
3033 } else if (strcmp(value
, "disabled") == 0) {
3034 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_DISABLED
;
3035 } else if (strcmp(value
, "enabled") == 0) {
3036 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_ENABLED
;
3037 } else if (strcmp(value
, "required") == 0) {
3038 spapr
->resize_hpt
= SPAPR_RESIZE_HPT_REQUIRED
;
3040 error_setg(errp
, "Bad value for \"resize-hpt\" property");
3044 static void spapr_get_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3045 void *opaque
, Error
**errp
)
3047 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3050 static void spapr_set_vsmt(Object
*obj
, Visitor
*v
, const char *name
,
3051 void *opaque
, Error
**errp
)
3053 visit_type_uint32(v
, name
, (uint32_t *)opaque
, errp
);
3056 static char *spapr_get_ic_mode(Object
*obj
, Error
**errp
)
3058 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3060 if (spapr
->irq
== &spapr_irq_xics_legacy
) {
3061 return g_strdup("legacy");
3062 } else if (spapr
->irq
== &spapr_irq_xics
) {
3063 return g_strdup("xics");
3064 } else if (spapr
->irq
== &spapr_irq_xive
) {
3065 return g_strdup("xive");
3067 g_assert_not_reached();
3070 static void spapr_set_ic_mode(Object
*obj
, const char *value
, Error
**errp
)
3072 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3074 /* The legacy IRQ backend can not be set */
3075 if (strcmp(value
, "xics") == 0) {
3076 spapr
->irq
= &spapr_irq_xics
;
3077 } else if (strcmp(value
, "xive") == 0) {
3078 spapr
->irq
= &spapr_irq_xive
;
3080 error_setg(errp
, "Bad value for \"ic-mode\" property");
3084 static void spapr_instance_init(Object
*obj
)
3086 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3087 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(spapr
);
3089 spapr
->htab_fd
= -1;
3090 spapr
->use_hotplug_event_source
= true;
3091 object_property_add_str(obj
, "kvm-type",
3092 spapr_get_kvm_type
, spapr_set_kvm_type
, NULL
);
3093 object_property_set_description(obj
, "kvm-type",
3094 "Specifies the KVM virtualization mode (HV, PR)",
3096 object_property_add_bool(obj
, "modern-hotplug-events",
3097 spapr_get_modern_hotplug_events
,
3098 spapr_set_modern_hotplug_events
,
3100 object_property_set_description(obj
, "modern-hotplug-events",
3101 "Use dedicated hotplug event mechanism in"
3102 " place of standard EPOW events when possible"
3103 " (required for memory hot-unplug support)",
3105 ppc_compat_add_property(obj
, "max-cpu-compat", &spapr
->max_compat_pvr
,
3106 "Maximum permitted CPU compatibility mode",
3109 object_property_add_str(obj
, "resize-hpt",
3110 spapr_get_resize_hpt
, spapr_set_resize_hpt
, NULL
);
3111 object_property_set_description(obj
, "resize-hpt",
3112 "Resizing of the Hash Page Table (enabled, disabled, required)",
3114 object_property_add(obj
, "vsmt", "uint32", spapr_get_vsmt
,
3115 spapr_set_vsmt
, NULL
, &spapr
->vsmt
, &error_abort
);
3116 object_property_set_description(obj
, "vsmt",
3117 "Virtual SMT: KVM behaves as if this were"
3118 " the host's SMT mode", &error_abort
);
3119 object_property_add_bool(obj
, "vfio-no-msix-emulation",
3120 spapr_get_msix_emulation
, NULL
, NULL
);
3122 /* The machine class defines the default interrupt controller mode */
3123 spapr
->irq
= smc
->irq
;
3124 object_property_add_str(obj
, "ic-mode", spapr_get_ic_mode
,
3125 spapr_set_ic_mode
, NULL
);
3126 object_property_set_description(obj
, "ic-mode",
3127 "Specifies the interrupt controller mode (xics, xive)",
3131 static void spapr_machine_finalizefn(Object
*obj
)
3133 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3135 g_free(spapr
->kvm_type
);
3138 void spapr_do_system_reset_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
3140 cpu_synchronize_state(cs
);
3141 ppc_cpu_do_system_reset(cs
);
3144 static void spapr_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
3149 async_run_on_cpu(cs
, spapr_do_system_reset_on_cpu
, RUN_ON_CPU_NULL
);
3153 static void spapr_add_lmbs(DeviceState
*dev
, uint64_t addr_start
, uint64_t size
,
3154 uint32_t node
, bool dedicated_hp_event_source
,
3157 sPAPRDRConnector
*drc
;
3158 uint32_t nr_lmbs
= size
/SPAPR_MEMORY_BLOCK_SIZE
;
3159 int i
, fdt_offset
, fdt_size
;
3161 uint64_t addr
= addr_start
;
3162 bool hotplugged
= spapr_drc_hotplugged(dev
);
3163 Error
*local_err
= NULL
;
3165 for (i
= 0; i
< nr_lmbs
; i
++) {
3166 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3167 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3170 fdt
= create_device_tree(&fdt_size
);
3171 fdt_offset
= spapr_populate_memory_node(fdt
, node
, addr
,
3172 SPAPR_MEMORY_BLOCK_SIZE
);
3174 spapr_drc_attach(drc
, dev
, fdt
, fdt_offset
, &local_err
);
3176 while (addr
> addr_start
) {
3177 addr
-= SPAPR_MEMORY_BLOCK_SIZE
;
3178 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3179 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3180 spapr_drc_detach(drc
);
3183 error_propagate(errp
, local_err
);
3187 spapr_drc_reset(drc
);
3189 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3191 /* send hotplug notification to the
3192 * guest only in case of hotplugged memory
3195 if (dedicated_hp_event_source
) {
3196 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3197 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3198 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3200 spapr_drc_index(drc
));
3202 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3208 static void spapr_memory_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3211 Error
*local_err
= NULL
;
3212 sPAPRMachineState
*ms
= SPAPR_MACHINE(hotplug_dev
);
3213 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3214 uint64_t size
, addr
;
3217 size
= memory_device_get_region_size(MEMORY_DEVICE(dev
), &error_abort
);
3219 pc_dimm_plug(dimm
, MACHINE(ms
), &local_err
);
3224 addr
= object_property_get_uint(OBJECT(dimm
),
3225 PC_DIMM_ADDR_PROP
, &local_err
);
3230 node
= object_property_get_uint(OBJECT(dev
), PC_DIMM_NODE_PROP
,
3232 spapr_add_lmbs(dev
, addr
, size
, node
,
3233 spapr_ovec_test(ms
->ov5_cas
, OV5_HP_EVT
),
3242 pc_dimm_unplug(dimm
, MACHINE(ms
));
3244 error_propagate(errp
, local_err
);
3247 static void spapr_memory_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3250 const sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(hotplug_dev
);
3251 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3252 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3253 Error
*local_err
= NULL
;
3258 if (!smc
->dr_lmb_enabled
) {
3259 error_setg(errp
, "Memory hotplug not supported for this machine");
3263 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &local_err
);
3265 error_propagate(errp
, local_err
);
3269 if (size
% SPAPR_MEMORY_BLOCK_SIZE
) {
3270 error_setg(errp
, "Hotplugged memory size must be a multiple of "
3271 "%" PRIu64
" MB", SPAPR_MEMORY_BLOCK_SIZE
/ MiB
);
3275 memdev
= object_property_get_link(OBJECT(dimm
), PC_DIMM_MEMDEV_PROP
,
3277 pagesize
= host_memory_backend_pagesize(MEMORY_BACKEND(memdev
));
3278 spapr_check_pagesize(spapr
, pagesize
, &local_err
);
3280 error_propagate(errp
, local_err
);
3284 pc_dimm_pre_plug(dimm
, MACHINE(hotplug_dev
), NULL
, errp
);
3287 struct sPAPRDIMMState
{
3290 QTAILQ_ENTRY(sPAPRDIMMState
) next
;
3293 static sPAPRDIMMState
*spapr_pending_dimm_unplugs_find(sPAPRMachineState
*s
,
3296 sPAPRDIMMState
*dimm_state
= NULL
;
3298 QTAILQ_FOREACH(dimm_state
, &s
->pending_dimm_unplugs
, next
) {
3299 if (dimm_state
->dimm
== dimm
) {
3306 static sPAPRDIMMState
*spapr_pending_dimm_unplugs_add(sPAPRMachineState
*spapr
,
3310 sPAPRDIMMState
*ds
= NULL
;
3313 * If this request is for a DIMM whose removal had failed earlier
3314 * (due to guest's refusal to remove the LMBs), we would have this
3315 * dimm already in the pending_dimm_unplugs list. In that
3316 * case don't add again.
3318 ds
= spapr_pending_dimm_unplugs_find(spapr
, dimm
);
3320 ds
= g_malloc0(sizeof(sPAPRDIMMState
));
3321 ds
->nr_lmbs
= nr_lmbs
;
3323 QTAILQ_INSERT_HEAD(&spapr
->pending_dimm_unplugs
, ds
, next
);
3328 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState
*spapr
,
3329 sPAPRDIMMState
*dimm_state
)
3331 QTAILQ_REMOVE(&spapr
->pending_dimm_unplugs
, dimm_state
, next
);
3335 static sPAPRDIMMState
*spapr_recover_pending_dimm_state(sPAPRMachineState
*ms
,
3338 sPAPRDRConnector
*drc
;
3339 uint64_t size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
),
3341 uint32_t nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3342 uint32_t avail_lmbs
= 0;
3343 uint64_t addr_start
, addr
;
3346 addr_start
= object_property_get_int(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3350 for (i
= 0; i
< nr_lmbs
; i
++) {
3351 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3352 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3357 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3360 return spapr_pending_dimm_unplugs_add(ms
, avail_lmbs
, dimm
);
3363 /* Callback to be called during DRC release. */
3364 void spapr_lmb_release(DeviceState
*dev
)
3366 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3367 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_ctrl
);
3368 sPAPRDIMMState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3370 /* This information will get lost if a migration occurs
3371 * during the unplug process. In this case recover it. */
3373 ds
= spapr_recover_pending_dimm_state(spapr
, PC_DIMM(dev
));
3375 /* The DRC being examined by the caller at least must be counted */
3376 g_assert(ds
->nr_lmbs
);
3379 if (--ds
->nr_lmbs
) {
3384 * Now that all the LMBs have been removed by the guest, call the
3385 * unplug handler chain. This can never fail.
3387 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3390 static void spapr_memory_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3392 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3393 sPAPRDIMMState
*ds
= spapr_pending_dimm_unplugs_find(spapr
, PC_DIMM(dev
));
3395 pc_dimm_unplug(PC_DIMM(dev
), MACHINE(hotplug_dev
));
3396 object_unparent(OBJECT(dev
));
3397 spapr_pending_dimm_unplugs_remove(spapr
, ds
);
3400 static void spapr_memory_unplug_request(HotplugHandler
*hotplug_dev
,
3401 DeviceState
*dev
, Error
**errp
)
3403 sPAPRMachineState
*spapr
= SPAPR_MACHINE(hotplug_dev
);
3404 Error
*local_err
= NULL
;
3405 PCDIMMDevice
*dimm
= PC_DIMM(dev
);
3407 uint64_t size
, addr_start
, addr
;
3409 sPAPRDRConnector
*drc
;
3411 size
= memory_device_get_region_size(MEMORY_DEVICE(dimm
), &error_abort
);
3412 nr_lmbs
= size
/ SPAPR_MEMORY_BLOCK_SIZE
;
3414 addr_start
= object_property_get_uint(OBJECT(dimm
), PC_DIMM_ADDR_PROP
,
3421 * An existing pending dimm state for this DIMM means that there is an
3422 * unplug operation in progress, waiting for the spapr_lmb_release
3423 * callback to complete the job (BQL can't cover that far). In this case,
3424 * bail out to avoid detaching DRCs that were already released.
3426 if (spapr_pending_dimm_unplugs_find(spapr
, dimm
)) {
3427 error_setg(&local_err
,
3428 "Memory unplug already in progress for device %s",
3433 spapr_pending_dimm_unplugs_add(spapr
, nr_lmbs
, dimm
);
3436 for (i
= 0; i
< nr_lmbs
; i
++) {
3437 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3438 addr
/ SPAPR_MEMORY_BLOCK_SIZE
);
3441 spapr_drc_detach(drc
);
3442 addr
+= SPAPR_MEMORY_BLOCK_SIZE
;
3445 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_LMB
,
3446 addr_start
/ SPAPR_MEMORY_BLOCK_SIZE
);
3447 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB
,
3448 nr_lmbs
, spapr_drc_index(drc
));
3450 error_propagate(errp
, local_err
);
3453 static void *spapr_populate_hotplug_cpu_dt(CPUState
*cs
, int *fdt_offset
,
3454 sPAPRMachineState
*spapr
)
3456 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3457 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
3458 int id
= spapr_get_vcpu_id(cpu
);
3460 int offset
, fdt_size
;
3463 fdt
= create_device_tree(&fdt_size
);
3464 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, id
);
3465 offset
= fdt_add_subnode(fdt
, 0, nodename
);
3467 spapr_populate_cpu_dt(cs
, fdt
, offset
, spapr
);
3470 *fdt_offset
= offset
;
3474 /* Callback to be called during DRC release. */
3475 void spapr_core_release(DeviceState
*dev
)
3477 HotplugHandler
*hotplug_ctrl
= qdev_get_hotplug_handler(dev
);
3479 /* Call the unplug handler chain. This can never fail. */
3480 hotplug_handler_unplug(hotplug_ctrl
, dev
, &error_abort
);
3483 static void spapr_core_unplug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
)
3485 MachineState
*ms
= MACHINE(hotplug_dev
);
3486 sPAPRMachineClass
*smc
= SPAPR_MACHINE_GET_CLASS(ms
);
3487 CPUCore
*cc
= CPU_CORE(dev
);
3488 CPUArchId
*core_slot
= spapr_find_cpu_slot(ms
, cc
->core_id
, NULL
);
3490 if (smc
->pre_2_10_has_unused_icps
) {
3491 sPAPRCPUCore
*sc
= SPAPR_CPU_CORE(OBJECT(dev
));
3494 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3495 CPUState
*cs
= CPU(sc
->threads
[i
]);
3497 pre_2_10_vmstate_register_dummy_icp(cs
->cpu_index
);
3502 core_slot
->cpu
= NULL
;
3503 object_unparent(OBJECT(dev
));
3507 void spapr_core_unplug_request(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3510 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3512 sPAPRDRConnector
*drc
;
3513 CPUCore
*cc
= CPU_CORE(dev
);
3515 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
)) {
3516 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3521 error_setg(errp
, "Boot CPU core may not be unplugged");
3525 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3526 spapr_vcpu_id(spapr
, cc
->core_id
));
3529 spapr_drc_detach(drc
);
3531 spapr_hotplug_req_remove_by_index(drc
);
3534 static void spapr_core_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3537 sPAPRMachineState
*spapr
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3538 MachineClass
*mc
= MACHINE_GET_CLASS(spapr
);
3539 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
3540 sPAPRCPUCore
*core
= SPAPR_CPU_CORE(OBJECT(dev
));
3541 CPUCore
*cc
= CPU_CORE(dev
);
3542 CPUState
*cs
= CPU(core
->threads
[0]);
3543 sPAPRDRConnector
*drc
;
3544 Error
*local_err
= NULL
;
3545 CPUArchId
*core_slot
;
3547 bool hotplugged
= spapr_drc_hotplugged(dev
);
3549 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3551 error_setg(errp
, "Unable to find CPU core with core-id: %d",
3555 drc
= spapr_drc_by_id(TYPE_SPAPR_DRC_CPU
,
3556 spapr_vcpu_id(spapr
, cc
->core_id
));
3558 g_assert(drc
|| !mc
->has_hotpluggable_cpus
);
3564 fdt
= spapr_populate_hotplug_cpu_dt(cs
, &fdt_offset
, spapr
);
3566 spapr_drc_attach(drc
, dev
, fdt
, fdt_offset
, &local_err
);
3569 error_propagate(errp
, local_err
);
3575 * Send hotplug notification interrupt to the guest only
3576 * in case of hotplugged CPUs.
3578 spapr_hotplug_req_add_by_index(drc
);
3580 spapr_drc_reset(drc
);
3584 core_slot
->cpu
= OBJECT(dev
);
3586 if (smc
->pre_2_10_has_unused_icps
) {
3589 for (i
= 0; i
< cc
->nr_threads
; i
++) {
3590 cs
= CPU(core
->threads
[i
]);
3591 pre_2_10_vmstate_unregister_dummy_icp(cs
->cpu_index
);
3596 static void spapr_core_pre_plug(HotplugHandler
*hotplug_dev
, DeviceState
*dev
,
3599 MachineState
*machine
= MACHINE(OBJECT(hotplug_dev
));
3600 MachineClass
*mc
= MACHINE_GET_CLASS(hotplug_dev
);
3601 Error
*local_err
= NULL
;
3602 CPUCore
*cc
= CPU_CORE(dev
);
3603 const char *base_core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3604 const char *type
= object_get_typename(OBJECT(dev
));
3605 CPUArchId
*core_slot
;
3608 if (dev
->hotplugged
&& !mc
->has_hotpluggable_cpus
) {
3609 error_setg(&local_err
, "CPU hotplug not supported for this machine");
3613 if (strcmp(base_core_type
, type
)) {
3614 error_setg(&local_err
, "CPU core type should be %s", base_core_type
);
3618 if (cc
->core_id
% smp_threads
) {
3619 error_setg(&local_err
, "invalid core id %d", cc
->core_id
);
3624 * In general we should have homogeneous threads-per-core, but old
3625 * (pre hotplug support) machine types allow the last core to have
3626 * reduced threads as a compatibility hack for when we allowed
3627 * total vcpus not a multiple of threads-per-core.
3629 if (mc
->has_hotpluggable_cpus
&& (cc
->nr_threads
!= smp_threads
)) {
3630 error_setg(&local_err
, "invalid nr-threads %d, must be %d",
3631 cc
->nr_threads
, smp_threads
);
3635 core_slot
= spapr_find_cpu_slot(MACHINE(hotplug_dev
), cc
->core_id
, &index
);
3637 error_setg(&local_err
, "core id %d out of range", cc
->core_id
);
3641 if (core_slot
->cpu
) {
3642 error_setg(&local_err
, "core %d already populated", cc
->core_id
);
3646 numa_cpu_pre_plug(core_slot
, dev
, &local_err
);
3649 error_propagate(errp
, local_err
);
3652 static void spapr_machine_device_plug(HotplugHandler
*hotplug_dev
,
3653 DeviceState
*dev
, Error
**errp
)
3655 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3656 spapr_memory_plug(hotplug_dev
, dev
, errp
);
3657 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3658 spapr_core_plug(hotplug_dev
, dev
, errp
);
3662 static void spapr_machine_device_unplug(HotplugHandler
*hotplug_dev
,
3663 DeviceState
*dev
, Error
**errp
)
3665 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3666 spapr_memory_unplug(hotplug_dev
, dev
);
3667 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3668 spapr_core_unplug(hotplug_dev
, dev
);
3672 static void spapr_machine_device_unplug_request(HotplugHandler
*hotplug_dev
,
3673 DeviceState
*dev
, Error
**errp
)
3675 sPAPRMachineState
*sms
= SPAPR_MACHINE(OBJECT(hotplug_dev
));
3676 MachineClass
*mc
= MACHINE_GET_CLASS(sms
);
3678 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3679 if (spapr_ovec_test(sms
->ov5_cas
, OV5_HP_EVT
)) {
3680 spapr_memory_unplug_request(hotplug_dev
, dev
, errp
);
3682 /* NOTE: this means there is a window after guest reset, prior to
3683 * CAS negotiation, where unplug requests will fail due to the
3684 * capability not being detected yet. This is a bit different than
3685 * the case with PCI unplug, where the events will be queued and
3686 * eventually handled by the guest after boot
3688 error_setg(errp
, "Memory hot unplug not supported for this guest");
3690 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3691 if (!mc
->has_hotpluggable_cpus
) {
3692 error_setg(errp
, "CPU hot unplug not supported on this machine");
3695 spapr_core_unplug_request(hotplug_dev
, dev
, errp
);
3699 static void spapr_machine_device_pre_plug(HotplugHandler
*hotplug_dev
,
3700 DeviceState
*dev
, Error
**errp
)
3702 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
)) {
3703 spapr_memory_pre_plug(hotplug_dev
, dev
, errp
);
3704 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3705 spapr_core_pre_plug(hotplug_dev
, dev
, errp
);
3709 static HotplugHandler
*spapr_get_hotplug_handler(MachineState
*machine
,
3712 if (object_dynamic_cast(OBJECT(dev
), TYPE_PC_DIMM
) ||
3713 object_dynamic_cast(OBJECT(dev
), TYPE_SPAPR_CPU_CORE
)) {
3714 return HOTPLUG_HANDLER(machine
);
3719 static CpuInstanceProperties
3720 spapr_cpu_index_to_props(MachineState
*machine
, unsigned cpu_index
)
3722 CPUArchId
*core_slot
;
3723 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3725 /* make sure possible_cpu are intialized */
3726 mc
->possible_cpu_arch_ids(machine
);
3727 /* get CPU core slot containing thread that matches cpu_index */
3728 core_slot
= spapr_find_cpu_slot(machine
, cpu_index
, NULL
);
3730 return core_slot
->props
;
3733 static int64_t spapr_get_default_cpu_node_id(const MachineState
*ms
, int idx
)
3735 return idx
/ smp_cores
% nb_numa_nodes
;
3738 static const CPUArchIdList
*spapr_possible_cpu_arch_ids(MachineState
*machine
)
3741 const char *core_type
;
3742 int spapr_max_cores
= max_cpus
/ smp_threads
;
3743 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
3745 if (!mc
->has_hotpluggable_cpus
) {
3746 spapr_max_cores
= QEMU_ALIGN_UP(smp_cpus
, smp_threads
) / smp_threads
;
3748 if (machine
->possible_cpus
) {
3749 assert(machine
->possible_cpus
->len
== spapr_max_cores
);
3750 return machine
->possible_cpus
;
3753 core_type
= spapr_get_cpu_core_type(machine
->cpu_type
);
3755 error_report("Unable to find sPAPR CPU Core definition");
3759 machine
->possible_cpus
= g_malloc0(sizeof(CPUArchIdList
) +
3760 sizeof(CPUArchId
) * spapr_max_cores
);
3761 machine
->possible_cpus
->len
= spapr_max_cores
;
3762 for (i
= 0; i
< machine
->possible_cpus
->len
; i
++) {
3763 int core_id
= i
* smp_threads
;
3765 machine
->possible_cpus
->cpus
[i
].type
= core_type
;
3766 machine
->possible_cpus
->cpus
[i
].vcpus_count
= smp_threads
;
3767 machine
->possible_cpus
->cpus
[i
].arch_id
= core_id
;
3768 machine
->possible_cpus
->cpus
[i
].props
.has_core_id
= true;
3769 machine
->possible_cpus
->cpus
[i
].props
.core_id
= core_id
;
3771 return machine
->possible_cpus
;
3774 static void spapr_phb_placement(sPAPRMachineState
*spapr
, uint32_t index
,
3775 uint64_t *buid
, hwaddr
*pio
,
3776 hwaddr
*mmio32
, hwaddr
*mmio64
,
3777 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
3780 * New-style PHB window placement.
3782 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3783 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3786 * Some guest kernels can't work with MMIO windows above 1<<46
3787 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3789 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3790 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3791 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3792 * 1TiB 64-bit MMIO windows for each PHB.
3794 const uint64_t base_buid
= 0x800000020000000ULL
;
3795 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3796 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3799 /* Sanity check natural alignments */
3800 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3801 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT
% SPAPR_PCI_MEM64_WIN_SIZE
) != 0);
3802 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE
% SPAPR_PCI_MEM32_WIN_SIZE
) != 0);
3803 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE
% SPAPR_PCI_IO_WIN_SIZE
) != 0);
3804 /* Sanity check bounds */
3805 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_IO_WIN_SIZE
) >
3806 SPAPR_PCI_MEM32_WIN_SIZE
);
3807 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS
* SPAPR_PCI_MEM32_WIN_SIZE
) >
3808 SPAPR_PCI_MEM64_WIN_SIZE
);
3810 if (index
>= SPAPR_MAX_PHBS
) {
3811 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %llu)",
3812 SPAPR_MAX_PHBS
- 1);
3816 *buid
= base_buid
+ index
;
3817 for (i
= 0; i
< n_dma
; ++i
) {
3818 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
3821 *pio
= SPAPR_PCI_BASE
+ index
* SPAPR_PCI_IO_WIN_SIZE
;
3822 *mmio32
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM32_WIN_SIZE
;
3823 *mmio64
= SPAPR_PCI_BASE
+ (index
+ 1) * SPAPR_PCI_MEM64_WIN_SIZE
;
3826 static ICSState
*spapr_ics_get(XICSFabric
*dev
, int irq
)
3828 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3830 return ics_valid_irq(spapr
->ics
, irq
) ? spapr
->ics
: NULL
;
3833 static void spapr_ics_resend(XICSFabric
*dev
)
3835 sPAPRMachineState
*spapr
= SPAPR_MACHINE(dev
);
3837 ics_resend(spapr
->ics
);
3840 static ICPState
*spapr_icp_get(XICSFabric
*xi
, int vcpu_id
)
3842 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
3844 return cpu
? ICP(cpu
->intc
) : NULL
;
3847 static void spapr_pic_print_info(InterruptStatsProvider
*obj
,
3850 sPAPRMachineState
*spapr
= SPAPR_MACHINE(obj
);
3852 spapr
->irq
->print_info(spapr
, mon
);
3855 int spapr_get_vcpu_id(PowerPCCPU
*cpu
)
3857 return cpu
->vcpu_id
;
3860 void spapr_set_vcpu_id(PowerPCCPU
*cpu
, int cpu_index
, Error
**errp
)
3862 sPAPRMachineState
*spapr
= SPAPR_MACHINE(qdev_get_machine());
3865 vcpu_id
= spapr_vcpu_id(spapr
, cpu_index
);
3867 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id
)) {
3868 error_setg(errp
, "Can't create CPU with id %d in KVM", vcpu_id
);
3869 error_append_hint(errp
, "Adjust the number of cpus to %d "
3870 "or try to raise the number of threads per core\n",
3871 vcpu_id
* smp_threads
/ spapr
->vsmt
);
3875 cpu
->vcpu_id
= vcpu_id
;
3878 PowerPCCPU
*spapr_find_cpu(int vcpu_id
)
3883 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
3885 if (spapr_get_vcpu_id(cpu
) == vcpu_id
) {
3893 static void spapr_machine_class_init(ObjectClass
*oc
, void *data
)
3895 MachineClass
*mc
= MACHINE_CLASS(oc
);
3896 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(oc
);
3897 FWPathProviderClass
*fwc
= FW_PATH_PROVIDER_CLASS(oc
);
3898 NMIClass
*nc
= NMI_CLASS(oc
);
3899 HotplugHandlerClass
*hc
= HOTPLUG_HANDLER_CLASS(oc
);
3900 PPCVirtualHypervisorClass
*vhc
= PPC_VIRTUAL_HYPERVISOR_CLASS(oc
);
3901 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
3902 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
3904 mc
->desc
= "pSeries Logical Partition (PAPR compliant)";
3905 mc
->ignore_boot_device_suffixes
= true;
3908 * We set up the default / latest behaviour here. The class_init
3909 * functions for the specific versioned machine types can override
3910 * these details for backwards compatibility
3912 mc
->init
= spapr_machine_init
;
3913 mc
->reset
= spapr_machine_reset
;
3914 mc
->block_default_type
= IF_SCSI
;
3915 mc
->max_cpus
= 1024;
3916 mc
->no_parallel
= 1;
3917 mc
->default_boot_order
= "";
3918 mc
->default_ram_size
= 512 * MiB
;
3919 mc
->default_display
= "std";
3920 mc
->kvm_type
= spapr_kvm_type
;
3921 machine_class_allow_dynamic_sysbus_dev(mc
, TYPE_SPAPR_PCI_HOST_BRIDGE
);
3922 mc
->pci_allow_0_address
= true;
3923 assert(!mc
->get_hotplug_handler
);
3924 mc
->get_hotplug_handler
= spapr_get_hotplug_handler
;
3925 hc
->pre_plug
= spapr_machine_device_pre_plug
;
3926 hc
->plug
= spapr_machine_device_plug
;
3927 mc
->cpu_index_to_instance_props
= spapr_cpu_index_to_props
;
3928 mc
->get_default_cpu_node_id
= spapr_get_default_cpu_node_id
;
3929 mc
->possible_cpu_arch_ids
= spapr_possible_cpu_arch_ids
;
3930 hc
->unplug_request
= spapr_machine_device_unplug_request
;
3931 hc
->unplug
= spapr_machine_device_unplug
;
3933 smc
->dr_lmb_enabled
= true;
3934 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
3935 mc
->has_hotpluggable_cpus
= true;
3936 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_ENABLED
;
3937 fwc
->get_dev_path
= spapr_get_fw_dev_path
;
3938 nc
->nmi_monitor_handler
= spapr_nmi
;
3939 smc
->phb_placement
= spapr_phb_placement
;
3940 vhc
->hypercall
= emulate_spapr_hypercall
;
3941 vhc
->hpt_mask
= spapr_hpt_mask
;
3942 vhc
->map_hptes
= spapr_map_hptes
;
3943 vhc
->unmap_hptes
= spapr_unmap_hptes
;
3944 vhc
->store_hpte
= spapr_store_hpte
;
3945 vhc
->get_patbe
= spapr_get_patbe
;
3946 vhc
->encode_hpt_for_kvm_pr
= spapr_encode_hpt_for_kvm_pr
;
3947 xic
->ics_get
= spapr_ics_get
;
3948 xic
->ics_resend
= spapr_ics_resend
;
3949 xic
->icp_get
= spapr_icp_get
;
3950 ispc
->print_info
= spapr_pic_print_info
;
3951 /* Force NUMA node memory size to be a multiple of
3952 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3953 * in which LMBs are represented and hot-added
3955 mc
->numa_mem_align_shift
= 28;
3957 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_OFF
;
3958 smc
->default_caps
.caps
[SPAPR_CAP_VSX
] = SPAPR_CAP_ON
;
3959 smc
->default_caps
.caps
[SPAPR_CAP_DFP
] = SPAPR_CAP_ON
;
3960 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_BROKEN
;
3961 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_BROKEN
;
3962 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_BROKEN
;
3963 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 16; /* 64kiB */
3964 smc
->default_caps
.caps
[SPAPR_CAP_NESTED_KVM_HV
] = SPAPR_CAP_OFF
;
3965 spapr_caps_add_properties(smc
, &error_abort
);
3966 smc
->irq
= &spapr_irq_xics
;
3969 static const TypeInfo spapr_machine_info
= {
3970 .name
= TYPE_SPAPR_MACHINE
,
3971 .parent
= TYPE_MACHINE
,
3973 .instance_size
= sizeof(sPAPRMachineState
),
3974 .instance_init
= spapr_instance_init
,
3975 .instance_finalize
= spapr_machine_finalizefn
,
3976 .class_size
= sizeof(sPAPRMachineClass
),
3977 .class_init
= spapr_machine_class_init
,
3978 .interfaces
= (InterfaceInfo
[]) {
3979 { TYPE_FW_PATH_PROVIDER
},
3981 { TYPE_HOTPLUG_HANDLER
},
3982 { TYPE_PPC_VIRTUAL_HYPERVISOR
},
3983 { TYPE_XICS_FABRIC
},
3984 { TYPE_INTERRUPT_STATS_PROVIDER
},
3989 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3990 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3993 MachineClass *mc = MACHINE_CLASS(oc); \
3994 spapr_machine_##suffix##_class_options(mc); \
3996 mc->alias = "pseries"; \
3997 mc->is_default = 1; \
4000 static const TypeInfo spapr_machine_##suffix##_info = { \
4001 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
4002 .parent = TYPE_SPAPR_MACHINE, \
4003 .class_init = spapr_machine_##suffix##_class_init, \
4005 static void spapr_machine_register_##suffix(void) \
4007 type_register(&spapr_machine_##suffix##_info); \
4009 type_init(spapr_machine_register_##suffix)
4014 static void spapr_machine_4_0_class_options(MachineClass
*mc
)
4016 /* Defaults for the latest behaviour inherited from the base class */
4019 DEFINE_SPAPR_MACHINE(4_0
, "4.0", true);
4024 #define SPAPR_COMPAT_3_1 \
4027 static void spapr_machine_3_1_class_options(MachineClass
*mc
)
4029 spapr_machine_4_0_class_options(mc
);
4030 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_3_1
);
4031 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
4034 DEFINE_SPAPR_MACHINE(3_1
, "3.1", false);
4039 #define SPAPR_COMPAT_3_0 \
4042 static void spapr_machine_3_0_class_options(MachineClass
*mc
)
4044 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4046 spapr_machine_3_1_class_options(mc
);
4047 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_3_0
);
4049 smc
->legacy_irq_allocation
= true;
4050 smc
->irq
= &spapr_irq_xics_legacy
;
4053 DEFINE_SPAPR_MACHINE(3_0
, "3.0", false);
4058 #define SPAPR_COMPAT_2_12 \
4061 .driver = TYPE_POWERPC_CPU, \
4062 .property = "pre-3.0-migration", \
4066 .driver = TYPE_SPAPR_CPU_CORE, \
4067 .property = "pre-3.0-migration", \
4071 static void spapr_machine_2_12_class_options(MachineClass
*mc
)
4073 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4075 spapr_machine_3_0_class_options(mc
);
4076 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_12
);
4078 /* We depend on kvm_enabled() to choose a default value for the
4079 * hpt-max-page-size capability. Of course we can't do it here
4080 * because this is too early and the HW accelerator isn't initialzed
4081 * yet. Postpone this to machine init (see default_caps_with_cpu()).
4083 smc
->default_caps
.caps
[SPAPR_CAP_HPT_MAXPAGESIZE
] = 0;
4086 DEFINE_SPAPR_MACHINE(2_12
, "2.12", false);
4088 static void spapr_machine_2_12_sxxm_class_options(MachineClass
*mc
)
4090 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4092 spapr_machine_2_12_class_options(mc
);
4093 smc
->default_caps
.caps
[SPAPR_CAP_CFPC
] = SPAPR_CAP_WORKAROUND
;
4094 smc
->default_caps
.caps
[SPAPR_CAP_SBBC
] = SPAPR_CAP_WORKAROUND
;
4095 smc
->default_caps
.caps
[SPAPR_CAP_IBS
] = SPAPR_CAP_FIXED_CCD
;
4098 DEFINE_SPAPR_MACHINE(2_12_sxxm
, "2.12-sxxm", false);
4103 #define SPAPR_COMPAT_2_11 \
4106 static void spapr_machine_2_11_class_options(MachineClass
*mc
)
4108 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4110 spapr_machine_2_12_class_options(mc
);
4111 smc
->default_caps
.caps
[SPAPR_CAP_HTM
] = SPAPR_CAP_ON
;
4112 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_11
);
4115 DEFINE_SPAPR_MACHINE(2_11
, "2.11", false);
4120 #define SPAPR_COMPAT_2_10 \
4123 static void spapr_machine_2_10_class_options(MachineClass
*mc
)
4125 spapr_machine_2_11_class_options(mc
);
4126 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_10
);
4129 DEFINE_SPAPR_MACHINE(2_10
, "2.10", false);
4134 #define SPAPR_COMPAT_2_9 \
4137 .driver = TYPE_POWERPC_CPU, \
4138 .property = "pre-2.10-migration", \
4142 static void spapr_machine_2_9_class_options(MachineClass *mc)
4144 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4146 spapr_machine_2_10_class_options(mc
);
4147 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_9
);
4148 mc
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
4149 smc
->pre_2_10_has_unused_icps
= true;
4150 smc
->resize_hpt_default
= SPAPR_RESIZE_HPT_DISABLED
;
4153 DEFINE_SPAPR_MACHINE(2_9
, "2.9", false);
4158 #define SPAPR_COMPAT_2_8 \
4161 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4162 .property = "pcie-extended-configuration-space", \
4166 static void spapr_machine_2_8_class_options(MachineClass
*mc
)
4168 spapr_machine_2_9_class_options(mc
);
4169 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_8
);
4170 mc
->numa_mem_align_shift
= 23;
4173 DEFINE_SPAPR_MACHINE(2_8
, "2.8", false);
4178 #define SPAPR_COMPAT_2_7 \
4181 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4182 .property = "mem_win_size", \
4183 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4186 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4187 .property = "mem64_win_size", \
4191 .driver = TYPE_POWERPC_CPU, \
4192 .property = "pre-2.8-migration", \
4196 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4197 .property = "pre-2.8-migration", \
4201 static void phb_placement_2_7(sPAPRMachineState
*spapr
, uint32_t index
,
4202 uint64_t *buid
, hwaddr
*pio
,
4203 hwaddr
*mmio32
, hwaddr
*mmio64
,
4204 unsigned n_dma
, uint32_t *liobns
, Error
**errp
)
4206 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4207 const uint64_t base_buid
= 0x800000020000000ULL
;
4208 const hwaddr phb_spacing
= 0x1000000000ULL
; /* 64 GiB */
4209 const hwaddr mmio_offset
= 0xa0000000; /* 2 GiB + 512 MiB */
4210 const hwaddr pio_offset
= 0x80000000; /* 2 GiB */
4211 const uint32_t max_index
= 255;
4212 const hwaddr phb0_alignment
= 0x10000000000ULL
; /* 1 TiB */
4214 uint64_t ram_top
= MACHINE(spapr
)->ram_size
;
4215 hwaddr phb0_base
, phb_base
;
4218 /* Do we have device memory? */
4219 if (MACHINE(spapr
)->maxram_size
> ram_top
) {
4220 /* Can't just use maxram_size, because there may be an
4221 * alignment gap between normal and device memory regions
4223 ram_top
= MACHINE(spapr
)->device_memory
->base
+
4224 memory_region_size(&MACHINE(spapr
)->device_memory
->mr
);
4227 phb0_base
= QEMU_ALIGN_UP(ram_top
, phb0_alignment
);
4229 if (index
> max_index
) {
4230 error_setg(errp
, "\"index\" for PAPR PHB is too large (max %u)",
4235 *buid
= base_buid
+ index
;
4236 for (i
= 0; i
< n_dma
; ++i
) {
4237 liobns
[i
] = SPAPR_PCI_LIOBN(index
, i
);
4240 phb_base
= phb0_base
+ index
* phb_spacing
;
4241 *pio
= phb_base
+ pio_offset
;
4242 *mmio32
= phb_base
+ mmio_offset
;
4244 * We don't set the 64-bit MMIO window, relying on the PHB's
4245 * fallback behaviour of automatically splitting a large "32-bit"
4246 * window into contiguous 32-bit and 64-bit windows
4250 static void spapr_machine_2_7_class_options(MachineClass
*mc
)
4252 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4254 spapr_machine_2_8_class_options(mc
);
4255 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power7_v2.3");
4256 mc
->default_machine_opts
= "modern-hotplug-events=off";
4257 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_7
);
4258 smc
->phb_placement
= phb_placement_2_7
;
4261 DEFINE_SPAPR_MACHINE(2_7
, "2.7", false);
4266 #define SPAPR_COMPAT_2_6 \
4269 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4271 .value = stringify(off),\
4274 static void spapr_machine_2_6_class_options(MachineClass
*mc
)
4276 spapr_machine_2_7_class_options(mc
);
4277 mc
->has_hotpluggable_cpus
= false;
4278 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_6
);
4281 DEFINE_SPAPR_MACHINE(2_6
, "2.6", false);
4286 #define SPAPR_COMPAT_2_5 \
4289 .driver = "spapr-vlan", \
4290 .property = "use-rx-buffer-pools", \
4294 static void spapr_machine_2_5_class_options(MachineClass
*mc
)
4296 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4298 spapr_machine_2_6_class_options(mc
);
4299 smc
->use_ohci_by_default
= true;
4300 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_5
);
4303 DEFINE_SPAPR_MACHINE(2_5
, "2.5", false);
4308 #define SPAPR_COMPAT_2_4 \
4311 static void spapr_machine_2_4_class_options(MachineClass
*mc
)
4313 sPAPRMachineClass
*smc
= SPAPR_MACHINE_CLASS(mc
);
4315 spapr_machine_2_5_class_options(mc
);
4316 smc
->dr_lmb_enabled
= false;
4317 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_4
);
4320 DEFINE_SPAPR_MACHINE(2_4
, "2.4", false);
4325 #define SPAPR_COMPAT_2_3 \
4328 .driver = "spapr-pci-host-bridge",\
4329 .property = "dynamic-reconfiguration",\
4333 static void spapr_machine_2_3_class_options(MachineClass
*mc
)
4335 spapr_machine_2_4_class_options(mc
);
4336 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_3
);
4338 DEFINE_SPAPR_MACHINE(2_3
, "2.3", false);
4344 #define SPAPR_COMPAT_2_2 \
4347 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4348 .property = "mem_win_size",\
4349 .value = "0x20000000",\
4352 static void spapr_machine_2_2_class_options(MachineClass
*mc
)
4354 spapr_machine_2_3_class_options(mc
);
4355 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_2
);
4356 mc
->default_machine_opts
= "modern-hotplug-events=off,suppress-vmdesc=on";
4358 DEFINE_SPAPR_MACHINE(2_2
, "2.2", false);
4363 #define SPAPR_COMPAT_2_1 \
4366 static void spapr_machine_2_1_class_options(MachineClass
*mc
)
4368 spapr_machine_2_2_class_options(mc
);
4369 SET_MACHINE_COMPAT(mc
, SPAPR_COMPAT_2_1
);
4371 DEFINE_SPAPR_MACHINE(2_1
, "2.1", false);
4373 static void spapr_machine_register_types(void)
4375 type_register_static(&spapr_machine_info
);
4378 type_init(spapr_machine_register_types
)