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Merge remote-tracking branch 'kraxel/testdev.1' into staging
[qemu.git] / hw / ppc.c
blobe473f9e9622d1d12c3a6b5c7d38b7799aa50025b
1 /*
2 * QEMU generic PowerPC hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "ppc.h"
26 #include "qemu/timer.h"
27 #include "sysemu/sysemu.h"
28 #include "nvram.h"
29 #include "qemu/log.h"
30 #include "loader.h"
31 #include "sysemu/kvm.h"
32 #include "kvm_ppc.h"
33
34 //#define PPC_DEBUG_IRQ
35 //#define PPC_DEBUG_TB
36
37 #ifdef PPC_DEBUG_IRQ
38 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__)
39 #else
40 # define LOG_IRQ(...) do { } while (0)
41 #endif
42
43
44 #ifdef PPC_DEBUG_TB
45 # define LOG_TB(...) qemu_log(__VA_ARGS__)
46 #else
47 # define LOG_TB(...) do { } while (0)
48 #endif
49
50 static void cpu_ppc_tb_stop (CPUPPCState *env);
51 static void cpu_ppc_tb_start (CPUPPCState *env);
52
53 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level)
54 {
55 CPUPPCState *env = &cpu->env;
56 unsigned int old_pending = env->pending_interrupts;
57
58 if (level) {
59 env->pending_interrupts |= 1 << n_IRQ;
60 cpu_interrupt(env, CPU_INTERRUPT_HARD);
61 } else {
62 env->pending_interrupts &= ~(1 << n_IRQ);
63 if (env->pending_interrupts == 0)
64 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
65 }
66
67 if (old_pending != env->pending_interrupts) {
68 #ifdef CONFIG_KVM
69 kvmppc_set_interrupt(cpu, n_IRQ, level);
70 #endif
71 }
72
73 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
74 "req %08x\n", __func__, env, n_IRQ, level,
75 env->pending_interrupts, env->interrupt_request);
76 }
77
78 /* PowerPC 6xx / 7xx internal IRQ controller */
79 static void ppc6xx_set_irq(void *opaque, int pin, int level)
80 {
81 PowerPCCPU *cpu = opaque;
82 CPUPPCState *env = &cpu->env;
83 int cur_level;
84
85 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
86 env, pin, level);
87 cur_level = (env->irq_input_state >> pin) & 1;
88 /* Don't generate spurious events */
89 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
90 switch (pin) {
91 case PPC6xx_INPUT_TBEN:
92 /* Level sensitive - active high */
93 LOG_IRQ("%s: %s the time base\n",
94 __func__, level ? "start" : "stop");
95 if (level) {
96 cpu_ppc_tb_start(env);
97 } else {
98 cpu_ppc_tb_stop(env);
99 }
100 case PPC6xx_INPUT_INT:
101 /* Level sensitive - active high */
102 LOG_IRQ("%s: set the external IRQ state to %d\n",
103 __func__, level);
104 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
105 break;
106 case PPC6xx_INPUT_SMI:
107 /* Level sensitive - active high */
108 LOG_IRQ("%s: set the SMI IRQ state to %d\n",
109 __func__, level);
110 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level);
111 break;
112 case PPC6xx_INPUT_MCP:
113 /* Negative edge sensitive */
114 /* XXX: TODO: actual reaction may depends on HID0 status
115 * 603/604/740/750: check HID0[EMCP]
116 */
117 if (cur_level == 1 && level == 0) {
118 LOG_IRQ("%s: raise machine check state\n",
119 __func__);
120 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
121 }
122 break;
123 case PPC6xx_INPUT_CKSTP_IN:
124 /* Level sensitive - active low */
125 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
126 /* XXX: Note that the only way to restart the CPU is to reset it */
127 if (level) {
128 LOG_IRQ("%s: stop the CPU\n", __func__);
129 env->halted = 1;
130 }
131 break;
132 case PPC6xx_INPUT_HRESET:
133 /* Level sensitive - active low */
134 if (level) {
135 LOG_IRQ("%s: reset the CPU\n", __func__);
136 cpu_interrupt(env, CPU_INTERRUPT_RESET);
137 }
138 break;
139 case PPC6xx_INPUT_SRESET:
140 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
141 __func__, level);
142 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
143 break;
144 default:
145 /* Unknown pin - do nothing */
146 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
147 return;
148 }
149 if (level)
150 env->irq_input_state |= 1 << pin;
151 else
152 env->irq_input_state &= ~(1 << pin);
153 }
154 }
155
156 void ppc6xx_irq_init(CPUPPCState *env)
157 {
158 PowerPCCPU *cpu = ppc_env_get_cpu(env);
159
160 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu,
161 PPC6xx_INPUT_NB);
162 }
163
164 #if defined(TARGET_PPC64)
165 /* PowerPC 970 internal IRQ controller */
166 static void ppc970_set_irq(void *opaque, int pin, int level)
167 {
168 PowerPCCPU *cpu = opaque;
169 CPUPPCState *env = &cpu->env;
170 int cur_level;
171
172 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
173 env, pin, level);
174 cur_level = (env->irq_input_state >> pin) & 1;
175 /* Don't generate spurious events */
176 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
177 switch (pin) {
178 case PPC970_INPUT_INT:
179 /* Level sensitive - active high */
180 LOG_IRQ("%s: set the external IRQ state to %d\n",
181 __func__, level);
182 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
183 break;
184 case PPC970_INPUT_THINT:
185 /* Level sensitive - active high */
186 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
187 level);
188 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level);
189 break;
190 case PPC970_INPUT_MCP:
191 /* Negative edge sensitive */
192 /* XXX: TODO: actual reaction may depends on HID0 status
193 * 603/604/740/750: check HID0[EMCP]
194 */
195 if (cur_level == 1 && level == 0) {
196 LOG_IRQ("%s: raise machine check state\n",
197 __func__);
198 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1);
199 }
200 break;
201 case PPC970_INPUT_CKSTP:
202 /* Level sensitive - active low */
203 /* XXX: TODO: relay the signal to CKSTP_OUT pin */
204 if (level) {
205 LOG_IRQ("%s: stop the CPU\n", __func__);
206 env->halted = 1;
207 } else {
208 LOG_IRQ("%s: restart the CPU\n", __func__);
209 env->halted = 0;
210 qemu_cpu_kick(CPU(cpu));
211 }
212 break;
213 case PPC970_INPUT_HRESET:
214 /* Level sensitive - active low */
215 if (level) {
216 cpu_interrupt(env, CPU_INTERRUPT_RESET);
217 }
218 break;
219 case PPC970_INPUT_SRESET:
220 LOG_IRQ("%s: set the RESET IRQ state to %d\n",
221 __func__, level);
222 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level);
223 break;
224 case PPC970_INPUT_TBEN:
225 LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
226 level);
227 /* XXX: TODO */
228 break;
229 default:
230 /* Unknown pin - do nothing */
231 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
232 return;
233 }
234 if (level)
235 env->irq_input_state |= 1 << pin;
236 else
237 env->irq_input_state &= ~(1 << pin);
238 }
239 }
240
241 void ppc970_irq_init(CPUPPCState *env)
242 {
243 PowerPCCPU *cpu = ppc_env_get_cpu(env);
244
245 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu,
246 PPC970_INPUT_NB);
247 }
248
249 /* POWER7 internal IRQ controller */
250 static void power7_set_irq(void *opaque, int pin, int level)
251 {
252 PowerPCCPU *cpu = opaque;
253 CPUPPCState *env = &cpu->env;
254
255 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
256 env, pin, level);
257
258 switch (pin) {
259 case POWER7_INPUT_INT:
260 /* Level sensitive - active high */
261 LOG_IRQ("%s: set the external IRQ state to %d\n",
262 __func__, level);
263 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
264 break;
265 default:
266 /* Unknown pin - do nothing */
267 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
268 return;
269 }
270 if (level) {
271 env->irq_input_state |= 1 << pin;
272 } else {
273 env->irq_input_state &= ~(1 << pin);
274 }
275 }
276
277 void ppcPOWER7_irq_init(CPUPPCState *env)
278 {
279 PowerPCCPU *cpu = ppc_env_get_cpu(env);
280
281 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu,
282 POWER7_INPUT_NB);
283 }
284 #endif /* defined(TARGET_PPC64) */
285
286 /* PowerPC 40x internal IRQ controller */
287 static void ppc40x_set_irq(void *opaque, int pin, int level)
288 {
289 PowerPCCPU *cpu = opaque;
290 CPUPPCState *env = &cpu->env;
291 int cur_level;
292
293 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
294 env, pin, level);
295 cur_level = (env->irq_input_state >> pin) & 1;
296 /* Don't generate spurious events */
297 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
298 switch (pin) {
299 case PPC40x_INPUT_RESET_SYS:
300 if (level) {
301 LOG_IRQ("%s: reset the PowerPC system\n",
302 __func__);
303 ppc40x_system_reset(env);
304 }
305 break;
306 case PPC40x_INPUT_RESET_CHIP:
307 if (level) {
308 LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
309 ppc40x_chip_reset(env);
310 }
311 break;
312 case PPC40x_INPUT_RESET_CORE:
313 /* XXX: TODO: update DBSR[MRR] */
314 if (level) {
315 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
316 ppc40x_core_reset(env);
317 }
318 break;
319 case PPC40x_INPUT_CINT:
320 /* Level sensitive - active high */
321 LOG_IRQ("%s: set the critical IRQ state to %d\n",
322 __func__, level);
323 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
324 break;
325 case PPC40x_INPUT_INT:
326 /* Level sensitive - active high */
327 LOG_IRQ("%s: set the external IRQ state to %d\n",
328 __func__, level);
329 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
330 break;
331 case PPC40x_INPUT_HALT:
332 /* Level sensitive - active low */
333 if (level) {
334 LOG_IRQ("%s: stop the CPU\n", __func__);
335 env->halted = 1;
336 } else {
337 LOG_IRQ("%s: restart the CPU\n", __func__);
338 env->halted = 0;
339 qemu_cpu_kick(CPU(cpu));
340 }
341 break;
342 case PPC40x_INPUT_DEBUG:
343 /* Level sensitive - active high */
344 LOG_IRQ("%s: set the debug pin state to %d\n",
345 __func__, level);
346 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
347 break;
348 default:
349 /* Unknown pin - do nothing */
350 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
351 return;
352 }
353 if (level)
354 env->irq_input_state |= 1 << pin;
355 else
356 env->irq_input_state &= ~(1 << pin);
357 }
358 }
359
360 void ppc40x_irq_init(CPUPPCState *env)
361 {
362 PowerPCCPU *cpu = ppc_env_get_cpu(env);
363
364 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
365 cpu, PPC40x_INPUT_NB);
366 }
367
368 /* PowerPC E500 internal IRQ controller */
369 static void ppce500_set_irq(void *opaque, int pin, int level)
370 {
371 PowerPCCPU *cpu = opaque;
372 CPUPPCState *env = &cpu->env;
373 int cur_level;
374
375 LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
376 env, pin, level);
377 cur_level = (env->irq_input_state >> pin) & 1;
378 /* Don't generate spurious events */
379 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
380 switch (pin) {
381 case PPCE500_INPUT_MCK:
382 if (level) {
383 LOG_IRQ("%s: reset the PowerPC system\n",
384 __func__);
385 qemu_system_reset_request();
386 }
387 break;
388 case PPCE500_INPUT_RESET_CORE:
389 if (level) {
390 LOG_IRQ("%s: reset the PowerPC core\n", __func__);
391 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level);
392 }
393 break;
394 case PPCE500_INPUT_CINT:
395 /* Level sensitive - active high */
396 LOG_IRQ("%s: set the critical IRQ state to %d\n",
397 __func__, level);
398 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level);
399 break;
400 case PPCE500_INPUT_INT:
401 /* Level sensitive - active high */
402 LOG_IRQ("%s: set the core IRQ state to %d\n",
403 __func__, level);
404 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level);
405 break;
406 case PPCE500_INPUT_DEBUG:
407 /* Level sensitive - active high */
408 LOG_IRQ("%s: set the debug pin state to %d\n",
409 __func__, level);
410 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level);
411 break;
412 default:
413 /* Unknown pin - do nothing */
414 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
415 return;
416 }
417 if (level)
418 env->irq_input_state |= 1 << pin;
419 else
420 env->irq_input_state &= ~(1 << pin);
421 }
422 }
423
424 void ppce500_irq_init(CPUPPCState *env)
425 {
426 PowerPCCPU *cpu = ppc_env_get_cpu(env);
427
428 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
429 cpu, PPCE500_INPUT_NB);
430 }
431 /*****************************************************************************/
432 /* PowerPC time base and decrementer emulation */
433
434 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset)
435 {
436 /* TB time in tb periods */
437 return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
438 }
439
440 uint64_t cpu_ppc_load_tbl (CPUPPCState *env)
441 {
442 ppc_tb_t *tb_env = env->tb_env;
443 uint64_t tb;
444
445 if (kvm_enabled()) {
446 return env->spr[SPR_TBL];
447 }
448
449 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
450 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
451
452 return tb;
453 }
454
455 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)
456 {
457 ppc_tb_t *tb_env = env->tb_env;
458 uint64_t tb;
459
460 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
461 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
462
463 return tb >> 32;
464 }
465
466 uint32_t cpu_ppc_load_tbu (CPUPPCState *env)
467 {
468 if (kvm_enabled()) {
469 return env->spr[SPR_TBU];
470 }
471
472 return _cpu_ppc_load_tbu(env);
473 }
474
475 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk,
476 int64_t *tb_offsetp, uint64_t value)
477 {
478 *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec());
479 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
480 __func__, value, *tb_offsetp);
481 }
482
483 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)
484 {
485 ppc_tb_t *tb_env = env->tb_env;
486 uint64_t tb;
487
488 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
489 tb &= 0xFFFFFFFF00000000ULL;
490 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
491 &tb_env->tb_offset, tb | (uint64_t)value);
492 }
493
494 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)
495 {
496 ppc_tb_t *tb_env = env->tb_env;
497 uint64_t tb;
498
499 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset);
500 tb &= 0x00000000FFFFFFFFULL;
501 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
502 &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
503 }
504
505 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)
506 {
507 _cpu_ppc_store_tbu(env, value);
508 }
509
510 uint64_t cpu_ppc_load_atbl (CPUPPCState *env)
511 {
512 ppc_tb_t *tb_env = env->tb_env;
513 uint64_t tb;
514
515 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
516 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
517
518 return tb;
519 }
520
521 uint32_t cpu_ppc_load_atbu (CPUPPCState *env)
522 {
523 ppc_tb_t *tb_env = env->tb_env;
524 uint64_t tb;
525
526 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
527 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
528
529 return tb >> 32;
530 }
531
532 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)
533 {
534 ppc_tb_t *tb_env = env->tb_env;
535 uint64_t tb;
536
537 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
538 tb &= 0xFFFFFFFF00000000ULL;
539 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
540 &tb_env->atb_offset, tb | (uint64_t)value);
541 }
542
543 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)
544 {
545 ppc_tb_t *tb_env = env->tb_env;
546 uint64_t tb;
547
548 tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset);
549 tb &= 0x00000000FFFFFFFFULL;
550 cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock),
551 &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
552 }
553
554 static void cpu_ppc_tb_stop (CPUPPCState *env)
555 {
556 ppc_tb_t *tb_env = env->tb_env;
557 uint64_t tb, atb, vmclk;
558
559 /* If the time base is already frozen, do nothing */
560 if (tb_env->tb_freq != 0) {
561 vmclk = qemu_get_clock_ns(vm_clock);
562 /* Get the time base */
563 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);
564 /* Get the alternate time base */
565 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);
566 /* Store the time base value (ie compute the current offset) */
567 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
568 /* Store the alternate time base value (compute the current offset) */
569 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
570 /* Set the time base frequency to zero */
571 tb_env->tb_freq = 0;
572 /* Now, the time bases are frozen to tb_offset / atb_offset value */
573 }
574 }
575
576 static void cpu_ppc_tb_start (CPUPPCState *env)
577 {
578 ppc_tb_t *tb_env = env->tb_env;
579 uint64_t tb, atb, vmclk;
580
581 /* If the time base is not frozen, do nothing */
582 if (tb_env->tb_freq == 0) {
583 vmclk = qemu_get_clock_ns(vm_clock);
584 /* Get the time base from tb_offset */
585 tb = tb_env->tb_offset;
586 /* Get the alternate time base from atb_offset */
587 atb = tb_env->atb_offset;
588 /* Restore the tb frequency from the decrementer frequency */
589 tb_env->tb_freq = tb_env->decr_freq;
590 /* Store the time base value */
591 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);
592 /* Store the alternate time base value */
593 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);
594 }
595 }
596
597 static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)
598 {
599 ppc_tb_t *tb_env = env->tb_env;
600 uint32_t decr;
601 int64_t diff;
602
603 diff = next - qemu_get_clock_ns(vm_clock);
604 if (diff >= 0) {
605 decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec());
606 } else if (tb_env->flags & PPC_TIMER_BOOKE) {
607 decr = 0;
608 } else {
609 decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec());
610 }
611 LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
612
613 return decr;
614 }
615
616 uint32_t cpu_ppc_load_decr (CPUPPCState *env)
617 {
618 ppc_tb_t *tb_env = env->tb_env;
619
620 if (kvm_enabled()) {
621 return env->spr[SPR_DECR];
622 }
623
624 return _cpu_ppc_load_decr(env, tb_env->decr_next);
625 }
626
627 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)
628 {
629 ppc_tb_t *tb_env = env->tb_env;
630
631 return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
632 }
633
634 uint64_t cpu_ppc_load_purr (CPUPPCState *env)
635 {
636 ppc_tb_t *tb_env = env->tb_env;
637 uint64_t diff;
638
639 diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start;
640
641 return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
642 }
643
644 /* When decrementer expires,
645 * all we need to do is generate or queue a CPU exception
646 */
647 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu)
648 {
649 /* Raise it */
650 LOG_TB("raise decrementer exception\n");
651 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1);
652 }
653
654 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu)
655 {
656 /* Raise it */
657 LOG_TB("raise decrementer exception\n");
658 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1);
659 }
660
661 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp,
662 struct QEMUTimer *timer,
663 void (*raise_excp)(PowerPCCPU *),
664 uint32_t decr, uint32_t value,
665 int is_excp)
666 {
667 CPUPPCState *env = &cpu->env;
668 ppc_tb_t *tb_env = env->tb_env;
669 uint64_t now, next;
670
671 LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
672 decr, value);
673
674 if (kvm_enabled()) {
675 /* KVM handles decrementer exceptions, we don't need our own timer */
676 return;
677 }
678
679 now = qemu_get_clock_ns(vm_clock);
680 next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq);
681 if (is_excp) {
682 next += *nextp - now;
683 }
684 if (next == now) {
685 next++;
686 }
687 *nextp = next;
688 /* Adjust timer */
689 qemu_mod_timer(timer, next);
690
691 /* If we set a negative value and the decrementer was positive, raise an
692 * exception.
693 */
694 if ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED)
695 && (value & 0x80000000)
696 && !(decr & 0x80000000)) {
697 (*raise_excp)(cpu);
698 }
699 }
700
701 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, uint32_t decr,
702 uint32_t value, int is_excp)
703 {
704 ppc_tb_t *tb_env = cpu->env.tb_env;
705
706 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer,
707 &cpu_ppc_decr_excp, decr, value, is_excp);
708 }
709
710 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)
711 {
712 PowerPCCPU *cpu = ppc_env_get_cpu(env);
713
714 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, 0);
715 }
716
717 static void cpu_ppc_decr_cb(void *opaque)
718 {
719 PowerPCCPU *cpu = opaque;
720
721 _cpu_ppc_store_decr(cpu, 0x00000000, 0xFFFFFFFF, 1);
722 }
723
724 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, uint32_t hdecr,
725 uint32_t value, int is_excp)
726 {
727 ppc_tb_t *tb_env = cpu->env.tb_env;
728
729 if (tb_env->hdecr_timer != NULL) {
730 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer,
731 &cpu_ppc_hdecr_excp, hdecr, value, is_excp);
732 }
733 }
734
735 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)
736 {
737 PowerPCCPU *cpu = ppc_env_get_cpu(env);
738
739 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 0);
740 }
741
742 static void cpu_ppc_hdecr_cb(void *opaque)
743 {
744 PowerPCCPU *cpu = opaque;
745
746 _cpu_ppc_store_hdecr(cpu, 0x00000000, 0xFFFFFFFF, 1);
747 }
748
749 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value)
750 {
751 ppc_tb_t *tb_env = cpu->env.tb_env;
752
753 tb_env->purr_load = value;
754 tb_env->purr_start = qemu_get_clock_ns(vm_clock);
755 }
756
757 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)
758 {
759 CPUPPCState *env = opaque;
760 PowerPCCPU *cpu = ppc_env_get_cpu(env);
761 ppc_tb_t *tb_env = env->tb_env;
762
763 tb_env->tb_freq = freq;
764 tb_env->decr_freq = freq;
765 /* There is a bug in Linux 2.4 kernels:
766 * if a decrementer exception is pending when it enables msr_ee at startup,
767 * it's not ready to handle it...
768 */
769 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0);
770 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 0);
771 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL);
772 }
773
774 /* Set up (once) timebase frequency (in Hz) */
775 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
776 {
777 PowerPCCPU *cpu = ppc_env_get_cpu(env);
778 ppc_tb_t *tb_env;
779
780 tb_env = g_malloc0(sizeof(ppc_tb_t));
781 env->tb_env = tb_env;
782 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
783 /* Create new timer */
784 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, cpu);
785 if (0) {
786 /* XXX: find a suitable condition to enable the hypervisor decrementer
787 */
788 tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb,
789 cpu);
790 } else {
791 tb_env->hdecr_timer = NULL;
792 }
793 cpu_ppc_set_tb_clk(env, freq);
794
795 return &cpu_ppc_set_tb_clk;
796 }
797
798 /* Specific helpers for POWER & PowerPC 601 RTC */
799 #if 0
800 static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env)
801 {
802 return cpu_ppc_tb_init(env, 7812500);
803 }
804 #endif
805
806 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)
807 {
808 _cpu_ppc_store_tbu(env, value);
809 }
810
811 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)
812 {
813 return _cpu_ppc_load_tbu(env);
814 }
815
816 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)
817 {
818 cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
819 }
820
821 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)
822 {
823 return cpu_ppc_load_tbl(env) & 0x3FFFFF80;
824 }
825
826 /*****************************************************************************/
827 /* PowerPC 40x timers */
828
829 /* PIT, FIT & WDT */
830 typedef struct ppc40x_timer_t ppc40x_timer_t;
831 struct ppc40x_timer_t {
832 uint64_t pit_reload; /* PIT auto-reload value */
833 uint64_t fit_next; /* Tick for next FIT interrupt */
834 struct QEMUTimer *fit_timer;
835 uint64_t wdt_next; /* Tick for next WDT interrupt */
836 struct QEMUTimer *wdt_timer;
837
838 /* 405 have the PIT, 440 have a DECR. */
839 unsigned int decr_excp;
840 };
841
842 /* Fixed interval timer */
843 static void cpu_4xx_fit_cb (void *opaque)
844 {
845 PowerPCCPU *cpu;
846 CPUPPCState *env;
847 ppc_tb_t *tb_env;
848 ppc40x_timer_t *ppc40x_timer;
849 uint64_t now, next;
850
851 env = opaque;
852 cpu = ppc_env_get_cpu(env);
853 tb_env = env->tb_env;
854 ppc40x_timer = tb_env->opaque;
855 now = qemu_get_clock_ns(vm_clock);
856 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {
857 case 0:
858 next = 1 << 9;
859 break;
860 case 1:
861 next = 1 << 13;
862 break;
863 case 2:
864 next = 1 << 17;
865 break;
866 case 3:
867 next = 1 << 21;
868 break;
869 default:
870 /* Cannot occur, but makes gcc happy */
871 return;
872 }
873 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq);
874 if (next == now)
875 next++;
876 qemu_mod_timer(ppc40x_timer->fit_timer, next);
877 env->spr[SPR_40x_TSR] |= 1 << 26;
878 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) {
879 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1);
880 }
881 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
882 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
883 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
884 }
885
886 /* Programmable interval timer */
887 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)
888 {
889 ppc40x_timer_t *ppc40x_timer;
890 uint64_t now, next;
891
892 ppc40x_timer = tb_env->opaque;
893 if (ppc40x_timer->pit_reload <= 1 ||
894 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
895 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
896 /* Stop PIT */
897 LOG_TB("%s: stop PIT\n", __func__);
898 qemu_del_timer(tb_env->decr_timer);
899 } else {
900 LOG_TB("%s: start PIT %016" PRIx64 "\n",
901 __func__, ppc40x_timer->pit_reload);
902 now = qemu_get_clock_ns(vm_clock);
903 next = now + muldiv64(ppc40x_timer->pit_reload,
904 get_ticks_per_sec(), tb_env->decr_freq);
905 if (is_excp)
906 next += tb_env->decr_next - now;
907 if (next == now)
908 next++;
909 qemu_mod_timer(tb_env->decr_timer, next);
910 tb_env->decr_next = next;
911 }
912 }
913
914 static void cpu_4xx_pit_cb (void *opaque)
915 {
916 PowerPCCPU *cpu;
917 CPUPPCState *env;
918 ppc_tb_t *tb_env;
919 ppc40x_timer_t *ppc40x_timer;
920
921 env = opaque;
922 cpu = ppc_env_get_cpu(env);
923 tb_env = env->tb_env;
924 ppc40x_timer = tb_env->opaque;
925 env->spr[SPR_40x_TSR] |= 1 << 27;
926 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) {
927 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1);
928 }
929 start_stop_pit(env, tb_env, 1);
930 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " "
931 "%016" PRIx64 "\n", __func__,
932 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
933 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
934 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
935 ppc40x_timer->pit_reload);
936 }
937
938 /* Watchdog timer */
939 static void cpu_4xx_wdt_cb (void *opaque)
940 {
941 PowerPCCPU *cpu;
942 CPUPPCState *env;
943 ppc_tb_t *tb_env;
944 ppc40x_timer_t *ppc40x_timer;
945 uint64_t now, next;
946
947 env = opaque;
948 cpu = ppc_env_get_cpu(env);
949 tb_env = env->tb_env;
950 ppc40x_timer = tb_env->opaque;
951 now = qemu_get_clock_ns(vm_clock);
952 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {
953 case 0:
954 next = 1 << 17;
955 break;
956 case 1:
957 next = 1 << 21;
958 break;
959 case 2:
960 next = 1 << 25;
961 break;
962 case 3:
963 next = 1 << 29;
964 break;
965 default:
966 /* Cannot occur, but makes gcc happy */
967 return;
968 }
969 next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq);
970 if (next == now)
971 next++;
972 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__,
973 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
974 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
975 case 0x0:
976 case 0x1:
977 qemu_mod_timer(ppc40x_timer->wdt_timer, next);
978 ppc40x_timer->wdt_next = next;
979 env->spr[SPR_40x_TSR] |= 1 << 31;
980 break;
981 case 0x2:
982 qemu_mod_timer(ppc40x_timer->wdt_timer, next);
983 ppc40x_timer->wdt_next = next;
984 env->spr[SPR_40x_TSR] |= 1 << 30;
985 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) {
986 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1);
987 }
988 break;
989 case 0x3:
990 env->spr[SPR_40x_TSR] &= ~0x30000000;
991 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
992 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {
993 case 0x0:
994 /* No reset */
995 break;
996 case 0x1: /* Core reset */
997 ppc40x_core_reset(env);
998 break;
999 case 0x2: /* Chip reset */
1000 ppc40x_chip_reset(env);
1001 break;
1002 case 0x3: /* System reset */
1003 ppc40x_system_reset(env);
1004 break;
1005 }
1006 }
1007 }
1008
1009 void store_40x_pit (CPUPPCState *env, target_ulong val)
1010 {
1011 ppc_tb_t *tb_env;
1012 ppc40x_timer_t *ppc40x_timer;
1013
1014 tb_env = env->tb_env;
1015 ppc40x_timer = tb_env->opaque;
1016 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val);
1017 ppc40x_timer->pit_reload = val;
1018 start_stop_pit(env, tb_env, 0);
1019 }
1020
1021 target_ulong load_40x_pit (CPUPPCState *env)
1022 {
1023 return cpu_ppc_load_decr(env);
1024 }
1025
1026 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)
1027 {
1028 CPUPPCState *env = opaque;
1029 ppc_tb_t *tb_env = env->tb_env;
1030
1031 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
1032 freq);
1033 tb_env->tb_freq = freq;
1034 tb_env->decr_freq = freq;
1035 /* XXX: we should also update all timers */
1036 }
1037
1038 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
1039 unsigned int decr_excp)
1040 {
1041 ppc_tb_t *tb_env;
1042 ppc40x_timer_t *ppc40x_timer;
1043
1044 tb_env = g_malloc0(sizeof(ppc_tb_t));
1045 env->tb_env = tb_env;
1046 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED;
1047 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
1048 tb_env->tb_freq = freq;
1049 tb_env->decr_freq = freq;
1050 tb_env->opaque = ppc40x_timer;
1051 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
1052 if (ppc40x_timer != NULL) {
1053 /* We use decr timer for PIT */
1054 tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env);
1055 ppc40x_timer->fit_timer =
1056 qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env);
1057 ppc40x_timer->wdt_timer =
1058 qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env);
1059 ppc40x_timer->decr_excp = decr_excp;
1060 }
1061
1062 return &ppc_40x_set_tb_clk;
1063 }
1064
1065 /*****************************************************************************/
1066 /* Embedded PowerPC Device Control Registers */
1067 typedef struct ppc_dcrn_t ppc_dcrn_t;
1068 struct ppc_dcrn_t {
1069 dcr_read_cb dcr_read;
1070 dcr_write_cb dcr_write;
1071 void *opaque;
1072 };
1073
1074 /* XXX: on 460, DCR addresses are 32 bits wide,
1075 * using DCRIPR to get the 22 upper bits of the DCR address
1076 */
1077 #define DCRN_NB 1024
1078 struct ppc_dcr_t {
1079 ppc_dcrn_t dcrn[DCRN_NB];
1080 int (*read_error)(int dcrn);
1081 int (*write_error)(int dcrn);
1082 };
1083
1084 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
1085 {
1086 ppc_dcrn_t *dcr;
1087
1088 if (dcrn < 0 || dcrn >= DCRN_NB)
1089 goto error;
1090 dcr = &dcr_env->dcrn[dcrn];
1091 if (dcr->dcr_read == NULL)
1092 goto error;
1093 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);
1094
1095 return 0;
1096
1097 error:
1098 if (dcr_env->read_error != NULL)
1099 return (*dcr_env->read_error)(dcrn);
1100
1101 return -1;
1102 }
1103
1104 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
1105 {
1106 ppc_dcrn_t *dcr;
1107
1108 if (dcrn < 0 || dcrn >= DCRN_NB)
1109 goto error;
1110 dcr = &dcr_env->dcrn[dcrn];
1111 if (dcr->dcr_write == NULL)
1112 goto error;
1113 (*dcr->dcr_write)(dcr->opaque, dcrn, val);
1114
1115 return 0;
1116
1117 error:
1118 if (dcr_env->write_error != NULL)
1119 return (*dcr_env->write_error)(dcrn);
1120
1121 return -1;
1122 }
1123
1124 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
1125 dcr_read_cb dcr_read, dcr_write_cb dcr_write)
1126 {
1127 ppc_dcr_t *dcr_env;
1128 ppc_dcrn_t *dcr;
1129
1130 dcr_env = env->dcr_env;
1131 if (dcr_env == NULL)
1132 return -1;
1133 if (dcrn < 0 || dcrn >= DCRN_NB)
1134 return -1;
1135 dcr = &dcr_env->dcrn[dcrn];
1136 if (dcr->opaque != NULL ||
1137 dcr->dcr_read != NULL ||
1138 dcr->dcr_write != NULL)
1139 return -1;
1140 dcr->opaque = opaque;
1141 dcr->dcr_read = dcr_read;
1142 dcr->dcr_write = dcr_write;
1143
1144 return 0;
1145 }
1146
1147 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),
1148 int (*write_error)(int dcrn))
1149 {
1150 ppc_dcr_t *dcr_env;
1151
1152 dcr_env = g_malloc0(sizeof(ppc_dcr_t));
1153 dcr_env->read_error = read_error;
1154 dcr_env->write_error = write_error;
1155 env->dcr_env = dcr_env;
1156
1157 return 0;
1158 }
1159
1160 /*****************************************************************************/
1161 /* Debug port */
1162 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val)
1163 {
1164 addr &= 0xF;
1165 switch (addr) {
1166 case 0:
1167 printf("%c", val);
1168 break;
1169 case 1:
1170 printf("\n");
1171 fflush(stdout);
1172 break;
1173 case 2:
1174 printf("Set loglevel to %04" PRIx32 "\n", val);
1175 cpu_set_log(val | 0x100);
1176 break;
1177 }
1178 }
1179
1180 /*****************************************************************************/
1181 /* NVRAM helpers */
1182 static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr)
1183 {
1184 return (*nvram->read_fn)(nvram->opaque, addr);
1185 }
1186
1187 static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val)
1188 {
1189 (*nvram->write_fn)(nvram->opaque, addr, val);
1190 }
1191
1192 static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value)
1193 {
1194 nvram_write(nvram, addr, value);
1195 }
1196
1197 static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr)
1198 {
1199 return nvram_read(nvram, addr);
1200 }
1201
1202 static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value)
1203 {
1204 nvram_write(nvram, addr, value >> 8);
1205 nvram_write(nvram, addr + 1, value & 0xFF);
1206 }
1207
1208 static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr)
1209 {
1210 uint16_t tmp;
1211
1212 tmp = nvram_read(nvram, addr) << 8;
1213 tmp |= nvram_read(nvram, addr + 1);
1214
1215 return tmp;
1216 }
1217
1218 static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value)
1219 {
1220 nvram_write(nvram, addr, value >> 24);
1221 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
1222 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
1223 nvram_write(nvram, addr + 3, value & 0xFF);
1224 }
1225
1226 uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr)
1227 {
1228 uint32_t tmp;
1229
1230 tmp = nvram_read(nvram, addr) << 24;
1231 tmp |= nvram_read(nvram, addr + 1) << 16;
1232 tmp |= nvram_read(nvram, addr + 2) << 8;
1233 tmp |= nvram_read(nvram, addr + 3);
1234
1235 return tmp;
1236 }
1237
1238 static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str,
1239 uint32_t max)
1240 {
1241 int i;
1242
1243 for (i = 0; i < max && str[i] != '\0'; i++) {
1244 nvram_write(nvram, addr + i, str[i]);
1245 }
1246 nvram_write(nvram, addr + i, str[i]);
1247 nvram_write(nvram, addr + max - 1, '\0');
1248 }
1249
1250 int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max)
1251 {
1252 int i;
1253
1254 memset(dst, 0, max);
1255 for (i = 0; i < max; i++) {
1256 dst[i] = NVRAM_get_byte(nvram, addr + i);
1257 if (dst[i] == '\0')
1258 break;
1259 }
1260
1261 return i;
1262 }
1263
1264 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
1265 {
1266 uint16_t tmp;
1267 uint16_t pd, pd1, pd2;
1268
1269 tmp = prev >> 8;
1270 pd = prev ^ value;
1271 pd1 = pd & 0x000F;
1272 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
1273 tmp ^= (pd1 << 3) | (pd1 << 8);
1274 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
1275
1276 return tmp;
1277 }
1278
1279 static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
1280 {
1281 uint32_t i;
1282 uint16_t crc = 0xFFFF;
1283 int odd;
1284
1285 odd = count & 1;
1286 count &= ~1;
1287 for (i = 0; i != count; i++) {
1288 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
1289 }
1290 if (odd) {
1291 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
1292 }
1293
1294 return crc;
1295 }
1296
1297 #define CMDLINE_ADDR 0x017ff000
1298
1299 int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
1300 const char *arch,
1301 uint32_t RAM_size, int boot_device,
1302 uint32_t kernel_image, uint32_t kernel_size,
1303 const char *cmdline,
1304 uint32_t initrd_image, uint32_t initrd_size,
1305 uint32_t NVRAM_image,
1306 int width, int height, int depth)
1307 {
1308 uint16_t crc;
1309
1310 /* Set parameters for Open Hack'Ware BIOS */
1311 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
1312 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
1313 NVRAM_set_word(nvram, 0x14, NVRAM_size);
1314 NVRAM_set_string(nvram, 0x20, arch, 16);
1315 NVRAM_set_lword(nvram, 0x30, RAM_size);
1316 NVRAM_set_byte(nvram, 0x34, boot_device);
1317 NVRAM_set_lword(nvram, 0x38, kernel_image);
1318 NVRAM_set_lword(nvram, 0x3C, kernel_size);
1319 if (cmdline) {
1320 /* XXX: put the cmdline in NVRAM too ? */
1321 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
1322 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
1323 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
1324 } else {
1325 NVRAM_set_lword(nvram, 0x40, 0);
1326 NVRAM_set_lword(nvram, 0x44, 0);
1327 }
1328 NVRAM_set_lword(nvram, 0x48, initrd_image);
1329 NVRAM_set_lword(nvram, 0x4C, initrd_size);
1330 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
1331
1332 NVRAM_set_word(nvram, 0x54, width);
1333 NVRAM_set_word(nvram, 0x56, height);
1334 NVRAM_set_word(nvram, 0x58, depth);
1335 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
1336 NVRAM_set_word(nvram, 0xFC, crc);
1337
1338 return 0;
1339 }
QEmu