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acpi: set fadt.smi_cmd to zero when SMM is not supported
[qemu.git] / hw / i386 / acpi-build.c
blob49aef4ebd1d72b626ad795150e9c50b5ac3acbec
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "qapi/qmp/qnum.h"
26 #include "acpi-build.h"
27 #include "acpi-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "hw/core/cpu.h"
32 #include "target/i386/cpu.h"
33 #include "hw/misc/pvpanic.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/acpi/cpu.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "hw/boards.h"
47 #include "sysemu/tpm_backend.h"
48 #include "hw/rtc/mc146818rtc_regs.h"
49 #include "migration/vmstate.h"
50 #include "hw/mem/memory-device.h"
51 #include "hw/mem/nvdimm.h"
52 #include "sysemu/numa.h"
53 #include "sysemu/reset.h"
54 #include "hw/hyperv/vmbus-bridge.h"
55
56 /* Supported chipsets: */
57 #include "hw/southbridge/piix.h"
58 #include "hw/acpi/pcihp.h"
59 #include "hw/i386/fw_cfg.h"
60 #include "hw/i386/ich9.h"
61 #include "hw/pci/pci_bus.h"
62 #include "hw/pci-host/q35.h"
63 #include "hw/i386/x86-iommu.h"
64
65 #include "hw/acpi/aml-build.h"
66 #include "hw/acpi/utils.h"
67 #include "hw/acpi/pci.h"
68
69 #include "qom/qom-qobject.h"
70 #include "hw/i386/amd_iommu.h"
71 #include "hw/i386/intel_iommu.h"
72
73 #include "hw/acpi/ipmi.h"
74 #include "hw/acpi/hmat.h"
75
76 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
77 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
78 * a little bit, there should be plenty of free space since the DSDT
79 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
80 */
81 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
82 #define ACPI_BUILD_ALIGN_SIZE 0x1000
83
84 #define ACPI_BUILD_TABLE_SIZE 0x20000
85
86 /* #define DEBUG_ACPI_BUILD */
87 #ifdef DEBUG_ACPI_BUILD
88 #define ACPI_BUILD_DPRINTF(fmt, ...) \
89 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
90 #else
91 #define ACPI_BUILD_DPRINTF(fmt, ...)
92 #endif
93
94 typedef struct AcpiPmInfo {
95 bool s3_disabled;
96 bool s4_disabled;
97 bool pcihp_bridge_en;
98 bool smi_on_cpuhp;
99 bool smi_on_cpu_unplug;
100 bool pcihp_root_en;
101 uint8_t s4_val;
102 AcpiFadtData fadt;
103 uint16_t cpu_hp_io_base;
104 uint16_t pcihp_io_base;
105 uint16_t pcihp_io_len;
106 } AcpiPmInfo;
107
108 typedef struct AcpiMiscInfo {
109 bool is_piix4;
110 bool has_hpet;
111 TPMVersion tpm_version;
112 const unsigned char *dsdt_code;
113 unsigned dsdt_size;
114 uint16_t pvpanic_port;
115 uint16_t applesmc_io_base;
116 } AcpiMiscInfo;
117
118 typedef struct AcpiBuildPciBusHotplugState {
119 GArray *device_table;
120 GArray *notify_table;
121 struct AcpiBuildPciBusHotplugState *parent;
122 bool pcihp_bridge_en;
123 } AcpiBuildPciBusHotplugState;
124
125 typedef struct FwCfgTPMConfig {
126 uint32_t tpmppi_address;
127 uint8_t tpm_version;
128 uint8_t tpmppi_version;
129 } QEMU_PACKED FwCfgTPMConfig;
130
131 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg);
132
133 const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = {
134 .space_id = AML_AS_SYSTEM_IO,
135 .address = NVDIMM_ACPI_IO_BASE,
136 .bit_width = NVDIMM_ACPI_IO_LEN << 3
137 };
138
139 static void init_common_fadt_data(MachineState *ms, Object *o,
140 AcpiFadtData *data)
141 {
142 X86MachineState *x86ms = X86_MACHINE(ms);
143 /*
144 * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old
145 * behavior for compatibility irrelevant to smm_enabled, which doesn't
146 * comforms to ACPI spec.
147 */
148 bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ?
149 true : x86_machine_is_smm_enabled(x86ms);
150 uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL);
151 AmlAddressSpace as = AML_AS_SYSTEM_IO;
152 AcpiFadtData fadt = {
153 .rev = 3,
154 .flags =
155 (1 << ACPI_FADT_F_WBINVD) |
156 (1 << ACPI_FADT_F_PROC_C1) |
157 (1 << ACPI_FADT_F_SLP_BUTTON) |
158 (1 << ACPI_FADT_F_RTC_S4) |
159 (1 << ACPI_FADT_F_USE_PLATFORM_CLOCK) |
160 /* APIC destination mode ("Flat Logical") has an upper limit of 8
161 * CPUs for more than 8 CPUs, "Clustered Logical" mode has to be
162 * used
163 */
164 ((ms->smp.max_cpus > 8) ?
165 (1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL) : 0),
166 .int_model = 1 /* Multiple APIC */,
167 .rtc_century = RTC_CENTURY,
168 .plvl2_lat = 0xfff /* C2 state not supported */,
169 .plvl3_lat = 0xfff /* C3 state not supported */,
170 .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0,
171 .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL),
172 .acpi_enable_cmd =
173 smm_enabled ?
174 object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) :
175 0,
176 .acpi_disable_cmd =
177 smm_enabled ?
178 object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) :
179 0,
180 .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io },
181 .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8,
182 .address = io + 0x04 },
183 .pm_tmr = { .space_id = as, .bit_width = 4 * 8, .address = io + 0x08 },
184 .gpe0_blk = { .space_id = as, .bit_width =
185 object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK_LEN, NULL) * 8,
186 .address = object_property_get_uint(o, ACPI_PM_PROP_GPE0_BLK, NULL)
187 },
188 };
189 *data = fadt;
190 }
191
192 static Object *object_resolve_type_unambiguous(const char *typename)
193 {
194 bool ambig;
195 Object *o = object_resolve_path_type("", typename, &ambig);
196
197 if (ambig || !o) {
198 return NULL;
199 }
200 return o;
201 }
202
203 static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
204 {
205 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
206 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
207 Object *obj = piix ? piix : lpc;
208 QObject *o;
209 pm->cpu_hp_io_base = 0;
210 pm->pcihp_io_base = 0;
211 pm->pcihp_io_len = 0;
212 pm->smi_on_cpuhp = false;
213 pm->smi_on_cpu_unplug = false;
214
215 assert(obj);
216 init_common_fadt_data(machine, obj, &pm->fadt);
217 if (piix) {
218 /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */
219 pm->fadt.rev = 1;
220 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
221 pm->pcihp_io_base =
222 object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
223 pm->pcihp_io_len =
224 object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
225 }
226 if (lpc) {
227 uint64_t smi_features = object_property_get_uint(lpc,
228 ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL);
229 struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO,
230 .bit_width = 8, .address = ICH9_RST_CNT_IOPORT };
231 pm->fadt.reset_reg = r;
232 pm->fadt.reset_val = 0xf;
233 pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP;
234 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
235 pm->smi_on_cpuhp =
236 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT));
237 pm->smi_on_cpu_unplug =
238 !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT));
239 }
240
241 /* The above need not be conditional on machine type because the reset port
242 * happens to be the same on PIIX (pc) and ICH9 (q35). */
243 QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
244
245 /* Fill in optional s3/s4 related properties */
246 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
247 if (o) {
248 pm->s3_disabled = qnum_get_uint(qobject_to(QNum, o));
249 } else {
250 pm->s3_disabled = false;
251 }
252 qobject_unref(o);
253 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
254 if (o) {
255 pm->s4_disabled = qnum_get_uint(qobject_to(QNum, o));
256 } else {
257 pm->s4_disabled = false;
258 }
259 qobject_unref(o);
260 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
261 if (o) {
262 pm->s4_val = qnum_get_uint(qobject_to(QNum, o));
263 } else {
264 pm->s4_val = false;
265 }
266 qobject_unref(o);
267
268 pm->pcihp_bridge_en =
269 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
270 NULL);
271 pm->pcihp_root_en =
272 object_property_get_bool(obj, "acpi-root-pci-hotplug",
273 NULL);
274 }
275
276 static void acpi_get_misc_info(AcpiMiscInfo *info)
277 {
278 Object *piix = object_resolve_type_unambiguous(TYPE_PIIX4_PM);
279 Object *lpc = object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE);
280 assert(!!piix != !!lpc);
281
282 if (piix) {
283 info->is_piix4 = true;
284 }
285 if (lpc) {
286 info->is_piix4 = false;
287 }
288
289 info->has_hpet = hpet_find();
290 info->tpm_version = tpm_get_version(tpm_find());
291 info->pvpanic_port = pvpanic_port();
292 info->applesmc_io_base = applesmc_port();
293 }
294
295 /*
296 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
297 * On i386 arch we only have two pci hosts, so we can look only for them.
298 */
299 static Object *acpi_get_i386_pci_host(void)
300 {
301 PCIHostState *host;
302
303 host = OBJECT_CHECK(PCIHostState,
304 object_resolve_path("/machine/i440fx", NULL),
305 TYPE_PCI_HOST_BRIDGE);
306 if (!host) {
307 host = OBJECT_CHECK(PCIHostState,
308 object_resolve_path("/machine/q35", NULL),
309 TYPE_PCI_HOST_BRIDGE);
310 }
311
312 return OBJECT(host);
313 }
314
315 static void acpi_get_pci_holes(Range *hole, Range *hole64)
316 {
317 Object *pci_host;
318
319 pci_host = acpi_get_i386_pci_host();
320 g_assert(pci_host);
321
322 range_set_bounds1(hole,
323 object_property_get_uint(pci_host,
324 PCI_HOST_PROP_PCI_HOLE_START,
325 NULL),
326 object_property_get_uint(pci_host,
327 PCI_HOST_PROP_PCI_HOLE_END,
328 NULL));
329 range_set_bounds1(hole64,
330 object_property_get_uint(pci_host,
331 PCI_HOST_PROP_PCI_HOLE64_START,
332 NULL),
333 object_property_get_uint(pci_host,
334 PCI_HOST_PROP_PCI_HOLE64_END,
335 NULL));
336 }
337
338 static void acpi_align_size(GArray *blob, unsigned align)
339 {
340 /* Align size to multiple of given size. This reduces the chance
341 * we need to change size in the future (breaking cross version migration).
342 */
343 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
344 }
345
346 /* FACS */
347 static void
348 build_facs(GArray *table_data)
349 {
350 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
351 memcpy(&facs->signature, "FACS", 4);
352 facs->length = cpu_to_le32(sizeof(*facs));
353 }
354
355 static void build_append_pcihp_notify_entry(Aml *method, int slot)
356 {
357 Aml *if_ctx;
358 int32_t devfn = PCI_DEVFN(slot, 0);
359
360 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
361 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
362 aml_append(method, if_ctx);
363 }
364
365 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
366 bool pcihp_bridge_en)
367 {
368 Aml *dev, *notify_method = NULL, *method;
369 QObject *bsel;
370 PCIBus *sec;
371 int i;
372
373 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
374 if (bsel) {
375 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
376
377 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
378 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
379 }
380
381 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
382 DeviceClass *dc;
383 PCIDeviceClass *pc;
384 PCIDevice *pdev = bus->devices[i];
385 int slot = PCI_SLOT(i);
386 bool hotplug_enabled_dev;
387 bool bridge_in_acpi;
388 bool cold_plugged_bridge;
389
390 if (!pdev) {
391 if (bsel) { /* add hotplug slots for non present devices */
392 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
393 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
394 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
395 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
396 aml_append(method,
397 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
398 );
399 aml_append(dev, method);
400 aml_append(parent_scope, dev);
401
402 build_append_pcihp_notify_entry(notify_method, slot);
403 }
404 continue;
405 }
406
407 pc = PCI_DEVICE_GET_CLASS(pdev);
408 dc = DEVICE_GET_CLASS(pdev);
409
410 /*
411 * Cold plugged bridges aren't themselves hot-pluggable.
412 * Hotplugged bridges *are* hot-pluggable.
413 */
414 cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged;
415 bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en;
416
417 hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge;
418
419 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
420 continue;
421 }
422
423 /* start to compose PCI slot descriptor */
424 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
425 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
426
427 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
428 /* add VGA specific AML methods */
429 int s3d;
430
431 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
432 s3d = 3;
433 } else {
434 s3d = 0;
435 }
436
437 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
438 aml_append(method, aml_return(aml_int(0)));
439 aml_append(dev, method);
440
441 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
442 aml_append(method, aml_return(aml_int(0)));
443 aml_append(dev, method);
444
445 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
446 aml_append(method, aml_return(aml_int(s3d)));
447 aml_append(dev, method);
448 } else if (hotplug_enabled_dev) {
449 /* add _SUN/_EJ0 to make slot hotpluggable */
450 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
451
452 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
453 aml_append(method,
454 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
455 );
456 aml_append(dev, method);
457
458 if (bsel) {
459 build_append_pcihp_notify_entry(notify_method, slot);
460 }
461 } else if (bridge_in_acpi) {
462 /*
463 * device is coldplugged bridge,
464 * add child device descriptions into its scope
465 */
466 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
467
468 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
469 }
470 /* slot descriptor has been composed, add it into parent context */
471 aml_append(parent_scope, dev);
472 }
473
474 if (bsel) {
475 aml_append(parent_scope, notify_method);
476 }
477
478 /* Append PCNT method to notify about events on local and child buses.
479 * Add this method for root bus only when hotplug is enabled since DSDT
480 * expects it.
481 */
482 if (bsel || pcihp_bridge_en) {
483 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
484
485 /* If bus supports hotplug select it and notify about local events */
486 if (bsel) {
487 uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel));
488
489 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
490 aml_append(method, aml_call2("DVNT", aml_name("PCIU"),
491 aml_int(1))); /* Device Check */
492 aml_append(method, aml_call2("DVNT", aml_name("PCID"),
493 aml_int(3))); /* Eject Request */
494 }
495
496 /* Notify about child bus events in any case */
497 if (pcihp_bridge_en) {
498 QLIST_FOREACH(sec, &bus->child, sibling) {
499 int32_t devfn = sec->parent_dev->devfn;
500
501 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
502 continue;
503 }
504
505 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
506 }
507 }
508
509 aml_append(parent_scope, method);
510 }
511 qobject_unref(bsel);
512 }
513
514 /**
515 * build_prt_entry:
516 * @link_name: link name for PCI route entry
517 *
518 * build AML package containing a PCI route entry for @link_name
519 */
520 static Aml *build_prt_entry(const char *link_name)
521 {
522 Aml *a_zero = aml_int(0);
523 Aml *pkg = aml_package(4);
524 aml_append(pkg, a_zero);
525 aml_append(pkg, a_zero);
526 aml_append(pkg, aml_name("%s", link_name));
527 aml_append(pkg, a_zero);
528 return pkg;
529 }
530
531 /*
532 * initialize_route - Initialize the interrupt routing rule
533 * through a specific LINK:
534 * if (lnk_idx == idx)
535 * route using link 'link_name'
536 */
537 static Aml *initialize_route(Aml *route, const char *link_name,
538 Aml *lnk_idx, int idx)
539 {
540 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
541 Aml *pkg = build_prt_entry(link_name);
542
543 aml_append(if_ctx, aml_store(pkg, route));
544
545 return if_ctx;
546 }
547
548 /*
549 * build_prt - Define interrupt rounting rules
550 *
551 * Returns an array of 128 routes, one for each device,
552 * based on device location.
553 * The main goal is to equaly distribute the interrupts
554 * over the 4 existing ACPI links (works only for i440fx).
555 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
556 *
557 */
558 static Aml *build_prt(bool is_pci0_prt)
559 {
560 Aml *method, *while_ctx, *pin, *res;
561
562 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
563 res = aml_local(0);
564 pin = aml_local(1);
565 aml_append(method, aml_store(aml_package(128), res));
566 aml_append(method, aml_store(aml_int(0), pin));
567
568 /* while (pin < 128) */
569 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
570 {
571 Aml *slot = aml_local(2);
572 Aml *lnk_idx = aml_local(3);
573 Aml *route = aml_local(4);
574
575 /* slot = pin >> 2 */
576 aml_append(while_ctx,
577 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
578 /* lnk_idx = (slot + pin) & 3 */
579 aml_append(while_ctx,
580 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
581 lnk_idx));
582
583 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
584 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
585 if (is_pci0_prt) {
586 Aml *if_device_1, *if_pin_4, *else_pin_4;
587
588 /* device 1 is the power-management device, needs SCI */
589 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
590 {
591 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
592 {
593 aml_append(if_pin_4,
594 aml_store(build_prt_entry("LNKS"), route));
595 }
596 aml_append(if_device_1, if_pin_4);
597 else_pin_4 = aml_else();
598 {
599 aml_append(else_pin_4,
600 aml_store(build_prt_entry("LNKA"), route));
601 }
602 aml_append(if_device_1, else_pin_4);
603 }
604 aml_append(while_ctx, if_device_1);
605 } else {
606 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
607 }
608 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
609 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
610
611 /* route[0] = 0x[slot]FFFF */
612 aml_append(while_ctx,
613 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
614 NULL),
615 aml_index(route, aml_int(0))));
616 /* route[1] = pin & 3 */
617 aml_append(while_ctx,
618 aml_store(aml_and(pin, aml_int(3), NULL),
619 aml_index(route, aml_int(1))));
620 /* res[pin] = route */
621 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
622 /* pin++ */
623 aml_append(while_ctx, aml_increment(pin));
624 }
625 aml_append(method, while_ctx);
626 /* return res*/
627 aml_append(method, aml_return(res));
628
629 return method;
630 }
631
632 static void build_hpet_aml(Aml *table)
633 {
634 Aml *crs;
635 Aml *field;
636 Aml *method;
637 Aml *if_ctx;
638 Aml *scope = aml_scope("_SB");
639 Aml *dev = aml_device("HPET");
640 Aml *zero = aml_int(0);
641 Aml *id = aml_local(0);
642 Aml *period = aml_local(1);
643
644 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
645 aml_append(dev, aml_name_decl("_UID", zero));
646
647 aml_append(dev,
648 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
649 HPET_LEN));
650 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
651 aml_append(field, aml_named_field("VEND", 32));
652 aml_append(field, aml_named_field("PRD", 32));
653 aml_append(dev, field);
654
655 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
656 aml_append(method, aml_store(aml_name("VEND"), id));
657 aml_append(method, aml_store(aml_name("PRD"), period));
658 aml_append(method, aml_shiftright(id, aml_int(16), id));
659 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
660 aml_equal(id, aml_int(0xffff))));
661 {
662 aml_append(if_ctx, aml_return(zero));
663 }
664 aml_append(method, if_ctx);
665
666 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
667 aml_lgreater(period, aml_int(100000000))));
668 {
669 aml_append(if_ctx, aml_return(zero));
670 }
671 aml_append(method, if_ctx);
672
673 aml_append(method, aml_return(aml_int(0x0F)));
674 aml_append(dev, method);
675
676 crs = aml_resource_template();
677 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
678 aml_append(dev, aml_name_decl("_CRS", crs));
679
680 aml_append(scope, dev);
681 aml_append(table, scope);
682 }
683
684 static Aml *build_vmbus_device_aml(VMBusBridge *vmbus_bridge)
685 {
686 Aml *dev;
687 Aml *method;
688 Aml *crs;
689
690 dev = aml_device("VMBS");
691 aml_append(dev, aml_name_decl("STA", aml_int(0xF)));
692 aml_append(dev, aml_name_decl("_HID", aml_string("VMBus")));
693 aml_append(dev, aml_name_decl("_UID", aml_int(0x0)));
694 aml_append(dev, aml_name_decl("_DDN", aml_string("VMBUS")));
695
696 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
697 aml_append(method, aml_store(aml_and(aml_name("STA"), aml_int(0xD), NULL),
698 aml_name("STA")));
699 aml_append(dev, method);
700
701 method = aml_method("_PS0", 0, AML_NOTSERIALIZED);
702 aml_append(method, aml_store(aml_or(aml_name("STA"), aml_int(0xF), NULL),
703 aml_name("STA")));
704 aml_append(dev, method);
705
706 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
707 aml_append(method, aml_return(aml_name("STA")));
708 aml_append(dev, method);
709
710 aml_append(dev, aml_name_decl("_PS3", aml_int(0x0)));
711
712 crs = aml_resource_template();
713 aml_append(crs, aml_irq_no_flags(vmbus_bridge->irq));
714 aml_append(dev, aml_name_decl("_CRS", crs));
715
716 return dev;
717 }
718
719 static void build_isa_devices_aml(Aml *table)
720 {
721 bool ambiguous;
722 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
723 Aml *scope;
724
725 assert(obj && !ambiguous);
726
727 scope = aml_scope("_SB.PCI0.ISA");
728 build_acpi_ipmi_devices(scope, BUS(obj), "\\_SB.PCI0.ISA");
729 isa_build_aml(ISA_BUS(obj), scope);
730
731 aml_append(table, scope);
732 }
733
734 static void build_dbg_aml(Aml *table)
735 {
736 Aml *field;
737 Aml *method;
738 Aml *while_ctx;
739 Aml *scope = aml_scope("\\");
740 Aml *buf = aml_local(0);
741 Aml *len = aml_local(1);
742 Aml *idx = aml_local(2);
743
744 aml_append(scope,
745 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
746 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
747 aml_append(field, aml_named_field("DBGB", 8));
748 aml_append(scope, field);
749
750 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
751
752 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
753 aml_append(method, aml_to_buffer(buf, buf));
754 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
755 aml_append(method, aml_store(aml_int(0), idx));
756
757 while_ctx = aml_while(aml_lless(idx, len));
758 aml_append(while_ctx,
759 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
760 aml_append(while_ctx, aml_increment(idx));
761 aml_append(method, while_ctx);
762
763 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
764 aml_append(scope, method);
765
766 aml_append(table, scope);
767 }
768
769 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
770 {
771 Aml *dev;
772 Aml *crs;
773 Aml *method;
774 uint32_t irqs[] = {5, 10, 11};
775
776 dev = aml_device("%s", name);
777 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
778 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
779
780 crs = aml_resource_template();
781 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
782 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
783 aml_append(dev, aml_name_decl("_PRS", crs));
784
785 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
786 aml_append(method, aml_return(aml_call1("IQST", reg)));
787 aml_append(dev, method);
788
789 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
790 aml_append(method, aml_or(reg, aml_int(0x80), reg));
791 aml_append(dev, method);
792
793 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
794 aml_append(method, aml_return(aml_call1("IQCR", reg)));
795 aml_append(dev, method);
796
797 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
798 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
799 aml_append(method, aml_store(aml_name("PRRI"), reg));
800 aml_append(dev, method);
801
802 return dev;
803 }
804
805 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
806 {
807 Aml *dev;
808 Aml *crs;
809 Aml *method;
810 uint32_t irqs;
811
812 dev = aml_device("%s", name);
813 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
814 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
815
816 crs = aml_resource_template();
817 irqs = gsi;
818 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
819 AML_SHARED, &irqs, 1));
820 aml_append(dev, aml_name_decl("_PRS", crs));
821
822 aml_append(dev, aml_name_decl("_CRS", crs));
823
824 /*
825 * _DIS can be no-op because the interrupt cannot be disabled.
826 */
827 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
828 aml_append(dev, method);
829
830 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
831 aml_append(dev, method);
832
833 return dev;
834 }
835
836 /* _CRS method - get current settings */
837 static Aml *build_iqcr_method(bool is_piix4)
838 {
839 Aml *if_ctx;
840 uint32_t irqs;
841 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
842 Aml *crs = aml_resource_template();
843
844 irqs = 0;
845 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
846 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
847 aml_append(method, aml_name_decl("PRR0", crs));
848
849 aml_append(method,
850 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
851
852 if (is_piix4) {
853 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
854 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
855 aml_append(method, if_ctx);
856 } else {
857 aml_append(method,
858 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
859 aml_name("PRRI")));
860 }
861
862 aml_append(method, aml_return(aml_name("PRR0")));
863 return method;
864 }
865
866 /* _STA method - get status */
867 static Aml *build_irq_status_method(void)
868 {
869 Aml *if_ctx;
870 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
871
872 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
873 aml_append(if_ctx, aml_return(aml_int(0x09)));
874 aml_append(method, if_ctx);
875 aml_append(method, aml_return(aml_int(0x0B)));
876 return method;
877 }
878
879 static void build_piix4_pci0_int(Aml *table)
880 {
881 Aml *dev;
882 Aml *crs;
883 Aml *field;
884 Aml *method;
885 uint32_t irqs;
886 Aml *sb_scope = aml_scope("_SB");
887 Aml *pci0_scope = aml_scope("PCI0");
888
889 aml_append(pci0_scope, build_prt(true));
890 aml_append(sb_scope, pci0_scope);
891
892 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
893 aml_append(field, aml_named_field("PRQ0", 8));
894 aml_append(field, aml_named_field("PRQ1", 8));
895 aml_append(field, aml_named_field("PRQ2", 8));
896 aml_append(field, aml_named_field("PRQ3", 8));
897 aml_append(sb_scope, field);
898
899 aml_append(sb_scope, build_irq_status_method());
900 aml_append(sb_scope, build_iqcr_method(true));
901
902 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
903 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
904 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
905 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
906
907 dev = aml_device("LNKS");
908 {
909 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
910 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
911
912 crs = aml_resource_template();
913 irqs = 9;
914 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
915 AML_ACTIVE_HIGH, AML_SHARED,
916 &irqs, 1));
917 aml_append(dev, aml_name_decl("_PRS", crs));
918
919 /* The SCI cannot be disabled and is always attached to GSI 9,
920 * so these are no-ops. We only need this link to override the
921 * polarity to active high and match the content of the MADT.
922 */
923 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
924 aml_append(method, aml_return(aml_int(0x0b)));
925 aml_append(dev, method);
926
927 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
928 aml_append(dev, method);
929
930 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
931 aml_append(method, aml_return(aml_name("_PRS")));
932 aml_append(dev, method);
933
934 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
935 aml_append(dev, method);
936 }
937 aml_append(sb_scope, dev);
938
939 aml_append(table, sb_scope);
940 }
941
942 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
943 {
944 int i;
945 int head;
946 Aml *pkg;
947 char base = name[3] < 'E' ? 'A' : 'E';
948 char *s = g_strdup(name);
949 Aml *a_nr = aml_int((nr << 16) | 0xffff);
950
951 assert(strlen(s) == 4);
952
953 head = name[3] - base;
954 for (i = 0; i < 4; i++) {
955 if (head + i > 3) {
956 head = i * -1;
957 }
958 s[3] = base + head + i;
959 pkg = aml_package(4);
960 aml_append(pkg, a_nr);
961 aml_append(pkg, aml_int(i));
962 aml_append(pkg, aml_name("%s", s));
963 aml_append(pkg, aml_int(0));
964 aml_append(ctx, pkg);
965 }
966 g_free(s);
967 }
968
969 static Aml *build_q35_routing_table(const char *str)
970 {
971 int i;
972 Aml *pkg;
973 char *name = g_strdup_printf("%s ", str);
974
975 pkg = aml_package(128);
976 for (i = 0; i < 0x18; i++) {
977 name[3] = 'E' + (i & 0x3);
978 append_q35_prt_entry(pkg, i, name);
979 }
980
981 name[3] = 'E';
982 append_q35_prt_entry(pkg, 0x18, name);
983
984 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
985 for (i = 0x0019; i < 0x1e; i++) {
986 name[3] = 'A';
987 append_q35_prt_entry(pkg, i, name);
988 }
989
990 /* PCIe->PCI bridge. use PIRQ[E-H] */
991 name[3] = 'E';
992 append_q35_prt_entry(pkg, 0x1e, name);
993 name[3] = 'A';
994 append_q35_prt_entry(pkg, 0x1f, name);
995
996 g_free(name);
997 return pkg;
998 }
999
1000 static void build_q35_pci0_int(Aml *table)
1001 {
1002 Aml *field;
1003 Aml *method;
1004 Aml *sb_scope = aml_scope("_SB");
1005 Aml *pci0_scope = aml_scope("PCI0");
1006
1007 /* Zero => PIC mode, One => APIC Mode */
1008 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1009 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1010 {
1011 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1012 }
1013 aml_append(table, method);
1014
1015 aml_append(pci0_scope,
1016 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1017 aml_append(pci0_scope,
1018 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1019
1020 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1021 {
1022 Aml *if_ctx;
1023 Aml *else_ctx;
1024
1025 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1026 section 6.2.8.1 */
1027 /* Note: we provide the same info as the PCI routing
1028 table of the Bochs BIOS */
1029 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1030 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1031 aml_append(method, if_ctx);
1032 else_ctx = aml_else();
1033 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1034 aml_append(method, else_ctx);
1035 }
1036 aml_append(pci0_scope, method);
1037 aml_append(sb_scope, pci0_scope);
1038
1039 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1040 aml_append(field, aml_named_field("PRQA", 8));
1041 aml_append(field, aml_named_field("PRQB", 8));
1042 aml_append(field, aml_named_field("PRQC", 8));
1043 aml_append(field, aml_named_field("PRQD", 8));
1044 aml_append(field, aml_reserved_field(0x20));
1045 aml_append(field, aml_named_field("PRQE", 8));
1046 aml_append(field, aml_named_field("PRQF", 8));
1047 aml_append(field, aml_named_field("PRQG", 8));
1048 aml_append(field, aml_named_field("PRQH", 8));
1049 aml_append(sb_scope, field);
1050
1051 aml_append(sb_scope, build_irq_status_method());
1052 aml_append(sb_scope, build_iqcr_method(false));
1053
1054 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1055 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1056 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1057 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1058 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1059 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1060 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1061 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1062
1063 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1064 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1065 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1066 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1067 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1068 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1069 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1070 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1071
1072 aml_append(table, sb_scope);
1073 }
1074
1075 static void build_q35_isa_bridge(Aml *table)
1076 {
1077 Aml *dev;
1078 Aml *scope;
1079
1080 scope = aml_scope("_SB.PCI0");
1081 dev = aml_device("ISA");
1082 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1083
1084 /* ICH9 PCI to ISA irq remapping */
1085 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1086 aml_int(0x60), 0x0C));
1087
1088 aml_append(scope, dev);
1089 aml_append(table, scope);
1090 }
1091
1092 static void build_piix4_isa_bridge(Aml *table)
1093 {
1094 Aml *dev;
1095 Aml *scope;
1096
1097 scope = aml_scope("_SB.PCI0");
1098 dev = aml_device("ISA");
1099 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1100
1101 /* PIIX PCI to ISA irq remapping */
1102 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1103 aml_int(0x60), 0x04));
1104
1105 aml_append(scope, dev);
1106 aml_append(table, scope);
1107 }
1108
1109 static void build_piix4_pci_hotplug(Aml *table)
1110 {
1111 Aml *scope;
1112 Aml *field;
1113 Aml *method;
1114
1115 scope = aml_scope("_SB.PCI0");
1116
1117 aml_append(scope,
1118 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1119 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1120 aml_append(field, aml_named_field("PCIU", 32));
1121 aml_append(field, aml_named_field("PCID", 32));
1122 aml_append(scope, field);
1123
1124 aml_append(scope,
1125 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1126 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1127 aml_append(field, aml_named_field("B0EJ", 32));
1128 aml_append(scope, field);
1129
1130 aml_append(scope,
1131 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1132 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1133 aml_append(field, aml_named_field("BNUM", 32));
1134 aml_append(scope, field);
1135
1136 aml_append(scope, aml_mutex("BLCK", 0));
1137
1138 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1139 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1140 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1141 aml_append(method,
1142 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1143 aml_append(method, aml_release(aml_name("BLCK")));
1144 aml_append(method, aml_return(aml_int(0)));
1145 aml_append(scope, method);
1146
1147 aml_append(table, scope);
1148 }
1149
1150 static Aml *build_q35_osc_method(void)
1151 {
1152 Aml *if_ctx;
1153 Aml *if_ctx2;
1154 Aml *else_ctx;
1155 Aml *method;
1156 Aml *a_cwd1 = aml_name("CDW1");
1157 Aml *a_ctrl = aml_local(0);
1158
1159 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1160 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1161
1162 if_ctx = aml_if(aml_equal(
1163 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1164 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1165 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1166
1167 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1168
1169 /*
1170 * Always allow native PME, AER (no dependencies)
1171 * Allow SHPC (PCI bridges can have SHPC controller)
1172 */
1173 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
1174
1175 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1176 /* Unknown revision */
1177 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1178 aml_append(if_ctx, if_ctx2);
1179
1180 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1181 /* Capabilities bits were masked */
1182 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1183 aml_append(if_ctx, if_ctx2);
1184
1185 /* Update DWORD3 in the buffer */
1186 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1187 aml_append(method, if_ctx);
1188
1189 else_ctx = aml_else();
1190 /* Unrecognized UUID */
1191 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1192 aml_append(method, else_ctx);
1193
1194 aml_append(method, aml_return(aml_arg(3)));
1195 return method;
1196 }
1197
1198 static void build_smb0(Aml *table, I2CBus *smbus, int devnr, int func)
1199 {
1200 Aml *scope = aml_scope("_SB.PCI0");
1201 Aml *dev = aml_device("SMB0");
1202
1203 aml_append(dev, aml_name_decl("_ADR", aml_int(devnr << 16 | func)));
1204 build_acpi_ipmi_devices(dev, BUS(smbus), "\\_SB.PCI0.SMB0");
1205 aml_append(scope, dev);
1206 aml_append(table, scope);
1207 }
1208
1209 static void
1210 build_dsdt(GArray *table_data, BIOSLinker *linker,
1211 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1212 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1213 {
1214 CrsRangeEntry *entry;
1215 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1216 CrsRangeSet crs_range_set;
1217 PCMachineState *pcms = PC_MACHINE(machine);
1218 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1219 X86MachineState *x86ms = X86_MACHINE(machine);
1220 AcpiMcfgInfo mcfg;
1221 uint32_t nr_mem = machine->ram_slots;
1222 int root_bus_limit = 0xFF;
1223 PCIBus *bus = NULL;
1224 TPMIf *tpm = tpm_find();
1225 int i;
1226 VMBusBridge *vmbus_bridge = vmbus_bridge_find();
1227
1228 dsdt = init_aml_allocator();
1229
1230 /* Reserve space for header */
1231 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1232
1233 build_dbg_aml(dsdt);
1234 if (misc->is_piix4) {
1235 sb_scope = aml_scope("_SB");
1236 dev = aml_device("PCI0");
1237 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1238 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1239 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1240 aml_append(sb_scope, dev);
1241 aml_append(dsdt, sb_scope);
1242
1243 build_hpet_aml(dsdt);
1244 build_piix4_isa_bridge(dsdt);
1245 build_isa_devices_aml(dsdt);
1246 if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
1247 build_piix4_pci_hotplug(dsdt);
1248 }
1249 build_piix4_pci0_int(dsdt);
1250 } else {
1251 sb_scope = aml_scope("_SB");
1252 dev = aml_device("PCI0");
1253 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1254 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1255 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1256 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
1257 aml_append(dev, build_q35_osc_method());
1258 aml_append(sb_scope, dev);
1259
1260 if (pm->smi_on_cpuhp) {
1261 /* reserve SMI block resources, IO ports 0xB2, 0xB3 */
1262 dev = aml_device("PCI0.SMI0");
1263 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
1264 aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources")));
1265 crs = aml_resource_template();
1266 aml_append(crs,
1267 aml_io(
1268 AML_DECODE16,
1269 ACPI_PORT_SMI_CMD,
1270 ACPI_PORT_SMI_CMD,
1271 1,
1272 2)
1273 );
1274 aml_append(dev, aml_name_decl("_CRS", crs));
1275 aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO,
1276 aml_int(ACPI_PORT_SMI_CMD), 2));
1277 field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK,
1278 AML_WRITE_AS_ZEROS);
1279 aml_append(field, aml_named_field("SMIC", 8));
1280 aml_append(field, aml_reserved_field(8));
1281 aml_append(dev, field);
1282 aml_append(sb_scope, dev);
1283 }
1284
1285 aml_append(dsdt, sb_scope);
1286
1287 build_hpet_aml(dsdt);
1288 build_q35_isa_bridge(dsdt);
1289 build_isa_devices_aml(dsdt);
1290 build_q35_pci0_int(dsdt);
1291 if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
1292 build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
1293 }
1294 }
1295
1296 if (vmbus_bridge) {
1297 sb_scope = aml_scope("_SB");
1298 aml_append(sb_scope, build_vmbus_device_aml(vmbus_bridge));
1299 aml_append(dsdt, sb_scope);
1300 }
1301
1302 if (pcmc->legacy_cpu_hotplug) {
1303 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1304 } else {
1305 CPUHotplugFeatures opts = {
1306 .acpi_1_compatible = true, .has_legacy_cphp = true,
1307 .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL,
1308 .fw_unplugs_cpu = pm->smi_on_cpu_unplug,
1309 };
1310 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1311 "\\_SB.PCI0", "\\_GPE._E02");
1312 }
1313
1314 if (pcms->memhp_io_base && nr_mem) {
1315 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0",
1316 "\\_GPE._E03", AML_SYSTEM_IO,
1317 pcms->memhp_io_base);
1318 }
1319
1320 scope = aml_scope("_GPE");
1321 {
1322 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1323
1324 if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1325 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1326 aml_append(method,
1327 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1328 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1329 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1330 aml_append(scope, method);
1331 }
1332
1333 if (machine->nvdimms_state->is_enabled) {
1334 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1335 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1336 aml_int(0x80)));
1337 aml_append(scope, method);
1338 }
1339 }
1340 aml_append(dsdt, scope);
1341
1342 crs_range_set_init(&crs_range_set);
1343 bus = PC_MACHINE(machine)->bus;
1344 if (bus) {
1345 QLIST_FOREACH(bus, &bus->child, sibling) {
1346 uint8_t bus_num = pci_bus_num(bus);
1347 uint8_t numa_node = pci_bus_numa_node(bus);
1348
1349 /* look only for expander root buses */
1350 if (!pci_bus_is_root(bus)) {
1351 continue;
1352 }
1353
1354 if (bus_num < root_bus_limit) {
1355 root_bus_limit = bus_num - 1;
1356 }
1357
1358 scope = aml_scope("\\_SB");
1359 dev = aml_device("PC%.02X", bus_num);
1360 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1361 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1362 if (pci_bus_is_express(bus)) {
1363 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1364 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1365 aml_append(dev, build_q35_osc_method());
1366 } else {
1367 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1368 }
1369
1370 if (numa_node != NUMA_NODE_UNASSIGNED) {
1371 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1372 }
1373
1374 aml_append(dev, build_prt(false));
1375 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
1376 0, 0, 0, 0);
1377 aml_append(dev, aml_name_decl("_CRS", crs));
1378 aml_append(scope, dev);
1379 aml_append(dsdt, scope);
1380 }
1381 }
1382
1383 /*
1384 * At this point crs_range_set has all the ranges used by pci
1385 * busses *other* than PCI0. These ranges will be excluded from
1386 * the PCI0._CRS. Add mmconfig to the set so it will be excluded
1387 * too.
1388 */
1389 if (acpi_get_mcfg(&mcfg)) {
1390 crs_range_insert(crs_range_set.mem_ranges,
1391 mcfg.base, mcfg.base + mcfg.size - 1);
1392 }
1393
1394 scope = aml_scope("\\_SB.PCI0");
1395 /* build PCI0._CRS */
1396 crs = aml_resource_template();
1397 aml_append(crs,
1398 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1399 0x0000, 0x0, root_bus_limit,
1400 0x0000, root_bus_limit + 1));
1401 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1402
1403 aml_append(crs,
1404 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1405 AML_POS_DECODE, AML_ENTIRE_RANGE,
1406 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1407
1408 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1409 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1410 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1411 aml_append(crs,
1412 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1413 AML_POS_DECODE, AML_ENTIRE_RANGE,
1414 0x0000, entry->base, entry->limit,
1415 0x0000, entry->limit - entry->base + 1));
1416 }
1417
1418 aml_append(crs,
1419 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1420 AML_CACHEABLE, AML_READ_WRITE,
1421 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1422
1423 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
1424 range_lob(pci_hole),
1425 range_upb(pci_hole));
1426 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
1427 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
1428 aml_append(crs,
1429 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1430 AML_NON_CACHEABLE, AML_READ_WRITE,
1431 0, entry->base, entry->limit,
1432 0, entry->limit - entry->base + 1));
1433 }
1434
1435 if (!range_is_empty(pci_hole64)) {
1436 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
1437 range_lob(pci_hole64),
1438 range_upb(pci_hole64));
1439 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
1440 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
1441 aml_append(crs,
1442 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1443 AML_MAX_FIXED,
1444 AML_CACHEABLE, AML_READ_WRITE,
1445 0, entry->base, entry->limit,
1446 0, entry->limit - entry->base + 1));
1447 }
1448 }
1449
1450 if (TPM_IS_TIS_ISA(tpm_find())) {
1451 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1452 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1453 }
1454 aml_append(scope, aml_name_decl("_CRS", crs));
1455
1456 /* reserve GPE0 block resources */
1457 dev = aml_device("GPE0");
1458 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1459 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1460 /* device present, functioning, decoding, not shown in UI */
1461 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1462 crs = aml_resource_template();
1463 aml_append(crs,
1464 aml_io(
1465 AML_DECODE16,
1466 pm->fadt.gpe0_blk.address,
1467 pm->fadt.gpe0_blk.address,
1468 1,
1469 pm->fadt.gpe0_blk.bit_width / 8)
1470 );
1471 aml_append(dev, aml_name_decl("_CRS", crs));
1472 aml_append(scope, dev);
1473
1474 crs_range_set_free(&crs_range_set);
1475
1476 /* reserve PCIHP resources */
1477 if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) {
1478 dev = aml_device("PHPR");
1479 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1480 aml_append(dev,
1481 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1482 /* device present, functioning, decoding, not shown in UI */
1483 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1484 crs = aml_resource_template();
1485 aml_append(crs,
1486 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
1487 pm->pcihp_io_len)
1488 );
1489 aml_append(dev, aml_name_decl("_CRS", crs));
1490 aml_append(scope, dev);
1491 }
1492 aml_append(dsdt, scope);
1493
1494 /* create S3_ / S4_ / S5_ packages if necessary */
1495 scope = aml_scope("\\");
1496 if (!pm->s3_disabled) {
1497 pkg = aml_package(4);
1498 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
1499 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1500 aml_append(pkg, aml_int(0)); /* reserved */
1501 aml_append(pkg, aml_int(0)); /* reserved */
1502 aml_append(scope, aml_name_decl("_S3", pkg));
1503 }
1504
1505 if (!pm->s4_disabled) {
1506 pkg = aml_package(4);
1507 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
1508 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
1509 aml_append(pkg, aml_int(pm->s4_val));
1510 aml_append(pkg, aml_int(0)); /* reserved */
1511 aml_append(pkg, aml_int(0)); /* reserved */
1512 aml_append(scope, aml_name_decl("_S4", pkg));
1513 }
1514
1515 pkg = aml_package(4);
1516 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
1517 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
1518 aml_append(pkg, aml_int(0)); /* reserved */
1519 aml_append(pkg, aml_int(0)); /* reserved */
1520 aml_append(scope, aml_name_decl("_S5", pkg));
1521 aml_append(dsdt, scope);
1522
1523 /* create fw_cfg node, unconditionally */
1524 {
1525 scope = aml_scope("\\_SB.PCI0");
1526 fw_cfg_add_acpi_dsdt(scope, x86ms->fw_cfg);
1527 aml_append(dsdt, scope);
1528 }
1529
1530 if (misc->applesmc_io_base) {
1531 scope = aml_scope("\\_SB.PCI0.ISA");
1532 dev = aml_device("SMC");
1533
1534 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
1535 /* device present, functioning, decoding, not shown in UI */
1536 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1537
1538 crs = aml_resource_template();
1539 aml_append(crs,
1540 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
1541 0x01, APPLESMC_MAX_DATA_LENGTH)
1542 );
1543 aml_append(crs, aml_irq_no_flags(6));
1544 aml_append(dev, aml_name_decl("_CRS", crs));
1545
1546 aml_append(scope, dev);
1547 aml_append(dsdt, scope);
1548 }
1549
1550 if (misc->pvpanic_port) {
1551 scope = aml_scope("\\_SB.PCI0.ISA");
1552
1553 dev = aml_device("PEVT");
1554 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
1555
1556 crs = aml_resource_template();
1557 aml_append(crs,
1558 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
1559 );
1560 aml_append(dev, aml_name_decl("_CRS", crs));
1561
1562 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
1563 aml_int(misc->pvpanic_port), 1));
1564 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1565 aml_append(field, aml_named_field("PEPT", 8));
1566 aml_append(dev, field);
1567
1568 /* device present, functioning, decoding, shown in UI */
1569 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1570
1571 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
1572 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
1573 aml_append(method, aml_return(aml_local(0)));
1574 aml_append(dev, method);
1575
1576 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
1577 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
1578 aml_append(dev, method);
1579
1580 aml_append(scope, dev);
1581 aml_append(dsdt, scope);
1582 }
1583
1584 sb_scope = aml_scope("\\_SB");
1585 {
1586 Object *pci_host;
1587 PCIBus *bus = NULL;
1588
1589 pci_host = acpi_get_i386_pci_host();
1590 if (pci_host) {
1591 bus = PCI_HOST_BRIDGE(pci_host)->bus;
1592 }
1593
1594 if (bus) {
1595 Aml *scope = aml_scope("PCI0");
1596 /* Scan all PCI buses. Generate tables to support hotplug. */
1597 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
1598
1599 if (TPM_IS_TIS_ISA(tpm)) {
1600 if (misc->tpm_version == TPM_VERSION_2_0) {
1601 dev = aml_device("TPM");
1602 aml_append(dev, aml_name_decl("_HID",
1603 aml_string("MSFT0101")));
1604 } else {
1605 dev = aml_device("ISA.TPM");
1606 aml_append(dev, aml_name_decl("_HID",
1607 aml_eisaid("PNP0C31")));
1608 }
1609
1610 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
1611 crs = aml_resource_template();
1612 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
1613 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
1614 /*
1615 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
1616 Rewrite to take IRQ from TPM device model and
1617 fix default IRQ value there to use some unused IRQ
1618 */
1619 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
1620 aml_append(dev, aml_name_decl("_CRS", crs));
1621
1622 tpm_build_ppi_acpi(tpm, dev);
1623
1624 aml_append(scope, dev);
1625 }
1626
1627 aml_append(sb_scope, scope);
1628 }
1629 }
1630
1631 if (TPM_IS_CRB(tpm)) {
1632 dev = aml_device("TPM");
1633 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
1634 crs = aml_resource_template();
1635 aml_append(crs, aml_memory32_fixed(TPM_CRB_ADDR_BASE,
1636 TPM_CRB_ADDR_SIZE, AML_READ_WRITE));
1637 aml_append(dev, aml_name_decl("_CRS", crs));
1638
1639 aml_append(dev, aml_name_decl("_STA", aml_int(0xf)));
1640
1641 tpm_build_ppi_acpi(tpm, dev);
1642
1643 aml_append(sb_scope, dev);
1644 }
1645
1646 aml_append(dsdt, sb_scope);
1647
1648 /* copy AML table into ACPI tables blob and patch header there */
1649 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
1650 build_header(linker, table_data,
1651 (void *)(table_data->data + table_data->len - dsdt->buf->len),
1652 "DSDT", dsdt->buf->len, 1, pcms->oem_id, pcms->oem_table_id);
1653 free_aml_allocator();
1654 }
1655
1656 static void
1657 build_hpet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1658 const char *oem_table_id)
1659 {
1660 Acpi20Hpet *hpet;
1661
1662 hpet = acpi_data_push(table_data, sizeof(*hpet));
1663 /* Note timer_block_id value must be kept in sync with value advertised by
1664 * emulated hpet
1665 */
1666 hpet->timer_block_id = cpu_to_le32(0x8086a201);
1667 hpet->addr.address = cpu_to_le64(HPET_BASE);
1668 build_header(linker, table_data,
1669 (void *)hpet, "HPET", sizeof(*hpet), 1, oem_id, oem_table_id);
1670 }
1671
1672 static void
1673 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog,
1674 const char *oem_id, const char *oem_table_id)
1675 {
1676 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
1677 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
1678 unsigned log_addr_offset =
1679 (char *)&tcpa->log_area_start_address - table_data->data;
1680
1681 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
1682 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
1683 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
1684
1685 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
1686 false /* high memory */);
1687
1688 /* log area start address to be filled by Guest linker */
1689 bios_linker_loader_add_pointer(linker,
1690 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
1691 ACPI_BUILD_TPMLOG_FILE, 0);
1692
1693 build_header(linker, table_data,
1694 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, oem_id, oem_table_id);
1695 }
1696
1697 #define HOLE_640K_START (640 * KiB)
1698 #define HOLE_640K_END (1 * MiB)
1699
1700 static void
1701 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
1702 {
1703 AcpiSystemResourceAffinityTable *srat;
1704 AcpiSratMemoryAffinity *numamem;
1705
1706 int i;
1707 int srat_start, numa_start, slots;
1708 uint64_t mem_len, mem_base, next_base;
1709 MachineClass *mc = MACHINE_GET_CLASS(machine);
1710 X86MachineState *x86ms = X86_MACHINE(machine);
1711 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
1712 PCMachineState *pcms = PC_MACHINE(machine);
1713 ram_addr_t hotplugabble_address_space_size =
1714 object_property_get_int(OBJECT(pcms), PC_MACHINE_DEVMEM_REGION_SIZE,
1715 NULL);
1716
1717 srat_start = table_data->len;
1718
1719 srat = acpi_data_push(table_data, sizeof *srat);
1720 srat->reserved1 = cpu_to_le32(1);
1721
1722 for (i = 0; i < apic_ids->len; i++) {
1723 int node_id = apic_ids->cpus[i].props.node_id;
1724 uint32_t apic_id = apic_ids->cpus[i].arch_id;
1725
1726 if (apic_id < 255) {
1727 AcpiSratProcessorAffinity *core;
1728
1729 core = acpi_data_push(table_data, sizeof *core);
1730 core->type = ACPI_SRAT_PROCESSOR_APIC;
1731 core->length = sizeof(*core);
1732 core->local_apic_id = apic_id;
1733 core->proximity_lo = node_id;
1734 memset(core->proximity_hi, 0, 3);
1735 core->local_sapic_eid = 0;
1736 core->flags = cpu_to_le32(1);
1737 } else {
1738 AcpiSratProcessorX2ApicAffinity *core;
1739
1740 core = acpi_data_push(table_data, sizeof *core);
1741 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
1742 core->length = sizeof(*core);
1743 core->x2apic_id = cpu_to_le32(apic_id);
1744 core->proximity_domain = cpu_to_le32(node_id);
1745 core->flags = cpu_to_le32(1);
1746 }
1747 }
1748
1749
1750 /* the memory map is a bit tricky, it contains at least one hole
1751 * from 640k-1M and possibly another one from 3.5G-4G.
1752 */
1753 next_base = 0;
1754 numa_start = table_data->len;
1755
1756 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
1757 mem_base = next_base;
1758 mem_len = pcms->node_mem[i - 1];
1759 next_base = mem_base + mem_len;
1760
1761 /* Cut out the 640K hole */
1762 if (mem_base <= HOLE_640K_START &&
1763 next_base > HOLE_640K_START) {
1764 mem_len -= next_base - HOLE_640K_START;
1765 if (mem_len > 0) {
1766 numamem = acpi_data_push(table_data, sizeof *numamem);
1767 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1768 MEM_AFFINITY_ENABLED);
1769 }
1770
1771 /* Check for the rare case: 640K < RAM < 1M */
1772 if (next_base <= HOLE_640K_END) {
1773 next_base = HOLE_640K_END;
1774 continue;
1775 }
1776 mem_base = HOLE_640K_END;
1777 mem_len = next_base - HOLE_640K_END;
1778 }
1779
1780 /* Cut out the ACPI_PCI hole */
1781 if (mem_base <= x86ms->below_4g_mem_size &&
1782 next_base > x86ms->below_4g_mem_size) {
1783 mem_len -= next_base - x86ms->below_4g_mem_size;
1784 if (mem_len > 0) {
1785 numamem = acpi_data_push(table_data, sizeof *numamem);
1786 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1787 MEM_AFFINITY_ENABLED);
1788 }
1789 mem_base = 1ULL << 32;
1790 mem_len = next_base - x86ms->below_4g_mem_size;
1791 next_base = mem_base + mem_len;
1792 }
1793
1794 if (mem_len > 0) {
1795 numamem = acpi_data_push(table_data, sizeof *numamem);
1796 build_srat_memory(numamem, mem_base, mem_len, i - 1,
1797 MEM_AFFINITY_ENABLED);
1798 }
1799 }
1800
1801 if (machine->nvdimms_state->is_enabled) {
1802 nvdimm_build_srat(table_data);
1803 }
1804
1805 slots = (table_data->len - numa_start) / sizeof *numamem;
1806 for (; slots < pcms->numa_nodes + 2; slots++) {
1807 numamem = acpi_data_push(table_data, sizeof *numamem);
1808 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
1809 }
1810
1811 /*
1812 * Entry is required for Windows to enable memory hotplug in OS
1813 * and for Linux to enable SWIOTLB when booted with less than
1814 * 4G of RAM. Windows works better if the entry sets proximity
1815 * to the highest NUMA node in the machine.
1816 * Memory devices may override proximity set by this entry,
1817 * providing _PXM method if necessary.
1818 */
1819 if (hotplugabble_address_space_size) {
1820 numamem = acpi_data_push(table_data, sizeof *numamem);
1821 build_srat_memory(numamem, machine->device_memory->base,
1822 hotplugabble_address_space_size, pcms->numa_nodes - 1,
1823 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
1824 }
1825
1826 build_header(linker, table_data,
1827 (void *)(table_data->data + srat_start),
1828 "SRAT",
1829 table_data->len - srat_start, 1, pcms->oem_id,
1830 pcms->oem_table_id);
1831 }
1832
1833 /*
1834 * VT-d spec 8.1 DMA Remapping Reporting Structure
1835 * (version Oct. 2014 or later)
1836 */
1837 static void
1838 build_dmar_q35(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1839 const char *oem_table_id)
1840 {
1841 int dmar_start = table_data->len;
1842
1843 AcpiTableDmar *dmar;
1844 AcpiDmarHardwareUnit *drhd;
1845 AcpiDmarRootPortATS *atsr;
1846 uint8_t dmar_flags = 0;
1847 X86IOMMUState *iommu = x86_iommu_get_default();
1848 AcpiDmarDeviceScope *scope = NULL;
1849 /* Root complex IOAPIC use one path[0] only */
1850 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
1851 IntelIOMMUState *intel_iommu = INTEL_IOMMU_DEVICE(iommu);
1852
1853 assert(iommu);
1854 if (x86_iommu_ir_supported(iommu)) {
1855 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
1856 }
1857
1858 dmar = acpi_data_push(table_data, sizeof(*dmar));
1859 dmar->host_address_width = intel_iommu->aw_bits - 1;
1860 dmar->flags = dmar_flags;
1861
1862 /* DMAR Remapping Hardware Unit Definition structure */
1863 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
1864 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
1865 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
1866 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
1867 drhd->pci_segment = cpu_to_le16(0);
1868 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
1869
1870 /* Scope definition for the root-complex IOAPIC. See VT-d spec
1871 * 8.3.1 (version Oct. 2014 or later). */
1872 scope = &drhd->scope[0];
1873 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
1874 scope->length = ioapic_scope_size;
1875 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
1876 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
1877 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
1878 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
1879
1880 if (iommu->dt_supported) {
1881 atsr = acpi_data_push(table_data, sizeof(*atsr));
1882 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
1883 atsr->length = cpu_to_le16(sizeof(*atsr));
1884 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
1885 atsr->pci_segment = cpu_to_le16(0);
1886 }
1887
1888 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
1889 "DMAR", table_data->len - dmar_start, 1, oem_id, oem_table_id);
1890 }
1891
1892 /*
1893 * Windows ACPI Emulated Devices Table
1894 * (Version 1.0 - April 6, 2009)
1895 * Spec: http://download.microsoft.com/download/7/E/7/7E7662CF-CBEA-470B-A97E-CE7CE0D98DC2/WAET.docx
1896 *
1897 * Helpful to speedup Windows guests and ignored by others.
1898 */
1899 static void
1900 build_waet(GArray *table_data, BIOSLinker *linker, const char *oem_id,
1901 const char *oem_table_id)
1902 {
1903 int waet_start = table_data->len;
1904
1905 /* WAET header */
1906 acpi_data_push(table_data, sizeof(AcpiTableHeader));
1907 /*
1908 * Set "ACPI PM timer good" flag.
1909 *
1910 * Tells Windows guests that our ACPI PM timer is reliable in the
1911 * sense that guest can read it only once to obtain a reliable value.
1912 * Which avoids costly VMExits caused by guest re-reading it unnecessarily.
1913 */
1914 build_append_int_noprefix(table_data, 1 << 1 /* ACPI PM timer good */, 4);
1915
1916 build_header(linker, table_data, (void *)(table_data->data + waet_start),
1917 "WAET", table_data->len - waet_start, 1, oem_id, oem_table_id);
1918 }
1919
1920 /*
1921 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
1922 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
1923 */
1924 #define IOAPIC_SB_DEVID (uint64_t)PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
1925
1926 /*
1927 * Insert IVHD entry for device and recurse, insert alias, or insert range as
1928 * necessary for the PCI topology.
1929 */
1930 static void
1931 insert_ivhd(PCIBus *bus, PCIDevice *dev, void *opaque)
1932 {
1933 GArray *table_data = opaque;
1934 uint32_t entry;
1935
1936 /* "Select" IVHD entry, type 0x2 */
1937 entry = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn) << 8 | 0x2;
1938 build_append_int_noprefix(table_data, entry, 4);
1939
1940 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) {
1941 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev));
1942 uint8_t sec = pci_bus_num(sec_bus);
1943 uint8_t sub = dev->config[PCI_SUBORDINATE_BUS];
1944
1945 if (pci_bus_is_express(sec_bus)) {
1946 /*
1947 * Walk the bus if there are subordinates, otherwise use a range
1948 * to cover an entire leaf bus. We could potentially also use a
1949 * range for traversed buses, but we'd need to take care not to
1950 * create both Select and Range entries covering the same device.
1951 * This is easier and potentially more compact.
1952 *
1953 * An example bare metal system seems to use Select entries for
1954 * root ports without a slot (ie. built-ins) and Range entries
1955 * when there is a slot. The same system also only hard-codes
1956 * the alias range for an onboard PCIe-to-PCI bridge, apparently
1957 * making no effort to support nested bridges. We attempt to
1958 * be more thorough here.
1959 */
1960 if (sec == sub) { /* leaf bus */
1961 /* "Start of Range" IVHD entry, type 0x3 */
1962 entry = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0)) << 8 | 0x3;
1963 build_append_int_noprefix(table_data, entry, 4);
1964 /* "End of Range" IVHD entry, type 0x4 */
1965 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
1966 build_append_int_noprefix(table_data, entry, 4);
1967 } else {
1968 pci_for_each_device(sec_bus, sec, insert_ivhd, table_data);
1969 }
1970 } else {
1971 /*
1972 * If the secondary bus is conventional, then we need to create an
1973 * Alias range for everything downstream. The range covers the
1974 * first devfn on the secondary bus to the last devfn on the
1975 * subordinate bus. The alias target depends on legacy versus
1976 * express bridges, just as in pci_device_iommu_address_space().
1977 * DeviceIDa vs DeviceIDb as per the AMD IOMMU spec.
1978 */
1979 uint16_t dev_id_a, dev_id_b;
1980
1981 dev_id_a = PCI_BUILD_BDF(sec, PCI_DEVFN(0, 0));
1982
1983 if (pci_is_express(dev) &&
1984 pcie_cap_get_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE) {
1985 dev_id_b = dev_id_a;
1986 } else {
1987 dev_id_b = PCI_BUILD_BDF(pci_bus_num(bus), dev->devfn);
1988 }
1989
1990 /* "Alias Start of Range" IVHD entry, type 0x43, 8 bytes */
1991 build_append_int_noprefix(table_data, dev_id_a << 8 | 0x43, 4);
1992 build_append_int_noprefix(table_data, dev_id_b << 8 | 0x0, 4);
1993
1994 /* "End of Range" IVHD entry, type 0x4 */
1995 entry = PCI_BUILD_BDF(sub, PCI_DEVFN(31, 7)) << 8 | 0x4;
1996 build_append_int_noprefix(table_data, entry, 4);
1997 }
1998 }
1999 }
2000
2001 /* For all PCI host bridges, walk and insert IVHD entries */
2002 static int
2003 ivrs_host_bridges(Object *obj, void *opaque)
2004 {
2005 GArray *ivhd_blob = opaque;
2006
2007 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
2008 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
2009
2010 if (bus) {
2011 pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_blob);
2012 }
2013 }
2014
2015 return 0;
2016 }
2017
2018 static void
2019 build_amd_iommu(GArray *table_data, BIOSLinker *linker, const char *oem_id,
2020 const char *oem_table_id)
2021 {
2022 int ivhd_table_len = 24;
2023 int iommu_start = table_data->len;
2024 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2025 GArray *ivhd_blob = g_array_new(false, true, 1);
2026
2027 /* IVRS header */
2028 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2029 /* IVinfo - IO virtualization information common to all
2030 * IOMMU units in a system
2031 */
2032 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2033 /* reserved */
2034 build_append_int_noprefix(table_data, 0, 8);
2035
2036 /* IVHD definition - type 10h */
2037 build_append_int_noprefix(table_data, 0x10, 1);
2038 /* virtualization flags */
2039 build_append_int_noprefix(table_data,
2040 (1UL << 0) | /* HtTunEn */
2041 (1UL << 4) | /* iotblSup */
2042 (1UL << 6) | /* PrefSup */
2043 (1UL << 7), /* PPRSup */
2044 1);
2045
2046 /*
2047 * A PCI bus walk, for each PCI host bridge, is necessary to create a
2048 * complete set of IVHD entries. Do this into a separate blob so that we
2049 * can calculate the total IVRS table length here and then append the new
2050 * blob further below. Fall back to an entry covering all devices, which
2051 * is sufficient when no aliases are present.
2052 */
2053 object_child_foreach_recursive(object_get_root(),
2054 ivrs_host_bridges, ivhd_blob);
2055
2056 if (!ivhd_blob->len) {
2057 /*
2058 * Type 1 device entry reporting all devices
2059 * These are 4-byte device entries currently reporting the range of
2060 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2061 */
2062 build_append_int_noprefix(ivhd_blob, 0x0000001, 4);
2063 }
2064
2065 ivhd_table_len += ivhd_blob->len;
2066
2067 /*
2068 * When interrupt remapping is supported, we add a special IVHD device
2069 * for type IO-APIC.
2070 */
2071 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2072 ivhd_table_len += 8;
2073 }
2074
2075 /* IVHD length */
2076 build_append_int_noprefix(table_data, ivhd_table_len, 2);
2077 /* DeviceID */
2078 build_append_int_noprefix(table_data, s->devid, 2);
2079 /* Capability offset */
2080 build_append_int_noprefix(table_data, s->capab_offset, 2);
2081 /* IOMMU base address */
2082 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2083 /* PCI Segment Group */
2084 build_append_int_noprefix(table_data, 0, 2);
2085 /* IOMMU info */
2086 build_append_int_noprefix(table_data, 0, 2);
2087 /* IOMMU Feature Reporting */
2088 build_append_int_noprefix(table_data,
2089 (48UL << 30) | /* HATS */
2090 (48UL << 28) | /* GATS */
2091 (1UL << 2) | /* GTSup */
2092 (1UL << 6), /* GASup */
2093 4);
2094
2095 /* IVHD entries as found above */
2096 g_array_append_vals(table_data, ivhd_blob->data, ivhd_blob->len);
2097 g_array_free(ivhd_blob, TRUE);
2098
2099 /*
2100 * Add a special IVHD device type.
2101 * Refer to spec - Table 95: IVHD device entry type codes
2102 *
2103 * Linux IOMMU driver checks for the special IVHD device (type IO-APIC).
2104 * See Linux kernel commit 'c2ff5cf5294bcbd7fa50f7d860e90a66db7e5059'
2105 */
2106 if (x86_iommu_ir_supported(x86_iommu_get_default())) {
2107 build_append_int_noprefix(table_data,
2108 (0x1ull << 56) | /* type IOAPIC */
2109 (IOAPIC_SB_DEVID << 40) | /* IOAPIC devid */
2110 0x48, /* special device */
2111 8);
2112 }
2113
2114 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2115 "IVRS", table_data->len - iommu_start, 1, oem_id,
2116 oem_table_id);
2117 }
2118
2119 typedef
2120 struct AcpiBuildState {
2121 /* Copy of table in RAM (for patching). */
2122 MemoryRegion *table_mr;
2123 /* Is table patched? */
2124 uint8_t patched;
2125 void *rsdp;
2126 MemoryRegion *rsdp_mr;
2127 MemoryRegion *linker_mr;
2128 } AcpiBuildState;
2129
2130 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2131 {
2132 Object *pci_host;
2133 QObject *o;
2134
2135 pci_host = acpi_get_i386_pci_host();
2136 g_assert(pci_host);
2137
2138 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2139 if (!o) {
2140 return false;
2141 }
2142 mcfg->base = qnum_get_uint(qobject_to(QNum, o));
2143 qobject_unref(o);
2144 if (mcfg->base == PCIE_BASE_ADDR_UNMAPPED) {
2145 return false;
2146 }
2147
2148 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2149 assert(o);
2150 mcfg->size = qnum_get_uint(qobject_to(QNum, o));
2151 qobject_unref(o);
2152 return true;
2153 }
2154
2155 static
2156 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2157 {
2158 PCMachineState *pcms = PC_MACHINE(machine);
2159 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2160 X86MachineState *x86ms = X86_MACHINE(machine);
2161 GArray *table_offsets;
2162 unsigned facs, dsdt, rsdt, fadt;
2163 AcpiPmInfo pm;
2164 AcpiMiscInfo misc;
2165 AcpiMcfgInfo mcfg;
2166 Range pci_hole, pci_hole64;
2167 uint8_t *u;
2168 size_t aml_len = 0;
2169 GArray *tables_blob = tables->table_data;
2170 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2171 Object *vmgenid_dev;
2172 char *oem_id;
2173 char *oem_table_id;
2174
2175 acpi_get_pm_info(machine, &pm);
2176 acpi_get_misc_info(&misc);
2177 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2178 acpi_get_slic_oem(&slic_oem);
2179
2180 if (slic_oem.id) {
2181 oem_id = slic_oem.id;
2182 } else {
2183 oem_id = pcms->oem_id;
2184 }
2185
2186 if (slic_oem.table_id) {
2187 oem_table_id = slic_oem.table_id;
2188 } else {
2189 oem_table_id = pcms->oem_table_id;
2190 }
2191
2192 table_offsets = g_array_new(false, true /* clear */,
2193 sizeof(uint32_t));
2194 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2195
2196 bios_linker_loader_alloc(tables->linker,
2197 ACPI_BUILD_TABLE_FILE, tables_blob,
2198 64 /* Ensure FACS is aligned */,
2199 false /* high memory */);
2200
2201 /*
2202 * FACS is pointed to by FADT.
2203 * We place it first since it's the only table that has alignment
2204 * requirements.
2205 */
2206 facs = tables_blob->len;
2207 build_facs(tables_blob);
2208
2209 /* DSDT is pointed to by FADT */
2210 dsdt = tables_blob->len;
2211 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2212 &pci_hole, &pci_hole64, machine);
2213
2214 /* Count the size of the DSDT and SSDT, we will need it for legacy
2215 * sizing of ACPI tables.
2216 */
2217 aml_len += tables_blob->len - dsdt;
2218
2219 /* ACPI tables pointed to by RSDT */
2220 fadt = tables_blob->len;
2221 acpi_add_table(table_offsets, tables_blob);
2222 pm.fadt.facs_tbl_offset = &facs;
2223 pm.fadt.dsdt_tbl_offset = &dsdt;
2224 pm.fadt.xdsdt_tbl_offset = &dsdt;
2225 build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id);
2226 aml_len += tables_blob->len - fadt;
2227
2228 acpi_add_table(table_offsets, tables_blob);
2229 acpi_build_madt(tables_blob, tables->linker, x86ms,
2230 ACPI_DEVICE_IF(x86ms->acpi_dev), pcms->oem_id,
2231 pcms->oem_table_id);
2232
2233 vmgenid_dev = find_vmgenid_dev();
2234 if (vmgenid_dev) {
2235 acpi_add_table(table_offsets, tables_blob);
2236 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2237 tables->vmgenid, tables->linker, pcms->oem_id);
2238 }
2239
2240 if (misc.has_hpet) {
2241 acpi_add_table(table_offsets, tables_blob);
2242 build_hpet(tables_blob, tables->linker, pcms->oem_id,
2243 pcms->oem_table_id);
2244 }
2245 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2246 if (misc.tpm_version == TPM_VERSION_1_2) {
2247 acpi_add_table(table_offsets, tables_blob);
2248 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog,
2249 pcms->oem_id, pcms->oem_table_id);
2250 } else { /* TPM_VERSION_2_0 */
2251 acpi_add_table(table_offsets, tables_blob);
2252 build_tpm2(tables_blob, tables->linker, tables->tcpalog,
2253 pcms->oem_id, pcms->oem_table_id);
2254 }
2255 }
2256 if (pcms->numa_nodes) {
2257 acpi_add_table(table_offsets, tables_blob);
2258 build_srat(tables_blob, tables->linker, machine);
2259 if (machine->numa_state->have_numa_distance) {
2260 acpi_add_table(table_offsets, tables_blob);
2261 build_slit(tables_blob, tables->linker, machine, pcms->oem_id,
2262 pcms->oem_table_id);
2263 }
2264 if (machine->numa_state->hmat_enabled) {
2265 acpi_add_table(table_offsets, tables_blob);
2266 build_hmat(tables_blob, tables->linker, machine->numa_state,
2267 pcms->oem_id, pcms->oem_table_id);
2268 }
2269 }
2270 if (acpi_get_mcfg(&mcfg)) {
2271 acpi_add_table(table_offsets, tables_blob);
2272 build_mcfg(tables_blob, tables->linker, &mcfg, pcms->oem_id,
2273 pcms->oem_table_id);
2274 }
2275 if (x86_iommu_get_default()) {
2276 IommuType IOMMUType = x86_iommu_get_type();
2277 if (IOMMUType == TYPE_AMD) {
2278 acpi_add_table(table_offsets, tables_blob);
2279 build_amd_iommu(tables_blob, tables->linker, pcms->oem_id,
2280 pcms->oem_table_id);
2281 } else if (IOMMUType == TYPE_INTEL) {
2282 acpi_add_table(table_offsets, tables_blob);
2283 build_dmar_q35(tables_blob, tables->linker, pcms->oem_id,
2284 pcms->oem_table_id);
2285 }
2286 }
2287 if (machine->nvdimms_state->is_enabled) {
2288 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2289 machine->nvdimms_state, machine->ram_slots,
2290 pcms->oem_id, pcms->oem_table_id);
2291 }
2292
2293 acpi_add_table(table_offsets, tables_blob);
2294 build_waet(tables_blob, tables->linker, pcms->oem_id, pcms->oem_table_id);
2295
2296 /* Add tables supplied by user (if any) */
2297 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2298 unsigned len = acpi_table_len(u);
2299
2300 acpi_add_table(table_offsets, tables_blob);
2301 g_array_append_vals(tables_blob, u, len);
2302 }
2303
2304 /* RSDT is pointed to by RSDP */
2305 rsdt = tables_blob->len;
2306 build_rsdt(tables_blob, tables->linker, table_offsets,
2307 oem_id, oem_table_id);
2308
2309 /* RSDP is in FSEG memory, so allocate it separately */
2310 {
2311 AcpiRsdpData rsdp_data = {
2312 .revision = 0,
2313 .oem_id = pcms->oem_id,
2314 .xsdt_tbl_offset = NULL,
2315 .rsdt_tbl_offset = &rsdt,
2316 };
2317 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
2318 if (!pcmc->rsdp_in_ram) {
2319 /* We used to allocate some extra space for RSDP revision 2 but
2320 * only used the RSDP revision 0 space. The extra bytes were
2321 * zeroed out and not used.
2322 * Here we continue wasting those extra 16 bytes to make sure we
2323 * don't break migration for machine types 2.2 and older due to
2324 * RSDP blob size mismatch.
2325 */
2326 build_append_int_noprefix(tables->rsdp, 0, 16);
2327 }
2328 }
2329
2330 /* We'll expose it all to Guest so we want to reduce
2331 * chance of size changes.
2332 *
2333 * We used to align the tables to 4k, but of course this would
2334 * too simple to be enough. 4k turned out to be too small an
2335 * alignment very soon, and in fact it is almost impossible to
2336 * keep the table size stable for all (max_cpus, max_memory_slots)
2337 * combinations. So the table size is always 64k for pc-i440fx-2.1
2338 * and we give an error if the table grows beyond that limit.
2339 *
2340 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2341 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2342 * than 2.0 and we can always pad the smaller tables with zeros. We can
2343 * then use the exact size of the 2.0 tables.
2344 *
2345 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2346 */
2347 if (pcmc->legacy_acpi_table_size) {
2348 /* Subtracting aml_len gives the size of fixed tables. Then add the
2349 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2350 */
2351 int legacy_aml_len =
2352 pcmc->legacy_acpi_table_size +
2353 ACPI_BUILD_LEGACY_CPU_AML_SIZE * x86ms->apic_id_limit;
2354 int legacy_table_size =
2355 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2356 ACPI_BUILD_ALIGN_SIZE);
2357 if (tables_blob->len > legacy_table_size) {
2358 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2359 warn_report("ACPI table size %u exceeds %d bytes,"
2360 " migration may not work",
2361 tables_blob->len, legacy_table_size);
2362 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2363 " or PCI bridges.");
2364 }
2365 g_array_set_size(tables_blob, legacy_table_size);
2366 } else {
2367 /* Make sure we have a buffer in case we need to resize the tables. */
2368 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2369 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2370 warn_report("ACPI table size %u exceeds %d bytes,"
2371 " migration may not work",
2372 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
2373 error_printf("Try removing CPUs, NUMA nodes, memory slots"
2374 " or PCI bridges.");
2375 }
2376 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2377 }
2378
2379 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2380
2381 /* Cleanup memory that's no longer used. */
2382 g_array_free(table_offsets, true);
2383 }
2384
2385 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2386 {
2387 uint32_t size = acpi_data_len(data);
2388
2389 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2390 memory_region_ram_resize(mr, size, &error_abort);
2391
2392 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2393 memory_region_set_dirty(mr, 0, size);
2394 }
2395
2396 static void acpi_build_update(void *build_opaque)
2397 {
2398 AcpiBuildState *build_state = build_opaque;
2399 AcpiBuildTables tables;
2400
2401 /* No state to update or already patched? Nothing to do. */
2402 if (!build_state || build_state->patched) {
2403 return;
2404 }
2405 build_state->patched = 1;
2406
2407 acpi_build_tables_init(&tables);
2408
2409 acpi_build(&tables, MACHINE(qdev_get_machine()));
2410
2411 acpi_ram_update(build_state->table_mr, tables.table_data);
2412
2413 if (build_state->rsdp) {
2414 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2415 } else {
2416 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2417 }
2418
2419 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2420 acpi_build_tables_cleanup(&tables, true);
2421 }
2422
2423 static void acpi_build_reset(void *build_opaque)
2424 {
2425 AcpiBuildState *build_state = build_opaque;
2426 build_state->patched = 0;
2427 }
2428
2429 static const VMStateDescription vmstate_acpi_build = {
2430 .name = "acpi_build",
2431 .version_id = 1,
2432 .minimum_version_id = 1,
2433 .fields = (VMStateField[]) {
2434 VMSTATE_UINT8(patched, AcpiBuildState),
2435 VMSTATE_END_OF_LIST()
2436 },
2437 };
2438
2439 void acpi_setup(void)
2440 {
2441 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2442 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2443 X86MachineState *x86ms = X86_MACHINE(pcms);
2444 AcpiBuildTables tables;
2445 AcpiBuildState *build_state;
2446 Object *vmgenid_dev;
2447 TPMIf *tpm;
2448 static FwCfgTPMConfig tpm_config;
2449
2450 if (!x86ms->fw_cfg) {
2451 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2452 return;
2453 }
2454
2455 if (!pcms->acpi_build_enabled) {
2456 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2457 return;
2458 }
2459
2460 if (!x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
2461 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2462 return;
2463 }
2464
2465 build_state = g_malloc0(sizeof *build_state);
2466
2467 acpi_build_tables_init(&tables);
2468 acpi_build(&tables, MACHINE(pcms));
2469
2470 /* Now expose it all to Guest */
2471 build_state->table_mr = acpi_add_rom_blob(acpi_build_update,
2472 build_state, tables.table_data,
2473 ACPI_BUILD_TABLE_FILE,
2474 ACPI_BUILD_TABLE_MAX_SIZE);
2475 assert(build_state->table_mr != NULL);
2476
2477 build_state->linker_mr =
2478 acpi_add_rom_blob(acpi_build_update, build_state,
2479 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE, 0);
2480
2481 fw_cfg_add_file(x86ms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2482 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2483
2484 tpm = tpm_find();
2485 if (tpm && object_property_get_bool(OBJECT(tpm), "ppi", &error_abort)) {
2486 tpm_config = (FwCfgTPMConfig) {
2487 .tpmppi_address = cpu_to_le32(TPM_PPI_ADDR_BASE),
2488 .tpm_version = tpm_get_version(tpm),
2489 .tpmppi_version = TPM_PPI_VERSION_1_30
2490 };
2491 fw_cfg_add_file(x86ms->fw_cfg, "etc/tpm/config",
2492 &tpm_config, sizeof tpm_config);
2493 }
2494
2495 vmgenid_dev = find_vmgenid_dev();
2496 if (vmgenid_dev) {
2497 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), x86ms->fw_cfg,
2498 tables.vmgenid);
2499 }
2500
2501 if (!pcmc->rsdp_in_ram) {
2502 /*
2503 * Keep for compatibility with old machine types.
2504 * Though RSDP is small, its contents isn't immutable, so
2505 * we'll update it along with the rest of tables on guest access.
2506 */
2507 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2508
2509 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2510 fw_cfg_add_file_callback(x86ms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2511 acpi_build_update, NULL, build_state,
2512 build_state->rsdp, rsdp_size, true);
2513 build_state->rsdp_mr = NULL;
2514 } else {
2515 build_state->rsdp = NULL;
2516 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update,
2517 build_state, tables.rsdp,
2518 ACPI_BUILD_RSDP_FILE, 0);
2519 }
2520
2521 qemu_register_reset(acpi_build_reset, build_state);
2522 acpi_build_reset(build_state);
2523 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2524
2525 /* Cleanup tables but don't free the memory: we track it
2526 * in build_state.
2527 */
2528 acpi_build_tables_cleanup(&tables, false);
2529 }
QEmu