hw/serial.c

   1 /*
   2  * QEMU 16550A UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2008 Citrix Systems, Inc.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw.h"
  26 #include "qemu-char.h"
  27 #include "isa.h"
  28 #include "pc.h"
  29 #include "qemu-timer.h"
  30 #include "sysemu.h"
  31
  32 //#define DEBUG_SERIAL
  33
  34 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  35
  36 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  37 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  38 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  39 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  40
  41 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  42 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  43
  44 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  45 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  46 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  47 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  48 #define UART_IIR_CTI    0x0C    /* Character Timeout Indication */
  49
  50 #define UART_IIR_FENF   0x80    /* Fifo enabled, but not functionning */
  51 #define UART_IIR_FE     0xC0    /* Fifo enabled */
  52
  53 /*
  54  * These are the definitions for the Modem Control Register
  55  */
  56 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  57 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  58 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  59 #define UART_MCR_RTS    0x02    /* RTS complement */
  60 #define UART_MCR_DTR    0x01    /* DTR complement */
  61
  62 /*
  63  * These are the definitions for the Modem Status Register
  64  */
  65 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  66 #define UART_MSR_RI     0x40    /* Ring Indicator */
  67 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  68 #define UART_MSR_CTS    0x10    /* Clear to Send */
  69 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  70 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  71 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  72 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  73 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  74
  75 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  76 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  77 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  78 #define UART_LSR_FE     0x08    /* Frame error indicator */
  79 #define UART_LSR_PE     0x04    /* Parity error indicator */
  80 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  81 #define UART_LSR_DR     0x01    /* Receiver data ready */
  82 #define UART_LSR_INT_ANY 0x1E   /* Any of the lsr-interrupt-triggering status bits */
  83
  84 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
  85
  86 #define UART_FCR_ITL_1      0x00 /* 1 byte ITL */
  87 #define UART_FCR_ITL_2      0x40 /* 4 bytes ITL */
  88 #define UART_FCR_ITL_3      0x80 /* 8 bytes ITL */
  89 #define UART_FCR_ITL_4      0xC0 /* 14 bytes ITL */
  90
  91 #define UART_FCR_DMS        0x08    /* DMA Mode Select */
  92 #define UART_FCR_XFR        0x04    /* XMIT Fifo Reset */
  93 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
  94 #define UART_FCR_FE         0x01    /* FIFO Enable */
  95
  96 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
  97
  98 #define XMIT_FIFO           0
  99 #define RECV_FIFO           1
 100 #define MAX_XMIT_RETRY      4
 101
 102 #ifdef DEBUG_SERIAL
 103 #define DPRINTF(fmt, ...) \
 104 do { fprintf(stderr, "serial: " fmt , ## __VA_ARGS__); } while (0)
 105 #else
 106 #define DPRINTF(fmt, ...) \
 107 do {} while (0)
 108 #endif
 109
 110 typedef struct SerialFIFO {
 111     uint8_t data[UART_FIFO_LENGTH];
 112     uint8_t count;
 113     uint8_t itl;                        /* Interrupt Trigger Level */
 114     uint8_t tail;
 115     uint8_t head;
 116 } SerialFIFO;
 117
 118 struct SerialState {
 119     uint16_t divider;
 120     uint8_t rbr; /* receive register */
 121     uint8_t thr; /* transmit holding register */
 122     uint8_t tsr; /* transmit shift register */
 123     uint8_t ier;
 124     uint8_t iir; /* read only */
 125     uint8_t lcr;
 126     uint8_t mcr;
 127     uint8_t lsr; /* read only */
 128     uint8_t msr; /* read only */
 129     uint8_t scr;
 130     uint8_t fcr;
 131     uint8_t fcr_vmstate; /* we can't write directly this value
 132                             it has side effects */
 133     /* NOTE: this hidden state is necessary for tx irq generation as
 134        it can be reset while reading iir */
 135     int thr_ipending;
 136     qemu_irq irq;
 137     CharDriverState *chr;
 138     int last_break_enable;
 139     int it_shift;
 140     int baudbase;
 141     int tsr_retry;
 142     uint32_t wakeup;
 143
 144     uint64_t last_xmit_ts;              /* Time when the last byte was successfully sent out of the tsr */
 145     SerialFIFO recv_fifo;
 146     SerialFIFO xmit_fifo;
 147
 148     struct QEMUTimer *fifo_timeout_timer;
 149     int timeout_ipending;                   /* timeout interrupt pending state */
 150     struct QEMUTimer *transmit_timer;
 151
 152
 153     uint64_t char_transmit_time;               /* time to transmit a char in ticks*/
 154     int poll_msl;
 155
 156     struct QEMUTimer *modem_status_poll;
 157     MemoryRegion io;
 158 };
 159
 160 typedef struct ISASerialState {
 161     ISADevice dev;
 162     uint32_t index;
 163     uint32_t iobase;
 164     uint32_t isairq;
 165     SerialState state;
 166 } ISASerialState;
 167
 168 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
 169
 170 static void fifo_clear(SerialState *s, int fifo)
 171 {
 172     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 173     memset(f->data, 0, UART_FIFO_LENGTH);
 174     f->count = 0;
 175     f->head = 0;
 176     f->tail = 0;
 177 }
 178
 179 static int fifo_put(SerialState *s, int fifo, uint8_t chr)
 180 {
 181     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 182
 183     /* Receive overruns do not overwrite FIFO contents. */
 184     if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
 185
 186         f->data[f->head++] = chr;
 187
 188         if (f->head == UART_FIFO_LENGTH)
 189             f->head = 0;
 190     }
 191
 192     if (f->count < UART_FIFO_LENGTH)
 193         f->count++;
 194     else if (fifo == RECV_FIFO)
 195         s->lsr |= UART_LSR_OE;
 196
 197     return 1;
 198 }
 199
 200 static uint8_t fifo_get(SerialState *s, int fifo)
 201 {
 202     SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
 203     uint8_t c;
 204
 205     if(f->count == 0)
 206         return 0;
 207
 208     c = f->data[f->tail++];
 209     if (f->tail == UART_FIFO_LENGTH)
 210         f->tail = 0;
 211     f->count--;
 212
 213     return c;
 214 }
 215
 216 static void serial_update_irq(SerialState *s)
 217 {
 218     uint8_t tmp_iir = UART_IIR_NO_INT;
 219
 220     if ((s->ier & UART_IER_RLSI) && (s->lsr & UART_LSR_INT_ANY)) {
 221         tmp_iir = UART_IIR_RLSI;
 222     } else if ((s->ier & UART_IER_RDI) && s->timeout_ipending) {
 223         /* Note that(s->ier & UART_IER_RDI) can mask this interrupt,
 224          * this is not in the specification but is observed on existing
 225          * hardware.  */
 226         tmp_iir = UART_IIR_CTI;
 227     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
 228                (!(s->fcr & UART_FCR_FE) ||
 229                 s->recv_fifo.count >= s->recv_fifo.itl)) {
 230         tmp_iir = UART_IIR_RDI;
 231     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
 232         tmp_iir = UART_IIR_THRI;
 233     } else if ((s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA)) {
 234         tmp_iir = UART_IIR_MSI;
 235     }
 236
 237     s->iir = tmp_iir | (s->iir & 0xF0);
 238
 239     if (tmp_iir != UART_IIR_NO_INT) {
 240         qemu_irq_raise(s->irq);
 241     } else {
 242         qemu_irq_lower(s->irq);
 243     }
 244 }
 245
 246 static void serial_update_parameters(SerialState *s)
 247 {
 248     int speed, parity, data_bits, stop_bits, frame_size;
 249     QEMUSerialSetParams ssp;
 250
 251     if (s->divider == 0)
 252         return;
 253
 254     /* Start bit. */
 255     frame_size = 1;
 256     if (s->lcr & 0x08) {
 257         /* Parity bit. */
 258         frame_size++;
 259         if (s->lcr & 0x10)
 260             parity = 'E';
 261         else
 262             parity = 'O';
 263     } else {
 264             parity = 'N';
 265     }
 266     if (s->lcr & 0x04)
 267         stop_bits = 2;
 268     else
 269         stop_bits = 1;
 270
 271     data_bits = (s->lcr & 0x03) + 5;
 272     frame_size += data_bits + stop_bits;
 273     speed = s->baudbase / s->divider;
 274     ssp.speed = speed;
 275     ssp.parity = parity;
 276     ssp.data_bits = data_bits;
 277     ssp.stop_bits = stop_bits;
 278     s->char_transmit_time =  (get_ticks_per_sec() / speed) * frame_size;
 279     qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 280
 281     DPRINTF("speed=%d parity=%c data=%d stop=%d\n",
 282            speed, parity, data_bits, stop_bits);
 283 }
 284
 285 static void serial_update_msl(SerialState *s)
 286 {
 287     uint8_t omsr;
 288     int flags;
 289
 290     qemu_del_timer(s->modem_status_poll);
 291
 292     if (qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP) {
 293         s->poll_msl = -1;
 294         return;
 295     }
 296
 297     omsr = s->msr;
 298
 299     s->msr = (flags & CHR_TIOCM_CTS) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
 300     s->msr = (flags & CHR_TIOCM_DSR) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
 301     s->msr = (flags & CHR_TIOCM_CAR) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
 302     s->msr = (flags & CHR_TIOCM_RI) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
 303
 304     if (s->msr != omsr) {
 305          /* Set delta bits */
 306          s->msr = s->msr | ((s->msr >> 4) ^ (omsr >> 4));
 307          /* UART_MSR_TERI only if change was from 1 -> 0 */
 308          if ((s->msr & UART_MSR_TERI) && !(omsr & UART_MSR_RI))
 309              s->msr &= ~UART_MSR_TERI;
 310          serial_update_irq(s);
 311     }
 312
 313     /* The real 16550A apparently has a 250ns response latency to line status changes.
 314        We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
 315
 316     if (s->poll_msl)
 317         qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 100);
 318 }
 319
 320 static void serial_xmit(void *opaque)
 321 {
 322     SerialState *s = opaque;
 323     uint64_t new_xmit_ts = qemu_get_clock_ns(vm_clock);
 324
 325     if (s->tsr_retry <= 0) {
 326         if (s->fcr & UART_FCR_FE) {
 327             s->tsr = fifo_get(s,XMIT_FIFO);
 328             if (!s->xmit_fifo.count)
 329                 s->lsr |= UART_LSR_THRE;
 330         } else {
 331             s->tsr = s->thr;
 332             s->lsr |= UART_LSR_THRE;
 333         }
 334     }
 335
 336     if (s->mcr & UART_MCR_LOOP) {
 337         /* in loopback mode, say that we just received a char */
 338         serial_receive1(s, &s->tsr, 1);
 339     } else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
 340         if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
 341             s->tsr_retry++;
 342             qemu_mod_timer(s->transmit_timer,  new_xmit_ts + s->char_transmit_time);
 343             return;
 344         } else if (s->poll_msl < 0) {
 345             /* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port, then
 346             drop any further failed writes instantly, until we get one that goes through.
 347             This is to prevent guests that log to unconnected pipes or pty's from stalling. */
 348             s->tsr_retry = -1;
 349         }
 350     }
 351     else {
 352         s->tsr_retry = 0;
 353     }
 354
 355     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
 356     if (!(s->lsr & UART_LSR_THRE))
 357         qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time);
 358
 359     if (s->lsr & UART_LSR_THRE) {
 360         s->lsr |= UART_LSR_TEMT;
 361         s->thr_ipending = 1;
 362         serial_update_irq(s);
 363     }
 364 }
 365
 366
 367 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 368 {
 369     SerialState *s = opaque;
 370
 371     addr &= 7;
 372     DPRINTF("write addr=0x%02x val=0x%02x\n", addr, val);
 373     switch(addr) {
 374     default:
 375     case 0:
 376         if (s->lcr & UART_LCR_DLAB) {
 377             s->divider = (s->divider & 0xff00) | val;
 378             serial_update_parameters(s);
 379         } else {
 380             s->thr = (uint8_t) val;
 381             if(s->fcr & UART_FCR_FE) {
 382                 fifo_put(s, XMIT_FIFO, s->thr);
 383                 s->thr_ipending = 0;
 384                 s->lsr &= ~UART_LSR_TEMT;
 385                 s->lsr &= ~UART_LSR_THRE;
 386                 serial_update_irq(s);
 387             } else {
 388                 s->thr_ipending = 0;
 389                 s->lsr &= ~UART_LSR_THRE;
 390                 serial_update_irq(s);
 391             }
 392             serial_xmit(s);
 393         }
 394         break;
 395     case 1:
 396         if (s->lcr & UART_LCR_DLAB) {
 397             s->divider = (s->divider & 0x00ff) | (val << 8);
 398             serial_update_parameters(s);
 399         } else {
 400             s->ier = val & 0x0f;
 401             /* If the backend device is a real serial port, turn polling of the modem
 402                status lines on physical port on or off depending on UART_IER_MSI state */
 403             if (s->poll_msl >= 0) {
 404                 if (s->ier & UART_IER_MSI) {
 405                      s->poll_msl = 1;
 406                      serial_update_msl(s);
 407                 } else {
 408                      qemu_del_timer(s->modem_status_poll);
 409                      s->poll_msl = 0;
 410                 }
 411             }
 412             if (s->lsr & UART_LSR_THRE) {
 413                 s->thr_ipending = 1;
 414                 serial_update_irq(s);
 415             }
 416         }
 417         break;
 418     case 2:
 419         val = val & 0xFF;
 420
 421         if (s->fcr == val)
 422             break;
 423
 424         /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
 425         if ((val ^ s->fcr) & UART_FCR_FE)
 426             val |= UART_FCR_XFR | UART_FCR_RFR;
 427
 428         /* FIFO clear */
 429
 430         if (val & UART_FCR_RFR) {
 431             qemu_del_timer(s->fifo_timeout_timer);
 432             s->timeout_ipending=0;
 433             fifo_clear(s,RECV_FIFO);
 434         }
 435
 436         if (val & UART_FCR_XFR) {
 437             fifo_clear(s,XMIT_FIFO);
 438         }
 439
 440         if (val & UART_FCR_FE) {
 441             s->iir |= UART_IIR_FE;
 442             /* Set RECV_FIFO trigger Level */
 443             switch (val & 0xC0) {
 444             case UART_FCR_ITL_1:
 445                 s->recv_fifo.itl = 1;
 446                 break;
 447             case UART_FCR_ITL_2:
 448                 s->recv_fifo.itl = 4;
 449                 break;
 450             case UART_FCR_ITL_3:
 451                 s->recv_fifo.itl = 8;
 452                 break;
 453             case UART_FCR_ITL_4:
 454                 s->recv_fifo.itl = 14;
 455                 break;
 456             }
 457         } else
 458             s->iir &= ~UART_IIR_FE;
 459
 460         /* Set fcr - or at least the bits in it that are supposed to "stick" */
 461         s->fcr = val & 0xC9;
 462         serial_update_irq(s);
 463         break;
 464     case 3:
 465         {
 466             int break_enable;
 467             s->lcr = val;
 468             serial_update_parameters(s);
 469             break_enable = (val >> 6) & 1;
 470             if (break_enable != s->last_break_enable) {
 471                 s->last_break_enable = break_enable;
 472                 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 473                                &break_enable);
 474             }
 475         }
 476         break;
 477     case 4:
 478         {
 479             int flags;
 480             int old_mcr = s->mcr;
 481             s->mcr = val & 0x1f;
 482             if (val & UART_MCR_LOOP)
 483                 break;
 484
 485             if (s->poll_msl >= 0 && old_mcr != s->mcr) {
 486
 487                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
 488
 489                 flags &= ~(CHR_TIOCM_RTS | CHR_TIOCM_DTR);
 490
 491                 if (val & UART_MCR_RTS)
 492                     flags |= CHR_TIOCM_RTS;
 493                 if (val & UART_MCR_DTR)
 494                     flags |= CHR_TIOCM_DTR;
 495
 496                 qemu_chr_fe_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
 497                 /* Update the modem status after a one-character-send wait-time, since there may be a response
 498                    from the device/computer at the other end of the serial line */
 499                 qemu_mod_timer(s->modem_status_poll, qemu_get_clock_ns(vm_clock) + s->char_transmit_time);
 500             }
 501         }
 502         break;
 503     case 5:
 504         break;
 505     case 6:
 506         break;
 507     case 7:
 508         s->scr = val;
 509         break;
 510     }
 511 }
 512
 513 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 514 {
 515     SerialState *s = opaque;
 516     uint32_t ret;
 517
 518     addr &= 7;
 519     switch(addr) {
 520     default:
 521     case 0:
 522         if (s->lcr & UART_LCR_DLAB) {
 523             ret = s->divider & 0xff;
 524         } else {
 525             if(s->fcr & UART_FCR_FE) {
 526                 ret = fifo_get(s,RECV_FIFO);
 527                 if (s->recv_fifo.count == 0)
 528                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 529                 else
 530                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
 531                 s->timeout_ipending = 0;
 532             } else {
 533                 ret = s->rbr;
 534                 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 535             }
 536             serial_update_irq(s);
 537             if (!(s->mcr & UART_MCR_LOOP)) {
 538                 /* in loopback mode, don't receive any data */
 539                 qemu_chr_accept_input(s->chr);
 540             }
 541         }
 542         break;
 543     case 1:
 544         if (s->lcr & UART_LCR_DLAB) {
 545             ret = (s->divider >> 8) & 0xff;
 546         } else {
 547             ret = s->ier;
 548         }
 549         break;
 550     case 2:
 551         ret = s->iir;
 552         if ((ret & UART_IIR_ID) == UART_IIR_THRI) {
 553             s->thr_ipending = 0;
 554             serial_update_irq(s);
 555         }
 556         break;
 557     case 3:
 558         ret = s->lcr;
 559         break;
 560     case 4:
 561         ret = s->mcr;
 562         break;
 563     case 5:
 564         ret = s->lsr;
 565         /* Clear break and overrun interrupts */
 566         if (s->lsr & (UART_LSR_BI|UART_LSR_OE)) {
 567             s->lsr &= ~(UART_LSR_BI|UART_LSR_OE);
 568             serial_update_irq(s);
 569         }
 570         break;
 571     case 6:
 572         if (s->mcr & UART_MCR_LOOP) {
 573             /* in loopback, the modem output pins are connected to the
 574                inputs */
 575             ret = (s->mcr & 0x0c) << 4;
 576             ret |= (s->mcr & 0x02) << 3;
 577             ret |= (s->mcr & 0x01) << 5;
 578         } else {
 579             if (s->poll_msl >= 0)
 580                 serial_update_msl(s);
 581             ret = s->msr;
 582             /* Clear delta bits & msr int after read, if they were set */
 583             if (s->msr & UART_MSR_ANY_DELTA) {
 584                 s->msr &= 0xF0;
 585                 serial_update_irq(s);
 586             }
 587         }
 588         break;
 589     case 7:
 590         ret = s->scr;
 591         break;
 592     }
 593     DPRINTF("read addr=0x%02x val=0x%02x\n", addr, ret);
 594     return ret;
 595 }
 596
 597 static int serial_can_receive(SerialState *s)
 598 {
 599     if(s->fcr & UART_FCR_FE) {
 600         if(s->recv_fifo.count < UART_FIFO_LENGTH)
 601         /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
 602         advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
 603         effectively overriding the ITL that the guest has set. */
 604              return (s->recv_fifo.count <= s->recv_fifo.itl) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
 605         else
 606              return 0;
 607     } else {
 608     return !(s->lsr & UART_LSR_DR);
 609     }
 610 }
 611
 612 static void serial_receive_break(SerialState *s)
 613 {
 614     s->rbr = 0;
 615     /* When the LSR_DR is set a null byte is pushed into the fifo */
 616     fifo_put(s, RECV_FIFO, '\0');
 617     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 618     serial_update_irq(s);
 619 }
 620
 621 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
 622 static void fifo_timeout_int (void *opaque) {
 623     SerialState *s = opaque;
 624     if (s->recv_fifo.count) {
 625         s->timeout_ipending = 1;
 626         serial_update_irq(s);
 627     }
 628 }
 629
 630 static int serial_can_receive1(void *opaque)
 631 {
 632     SerialState *s = opaque;
 633     return serial_can_receive(s);
 634 }
 635
 636 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 637 {
 638     SerialState *s = opaque;
 639
 640     if (s->wakeup) {
 641         qemu_system_wakeup_request(QEMU_WAKEUP_REASON_OTHER);
 642     }
 643     if(s->fcr & UART_FCR_FE) {
 644         int i;
 645         for (i = 0; i < size; i++) {
 646             fifo_put(s, RECV_FIFO, buf[i]);
 647         }
 648         s->lsr |= UART_LSR_DR;
 649         /* call the timeout receive callback in 4 char transmit time */
 650         qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
 651     } else {
 652         if (s->lsr & UART_LSR_DR)
 653             s->lsr |= UART_LSR_OE;
 654         s->rbr = buf[0];
 655         s->lsr |= UART_LSR_DR;
 656     }
 657     serial_update_irq(s);
 658 }
 659
 660 static void serial_event(void *opaque, int event)
 661 {
 662     SerialState *s = opaque;
 663     DPRINTF("event %x\n", event);
 664     if (event == CHR_EVENT_BREAK)
 665         serial_receive_break(s);
 666 }
 667
 668 static void serial_pre_save(void *opaque)
 669 {
 670     SerialState *s = opaque;
 671     s->fcr_vmstate = s->fcr;
 672 }
 673
 674 static int serial_post_load(void *opaque, int version_id)
 675 {
 676     SerialState *s = opaque;
 677
 678     if (version_id < 3) {
 679         s->fcr_vmstate = 0;
 680     }
 681     /* Initialize fcr via setter to perform essential side-effects */
 682     serial_ioport_write(s, 0x02, s->fcr_vmstate);
 683     serial_update_parameters(s);
 684     return 0;
 685 }
 686
 687 static const VMStateDescription vmstate_serial = {
 688     .name = "serial",
 689     .version_id = 3,
 690     .minimum_version_id = 2,
 691     .pre_save = serial_pre_save,
 692     .post_load = serial_post_load,
 693     .fields      = (VMStateField []) {
 694         VMSTATE_UINT16_V(divider, SerialState, 2),
 695         VMSTATE_UINT8(rbr, SerialState),
 696         VMSTATE_UINT8(ier, SerialState),
 697         VMSTATE_UINT8(iir, SerialState),
 698         VMSTATE_UINT8(lcr, SerialState),
 699         VMSTATE_UINT8(mcr, SerialState),
 700         VMSTATE_UINT8(lsr, SerialState),
 701         VMSTATE_UINT8(msr, SerialState),
 702         VMSTATE_UINT8(scr, SerialState),
 703         VMSTATE_UINT8_V(fcr_vmstate, SerialState, 3),
 704         VMSTATE_END_OF_LIST()
 705     }
 706 };
 707
 708 static void serial_reset(void *opaque)
 709 {
 710     SerialState *s = opaque;
 711
 712     s->rbr = 0;
 713     s->ier = 0;
 714     s->iir = UART_IIR_NO_INT;
 715     s->lcr = 0;
 716     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 717     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 718     /* Default to 9600 baud, 1 start bit, 8 data bits, 1 stop bit, no parity. */
 719     s->divider = 0x0C;
 720     s->mcr = UART_MCR_OUT2;
 721     s->scr = 0;
 722     s->tsr_retry = 0;
 723     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
 724     s->poll_msl = 0;
 725
 726     fifo_clear(s,RECV_FIFO);
 727     fifo_clear(s,XMIT_FIFO);
 728
 729     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
 730
 731     s->thr_ipending = 0;
 732     s->last_break_enable = 0;
 733     qemu_irq_lower(s->irq);
 734 }
 735
 736 static void serial_init_core(SerialState *s)
 737 {
 738     if (!s->chr) {
 739         fprintf(stderr, "Can't create serial device, empty char device\n");
 740         exit(1);
 741     }
 742
 743     s->modem_status_poll = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_update_msl, s);
 744
 745     s->fifo_timeout_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) fifo_timeout_int, s);
 746     s->transmit_timer = qemu_new_timer_ns(vm_clock, (QEMUTimerCB *) serial_xmit, s);
 747
 748     qemu_register_reset(serial_reset, s);
 749
 750     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
 751                           serial_event, s);
 752 }
 753
 754 /* Change the main reference oscillator frequency. */
 755 void serial_set_frequency(SerialState *s, uint32_t frequency)
 756 {
 757     s->baudbase = frequency;
 758     serial_update_parameters(s);
 759 }
 760
 761 static const int isa_serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 762 static const int isa_serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 763
 764 static const MemoryRegionPortio serial_portio[] = {
 765     { 0, 8, 1, .read = serial_ioport_read, .write = serial_ioport_write },
 766     PORTIO_END_OF_LIST()
 767 };
 768
 769 static const MemoryRegionOps serial_io_ops = {
 770     .old_portio = serial_portio
 771 };
 772
 773 static int serial_isa_initfn(ISADevice *dev)
 774 {
 775     static int index;
 776     ISASerialState *isa = DO_UPCAST(ISASerialState, dev, dev);
 777     SerialState *s = &isa->state;
 778
 779     if (isa->index == -1)
 780         isa->index = index;
 781     if (isa->index >= MAX_SERIAL_PORTS)
 782         return -1;
 783     if (isa->iobase == -1)
 784         isa->iobase = isa_serial_io[isa->index];
 785     if (isa->isairq == -1)
 786         isa->isairq = isa_serial_irq[isa->index];
 787     index++;
 788
 789     s->baudbase = 115200;
 790     isa_init_irq(dev, &s->irq, isa->isairq);
 791     serial_init_core(s);
 792     qdev_set_legacy_instance_id(&dev->qdev, isa->iobase, 3);
 793
 794     memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
 795     isa_register_ioport(dev, &s->io, isa->iobase);
 796     return 0;
 797 }
 798
 799 static const VMStateDescription vmstate_isa_serial = {
 800     .name = "serial",
 801     .version_id = 3,
 802     .minimum_version_id = 2,
 803     .fields      = (VMStateField []) {
 804         VMSTATE_STRUCT(state, ISASerialState, 0, vmstate_serial, SerialState),
 805         VMSTATE_END_OF_LIST()
 806     }
 807 };
 808
 809 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
 810                          CharDriverState *chr)
 811 {
 812     SerialState *s;
 813
 814     s = g_malloc0(sizeof(SerialState));
 815
 816     s->irq = irq;
 817     s->baudbase = baudbase;
 818     s->chr = chr;
 819     serial_init_core(s);
 820
 821     vmstate_register(NULL, base, &vmstate_serial, s);
 822
 823     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 824     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 825     return s;
 826 }
 827
 828 /* Memory mapped interface */
 829 static uint64_t serial_mm_read(void *opaque, target_phys_addr_t addr,
 830                                unsigned size)
 831 {
 832     SerialState *s = opaque;
 833     return serial_ioport_read(s, addr >> s->it_shift);
 834 }
 835
 836 static void serial_mm_write(void *opaque, target_phys_addr_t addr,
 837                             uint64_t value, unsigned size)
 838 {
 839     SerialState *s = opaque;
 840     value &= ~0u >> (32 - (size * 8));
 841     serial_ioport_write(s, addr >> s->it_shift, value);
 842 }
 843
 844 static const MemoryRegionOps serial_mm_ops[3] = {
 845     [DEVICE_NATIVE_ENDIAN] = {
 846         .read = serial_mm_read,
 847         .write = serial_mm_write,
 848         .endianness = DEVICE_NATIVE_ENDIAN,
 849     },
 850     [DEVICE_LITTLE_ENDIAN] = {
 851         .read = serial_mm_read,
 852         .write = serial_mm_write,
 853         .endianness = DEVICE_LITTLE_ENDIAN,
 854     },
 855     [DEVICE_BIG_ENDIAN] = {
 856         .read = serial_mm_read,
 857         .write = serial_mm_write,
 858         .endianness = DEVICE_BIG_ENDIAN,
 859     },
 860 };
 861
 862 SerialState *serial_mm_init(MemoryRegion *address_space,
 863                             target_phys_addr_t base, int it_shift,
 864                             qemu_irq irq, int baudbase,
 865                             CharDriverState *chr, enum device_endian end)
 866 {
 867     SerialState *s;
 868
 869     s = g_malloc0(sizeof(SerialState));
 870
 871     s->it_shift = it_shift;
 872     s->irq = irq;
 873     s->baudbase = baudbase;
 874     s->chr = chr;
 875
 876     serial_init_core(s);
 877     vmstate_register(NULL, base, &vmstate_serial, s);
 878
 879     memory_region_init_io(&s->io, &serial_mm_ops[end], s,
 880                           "serial", 8 << it_shift);
 881     memory_region_add_subregion(address_space, base, &s->io);
 882
 883     serial_update_msl(s);
 884     return s;
 885 }
 886
 887 static Property serial_isa_properties[] = {
 888     DEFINE_PROP_UINT32("index", ISASerialState, index,   -1),
 889     DEFINE_PROP_HEX32("iobase", ISASerialState, iobase,  -1),
 890     DEFINE_PROP_UINT32("irq",   ISASerialState, isairq,  -1),
 891     DEFINE_PROP_CHR("chardev",  ISASerialState, state.chr),
 892     DEFINE_PROP_UINT32("wakeup", ISASerialState, state.wakeup, 0),
 893     DEFINE_PROP_END_OF_LIST(),
 894 };
 895
 896 static void serial_isa_class_initfn(ObjectClass *klass, void *data)
 897 {
 898     DeviceClass *dc = DEVICE_CLASS(klass);
 899     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 900     ic->init = serial_isa_initfn;
 901     dc->vmsd = &vmstate_isa_serial;
 902     dc->props = serial_isa_properties;
 903 }
 904
 905 static TypeInfo serial_isa_info = {
 906     .name          = "isa-serial",
 907     .parent        = TYPE_ISA_DEVICE,
 908     .instance_size = sizeof(ISASerialState),
 909     .class_init    = serial_isa_class_initfn,
 910 };
 911
 912 static void serial_register_types(void)
 913 {
 914     type_register_static(&serial_isa_info);
 915 }
 916
 917 type_init(serial_register_types)