2 * ARM Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
10 /* This file contains implementation code for the RealView EB interrupt
11 * controller, MPCore distributed interrupt controller and ARMv7-M
12 * Nested Vectored Interrupt Controller.
13 * It is compiled in two ways:
14 * (1) as a standalone file to produce a sysbus device which is a GIC
15 * that can be used on the realview board and as one of the builtin
16 * private peripherals for the ARM MP CPUs (11MPCore, A9, etc)
17 * (2) by being directly #included into armv7m_nvic.c to produce the
21 #include "hw/sysbus.h"
22 #include "gic_internal.h"
28 #define DPRINTF(fmt, ...) \
29 do { fprintf(stderr, "arm_gic: " fmt , ## __VA_ARGS__); } while (0)
31 #define DPRINTF(fmt, ...) do {} while(0)
34 static const uint8_t gic_id_11mpcore
[] = {
35 0x00, 0x00, 0x00, 0x00, 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
38 static const uint8_t gic_id_gicv1
[] = {
39 0x04, 0x00, 0x00, 0x00, 0x90, 0xb3, 0x1b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
42 static const uint8_t gic_id_gicv2
[] = {
43 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b, 0x00, 0x0d, 0xf0, 0x05, 0xb1
46 static inline int gic_get_current_cpu(GICState
*s
)
49 return current_cpu
->cpu_index
;
54 /* Return true if this GIC config has interrupt groups, which is
55 * true if we're a GICv2, or a GICv1 with the security extensions.
57 static inline bool gic_has_groups(GICState
*s
)
59 return s
->revision
== 2 || s
->security_extn
;
62 /* TODO: Many places that call this routine could be optimized. */
63 /* Update interrupt status after enabled or pending bits have been changed. */
64 void gic_update(GICState
*s
)
69 int irq_level
, fiq_level
;
73 for (cpu
= 0; cpu
< s
->num_cpu
; cpu
++) {
75 s
->current_pending
[cpu
] = 1023;
76 if (!(s
->ctlr
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
))
77 || !(s
->cpu_ctlr
[cpu
] & (GICC_CTLR_EN_GRP0
| GICC_CTLR_EN_GRP1
))) {
78 qemu_irq_lower(s
->parent_irq
[cpu
]);
79 qemu_irq_lower(s
->parent_fiq
[cpu
]);
84 for (irq
= 0; irq
< s
->num_irq
; irq
++) {
85 if (GIC_TEST_ENABLED(irq
, cm
) && gic_test_pending(s
, irq
, cm
) &&
86 (irq
< GIC_INTERNAL
|| GIC_TARGET(irq
) & cm
)) {
87 if (GIC_GET_PRIORITY(irq
, cpu
) < best_prio
) {
88 best_prio
= GIC_GET_PRIORITY(irq
, cpu
);
94 irq_level
= fiq_level
= 0;
96 if (best_prio
< s
->priority_mask
[cpu
]) {
97 s
->current_pending
[cpu
] = best_irq
;
98 if (best_prio
< s
->running_priority
[cpu
]) {
99 int group
= GIC_TEST_GROUP(best_irq
, cm
);
101 if (extract32(s
->ctlr
, group
, 1) &&
102 extract32(s
->cpu_ctlr
[cpu
], group
, 1)) {
103 if (group
== 0 && s
->cpu_ctlr
[cpu
] & GICC_CTLR_FIQ_EN
) {
104 DPRINTF("Raised pending FIQ %d (cpu %d)\n",
108 DPRINTF("Raised pending IRQ %d (cpu %d)\n",
116 qemu_set_irq(s
->parent_irq
[cpu
], irq_level
);
117 qemu_set_irq(s
->parent_fiq
[cpu
], fiq_level
);
121 void gic_set_pending_private(GICState
*s
, int cpu
, int irq
)
125 if (gic_test_pending(s
, irq
, cm
)) {
129 DPRINTF("Set %d pending cpu %d\n", irq
, cpu
);
130 GIC_SET_PENDING(irq
, cm
);
134 static void gic_set_irq_11mpcore(GICState
*s
, int irq
, int level
,
138 GIC_SET_LEVEL(irq
, cm
);
139 if (GIC_TEST_EDGE_TRIGGER(irq
) || GIC_TEST_ENABLED(irq
, cm
)) {
140 DPRINTF("Set %d pending mask %x\n", irq
, target
);
141 GIC_SET_PENDING(irq
, target
);
144 GIC_CLEAR_LEVEL(irq
, cm
);
148 static void gic_set_irq_generic(GICState
*s
, int irq
, int level
,
152 GIC_SET_LEVEL(irq
, cm
);
153 DPRINTF("Set %d pending mask %x\n", irq
, target
);
154 if (GIC_TEST_EDGE_TRIGGER(irq
)) {
155 GIC_SET_PENDING(irq
, target
);
158 GIC_CLEAR_LEVEL(irq
, cm
);
162 /* Process a change in an external IRQ input. */
163 static void gic_set_irq(void *opaque
, int irq
, int level
)
165 /* Meaning of the 'irq' parameter:
166 * [0..N-1] : external interrupts
167 * [N..N+31] : PPI (internal) interrupts for CPU 0
168 * [N+32..N+63] : PPI (internal interrupts for CPU 1
171 GICState
*s
= (GICState
*)opaque
;
173 if (irq
< (s
->num_irq
- GIC_INTERNAL
)) {
174 /* The first external input line is internal interrupt 32. */
177 target
= GIC_TARGET(irq
);
180 irq
-= (s
->num_irq
- GIC_INTERNAL
);
181 cpu
= irq
/ GIC_INTERNAL
;
187 assert(irq
>= GIC_NR_SGIS
);
189 if (level
== GIC_TEST_LEVEL(irq
, cm
)) {
193 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
194 gic_set_irq_11mpcore(s
, irq
, level
, cm
, target
);
196 gic_set_irq_generic(s
, irq
, level
, cm
, target
);
202 static uint16_t gic_get_current_pending_irq(GICState
*s
, int cpu
,
205 uint16_t pending_irq
= s
->current_pending
[cpu
];
207 if (pending_irq
< GIC_MAXIRQ
&& gic_has_groups(s
)) {
208 int group
= GIC_TEST_GROUP(pending_irq
, (1 << cpu
));
209 /* On a GIC without the security extensions, reading this register
210 * behaves in the same way as a secure access to a GIC with them.
212 bool secure
= !s
->security_extn
|| attrs
.secure
;
214 if (group
== 0 && !secure
) {
215 /* Group0 interrupts hidden from Non-secure access */
218 if (group
== 1 && secure
&& !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_ACK_CTL
)) {
219 /* Group1 interrupts only seen by Secure access if
228 static int gic_get_group_priority(GICState
*s
, int cpu
, int irq
)
230 /* Return the group priority of the specified interrupt
231 * (which is the top bits of its priority, with the number
232 * of bits masked determined by the applicable binary point register).
237 if (gic_has_groups(s
) &&
238 !(s
->cpu_ctlr
[cpu
] & GICC_CTLR_CBPR
) &&
239 GIC_TEST_GROUP(irq
, (1 << cpu
))) {
245 /* a BPR of 0 means the group priority bits are [7:1];
246 * a BPR of 1 means they are [7:2], and so on down to
247 * a BPR of 7 meaning no group priority bits at all.
249 mask
= ~0U << ((bpr
& 7) + 1);
251 return GIC_GET_PRIORITY(irq
, cpu
) & mask
;
254 static void gic_activate_irq(GICState
*s
, int cpu
, int irq
)
256 /* Set the appropriate Active Priority Register bit for this IRQ,
257 * and update the running priority.
259 int prio
= gic_get_group_priority(s
, cpu
, irq
);
260 int preemption_level
= prio
>> (GIC_MIN_BPR
+ 1);
261 int regno
= preemption_level
/ 32;
262 int bitno
= preemption_level
% 32;
264 if (gic_has_groups(s
) && GIC_TEST_GROUP(irq
, (1 << cpu
))) {
265 s
->nsapr
[regno
][cpu
] |= (1 << bitno
);
267 s
->apr
[regno
][cpu
] |= (1 << bitno
);
270 s
->running_priority
[cpu
] = prio
;
271 GIC_SET_ACTIVE(irq
, 1 << cpu
);
274 static int gic_get_prio_from_apr_bits(GICState
*s
, int cpu
)
276 /* Recalculate the current running priority for this CPU based
277 * on the set bits in the Active Priority Registers.
280 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
281 uint32_t apr
= s
->apr
[i
][cpu
] | s
->nsapr
[i
][cpu
];
285 return (i
* 32 + ctz32(apr
)) << (GIC_MIN_BPR
+ 1);
290 static void gic_drop_prio(GICState
*s
, int cpu
, int group
)
292 /* Drop the priority of the currently active interrupt in the
295 * Note that we can guarantee (because of the requirement to nest
296 * GICC_IAR reads [which activate an interrupt and raise priority]
297 * with GICC_EOIR writes [which drop the priority for the interrupt])
298 * that the interrupt we're being called for is the highest priority
299 * active interrupt, meaning that it has the lowest set bit in the
302 * If the guest does not honour the ordering constraints then the
303 * behaviour of the GIC is UNPREDICTABLE, which for us means that
304 * the values of the APR registers might become incorrect and the
305 * running priority will be wrong, so interrupts that should preempt
306 * might not do so, and interrupts that should not preempt might do so.
310 for (i
= 0; i
< GIC_NR_APRS
; i
++) {
311 uint32_t *papr
= group
? &s
->nsapr
[i
][cpu
] : &s
->apr
[i
][cpu
];
315 /* Clear lowest set bit */
320 s
->running_priority
[cpu
] = gic_get_prio_from_apr_bits(s
, cpu
);
323 uint32_t gic_acknowledge_irq(GICState
*s
, int cpu
, MemTxAttrs attrs
)
328 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
329 * for the case where this GIC supports grouping and the pending interrupt
330 * is in the wrong group.
332 irq
= gic_get_current_pending_irq(s
, cpu
, attrs
);
334 if (irq
>= GIC_MAXIRQ
) {
335 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq
);
339 if (GIC_GET_PRIORITY(irq
, cpu
) >= s
->running_priority
[cpu
]) {
340 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq
);
344 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
345 /* Clear pending flags for both level and edge triggered interrupts.
346 * Level triggered IRQs will be reasserted once they become inactive.
348 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
351 if (irq
< GIC_NR_SGIS
) {
352 /* Lookup the source CPU for the SGI and clear this in the
353 * sgi_pending map. Return the src and clear the overall pending
354 * state on this CPU if the SGI is not pending from any CPUs.
356 assert(s
->sgi_pending
[irq
][cpu
] != 0);
357 src
= ctz32(s
->sgi_pending
[irq
][cpu
]);
358 s
->sgi_pending
[irq
][cpu
] &= ~(1 << src
);
359 if (s
->sgi_pending
[irq
][cpu
] == 0) {
360 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
362 ret
= irq
| ((src
& 0x7) << 10);
364 /* Clear pending state for both level and edge triggered
365 * interrupts. (level triggered interrupts with an active line
366 * remain pending, see gic_test_pending)
368 GIC_CLEAR_PENDING(irq
, GIC_TEST_MODEL(irq
) ? ALL_CPU_MASK
: cm
);
373 gic_activate_irq(s
, cpu
, irq
);
375 DPRINTF("ACK %d\n", irq
);
379 void gic_set_priority(GICState
*s
, int cpu
, int irq
, uint8_t val
,
382 if (s
->security_extn
&& !attrs
.secure
) {
383 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
384 return; /* Ignore Non-secure access of Group0 IRQ */
386 val
= 0x80 | (val
>> 1); /* Non-secure view */
389 if (irq
< GIC_INTERNAL
) {
390 s
->priority1
[irq
][cpu
] = val
;
392 s
->priority2
[(irq
) - GIC_INTERNAL
] = val
;
396 static uint32_t gic_get_priority(GICState
*s
, int cpu
, int irq
,
399 uint32_t prio
= GIC_GET_PRIORITY(irq
, cpu
);
401 if (s
->security_extn
&& !attrs
.secure
) {
402 if (!GIC_TEST_GROUP(irq
, (1 << cpu
))) {
403 return 0; /* Non-secure access cannot read priority of Group0 IRQ */
405 prio
= (prio
<< 1) & 0xff; /* Non-secure view */
410 static void gic_set_priority_mask(GICState
*s
, int cpu
, uint8_t pmask
,
413 if (s
->security_extn
&& !attrs
.secure
) {
414 if (s
->priority_mask
[cpu
] & 0x80) {
415 /* Priority Mask in upper half */
416 pmask
= 0x80 | (pmask
>> 1);
418 /* Non-secure write ignored if priority mask is in lower half */
422 s
->priority_mask
[cpu
] = pmask
;
425 static uint32_t gic_get_priority_mask(GICState
*s
, int cpu
, MemTxAttrs attrs
)
427 uint32_t pmask
= s
->priority_mask
[cpu
];
429 if (s
->security_extn
&& !attrs
.secure
) {
431 /* Priority Mask in upper half, return Non-secure view */
432 pmask
= (pmask
<< 1) & 0xff;
434 /* Priority Mask in lower half, RAZ */
441 static uint32_t gic_get_cpu_control(GICState
*s
, int cpu
, MemTxAttrs attrs
)
443 uint32_t ret
= s
->cpu_ctlr
[cpu
];
445 if (s
->security_extn
&& !attrs
.secure
) {
446 /* Construct the NS banked view of GICC_CTLR from the correct
447 * bits of the S banked view. We don't need to move the bypass
448 * control bits because we don't implement that (IMPDEF) part
449 * of the GIC architecture.
451 ret
= (ret
& (GICC_CTLR_EN_GRP1
| GICC_CTLR_EOIMODE_NS
)) >> 1;
456 static void gic_set_cpu_control(GICState
*s
, int cpu
, uint32_t value
,
461 if (s
->security_extn
&& !attrs
.secure
) {
462 /* The NS view can only write certain bits in the register;
463 * the rest are unchanged
465 mask
= GICC_CTLR_EN_GRP1
;
466 if (s
->revision
== 2) {
467 mask
|= GICC_CTLR_EOIMODE_NS
;
469 s
->cpu_ctlr
[cpu
] &= ~mask
;
470 s
->cpu_ctlr
[cpu
] |= (value
<< 1) & mask
;
472 if (s
->revision
== 2) {
473 mask
= s
->security_extn
? GICC_CTLR_V2_S_MASK
: GICC_CTLR_V2_MASK
;
475 mask
= s
->security_extn
? GICC_CTLR_V1_S_MASK
: GICC_CTLR_V1_MASK
;
477 s
->cpu_ctlr
[cpu
] = value
& mask
;
479 DPRINTF("CPU Interface %d: Group0 Interrupts %sabled, "
480 "Group1 Interrupts %sabled\n", cpu
,
481 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP0
) ? "En" : "Dis",
482 (s
->cpu_ctlr
[cpu
] & GICC_CTLR_EN_GRP1
) ? "En" : "Dis");
485 static uint8_t gic_get_running_priority(GICState
*s
, int cpu
, MemTxAttrs attrs
)
487 if (s
->security_extn
&& !attrs
.secure
) {
488 if (s
->running_priority
[cpu
] & 0x80) {
489 /* Running priority in upper half of range: return the Non-secure
490 * view of the priority.
492 return s
->running_priority
[cpu
] << 1;
494 /* Running priority in lower half of range: RAZ */
498 return s
->running_priority
[cpu
];
502 void gic_complete_irq(GICState
*s
, int cpu
, int irq
, MemTxAttrs attrs
)
507 DPRINTF("EOI %d\n", irq
);
508 if (irq
>= s
->num_irq
) {
509 /* This handles two cases:
510 * 1. If software writes the ID of a spurious interrupt [ie 1023]
511 * to the GICC_EOIR, the GIC ignores that write.
512 * 2. If software writes the number of a non-existent interrupt
513 * this must be a subcase of "value written does not match the last
514 * valid interrupt value read from the Interrupt Acknowledge
515 * register" and so this is UNPREDICTABLE. We choose to ignore it.
519 if (s
->running_priority
[cpu
] == 0x100) {
520 return; /* No active IRQ. */
523 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
524 /* Mark level triggered interrupts as pending if they are still
526 if (!GIC_TEST_EDGE_TRIGGER(irq
) && GIC_TEST_ENABLED(irq
, cm
)
527 && GIC_TEST_LEVEL(irq
, cm
) && (GIC_TARGET(irq
) & cm
) != 0) {
528 DPRINTF("Set %d pending mask %x\n", irq
, cm
);
529 GIC_SET_PENDING(irq
, cm
);
533 group
= gic_has_groups(s
) && GIC_TEST_GROUP(irq
, cm
);
535 if (s
->security_extn
&& !attrs
.secure
&& !group
) {
536 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq
);
540 /* Secure EOI with GICC_CTLR.AckCtl == 0 when the IRQ is a Group 1
541 * interrupt is UNPREDICTABLE. We choose to handle it as if AckCtl == 1,
542 * i.e. go ahead and complete the irq anyway.
545 gic_drop_prio(s
, cpu
, group
);
546 GIC_CLEAR_ACTIVE(irq
, cm
);
550 static uint32_t gic_dist_readb(void *opaque
, hwaddr offset
, MemTxAttrs attrs
)
552 GICState
*s
= (GICState
*)opaque
;
560 cpu
= gic_get_current_cpu(s
);
562 if (offset
< 0x100) {
563 if (offset
== 0) { /* GICD_CTLR */
564 if (s
->security_extn
&& !attrs
.secure
) {
565 /* The NS bank of this register is just an alias of the
566 * EnableGrp1 bit in the S bank version.
568 return extract32(s
->ctlr
, 1, 1);
574 /* Interrupt Controller Type Register */
575 return ((s
->num_irq
/ 32) - 1)
576 | ((s
->num_cpu
- 1) << 5)
577 | (s
->security_extn
<< 10);
580 if (offset
>= 0x80) {
581 /* Interrupt Group Registers: these RAZ/WI if this is an NS
582 * access to a GIC with the security extensions, or if the GIC
583 * doesn't have groups at all.
586 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
587 /* Every byte offset holds 8 group status bits */
588 irq
= (offset
- 0x080) * 8 + GIC_BASE_IRQ
;
589 if (irq
>= s
->num_irq
) {
592 for (i
= 0; i
< 8; i
++) {
593 if (GIC_TEST_GROUP(irq
+ i
, cm
)) {
601 } else if (offset
< 0x200) {
602 /* Interrupt Set/Clear Enable. */
604 irq
= (offset
- 0x100) * 8;
606 irq
= (offset
- 0x180) * 8;
608 if (irq
>= s
->num_irq
)
611 for (i
= 0; i
< 8; i
++) {
612 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
616 } else if (offset
< 0x300) {
617 /* Interrupt Set/Clear Pending. */
619 irq
= (offset
- 0x200) * 8;
621 irq
= (offset
- 0x280) * 8;
623 if (irq
>= s
->num_irq
)
626 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
627 for (i
= 0; i
< 8; i
++) {
628 if (gic_test_pending(s
, irq
+ i
, mask
)) {
632 } else if (offset
< 0x400) {
633 /* Interrupt Active. */
634 irq
= (offset
- 0x300) * 8 + GIC_BASE_IRQ
;
635 if (irq
>= s
->num_irq
)
638 mask
= (irq
< GIC_INTERNAL
) ? cm
: ALL_CPU_MASK
;
639 for (i
= 0; i
< 8; i
++) {
640 if (GIC_TEST_ACTIVE(irq
+ i
, mask
)) {
644 } else if (offset
< 0x800) {
645 /* Interrupt Priority. */
646 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
647 if (irq
>= s
->num_irq
)
649 res
= gic_get_priority(s
, cpu
, irq
, attrs
);
650 } else if (offset
< 0xc00) {
651 /* Interrupt CPU Target. */
652 if (s
->num_cpu
== 1 && s
->revision
!= REV_11MPCORE
) {
653 /* For uniprocessor GICs these RAZ/WI */
656 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
657 if (irq
>= s
->num_irq
) {
660 if (irq
>= 29 && irq
<= 31) {
663 res
= GIC_TARGET(irq
);
666 } else if (offset
< 0xf00) {
667 /* Interrupt Configuration. */
668 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
669 if (irq
>= s
->num_irq
)
672 for (i
= 0; i
< 4; i
++) {
673 if (GIC_TEST_MODEL(irq
+ i
))
674 res
|= (1 << (i
* 2));
675 if (GIC_TEST_EDGE_TRIGGER(irq
+ i
))
676 res
|= (2 << (i
* 2));
678 } else if (offset
< 0xf10) {
680 } else if (offset
< 0xf30) {
681 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
685 if (offset
< 0xf20) {
686 /* GICD_CPENDSGIRn */
687 irq
= (offset
- 0xf10);
689 irq
= (offset
- 0xf20);
690 /* GICD_SPENDSGIRn */
693 res
= s
->sgi_pending
[irq
][cpu
];
694 } else if (offset
< 0xfd0) {
696 } else if (offset
< 0x1000) {
700 switch (s
->revision
) {
702 res
= gic_id_11mpcore
[(offset
- 0xfd0) >> 2];
705 res
= gic_id_gicv1
[(offset
- 0xfd0) >> 2];
708 res
= gic_id_gicv2
[(offset
- 0xfd0) >> 2];
711 /* Shouldn't be able to get here */
718 g_assert_not_reached();
722 qemu_log_mask(LOG_GUEST_ERROR
,
723 "gic_dist_readb: Bad offset %x\n", (int)offset
);
727 static MemTxResult
gic_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
728 unsigned size
, MemTxAttrs attrs
)
732 *data
= gic_dist_readb(opaque
, offset
, attrs
);
735 *data
= gic_dist_readb(opaque
, offset
, attrs
);
736 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
739 *data
= gic_dist_readb(opaque
, offset
, attrs
);
740 *data
|= gic_dist_readb(opaque
, offset
+ 1, attrs
) << 8;
741 *data
|= gic_dist_readb(opaque
, offset
+ 2, attrs
) << 16;
742 *data
|= gic_dist_readb(opaque
, offset
+ 3, attrs
) << 24;
749 static void gic_dist_writeb(void *opaque
, hwaddr offset
,
750 uint32_t value
, MemTxAttrs attrs
)
752 GICState
*s
= (GICState
*)opaque
;
757 cpu
= gic_get_current_cpu(s
);
758 if (offset
< 0x100) {
760 if (s
->security_extn
&& !attrs
.secure
) {
761 /* NS version is just an alias of the S version's bit 1 */
762 s
->ctlr
= deposit32(s
->ctlr
, 1, 1, value
);
763 } else if (gic_has_groups(s
)) {
764 s
->ctlr
= value
& (GICD_CTLR_EN_GRP0
| GICD_CTLR_EN_GRP1
);
766 s
->ctlr
= value
& GICD_CTLR_EN_GRP0
;
768 DPRINTF("Distributor: Group0 %sabled; Group 1 %sabled\n",
769 s
->ctlr
& GICD_CTLR_EN_GRP0
? "En" : "Dis",
770 s
->ctlr
& GICD_CTLR_EN_GRP1
? "En" : "Dis");
771 } else if (offset
< 4) {
773 } else if (offset
>= 0x80) {
774 /* Interrupt Group Registers: RAZ/WI for NS access to secure
775 * GIC, or for GICs without groups.
777 if (!(s
->security_extn
&& !attrs
.secure
) && gic_has_groups(s
)) {
778 /* Every byte offset holds 8 group status bits */
779 irq
= (offset
- 0x80) * 8 + GIC_BASE_IRQ
;
780 if (irq
>= s
->num_irq
) {
783 for (i
= 0; i
< 8; i
++) {
784 /* Group bits are banked for private interrupts */
785 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
786 if (value
& (1 << i
)) {
787 /* Group1 (Non-secure) */
788 GIC_SET_GROUP(irq
+ i
, cm
);
790 /* Group0 (Secure) */
791 GIC_CLEAR_GROUP(irq
+ i
, cm
);
798 } else if (offset
< 0x180) {
799 /* Interrupt Set Enable. */
800 irq
= (offset
- 0x100) * 8 + GIC_BASE_IRQ
;
801 if (irq
>= s
->num_irq
)
803 if (irq
< GIC_NR_SGIS
) {
807 for (i
= 0; i
< 8; i
++) {
808 if (value
& (1 << i
)) {
810 (irq
< GIC_INTERNAL
) ? (1 << cpu
) : GIC_TARGET(irq
+ i
);
811 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
813 if (!GIC_TEST_ENABLED(irq
+ i
, cm
)) {
814 DPRINTF("Enabled IRQ %d\n", irq
+ i
);
816 GIC_SET_ENABLED(irq
+ i
, cm
);
817 /* If a raised level triggered IRQ enabled then mark
819 if (GIC_TEST_LEVEL(irq
+ i
, mask
)
820 && !GIC_TEST_EDGE_TRIGGER(irq
+ i
)) {
821 DPRINTF("Set %d pending mask %x\n", irq
+ i
, mask
);
822 GIC_SET_PENDING(irq
+ i
, mask
);
826 } else if (offset
< 0x200) {
827 /* Interrupt Clear Enable. */
828 irq
= (offset
- 0x180) * 8 + GIC_BASE_IRQ
;
829 if (irq
>= s
->num_irq
)
831 if (irq
< GIC_NR_SGIS
) {
835 for (i
= 0; i
< 8; i
++) {
836 if (value
& (1 << i
)) {
837 int cm
= (irq
< GIC_INTERNAL
) ? (1 << cpu
) : ALL_CPU_MASK
;
839 if (GIC_TEST_ENABLED(irq
+ i
, cm
)) {
840 DPRINTF("Disabled IRQ %d\n", irq
+ i
);
842 GIC_CLEAR_ENABLED(irq
+ i
, cm
);
845 } else if (offset
< 0x280) {
846 /* Interrupt Set Pending. */
847 irq
= (offset
- 0x200) * 8 + GIC_BASE_IRQ
;
848 if (irq
>= s
->num_irq
)
850 if (irq
< GIC_NR_SGIS
) {
854 for (i
= 0; i
< 8; i
++) {
855 if (value
& (1 << i
)) {
856 GIC_SET_PENDING(irq
+ i
, GIC_TARGET(irq
+ i
));
859 } else if (offset
< 0x300) {
860 /* Interrupt Clear Pending. */
861 irq
= (offset
- 0x280) * 8 + GIC_BASE_IRQ
;
862 if (irq
>= s
->num_irq
)
864 if (irq
< GIC_NR_SGIS
) {
868 for (i
= 0; i
< 8; i
++) {
869 /* ??? This currently clears the pending bit for all CPUs, even
870 for per-CPU interrupts. It's unclear whether this is the
872 if (value
& (1 << i
)) {
873 GIC_CLEAR_PENDING(irq
+ i
, ALL_CPU_MASK
);
876 } else if (offset
< 0x400) {
877 /* Interrupt Active. */
879 } else if (offset
< 0x800) {
880 /* Interrupt Priority. */
881 irq
= (offset
- 0x400) + GIC_BASE_IRQ
;
882 if (irq
>= s
->num_irq
)
884 gic_set_priority(s
, cpu
, irq
, value
, attrs
);
885 } else if (offset
< 0xc00) {
886 /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
887 * annoying exception of the 11MPCore's GIC.
889 if (s
->num_cpu
!= 1 || s
->revision
== REV_11MPCORE
) {
890 irq
= (offset
- 0x800) + GIC_BASE_IRQ
;
891 if (irq
>= s
->num_irq
) {
896 } else if (irq
< GIC_INTERNAL
) {
897 value
= ALL_CPU_MASK
;
899 s
->irq_target
[irq
] = value
& ALL_CPU_MASK
;
901 } else if (offset
< 0xf00) {
902 /* Interrupt Configuration. */
903 irq
= (offset
- 0xc00) * 4 + GIC_BASE_IRQ
;
904 if (irq
>= s
->num_irq
)
906 if (irq
< GIC_NR_SGIS
)
908 for (i
= 0; i
< 4; i
++) {
909 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
910 if (value
& (1 << (i
* 2))) {
911 GIC_SET_MODEL(irq
+ i
);
913 GIC_CLEAR_MODEL(irq
+ i
);
916 if (value
& (2 << (i
* 2))) {
917 GIC_SET_EDGE_TRIGGER(irq
+ i
);
919 GIC_CLEAR_EDGE_TRIGGER(irq
+ i
);
922 } else if (offset
< 0xf10) {
923 /* 0xf00 is only handled for 32-bit writes. */
925 } else if (offset
< 0xf20) {
926 /* GICD_CPENDSGIRn */
927 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
930 irq
= (offset
- 0xf10);
932 s
->sgi_pending
[irq
][cpu
] &= ~value
;
933 if (s
->sgi_pending
[irq
][cpu
] == 0) {
934 GIC_CLEAR_PENDING(irq
, 1 << cpu
);
936 } else if (offset
< 0xf30) {
937 /* GICD_SPENDSGIRn */
938 if (s
->revision
== REV_11MPCORE
|| s
->revision
== REV_NVIC
) {
941 irq
= (offset
- 0xf20);
943 GIC_SET_PENDING(irq
, 1 << cpu
);
944 s
->sgi_pending
[irq
][cpu
] |= value
;
951 qemu_log_mask(LOG_GUEST_ERROR
,
952 "gic_dist_writeb: Bad offset %x\n", (int)offset
);
955 static void gic_dist_writew(void *opaque
, hwaddr offset
,
956 uint32_t value
, MemTxAttrs attrs
)
958 gic_dist_writeb(opaque
, offset
, value
& 0xff, attrs
);
959 gic_dist_writeb(opaque
, offset
+ 1, value
>> 8, attrs
);
962 static void gic_dist_writel(void *opaque
, hwaddr offset
,
963 uint32_t value
, MemTxAttrs attrs
)
965 GICState
*s
= (GICState
*)opaque
;
966 if (offset
== 0xf00) {
972 cpu
= gic_get_current_cpu(s
);
974 switch ((value
>> 24) & 3) {
976 mask
= (value
>> 16) & ALL_CPU_MASK
;
979 mask
= ALL_CPU_MASK
^ (1 << cpu
);
985 DPRINTF("Bad Soft Int target filter\n");
989 GIC_SET_PENDING(irq
, mask
);
990 target_cpu
= ctz32(mask
);
991 while (target_cpu
< GIC_NCPU
) {
992 s
->sgi_pending
[irq
][target_cpu
] |= (1 << cpu
);
993 mask
&= ~(1 << target_cpu
);
994 target_cpu
= ctz32(mask
);
999 gic_dist_writew(opaque
, offset
, value
& 0xffff, attrs
);
1000 gic_dist_writew(opaque
, offset
+ 2, value
>> 16, attrs
);
1003 static MemTxResult
gic_dist_write(void *opaque
, hwaddr offset
, uint64_t data
,
1004 unsigned size
, MemTxAttrs attrs
)
1008 gic_dist_writeb(opaque
, offset
, data
, attrs
);
1011 gic_dist_writew(opaque
, offset
, data
, attrs
);
1014 gic_dist_writel(opaque
, offset
, data
, attrs
);
1021 static inline uint32_t gic_apr_ns_view(GICState
*s
, int cpu
, int regno
)
1023 /* Return the Nonsecure view of GICC_APR<regno>. This is the
1024 * second half of GICC_NSAPR.
1026 switch (GIC_MIN_BPR
) {
1029 return s
->nsapr
[regno
+ 2][cpu
];
1034 return s
->nsapr
[regno
+ 1][cpu
];
1039 return extract32(s
->nsapr
[0][cpu
], 16, 16);
1044 return extract32(s
->nsapr
[0][cpu
], 8, 8);
1048 g_assert_not_reached();
1053 static inline void gic_apr_write_ns_view(GICState
*s
, int cpu
, int regno
,
1056 /* Write the Nonsecure view of GICC_APR<regno>. */
1057 switch (GIC_MIN_BPR
) {
1060 s
->nsapr
[regno
+ 2][cpu
] = value
;
1065 s
->nsapr
[regno
+ 1][cpu
] = value
;
1070 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 16, 16, value
);
1075 s
->nsapr
[0][cpu
] = deposit32(s
->nsapr
[0][cpu
], 8, 8, value
);
1079 g_assert_not_reached();
1083 static MemTxResult
gic_cpu_read(GICState
*s
, int cpu
, int offset
,
1084 uint64_t *data
, MemTxAttrs attrs
)
1087 case 0x00: /* Control */
1088 *data
= gic_get_cpu_control(s
, cpu
, attrs
);
1090 case 0x04: /* Priority mask */
1091 *data
= gic_get_priority_mask(s
, cpu
, attrs
);
1093 case 0x08: /* Binary Point */
1094 if (s
->security_extn
&& !attrs
.secure
) {
1095 /* BPR is banked. Non-secure copy stored in ABPR. */
1096 *data
= s
->abpr
[cpu
];
1098 *data
= s
->bpr
[cpu
];
1101 case 0x0c: /* Acknowledge */
1102 *data
= gic_acknowledge_irq(s
, cpu
, attrs
);
1104 case 0x14: /* Running Priority */
1105 *data
= gic_get_running_priority(s
, cpu
, attrs
);
1107 case 0x18: /* Highest Pending Interrupt */
1108 *data
= gic_get_current_pending_irq(s
, cpu
, attrs
);
1110 case 0x1c: /* Aliased Binary Point */
1111 /* GIC v2, no security: ABPR
1112 * GIC v1, no security: not implemented (RAZ/WI)
1113 * With security extensions, secure access: ABPR (alias of NS BPR)
1114 * With security extensions, nonsecure access: RAZ/WI
1116 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1119 *data
= s
->abpr
[cpu
];
1122 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1124 int regno
= (offset
- 0xd0) / 4;
1126 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1128 } else if (s
->security_extn
&& !attrs
.secure
) {
1129 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1130 *data
= gic_apr_ns_view(s
, regno
, cpu
);
1132 *data
= s
->apr
[regno
][cpu
];
1136 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1138 int regno
= (offset
- 0xe0) / 4;
1140 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2 || !gic_has_groups(s
) ||
1141 (s
->security_extn
&& !attrs
.secure
)) {
1144 *data
= s
->nsapr
[regno
][cpu
];
1149 qemu_log_mask(LOG_GUEST_ERROR
,
1150 "gic_cpu_read: Bad offset %x\n", (int)offset
);
1156 static MemTxResult
gic_cpu_write(GICState
*s
, int cpu
, int offset
,
1157 uint32_t value
, MemTxAttrs attrs
)
1160 case 0x00: /* Control */
1161 gic_set_cpu_control(s
, cpu
, value
, attrs
);
1163 case 0x04: /* Priority mask */
1164 gic_set_priority_mask(s
, cpu
, value
, attrs
);
1166 case 0x08: /* Binary Point */
1167 if (s
->security_extn
&& !attrs
.secure
) {
1168 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1170 s
->bpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_BPR
);
1173 case 0x10: /* End Of Interrupt */
1174 gic_complete_irq(s
, cpu
, value
& 0x3ff, attrs
);
1176 case 0x1c: /* Aliased Binary Point */
1177 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1178 /* unimplemented, or NS access: RAZ/WI */
1181 s
->abpr
[cpu
] = MAX(value
& 0x7, GIC_MIN_ABPR
);
1184 case 0xd0: case 0xd4: case 0xd8: case 0xdc:
1186 int regno
= (offset
- 0xd0) / 4;
1188 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1191 if (s
->security_extn
&& !attrs
.secure
) {
1192 /* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
1193 gic_apr_write_ns_view(s
, regno
, cpu
, value
);
1195 s
->apr
[regno
][cpu
] = value
;
1199 case 0xe0: case 0xe4: case 0xe8: case 0xec:
1201 int regno
= (offset
- 0xe0) / 4;
1203 if (regno
>= GIC_NR_APRS
|| s
->revision
!= 2) {
1206 if (!gic_has_groups(s
) || (s
->security_extn
&& !attrs
.secure
)) {
1209 s
->nsapr
[regno
][cpu
] = value
;
1213 qemu_log_mask(LOG_GUEST_ERROR
,
1214 "gic_cpu_write: Bad offset %x\n", (int)offset
);
1221 /* Wrappers to read/write the GIC CPU interface for the current CPU */
1222 static MemTxResult
gic_thiscpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1223 unsigned size
, MemTxAttrs attrs
)
1225 GICState
*s
= (GICState
*)opaque
;
1226 return gic_cpu_read(s
, gic_get_current_cpu(s
), addr
, data
, attrs
);
1229 static MemTxResult
gic_thiscpu_write(void *opaque
, hwaddr addr
,
1230 uint64_t value
, unsigned size
,
1233 GICState
*s
= (GICState
*)opaque
;
1234 return gic_cpu_write(s
, gic_get_current_cpu(s
), addr
, value
, attrs
);
1237 /* Wrappers to read/write the GIC CPU interface for a specific CPU.
1238 * These just decode the opaque pointer into GICState* + cpu id.
1240 static MemTxResult
gic_do_cpu_read(void *opaque
, hwaddr addr
, uint64_t *data
,
1241 unsigned size
, MemTxAttrs attrs
)
1243 GICState
**backref
= (GICState
**)opaque
;
1244 GICState
*s
= *backref
;
1245 int id
= (backref
- s
->backref
);
1246 return gic_cpu_read(s
, id
, addr
, data
, attrs
);
1249 static MemTxResult
gic_do_cpu_write(void *opaque
, hwaddr addr
,
1250 uint64_t value
, unsigned size
,
1253 GICState
**backref
= (GICState
**)opaque
;
1254 GICState
*s
= *backref
;
1255 int id
= (backref
- s
->backref
);
1256 return gic_cpu_write(s
, id
, addr
, value
, attrs
);
1259 static const MemoryRegionOps gic_ops
[2] = {
1261 .read_with_attrs
= gic_dist_read
,
1262 .write_with_attrs
= gic_dist_write
,
1263 .endianness
= DEVICE_NATIVE_ENDIAN
,
1266 .read_with_attrs
= gic_thiscpu_read
,
1267 .write_with_attrs
= gic_thiscpu_write
,
1268 .endianness
= DEVICE_NATIVE_ENDIAN
,
1272 static const MemoryRegionOps gic_cpu_ops
= {
1273 .read_with_attrs
= gic_do_cpu_read
,
1274 .write_with_attrs
= gic_do_cpu_write
,
1275 .endianness
= DEVICE_NATIVE_ENDIAN
,
1278 /* This function is used by nvic model */
1279 void gic_init_irqs_and_distributor(GICState
*s
)
1281 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1284 static void arm_gic_realize(DeviceState
*dev
, Error
**errp
)
1286 /* Device instance realize function for the GIC sysbus device */
1288 GICState
*s
= ARM_GIC(dev
);
1289 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
1290 ARMGICClass
*agc
= ARM_GIC_GET_CLASS(s
);
1291 Error
*local_err
= NULL
;
1293 agc
->parent_realize(dev
, &local_err
);
1295 error_propagate(errp
, local_err
);
1299 /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
1300 gic_init_irqs_and_mmio(s
, gic_set_irq
, gic_ops
);
1302 /* Extra core-specific regions for the CPU interfaces. This is
1303 * necessary for "franken-GIC" implementations, for example on
1305 * NB that the memory region size of 0x100 applies for the 11MPCore
1306 * and also cores following the GIC v1 spec (ie A9).
1307 * GIC v2 defines a larger memory region (0x1000) so this will need
1308 * to be extended when we implement A15.
1310 for (i
= 0; i
< s
->num_cpu
; i
++) {
1312 memory_region_init_io(&s
->cpuiomem
[i
+1], OBJECT(s
), &gic_cpu_ops
,
1313 &s
->backref
[i
], "gic_cpu", 0x100);
1314 sysbus_init_mmio(sbd
, &s
->cpuiomem
[i
+1]);
1318 static void arm_gic_class_init(ObjectClass
*klass
, void *data
)
1320 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1321 ARMGICClass
*agc
= ARM_GIC_CLASS(klass
);
1323 agc
->parent_realize
= dc
->realize
;
1324 dc
->realize
= arm_gic_realize
;
1327 static const TypeInfo arm_gic_info
= {
1328 .name
= TYPE_ARM_GIC
,
1329 .parent
= TYPE_ARM_GIC_COMMON
,
1330 .instance_size
= sizeof(GICState
),
1331 .class_init
= arm_gic_class_init
,
1332 .class_size
= sizeof(ARMGICClass
),
1335 static void arm_gic_register_types(void)
1337 type_register_static(&arm_gic_info
);
1340 type_init(arm_gic_register_types
)