hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32
  33 /*
  34  * I440FX chipset data sheet.
  35  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  36  */
  37
  38 typedef PCIHostState I440FXState;
  39
  40 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  41 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  42 #define PIIX_PIRQC              0x60
  43
  44 typedef struct PIIX3State {
  45     PCIDevice dev;
  46
  47     /*
  48      * bitmap to track pic levels.
  49      * The pic level is the logical OR of all the PCI irqs mapped to it
  50      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  51      *
  52      * PIRQ is mapped to PIC pins, we track it by
  53      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  54      * pic_irq * PIIX_NUM_PIRQS + pirq
  55      */
  56 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  57 #error "unable to encode pic state in 64bit in pic_levels."
  58 #endif
  59     uint64_t pic_levels;
  60
  61     qemu_irq *pic;
  62
  63     /* This member isn't used. Just for save/load compatibility */
  64     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  65 } PIIX3State;
  66
  67 struct PCII440FXState {
  68     PCIDevice dev;
  69     target_phys_addr_t isa_page_descs[384 / 4];
  70     uint8_t smm_enabled;
  71     PIIX3State *piix3;
  72 };
  73
  74
  75 #define I440FX_PAM      0x59
  76 #define I440FX_PAM_SIZE 7
  77 #define I440FX_SMRAM    0x72
  78
  79 static void piix3_set_irq(void *opaque, int pirq, int level);
  80
  81 /* return the global irq number corresponding to a given device irq
  82    pin. We could also use the bus number to have a more precise
  83    mapping. */
  84 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
  85 {
  86     int slot_addend;
  87     slot_addend = (pci_dev->devfn >> 3) - 1;
  88     return (pci_intx + slot_addend) & 3;
  89 }
  90
  91 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  92 {
  93     uint32_t addr;
  94
  95     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  96     switch(r) {
  97     case 3:
  98         /* RAM */
  99         cpu_register_physical_memory(start, end - start,
 100                                      start);
 101         break;
 102     case 1:
 103         /* ROM (XXX: not quite correct) */
 104         cpu_register_physical_memory(start, end - start,
 105                                      start | IO_MEM_ROM);
 106         break;
 107     case 2:
 108     case 0:
 109         /* XXX: should distinguish read/write cases */
 110         for(addr = start; addr < end; addr += 4096) {
 111             cpu_register_physical_memory(addr, 4096,
 112                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 113         }
 114         break;
 115     }
 116 }
 117
 118 static void i440fx_update_memory_mappings(PCII440FXState *d)
 119 {
 120     int i, r;
 121     uint32_t smram, addr;
 122
 123     update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3);
 124     for(i = 0; i < 12; i++) {
 125         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 126         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 127     }
 128     smram = d->dev.config[I440FX_SMRAM];
 129     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 130         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 131     } else {
 132         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 133             cpu_register_physical_memory(addr, 4096,
 134                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 135         }
 136     }
 137 }
 138
 139 static void i440fx_set_smm(int val, void *arg)
 140 {
 141     PCII440FXState *d = arg;
 142
 143     val = (val != 0);
 144     if (d->smm_enabled != val) {
 145         d->smm_enabled = val;
 146         i440fx_update_memory_mappings(d);
 147     }
 148 }
 149
 150
 151 /* XXX: suppress when better memory API. We make the assumption that
 152    no device (in particular the VGA) changes the memory mappings in
 153    the 0xa0000-0x100000 range */
 154 void i440fx_init_memory_mappings(PCII440FXState *d)
 155 {
 156     int i;
 157     for(i = 0; i < 96; i++) {
 158         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 159     }
 160 }
 161
 162 static void i440fx_write_config(PCIDevice *dev,
 163                                 uint32_t address, uint32_t val, int len)
 164 {
 165     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 166
 167     /* XXX: implement SMRAM.D_LOCK */
 168     pci_default_write_config(dev, address, val, len);
 169     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 170         range_covers_byte(address, len, I440FX_SMRAM)) {
 171         i440fx_update_memory_mappings(d);
 172     }
 173 }
 174
 175 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 176 {
 177     PCII440FXState *d = opaque;
 178     int ret, i;
 179
 180     ret = pci_device_load(&d->dev, f);
 181     if (ret < 0)
 182         return ret;
 183     i440fx_update_memory_mappings(d);
 184     qemu_get_8s(f, &d->smm_enabled);
 185
 186     if (version_id == 2) {
 187         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 188             qemu_get_be32(f); /* dummy load for compatibility */
 189         }
 190     }
 191
 192     return 0;
 193 }
 194
 195 static int i440fx_post_load(void *opaque, int version_id)
 196 {
 197     PCII440FXState *d = opaque;
 198
 199     i440fx_update_memory_mappings(d);
 200     return 0;
 201 }
 202
 203 static const VMStateDescription vmstate_i440fx = {
 204     .name = "I440FX",
 205     .version_id = 3,
 206     .minimum_version_id = 3,
 207     .minimum_version_id_old = 1,
 208     .load_state_old = i440fx_load_old,
 209     .post_load = i440fx_post_load,
 210     .fields      = (VMStateField []) {
 211         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 212         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 213         VMSTATE_END_OF_LIST()
 214     }
 215 };
 216
 217 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 218 {
 219     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 220
 221     pci_host_conf_register_ioport(0xcf8, s);
 222
 223     pci_host_data_register_ioport(0xcfc, s);
 224     return 0;
 225 }
 226
 227 static int i440fx_initfn(PCIDevice *dev)
 228 {
 229     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 230
 231     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 232     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 233     d->dev.config[0x08] = 0x02; // revision
 234     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 235
 236     d->dev.config[I440FX_SMRAM] = 0x02;
 237
 238     cpu_smm_register(&i440fx_set_smm, d);
 239     return 0;
 240 }
 241
 242 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, ram_addr_t ram_size)
 243 {
 244     DeviceState *dev;
 245     PCIBus *b;
 246     PCIDevice *d;
 247     I440FXState *s;
 248     PIIX3State *piix3;
 249
 250     dev = qdev_create(NULL, "i440FX-pcihost");
 251     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 252     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 253     s->bus = b;
 254     qdev_init_nofail(dev);
 255
 256     d = pci_create_simple(b, 0, "i440FX");
 257     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 258
 259     piix3 = DO_UPCAST(PIIX3State, dev,
 260                       pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 261     piix3->pic = pic;
 262     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, PIIX_NUM_PIRQS);
 263     (*pi440fx_state)->piix3 = piix3;
 264
 265     *piix3_devfn = piix3->dev.devfn;
 266
 267     ram_size = ram_size / 8 / 1024 / 1024;
 268     if (ram_size > 255)
 269         ram_size = 255;
 270     (*pi440fx_state)->dev.config[0x57]=ram_size;
 271
 272     return b;
 273 }
 274
 275 /* PIIX3 PCI to ISA bridge */
 276 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 277 {
 278     qemu_set_irq(piix3->pic[pic_irq],
 279                  !!(piix3->pic_levels &
 280                     (((1UL << PIIX_NUM_PIRQS) - 1) <<
 281                      (pic_irq * PIIX_NUM_PIRQS))));
 282 }
 283
 284 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 285 {
 286     int pic_irq;
 287     uint64_t mask;
 288
 289     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 290     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 291         return;
 292     }
 293
 294     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 295     piix3->pic_levels &= ~mask;
 296     piix3->pic_levels |= mask * !!level;
 297
 298     piix3_set_irq_pic(piix3, pic_irq);
 299 }
 300
 301 static void piix3_set_irq(void *opaque, int pirq, int level)
 302 {
 303     PIIX3State *piix3 = opaque;
 304     piix3_set_irq_level(piix3, pirq, level);
 305 }
 306
 307 /* irq routing is changed. so rebuild bitmap */
 308 static void piix3_update_irq_levels(PIIX3State *piix3)
 309 {
 310     int pirq;
 311
 312     piix3->pic_levels = 0;
 313     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 314         piix3_set_irq_level(piix3, pirq,
 315                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 316     }
 317 }
 318
 319 static void piix3_write_config(PCIDevice *dev,
 320                                uint32_t address, uint32_t val, int len)
 321 {
 322     pci_default_write_config(dev, address, val, len);
 323     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 324         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 325         int pic_irq;
 326         piix3_update_irq_levels(piix3);
 327         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 328             piix3_set_irq_pic(piix3, pic_irq);
 329         }
 330     }
 331 }
 332
 333 static void piix3_reset(void *opaque)
 334 {
 335     PIIX3State *d = opaque;
 336     uint8_t *pci_conf = d->dev.config;
 337
 338     pci_conf[0x04] = 0x07; // master, memory and I/O
 339     pci_conf[0x05] = 0x00;
 340     pci_conf[0x06] = 0x00;
 341     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 342     pci_conf[0x4c] = 0x4d;
 343     pci_conf[0x4e] = 0x03;
 344     pci_conf[0x4f] = 0x00;
 345     pci_conf[0x60] = 0x80;
 346     pci_conf[0x61] = 0x80;
 347     pci_conf[0x62] = 0x80;
 348     pci_conf[0x63] = 0x80;
 349     pci_conf[0x69] = 0x02;
 350     pci_conf[0x70] = 0x80;
 351     pci_conf[0x76] = 0x0c;
 352     pci_conf[0x77] = 0x0c;
 353     pci_conf[0x78] = 0x02;
 354     pci_conf[0x79] = 0x00;
 355     pci_conf[0x80] = 0x00;
 356     pci_conf[0x82] = 0x00;
 357     pci_conf[0xa0] = 0x08;
 358     pci_conf[0xa2] = 0x00;
 359     pci_conf[0xa3] = 0x00;
 360     pci_conf[0xa4] = 0x00;
 361     pci_conf[0xa5] = 0x00;
 362     pci_conf[0xa6] = 0x00;
 363     pci_conf[0xa7] = 0x00;
 364     pci_conf[0xa8] = 0x0f;
 365     pci_conf[0xaa] = 0x00;
 366     pci_conf[0xab] = 0x00;
 367     pci_conf[0xac] = 0x00;
 368     pci_conf[0xae] = 0x00;
 369
 370     d->pic_levels = 0;
 371 }
 372
 373 static int piix3_post_load(void *opaque, int version_id)
 374 {
 375     PIIX3State *piix3 = opaque;
 376     piix3_update_irq_levels(piix3);
 377     return 0;
 378 }
 379
 380 static void piix3_pre_save(void *opaque)
 381 {
 382     int i;
 383     PIIX3State *piix3 = opaque;
 384
 385     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 386         piix3->pci_irq_levels_vmstate[i] =
 387             pci_bus_get_irq_level(piix3->dev.bus, i);
 388     }
 389 }
 390
 391 static const VMStateDescription vmstate_piix3 = {
 392     .name = "PIIX3",
 393     .version_id = 3,
 394     .minimum_version_id = 2,
 395     .minimum_version_id_old = 2,
 396     .post_load = piix3_post_load,
 397     .pre_save = piix3_pre_save,
 398     .fields      = (VMStateField []) {
 399         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 400         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 401                               PIIX_NUM_PIRQS, 3),
 402         VMSTATE_END_OF_LIST()
 403     }
 404 };
 405
 406 static int piix3_initfn(PCIDevice *dev)
 407 {
 408     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 409     uint8_t *pci_conf;
 410
 411     isa_bus_new(&d->dev.qdev);
 412
 413     pci_conf = d->dev.config;
 414     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 415     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 416     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 417
 418     qemu_register_reset(piix3_reset, d);
 419     return 0;
 420 }
 421
 422 static PCIDeviceInfo i440fx_info[] = {
 423     {
 424         .qdev.name    = "i440FX",
 425         .qdev.desc    = "Host bridge",
 426         .qdev.size    = sizeof(PCII440FXState),
 427         .qdev.vmsd    = &vmstate_i440fx,
 428         .qdev.no_user = 1,
 429         .no_hotplug   = 1,
 430         .init         = i440fx_initfn,
 431         .config_write = i440fx_write_config,
 432     },{
 433         .qdev.name    = "PIIX3",
 434         .qdev.desc    = "ISA bridge",
 435         .qdev.size    = sizeof(PIIX3State),
 436         .qdev.vmsd    = &vmstate_piix3,
 437         .qdev.no_user = 1,
 438         .no_hotplug   = 1,
 439         .init         = piix3_initfn,
 440         .config_write = piix3_write_config,
 441     },{
 442         /* end of list */
 443     }
 444 };
 445
 446 static SysBusDeviceInfo i440fx_pcihost_info = {
 447     .init         = i440fx_pcihost_initfn,
 448     .qdev.name    = "i440FX-pcihost",
 449     .qdev.fw_name = "pci",
 450     .qdev.size    = sizeof(I440FXState),
 451     .qdev.no_user = 1,
 452 };
 453
 454 static void i440fx_register(void)
 455 {
 456     sysbus_register_withprop(&i440fx_pcihost_info);
 457     pci_qdev_register_many(i440fx_info);
 458 }
 459 device_init(i440fx_register);