2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qapi/error.h"
23 #include "sysemu/sysemu.h"
24 #include "sysemu/numa.h"
25 #include "sysemu/cpus.h"
27 #include "target/ppc/cpu.h"
29 #include "hw/ppc/fdt.h"
30 #include "hw/ppc/ppc.h"
31 #include "hw/ppc/pnv.h"
32 #include "hw/ppc/pnv_core.h"
33 #include "hw/loader.h"
34 #include "exec/address-spaces.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38 #include "hw/ipmi/ipmi.h"
39 #include "target/ppc/mmu-hash64.h"
41 #include "hw/ppc/xics.h"
42 #include "hw/ppc/pnv_xscom.h"
44 #include "hw/isa/isa.h"
45 #include "hw/char/serial.h"
46 #include "hw/timer/mc146818rtc.h"
50 #define FDT_MAX_SIZE (1 * MiB)
52 #define FW_FILE_NAME "skiboot.lid"
53 #define FW_LOAD_ADDR 0x0
54 #define FW_MAX_SIZE (4 * MiB)
56 #define KERNEL_LOAD_ADDR 0x20000000
57 #define KERNEL_MAX_SIZE (256 * MiB)
58 #define INITRD_LOAD_ADDR 0x60000000
59 #define INITRD_MAX_SIZE (256 * MiB)
61 static const char *pnv_chip_core_typename(const PnvChip
*o
)
63 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
64 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
65 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
66 const char *core_type
= object_class_get_name(object_class_by_name(s
));
72 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
73 * 4 * 4 sockets * 12 cores * 8 threads = 1536
79 * Memory nodes are created by hostboot, one for each range of memory
80 * that has a different "affinity". In practice, it means one range
83 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
86 uint64_t mem_reg_property
[2];
89 mem_reg_property
[0] = cpu_to_be64(start
);
90 mem_reg_property
[1] = cpu_to_be64(size
);
92 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
93 off
= fdt_add_subnode(fdt
, 0, mem_name
);
96 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
97 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
98 sizeof(mem_reg_property
))));
99 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
102 static int get_cpus_node(void *fdt
)
104 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
106 if (cpus_offset
< 0) {
107 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
109 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
110 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
118 * The PowerNV cores (and threads) need to use real HW ids and not an
119 * incremental index like it has been done on other platforms. This HW
120 * id is stored in the CPU PIR, it is used to create cpu nodes in the
121 * device tree, used in XSCOM to address cores and in interrupt
124 static void pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
126 PowerPCCPU
*cpu
= pc
->threads
[0];
127 CPUState
*cs
= CPU(cpu
);
128 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
129 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
130 CPUPPCState
*env
= &cpu
->env
;
131 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
132 uint32_t servers_prop
[smt_threads
];
134 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
135 0xffffffff, 0xffffffff};
136 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
137 uint32_t cpufreq
= 1000000000;
138 uint32_t page_sizes_prop
[64];
139 size_t page_sizes_prop_size
;
140 const uint8_t pa_features
[] = { 24, 0,
141 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
142 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
143 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
144 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
147 int cpus_offset
= get_cpus_node(fdt
);
149 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
150 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
154 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
156 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
157 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
158 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
160 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
161 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
162 env
->dcache_line_size
)));
163 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
164 env
->dcache_line_size
)));
165 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
166 env
->icache_line_size
)));
167 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
168 env
->icache_line_size
)));
170 if (pcc
->l1_dcache_size
) {
171 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
172 pcc
->l1_dcache_size
)));
174 warn_report("Unknown L1 dcache size for cpu");
176 if (pcc
->l1_icache_size
) {
177 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
178 pcc
->l1_icache_size
)));
180 warn_report("Unknown L1 icache size for cpu");
183 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
184 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
185 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", cpu
->hash64_opts
->slb_size
)));
186 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
187 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
189 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
190 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
193 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
194 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
195 segs
, sizeof(segs
))));
198 /* Advertise VMX/VSX (vector extensions) if available
199 * 0 / no property == no vector extensions
200 * 1 == VMX / Altivec available
201 * 2 == VSX available */
202 if (env
->insns_flags
& PPC_ALTIVEC
) {
203 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
205 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
208 /* Advertise DFP (Decimal Floating Point) if available
209 * 0 / no property == no DFP
210 * 1 == DFP available */
211 if (env
->insns_flags2
& PPC2_DFP
) {
212 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
215 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
216 sizeof(page_sizes_prop
));
217 if (page_sizes_prop_size
) {
218 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
219 page_sizes_prop
, page_sizes_prop_size
)));
222 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
223 pa_features
, sizeof(pa_features
))));
225 /* Build interrupt servers properties */
226 for (i
= 0; i
< smt_threads
; i
++) {
227 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
229 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
230 servers_prop
, sizeof(servers_prop
))));
233 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
236 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
238 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
239 uint32_t irange
[2], i
, rsize
;
243 irange
[0] = cpu_to_be32(pir
);
244 irange
[1] = cpu_to_be32(nr_threads
);
246 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
247 reg
= g_malloc(rsize
);
248 for (i
= 0; i
< nr_threads
; i
++) {
249 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
250 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
253 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
254 offset
= fdt_add_subnode(fdt
, 0, name
);
258 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
259 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
260 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
261 "PowerPC-External-Interrupt-Presentation")));
262 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
263 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
264 irange
, sizeof(irange
))));
265 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
266 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
270 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
272 const char *typename
= pnv_chip_core_typename(chip
);
273 size_t typesize
= object_type_get_instance_size(typename
);
276 pnv_dt_xscom(chip
, fdt
, 0);
278 for (i
= 0; i
< chip
->nr_cores
; i
++) {
279 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
281 pnv_dt_core(chip
, pnv_core
, fdt
);
283 /* Interrupt Control Presenters (ICP). One per core. */
284 pnv_dt_icp(chip
, fdt
, pnv_core
->pir
, CPU_CORE(pnv_core
)->nr_threads
);
287 if (chip
->ram_size
) {
288 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
292 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
294 const char *typename
= pnv_chip_core_typename(chip
);
295 size_t typesize
= object_type_get_instance_size(typename
);
298 pnv_dt_xscom(chip
, fdt
, 0);
300 for (i
= 0; i
< chip
->nr_cores
; i
++) {
301 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
303 pnv_dt_core(chip
, pnv_core
, fdt
);
306 if (chip
->ram_size
) {
307 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
310 pnv_dt_lpc(chip
, fdt
, 0);
313 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
315 uint32_t io_base
= d
->ioport_id
;
316 uint32_t io_regs
[] = {
318 cpu_to_be32(io_base
),
324 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
325 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
329 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
330 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
333 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
335 const char compatible
[] = "ns16550\0pnpPNP,501";
336 uint32_t io_base
= d
->ioport_id
;
337 uint32_t io_regs
[] = {
339 cpu_to_be32(io_base
),
345 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
346 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
350 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
351 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
352 sizeof(compatible
))));
354 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
355 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
356 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
357 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
358 fdt_get_phandle(fdt
, lpc_off
))));
360 /* This is needed by Linux */
361 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
364 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
366 const char compatible
[] = "bt\0ipmi-bt";
368 uint32_t io_regs
[] = {
370 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
377 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
378 io_regs
[1] = cpu_to_be32(io_base
);
380 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
382 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
383 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
387 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
388 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
389 sizeof(compatible
))));
391 /* Mark it as reserved to avoid Linux trying to claim it */
392 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
393 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
394 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
395 fdt_get_phandle(fdt
, lpc_off
))));
398 typedef struct ForeachPopulateArgs
{
401 } ForeachPopulateArgs
;
403 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
405 ForeachPopulateArgs
*args
= opaque
;
406 ISADevice
*d
= ISA_DEVICE(dev
);
408 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
409 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
410 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
411 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
412 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
413 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
415 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
422 /* The default LPC bus of a multichip system is on chip 0. It's
423 * recognized by the firmware (skiboot) using a "primary" property.
425 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
427 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
428 ForeachPopulateArgs args
= {
430 .offset
= isa_offset
,
433 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
435 /* ISA devices are not necessarily parented to the ISA bus so we
436 * can not use object_child_foreach() */
437 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
441 static void *pnv_dt_create(MachineState
*machine
)
443 const char plat_compat
[] = "qemu,powernv\0ibm,powernv";
444 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
450 fdt
= g_malloc0(FDT_MAX_SIZE
);
451 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
454 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
455 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
456 _FDT((fdt_setprop_string(fdt
, 0, "model",
457 "IBM PowerNV (emulated by qemu)")));
458 _FDT((fdt_setprop(fdt
, 0, "compatible", plat_compat
,
459 sizeof(plat_compat
))));
461 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
462 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
464 _FDT((fdt_property_string(fdt
, "system-id", buf
)));
468 off
= fdt_add_subnode(fdt
, 0, "chosen");
469 if (machine
->kernel_cmdline
) {
470 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
471 machine
->kernel_cmdline
)));
474 if (pnv
->initrd_size
) {
475 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
476 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
478 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
479 &start_prop
, sizeof(start_prop
))));
480 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
481 &end_prop
, sizeof(end_prop
))));
484 /* Populate device tree for each chip */
485 for (i
= 0; i
< pnv
->num_chips
; i
++) {
486 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
489 /* Populate ISA devices on chip 0 */
490 pnv_dt_isa(pnv
, fdt
);
493 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
499 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
501 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
504 pnv_bmc_powerdown(pnv
->bmc
);
508 static void pnv_reset(void)
510 MachineState
*machine
= MACHINE(qdev_get_machine());
511 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
515 qemu_devices_reset();
517 /* OpenPOWER systems have a BMC, which can be defined on the
520 * -device ipmi-bmc-sim,id=bmc0
522 * This is the internal simulator but it could also be an external
525 obj
= object_resolve_path_type("", "ipmi-bmc-sim", NULL
);
527 pnv
->bmc
= IPMI_BMC(obj
);
530 fdt
= pnv_dt_create(machine
);
532 /* Pack resulting tree */
533 _FDT((fdt_pack(fdt
)));
535 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
538 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
540 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
541 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
544 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
546 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
547 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
550 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
552 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
553 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
556 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
558 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
561 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
563 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
565 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
568 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
570 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
572 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
573 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
576 static void pnv_init(MachineState
*machine
)
578 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
586 if (machine
->ram_size
< (1 * GiB
)) {
587 warn_report("skiboot may not work with < 1GB of RAM");
590 ram
= g_new(MemoryRegion
, 1);
591 memory_region_allocate_system_memory(ram
, NULL
, "pnv.ram",
593 memory_region_add_subregion(get_system_memory(), 0, ram
);
595 /* load skiboot firmware */
596 if (bios_name
== NULL
) {
597 bios_name
= FW_FILE_NAME
;
600 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
602 error_report("Could not find OPAL firmware '%s'", bios_name
);
606 fw_size
= load_image_targphys(fw_filename
, FW_LOAD_ADDR
, FW_MAX_SIZE
);
608 error_report("Could not load OPAL firmware '%s'", fw_filename
);
614 if (machine
->kernel_filename
) {
617 kernel_size
= load_image_targphys(machine
->kernel_filename
,
618 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
619 if (kernel_size
< 0) {
620 error_report("Could not load kernel '%s'",
621 machine
->kernel_filename
);
627 if (machine
->initrd_filename
) {
628 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
629 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
630 pnv
->initrd_base
, INITRD_MAX_SIZE
);
631 if (pnv
->initrd_size
< 0) {
632 error_report("Could not load initial ram disk '%s'",
633 machine
->initrd_filename
);
638 /* Create the processor chips */
639 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
640 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
641 i
, machine
->cpu_type
);
642 if (!object_class_by_name(chip_typename
)) {
643 error_report("invalid CPU model '%.*s' for %s machine",
644 i
, machine
->cpu_type
, MACHINE_GET_CLASS(machine
)->name
);
648 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
649 for (i
= 0; i
< pnv
->num_chips
; i
++) {
651 Object
*chip
= object_new(chip_typename
);
653 pnv
->chips
[i
] = PNV_CHIP(chip
);
655 /* TODO: put all the memory in one node on chip 0 until we find a
656 * way to specify different ranges for each chip
659 object_property_set_int(chip
, machine
->ram_size
, "ram-size",
663 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", PNV_CHIP_HWID(i
));
664 object_property_add_child(OBJECT(pnv
), chip_name
, chip
, &error_fatal
);
665 object_property_set_int(chip
, PNV_CHIP_HWID(i
), "chip-id",
667 object_property_set_int(chip
, smp_cores
, "nr-cores", &error_fatal
);
668 object_property_set_bool(chip
, true, "realized", &error_fatal
);
670 g_free(chip_typename
);
672 /* Instantiate ISA bus on chip 0 */
673 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
675 /* Create serial port */
676 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
678 /* Create an RTC ISA device too */
679 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
681 /* OpenPOWER systems use a IPMI SEL Event message to notify the
682 * host to powerdown */
683 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
684 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
688 * 0:21 Reserved - Read as zeros
693 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
695 return (chip
->chip_id
<< 7) | (core_id
<< 3);
698 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
701 Error
*local_err
= NULL
;
703 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
705 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, XICS_FABRIC(qdev_get_machine()),
708 error_propagate(errp
, local_err
);
716 * 0:48 Reserved - Read as zeroes
719 * 56 Reserved - Read as zero
723 * We only care about the lower bits. uint32_t is fine for the moment.
725 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
727 return (chip
->chip_id
<< 8) | (core_id
<< 2);
730 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
733 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
734 Error
*local_err
= NULL
;
736 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
739 * The core creates its interrupt presenter but the XIVE interrupt
740 * controller object is initialized afterwards. Hopefully, it's
741 * only used at runtime.
743 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_ROUTER(&chip9
->xive
), errp
);
745 error_propagate(errp
, local_err
);
752 /* Allowed core identifiers on a POWER8 Processor Chip :
761 * <EX7,8 reserved> <reserved>
770 #define POWER8E_CORE_MASK (0x7070ull)
771 #define POWER8_CORE_MASK (0x7e7eull)
774 * POWER9 has 24 cores, ids starting at 0x0
776 #define POWER9_CORE_MASK (0xffffffffffffffull)
778 static void pnv_chip_power8_instance_init(Object
*obj
)
780 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
782 object_initialize_child(obj
, "psi", &chip8
->psi
, sizeof(chip8
->psi
),
783 TYPE_PNV8_PSI
, &error_abort
, NULL
);
784 object_property_add_const_link(OBJECT(&chip8
->psi
), "xics",
785 OBJECT(qdev_get_machine()), &error_abort
);
787 object_initialize_child(obj
, "lpc", &chip8
->lpc
, sizeof(chip8
->lpc
),
788 TYPE_PNV8_LPC
, &error_abort
, NULL
);
789 object_property_add_const_link(OBJECT(&chip8
->lpc
), "psi",
790 OBJECT(&chip8
->psi
), &error_abort
);
792 object_initialize_child(obj
, "occ", &chip8
->occ
, sizeof(chip8
->occ
),
793 TYPE_PNV8_OCC
, &error_abort
, NULL
);
794 object_property_add_const_link(OBJECT(&chip8
->occ
), "psi",
795 OBJECT(&chip8
->psi
), &error_abort
);
798 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
800 PnvChip
*chip
= PNV_CHIP(chip8
);
801 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
802 const char *typename
= pnv_chip_core_typename(chip
);
803 size_t typesize
= object_type_get_instance_size(typename
);
806 XICSFabric
*xi
= XICS_FABRIC(qdev_get_machine());
808 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
809 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
810 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip8
->icp_mmio
);
813 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
815 /* Map the ICP registers for each thread */
816 for (i
= 0; i
< chip
->nr_cores
; i
++) {
817 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
818 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
820 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
821 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
822 PnvICPState
*icp
= PNV_ICP(xics_icp_get(xi
, pir
));
824 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
830 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
832 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
833 PnvChip
*chip
= PNV_CHIP(dev
);
834 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
835 Pnv8Psi
*psi8
= &chip8
->psi
;
836 Error
*local_err
= NULL
;
838 pcc
->parent_realize(dev
, &local_err
);
840 error_propagate(errp
, local_err
);
844 /* Processor Service Interface (PSI) Host Bridge */
845 object_property_set_int(OBJECT(&chip8
->psi
), PNV_PSIHB_BASE(chip
),
846 "bar", &error_fatal
);
847 object_property_set_bool(OBJECT(&chip8
->psi
), true, "realized", &local_err
);
849 error_propagate(errp
, local_err
);
852 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
853 &PNV_PSI(psi8
)->xscom_regs
);
855 /* Create LPC controller */
856 object_property_set_bool(OBJECT(&chip8
->lpc
), true, "realized",
858 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
860 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
861 (uint64_t) PNV_XSCOM_BASE(chip
),
864 /* Interrupt Management Area. This is the memory region holding
865 * all the Interrupt Control Presenter (ICP) registers */
866 pnv_chip_icp_realize(chip8
, &local_err
);
868 error_propagate(errp
, local_err
);
872 /* Create the simplified OCC model */
873 object_property_set_bool(OBJECT(&chip8
->occ
), true, "realized", &local_err
);
875 error_propagate(errp
, local_err
);
878 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
881 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
883 DeviceClass
*dc
= DEVICE_CLASS(klass
);
884 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
886 k
->chip_type
= PNV_CHIP_POWER8E
;
887 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
888 k
->cores_mask
= POWER8E_CORE_MASK
;
889 k
->core_pir
= pnv_chip_core_pir_p8
;
890 k
->intc_create
= pnv_chip_power8_intc_create
;
891 k
->isa_create
= pnv_chip_power8_isa_create
;
892 k
->dt_populate
= pnv_chip_power8_dt_populate
;
893 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
894 k
->xscom_base
= 0x003fc0000000000ull
;
895 dc
->desc
= "PowerNV Chip POWER8E";
897 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
901 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
903 DeviceClass
*dc
= DEVICE_CLASS(klass
);
904 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
906 k
->chip_type
= PNV_CHIP_POWER8
;
907 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
908 k
->cores_mask
= POWER8_CORE_MASK
;
909 k
->core_pir
= pnv_chip_core_pir_p8
;
910 k
->intc_create
= pnv_chip_power8_intc_create
;
911 k
->isa_create
= pnv_chip_power8_isa_create
;
912 k
->dt_populate
= pnv_chip_power8_dt_populate
;
913 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
914 k
->xscom_base
= 0x003fc0000000000ull
;
915 dc
->desc
= "PowerNV Chip POWER8";
917 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
921 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
923 DeviceClass
*dc
= DEVICE_CLASS(klass
);
924 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
926 k
->chip_type
= PNV_CHIP_POWER8NVL
;
927 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
928 k
->cores_mask
= POWER8_CORE_MASK
;
929 k
->core_pir
= pnv_chip_core_pir_p8
;
930 k
->intc_create
= pnv_chip_power8_intc_create
;
931 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
932 k
->dt_populate
= pnv_chip_power8_dt_populate
;
933 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
934 k
->xscom_base
= 0x003fc0000000000ull
;
935 dc
->desc
= "PowerNV Chip POWER8NVL";
937 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
941 static void pnv_chip_power9_instance_init(Object
*obj
)
943 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
945 object_initialize_child(obj
, "xive", &chip9
->xive
, sizeof(chip9
->xive
),
946 TYPE_PNV_XIVE
, &error_abort
, NULL
);
947 object_property_add_const_link(OBJECT(&chip9
->xive
), "chip", obj
,
950 object_initialize_child(obj
, "psi", &chip9
->psi
, sizeof(chip9
->psi
),
951 TYPE_PNV9_PSI
, &error_abort
, NULL
);
952 object_property_add_const_link(OBJECT(&chip9
->psi
), "chip", obj
,
955 object_initialize_child(obj
, "lpc", &chip9
->lpc
, sizeof(chip9
->lpc
),
956 TYPE_PNV9_LPC
, &error_abort
, NULL
);
957 object_property_add_const_link(OBJECT(&chip9
->lpc
), "psi",
958 OBJECT(&chip9
->psi
), &error_abort
);
961 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
963 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
964 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
965 PnvChip
*chip
= PNV_CHIP(dev
);
966 Pnv9Psi
*psi9
= &chip9
->psi
;
967 Error
*local_err
= NULL
;
969 pcc
->parent_realize(dev
, &local_err
);
971 error_propagate(errp
, local_err
);
975 /* XIVE interrupt controller (POWER9) */
976 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_IC_BASE(chip
),
977 "ic-bar", &error_fatal
);
978 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_VC_BASE(chip
),
979 "vc-bar", &error_fatal
);
980 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_PC_BASE(chip
),
981 "pc-bar", &error_fatal
);
982 object_property_set_int(OBJECT(&chip9
->xive
), PNV9_XIVE_TM_BASE(chip
),
983 "tm-bar", &error_fatal
);
984 object_property_set_bool(OBJECT(&chip9
->xive
), true, "realized",
987 error_propagate(errp
, local_err
);
990 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
991 &chip9
->xive
.xscom_regs
);
993 /* Processor Service Interface (PSI) Host Bridge */
994 object_property_set_int(OBJECT(&chip9
->psi
), PNV9_PSIHB_BASE(chip
),
995 "bar", &error_fatal
);
996 object_property_set_bool(OBJECT(&chip9
->psi
), true, "realized", &local_err
);
998 error_propagate(errp
, local_err
);
1001 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1002 &PNV_PSI(psi9
)->xscom_regs
);
1005 object_property_set_bool(OBJECT(&chip9
->lpc
), true, "realized", &local_err
);
1007 error_propagate(errp
, local_err
);
1010 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1011 &chip9
->lpc
.xscom_regs
);
1013 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1014 (uint64_t) PNV9_LPCM_BASE(chip
));
1017 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1019 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1020 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1022 k
->chip_type
= PNV_CHIP_POWER9
;
1023 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1024 k
->cores_mask
= POWER9_CORE_MASK
;
1025 k
->core_pir
= pnv_chip_core_pir_p9
;
1026 k
->intc_create
= pnv_chip_power9_intc_create
;
1027 k
->isa_create
= pnv_chip_power9_isa_create
;
1028 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1029 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1030 k
->xscom_base
= 0x00603fc00000000ull
;
1031 dc
->desc
= "PowerNV Chip POWER9";
1033 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1034 &k
->parent_realize
);
1037 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
1039 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1043 * No custom mask for this chip, let's use the default one from *
1046 if (!chip
->cores_mask
) {
1047 chip
->cores_mask
= pcc
->cores_mask
;
1050 /* filter alien core ids ! some are reserved */
1051 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
1052 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
1056 chip
->cores_mask
&= pcc
->cores_mask
;
1058 /* now that we have a sane layout, let check the number of cores */
1059 cores_max
= ctpop64(chip
->cores_mask
);
1060 if (chip
->nr_cores
> cores_max
) {
1061 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
1067 static void pnv_chip_instance_init(Object
*obj
)
1069 PNV_CHIP(obj
)->xscom_base
= PNV_CHIP_GET_CLASS(obj
)->xscom_base
;
1072 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
1074 Error
*error
= NULL
;
1075 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1076 const char *typename
= pnv_chip_core_typename(chip
);
1077 size_t typesize
= object_type_get_instance_size(typename
);
1080 if (!object_class_by_name(typename
)) {
1081 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
1086 pnv_chip_core_sanitize(chip
, &error
);
1088 error_propagate(errp
, error
);
1092 chip
->cores
= g_malloc0(typesize
* chip
->nr_cores
);
1094 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
1095 && (i
< chip
->nr_cores
); core_hwid
++) {
1097 void *pnv_core
= chip
->cores
+ i
* typesize
;
1098 uint64_t xscom_core_base
;
1100 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
1104 object_initialize(pnv_core
, typesize
, typename
);
1105 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
1106 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
),
1108 object_property_set_int(OBJECT(pnv_core
), smp_threads
, "nr-threads",
1110 object_property_set_int(OBJECT(pnv_core
), core_hwid
,
1111 CPU_CORE_PROP_CORE_ID
, &error_fatal
);
1112 object_property_set_int(OBJECT(pnv_core
),
1113 pcc
->core_pir(chip
, core_hwid
),
1114 "pir", &error_fatal
);
1115 object_property_add_const_link(OBJECT(pnv_core
), "chip",
1116 OBJECT(chip
), &error_fatal
);
1117 object_property_set_bool(OBJECT(pnv_core
), true, "realized",
1119 object_unref(OBJECT(pnv_core
));
1121 /* Each core has an XSCOM MMIO region */
1122 if (!pnv_chip_is_power9(chip
)) {
1123 xscom_core_base
= PNV_XSCOM_EX_BASE(core_hwid
);
1125 xscom_core_base
= PNV_XSCOM_P9_EC_BASE(core_hwid
);
1128 pnv_xscom_add_subregion(chip
, xscom_core_base
,
1129 &PNV_CORE(pnv_core
)->xscom_regs
);
1134 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
1136 PnvChip
*chip
= PNV_CHIP(dev
);
1137 Error
*error
= NULL
;
1140 pnv_xscom_realize(chip
, &error
);
1142 error_propagate(errp
, error
);
1145 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
1148 pnv_chip_core_realize(chip
, &error
);
1150 error_propagate(errp
, error
);
1155 static Property pnv_chip_properties
[] = {
1156 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
1157 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
1158 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
1159 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
1160 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
1161 DEFINE_PROP_END_OF_LIST(),
1164 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
1166 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1168 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
1169 dc
->realize
= pnv_chip_realize
;
1170 dc
->props
= pnv_chip_properties
;
1171 dc
->desc
= "PowerNV Chip";
1174 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
1176 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1179 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1180 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1182 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
1183 return &chip8
->psi
.ics
;
1189 static void pnv_ics_resend(XICSFabric
*xi
)
1191 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1194 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1195 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1196 ics_resend(&chip8
->psi
.ics
);
1200 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
1202 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
1204 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
1207 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
1210 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1215 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1217 if (pnv_chip_is_power9(pnv
->chips
[0])) {
1218 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1220 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
1224 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1225 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
1229 static void pnv_get_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1230 void *opaque
, Error
**errp
)
1232 visit_type_uint32(v
, name
, &PNV_MACHINE(obj
)->num_chips
, errp
);
1235 static void pnv_set_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1236 void *opaque
, Error
**errp
)
1238 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1240 Error
*local_err
= NULL
;
1242 visit_type_uint32(v
, name
, &num_chips
, &local_err
);
1244 error_propagate(errp
, local_err
);
1249 * TODO: should we decide on how many chips we can create based
1250 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1252 if (!is_power_of_2(num_chips
) || num_chips
> 4) {
1253 error_setg(errp
, "invalid number of chips: '%d'", num_chips
);
1257 pnv
->num_chips
= num_chips
;
1260 static void pnv_machine_instance_init(Object
*obj
)
1262 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
1266 static void pnv_machine_class_props_init(ObjectClass
*oc
)
1268 object_class_property_add(oc
, "num-chips", "uint32",
1269 pnv_get_num_chips
, pnv_set_num_chips
,
1271 object_class_property_set_description(oc
, "num-chips",
1272 "Specifies the number of processor chips",
1276 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
1278 MachineClass
*mc
= MACHINE_CLASS(oc
);
1279 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1280 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1282 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
1283 mc
->init
= pnv_init
;
1284 mc
->reset
= pnv_reset
;
1285 mc
->max_cpus
= MAX_CPUS
;
1286 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
1287 mc
->block_default_type
= IF_IDE
; /* Pnv provides a AHCI device for
1289 mc
->no_parallel
= 1;
1290 mc
->default_boot_order
= NULL
;
1291 mc
->default_ram_size
= 1 * GiB
;
1292 xic
->icp_get
= pnv_icp_get
;
1293 xic
->ics_get
= pnv_ics_get
;
1294 xic
->ics_resend
= pnv_ics_resend
;
1295 ispc
->print_info
= pnv_pic_print_info
;
1297 pnv_machine_class_props_init(oc
);
1300 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
1303 .class_init = class_initfn, \
1304 .parent = TYPE_PNV8_CHIP, \
1307 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
1310 .class_init = class_initfn, \
1311 .parent = TYPE_PNV9_CHIP, \
1314 static const TypeInfo types
[] = {
1316 .name
= TYPE_PNV_MACHINE
,
1317 .parent
= TYPE_MACHINE
,
1318 .instance_size
= sizeof(PnvMachineState
),
1319 .instance_init
= pnv_machine_instance_init
,
1320 .class_init
= pnv_machine_class_init
,
1321 .interfaces
= (InterfaceInfo
[]) {
1322 { TYPE_XICS_FABRIC
},
1323 { TYPE_INTERRUPT_STATS_PROVIDER
},
1328 .name
= TYPE_PNV_CHIP
,
1329 .parent
= TYPE_SYS_BUS_DEVICE
,
1330 .class_init
= pnv_chip_class_init
,
1331 .instance_init
= pnv_chip_instance_init
,
1332 .instance_size
= sizeof(PnvChip
),
1333 .class_size
= sizeof(PnvChipClass
),
1338 * P9 chip and variants
1341 .name
= TYPE_PNV9_CHIP
,
1342 .parent
= TYPE_PNV_CHIP
,
1343 .instance_init
= pnv_chip_power9_instance_init
,
1344 .instance_size
= sizeof(Pnv9Chip
),
1346 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
1349 * P8 chip and variants
1352 .name
= TYPE_PNV8_CHIP
,
1353 .parent
= TYPE_PNV_CHIP
,
1354 .instance_init
= pnv_chip_power8_instance_init
,
1355 .instance_size
= sizeof(Pnv8Chip
),
1357 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
1358 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
1359 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
1360 pnv_chip_power8nvl_class_init
),