hw/pc_piix.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "apic.h"
  28 #include "pci.h"
  29 #include "usb-uhci.h"
  30 #include "usb-ohci.h"
  31 #include "net.h"
  32 #include "boards.h"
  33 #include "ide.h"
  34 #include "kvm.h"
  35 #include "kvmclock.h"
  36 #include "sysemu.h"
  37 #include "sysbus.h"
  38 #include "arch_init.h"
  39 #include "blockdev.h"
  40
  41 #define MAX_IDE_BUS 2
  42
  43 static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
  44 static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
  45 static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
  46
  47 static void ioapic_init(IsaIrqState *isa_irq_state)
  48 {
  49     DeviceState *dev;
  50     SysBusDevice *d;
  51     unsigned int i;
  52
  53     dev = qdev_create(NULL, "ioapic");
  54     qdev_init_nofail(dev);
  55     d = sysbus_from_qdev(dev);
  56     sysbus_mmio_map(d, 0, 0xfec00000);
  57
  58     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  59         isa_irq_state->ioapic[i] = qdev_get_gpio_in(dev, i);
  60     }
  61 }
  62
  63 /* PC hardware initialisation */
  64 static void pc_init1(ram_addr_t ram_size,
  65                      const char *boot_device,
  66                      const char *kernel_filename,
  67                      const char *kernel_cmdline,
  68                      const char *initrd_filename,
  69                      const char *cpu_model,
  70                      int pci_enabled,
  71                      int kvmclock_enabled)
  72 {
  73     int i;
  74     ram_addr_t below_4g_mem_size, above_4g_mem_size;
  75     PCIBus *pci_bus;
  76     PCII440FXState *i440fx_state;
  77     int piix3_devfn = -1;
  78     qemu_irq *cpu_irq;
  79     qemu_irq *isa_irq;
  80     qemu_irq *i8259;
  81     qemu_irq *cmos_s3;
  82     qemu_irq *smi_irq;
  83     IsaIrqState *isa_irq_state;
  84     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
  85     BusState *idebus[MAX_IDE_BUS];
  86     ISADevice *rtc_state;
  87
  88     pc_cpus_init(cpu_model);
  89
  90     if (kvmclock_enabled) {
  91         kvmclock_create();
  92     }
  93
  94     /* allocate ram and load rom/bios */
  95     pc_memory_init(ram_size, kernel_filename, kernel_cmdline, initrd_filename,
  96                    &below_4g_mem_size, &above_4g_mem_size);
  97
  98     cpu_irq = pc_allocate_cpu_irq();
  99     i8259 = i8259_init(cpu_irq[0]);
 100     isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
 101     isa_irq_state->i8259 = i8259;
 102     if (pci_enabled) {
 103         ioapic_init(isa_irq_state);
 104     }
 105     isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
 106
 107     if (pci_enabled) {
 108         pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq, ram_size);
 109     } else {
 110         pci_bus = NULL;
 111         i440fx_state = NULL;
 112         isa_bus_new(NULL);
 113     }
 114     isa_bus_irqs(isa_irq);
 115
 116     pc_register_ferr_irq(isa_reserve_irq(13));
 117
 118     pc_vga_init(pci_enabled? pci_bus: NULL);
 119
 120     /* init basic PC hardware */
 121     pc_basic_device_init(isa_irq, &rtc_state);
 122
 123     for(i = 0; i < nb_nics; i++) {
 124         NICInfo *nd = &nd_table[i];
 125
 126         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
 127             pc_init_ne2k_isa(nd);
 128         else
 129             pci_nic_init_nofail(nd, "e1000", NULL);
 130     }
 131
 132     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 133         fprintf(stderr, "qemu: too many IDE bus\n");
 134         exit(1);
 135     }
 136
 137     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 138         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 139     }
 140
 141     if (pci_enabled) {
 142         PCIDevice *dev;
 143         dev = pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
 144         idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
 145         idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
 146     } else {
 147         for(i = 0; i < MAX_IDE_BUS; i++) {
 148             ISADevice *dev;
 149             dev = isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 150                                hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
 151             idebus[i] = qdev_get_child_bus(&dev->qdev, "ide.0");
 152         }
 153     }
 154
 155     audio_init(isa_irq, pci_enabled ? pci_bus : NULL);
 156
 157     pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
 158                  idebus[0], idebus[1], rtc_state);
 159
 160     if (pci_enabled && usb_enabled) {
 161         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
 162     }
 163
 164     if (pci_enabled && acpi_enabled) {
 165         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
 166         i2c_bus *smbus;
 167
 168         cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
 169         smi_irq = qemu_allocate_irqs(pc_acpi_smi_interrupt, first_cpu, 1);
 170         /* TODO: Populate SPD eeprom data.  */
 171         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
 172                               isa_reserve_irq(9), *cmos_s3, *smi_irq,
 173                               kvm_enabled());
 174         for (i = 0; i < 8; i++) {
 175             DeviceState *eeprom;
 176             eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
 177             qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
 178             qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
 179             qdev_init_nofail(eeprom);
 180         }
 181     }
 182
 183     if (i440fx_state) {
 184         i440fx_init_memory_mappings(i440fx_state);
 185     }
 186
 187     if (pci_enabled) {
 188         pc_pci_device_init(pci_bus);
 189     }
 190 }
 191
 192 static void pc_init_pci(ram_addr_t ram_size,
 193                         const char *boot_device,
 194                         const char *kernel_filename,
 195                         const char *kernel_cmdline,
 196                         const char *initrd_filename,
 197                         const char *cpu_model)
 198 {
 199     pc_init1(ram_size, boot_device,
 200              kernel_filename, kernel_cmdline,
 201              initrd_filename, cpu_model, 1, 1);
 202 }
 203
 204 static void pc_init_pci_no_kvmclock(ram_addr_t ram_size,
 205                                     const char *boot_device,
 206                                     const char *kernel_filename,
 207                                     const char *kernel_cmdline,
 208                                     const char *initrd_filename,
 209                                     const char *cpu_model)
 210 {
 211     pc_init1(ram_size, boot_device,
 212              kernel_filename, kernel_cmdline,
 213              initrd_filename, cpu_model, 1, 0);
 214 }
 215
 216 static void pc_init_isa(ram_addr_t ram_size,
 217                         const char *boot_device,
 218                         const char *kernel_filename,
 219                         const char *kernel_cmdline,
 220                         const char *initrd_filename,
 221                         const char *cpu_model)
 222 {
 223     if (cpu_model == NULL)
 224         cpu_model = "486";
 225     pc_init1(ram_size, boot_device,
 226              kernel_filename, kernel_cmdline,
 227              initrd_filename, cpu_model, 0, 1);
 228 }
 229
 230 static QEMUMachine pc_machine = {
 231     .name = "pc-0.14",
 232     .alias = "pc",
 233     .desc = "Standard PC",
 234     .init = pc_init_pci,
 235     .max_cpus = 255,
 236     .is_default = 1,
 237 };
 238
 239 static QEMUMachine pc_machine_v0_13 = {
 240     .name = "pc-0.13",
 241     .desc = "Standard PC",
 242     .init = pc_init_pci_no_kvmclock,
 243     .max_cpus = 255,
 244     .compat_props = (GlobalProperty[]) {
 245         {
 246             .driver   = "virtio-9p-pci",
 247             .property = "vectors",
 248             .value    = stringify(0),
 249         },{
 250             .driver   = "VGA",
 251             .property = "rombar",
 252             .value    = stringify(0),
 253         },{
 254             .driver   = "vmware-svga",
 255             .property = "rombar",
 256             .value    = stringify(0),
 257         },{
 258             .driver   = "PCI",
 259             .property = "command_serr_enable",
 260             .value    = "off",
 261         },
 262         { /* end of list */ }
 263     },
 264 };
 265
 266 static QEMUMachine pc_machine_v0_12 = {
 267     .name = "pc-0.12",
 268     .desc = "Standard PC",
 269     .init = pc_init_pci_no_kvmclock,
 270     .max_cpus = 255,
 271     .compat_props = (GlobalProperty[]) {
 272         {
 273             .driver   = "virtio-serial-pci",
 274             .property = "max_ports",
 275             .value    = stringify(1),
 276         },{
 277             .driver   = "virtio-serial-pci",
 278             .property = "vectors",
 279             .value    = stringify(0),
 280         },{
 281             .driver   = "VGA",
 282             .property = "rombar",
 283             .value    = stringify(0),
 284         },{
 285             .driver   = "vmware-svga",
 286             .property = "rombar",
 287             .value    = stringify(0),
 288         },{
 289             .driver   = "PCI",
 290             .property = "command_serr_enable",
 291             .value    = "off",
 292         },
 293         { /* end of list */ }
 294     }
 295 };
 296
 297 static QEMUMachine pc_machine_v0_11 = {
 298     .name = "pc-0.11",
 299     .desc = "Standard PC, qemu 0.11",
 300     .init = pc_init_pci_no_kvmclock,
 301     .max_cpus = 255,
 302     .compat_props = (GlobalProperty[]) {
 303         {
 304             .driver   = "virtio-blk-pci",
 305             .property = "vectors",
 306             .value    = stringify(0),
 307         },{
 308             .driver   = "virtio-serial-pci",
 309             .property = "max_ports",
 310             .value    = stringify(1),
 311         },{
 312             .driver   = "virtio-serial-pci",
 313             .property = "vectors",
 314             .value    = stringify(0),
 315         },{
 316             .driver   = "ide-drive",
 317             .property = "ver",
 318             .value    = "0.11",
 319         },{
 320             .driver   = "scsi-disk",
 321             .property = "ver",
 322             .value    = "0.11",
 323         },{
 324             .driver   = "PCI",
 325             .property = "rombar",
 326             .value    = stringify(0),
 327         },{
 328             .driver   = "PCI",
 329             .property = "command_serr_enable",
 330             .value    = "off",
 331         },
 332         { /* end of list */ }
 333     }
 334 };
 335
 336 static QEMUMachine pc_machine_v0_10 = {
 337     .name = "pc-0.10",
 338     .desc = "Standard PC, qemu 0.10",
 339     .init = pc_init_pci_no_kvmclock,
 340     .max_cpus = 255,
 341     .compat_props = (GlobalProperty[]) {
 342         {
 343             .driver   = "virtio-blk-pci",
 344             .property = "class",
 345             .value    = stringify(PCI_CLASS_STORAGE_OTHER),
 346         },{
 347             .driver   = "virtio-serial-pci",
 348             .property = "class",
 349             .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
 350         },{
 351             .driver   = "virtio-serial-pci",
 352             .property = "max_ports",
 353             .value    = stringify(1),
 354         },{
 355             .driver   = "virtio-serial-pci",
 356             .property = "vectors",
 357             .value    = stringify(0),
 358         },{
 359             .driver   = "virtio-net-pci",
 360             .property = "vectors",
 361             .value    = stringify(0),
 362         },{
 363             .driver   = "virtio-blk-pci",
 364             .property = "vectors",
 365             .value    = stringify(0),
 366         },{
 367             .driver   = "ide-drive",
 368             .property = "ver",
 369             .value    = "0.10",
 370         },{
 371             .driver   = "scsi-disk",
 372             .property = "ver",
 373             .value    = "0.10",
 374         },{
 375             .driver   = "PCI",
 376             .property = "rombar",
 377             .value    = stringify(0),
 378         },{
 379             .driver   = "PCI",
 380             .property = "command_serr_enable",
 381             .value    = "off",
 382         },
 383         { /* end of list */ }
 384     },
 385 };
 386
 387 static QEMUMachine isapc_machine = {
 388     .name = "isapc",
 389     .desc = "ISA-only PC",
 390     .init = pc_init_isa,
 391     .max_cpus = 1,
 392 };
 393
 394 static void pc_machine_init(void)
 395 {
 396     qemu_register_machine(&pc_machine);
 397     qemu_register_machine(&pc_machine_v0_13);
 398     qemu_register_machine(&pc_machine_v0_12);
 399     qemu_register_machine(&pc_machine_v0_11);
 400     qemu_register_machine(&pc_machine_v0_10);
 401     qemu_register_machine(&isapc_machine);
 402 }
 403
 404 machine_init(pc_machine_init);