hw/timer/stm32f2xx_timer.c

   1 /*
   2  * STM32F2XX Timer
   3  *
   4  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/timer/stm32f2xx_timer.h"
  27 #include "qemu/log.h"
  28
  29 #ifndef STM_TIMER_ERR_DEBUG
  30 #define STM_TIMER_ERR_DEBUG 0
  31 #endif
  32
  33 #define DB_PRINT_L(lvl, fmt, args...) do { \
  34     if (STM_TIMER_ERR_DEBUG >= lvl) { \
  35         qemu_log("%s: " fmt, __func__, ## args); \
  36     } \
  37 } while (0)
  38
  39 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  40
  41 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now);
  42
  43 static void stm32f2xx_timer_interrupt(void *opaque)
  44 {
  45     STM32F2XXTimerState *s = opaque;
  46
  47     DB_PRINT("Interrupt\n");
  48
  49     if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) {
  50         s->tim_sr |= 1;
  51         qemu_irq_pulse(s->irq);
  52         stm32f2xx_timer_set_alarm(s, s->hit_time);
  53     }
  54
  55     if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) &&
  56         !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) &&
  57         s->tim_ccmr1 & TIM_CCMR1_OC2PE &&
  58         s->tim_ccer & TIM_CCER_CC2E) {
  59         /* PWM 2 - Mode 1 */
  60         DB_PRINT("PWM2 Duty Cycle: %d%%\n",
  61                 s->tim_ccr2 / (100 * (s->tim_psc + 1)));
  62     }
  63 }
  64
  65 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t)
  66 {
  67     return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1);
  68 }
  69
  70 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now)
  71 {
  72     uint64_t ticks;
  73     int64_t now_ticks;
  74
  75     if (s->tim_arr == 0) {
  76         return;
  77     }
  78
  79     DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1);
  80
  81     now_ticks = stm32f2xx_ns_to_ticks(s, now);
  82     ticks = s->tim_arr - (now_ticks - s->tick_offset);
  83
  84     DB_PRINT("Alarm set in %d ticks\n", (int) ticks);
  85
  86     s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1),
  87                                1000000000ULL, s->freq_hz);
  88
  89     timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time);
  90     DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time);
  91 }
  92
  93 static void stm32f2xx_timer_reset(DeviceState *dev)
  94 {
  95     STM32F2XXTimerState *s = STM32F2XXTIMER(dev);
  96     int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  97
  98     s->tim_cr1 = 0;
  99     s->tim_cr2 = 0;
 100     s->tim_smcr = 0;
 101     s->tim_dier = 0;
 102     s->tim_sr = 0;
 103     s->tim_egr = 0;
 104     s->tim_ccmr1 = 0;
 105     s->tim_ccmr2 = 0;
 106     s->tim_ccer = 0;
 107     s->tim_psc = 0;
 108     s->tim_arr = 0;
 109     s->tim_ccr1 = 0;
 110     s->tim_ccr2 = 0;
 111     s->tim_ccr3 = 0;
 112     s->tim_ccr4 = 0;
 113     s->tim_dcr = 0;
 114     s->tim_dmar = 0;
 115     s->tim_or = 0;
 116
 117     s->tick_offset = stm32f2xx_ns_to_ticks(s, now);
 118 }
 119
 120 static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset,
 121                            unsigned size)
 122 {
 123     STM32F2XXTimerState *s = opaque;
 124
 125     DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
 126
 127     switch (offset) {
 128     case TIM_CR1:
 129         return s->tim_cr1;
 130     case TIM_CR2:
 131         return s->tim_cr2;
 132     case TIM_SMCR:
 133         return s->tim_smcr;
 134     case TIM_DIER:
 135         return s->tim_dier;
 136     case TIM_SR:
 137         return s->tim_sr;
 138     case TIM_EGR:
 139         return s->tim_egr;
 140     case TIM_CCMR1:
 141         return s->tim_ccmr1;
 142     case TIM_CCMR2:
 143         return s->tim_ccmr2;
 144     case TIM_CCER:
 145         return s->tim_ccer;
 146     case TIM_CNT:
 147         return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) -
 148                s->tick_offset;
 149     case TIM_PSC:
 150         return s->tim_psc;
 151     case TIM_ARR:
 152         return s->tim_arr;
 153     case TIM_CCR1:
 154         return s->tim_ccr1;
 155     case TIM_CCR2:
 156         return s->tim_ccr2;
 157     case TIM_CCR3:
 158         return s->tim_ccr3;
 159     case TIM_CCR4:
 160         return s->tim_ccr4;
 161     case TIM_DCR:
 162         return s->tim_dcr;
 163     case TIM_DMAR:
 164         return s->tim_dmar;
 165     case TIM_OR:
 166         return s->tim_or;
 167     default:
 168         qemu_log_mask(LOG_GUEST_ERROR,
 169                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
 170     }
 171
 172     return 0;
 173 }
 174
 175 static void stm32f2xx_timer_write(void *opaque, hwaddr offset,
 176                         uint64_t val64, unsigned size)
 177 {
 178     STM32F2XXTimerState *s = opaque;
 179     uint32_t value = val64;
 180     int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 181     uint32_t timer_val = 0;
 182
 183     DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset);
 184
 185     switch (offset) {
 186     case TIM_CR1:
 187         s->tim_cr1 = value;
 188         return;
 189     case TIM_CR2:
 190         s->tim_cr2 = value;
 191         return;
 192     case TIM_SMCR:
 193         s->tim_smcr = value;
 194         return;
 195     case TIM_DIER:
 196         s->tim_dier = value;
 197         return;
 198     case TIM_SR:
 199         /* This is set by hardware and cleared by software */
 200         s->tim_sr &= value;
 201         return;
 202     case TIM_EGR:
 203         s->tim_egr = value;
 204         if (s->tim_egr & TIM_EGR_UG) {
 205             timer_val = 0;
 206             break;
 207         }
 208         return;
 209     case TIM_CCMR1:
 210         s->tim_ccmr1 = value;
 211         return;
 212     case TIM_CCMR2:
 213         s->tim_ccmr2 = value;
 214         return;
 215     case TIM_CCER:
 216         s->tim_ccer = value;
 217         return;
 218     case TIM_PSC:
 219         timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset;
 220         s->tim_psc = value & 0xFFFF;
 221         value = timer_val;
 222         break;
 223     case TIM_CNT:
 224         timer_val = value;
 225         break;
 226     case TIM_ARR:
 227         s->tim_arr = value;
 228         stm32f2xx_timer_set_alarm(s, now);
 229         return;
 230     case TIM_CCR1:
 231         s->tim_ccr1 = value;
 232         return;
 233     case TIM_CCR2:
 234         s->tim_ccr2 = value;
 235         return;
 236     case TIM_CCR3:
 237         s->tim_ccr3 = value;
 238         return;
 239     case TIM_CCR4:
 240         s->tim_ccr4 = value;
 241         return;
 242     case TIM_DCR:
 243         s->tim_dcr = value;
 244         return;
 245     case TIM_DMAR:
 246         s->tim_dmar = value;
 247         return;
 248     case TIM_OR:
 249         s->tim_or = value;
 250         return;
 251     default:
 252         qemu_log_mask(LOG_GUEST_ERROR,
 253                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
 254         return;
 255     }
 256
 257     /* This means that a register write has affected the timer in a way that
 258      * requires a refresh of both tick_offset and the alarm.
 259      */
 260     s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val;
 261     stm32f2xx_timer_set_alarm(s, now);
 262 }
 263
 264 static const MemoryRegionOps stm32f2xx_timer_ops = {
 265     .read = stm32f2xx_timer_read,
 266     .write = stm32f2xx_timer_write,
 267     .endianness = DEVICE_NATIVE_ENDIAN,
 268 };
 269
 270 static const VMStateDescription vmstate_stm32f2xx_timer = {
 271     .name = TYPE_STM32F2XX_TIMER,
 272     .version_id = 1,
 273     .minimum_version_id = 1,
 274     .fields = (VMStateField[]) {
 275         VMSTATE_INT64(tick_offset, STM32F2XXTimerState),
 276         VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState),
 277         VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState),
 278         VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState),
 279         VMSTATE_UINT32(tim_dier, STM32F2XXTimerState),
 280         VMSTATE_UINT32(tim_sr, STM32F2XXTimerState),
 281         VMSTATE_UINT32(tim_egr, STM32F2XXTimerState),
 282         VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState),
 283         VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState),
 284         VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState),
 285         VMSTATE_UINT32(tim_psc, STM32F2XXTimerState),
 286         VMSTATE_UINT32(tim_arr, STM32F2XXTimerState),
 287         VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState),
 288         VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState),
 289         VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState),
 290         VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState),
 291         VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState),
 292         VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState),
 293         VMSTATE_UINT32(tim_or, STM32F2XXTimerState),
 294         VMSTATE_END_OF_LIST()
 295     }
 296 };
 297
 298 static Property stm32f2xx_timer_properties[] = {
 299     DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState,
 300                        freq_hz, 1000000000),
 301     DEFINE_PROP_END_OF_LIST(),
 302 };
 303
 304 static void stm32f2xx_timer_init(Object *obj)
 305 {
 306     STM32F2XXTimerState *s = STM32F2XXTIMER(obj);
 307
 308     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 309
 310     memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s,
 311                           "stm32f2xx_timer", 0x400);
 312     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 313
 314     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s);
 315 }
 316
 317 static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data)
 318 {
 319     DeviceClass *dc = DEVICE_CLASS(klass);
 320
 321     dc->reset = stm32f2xx_timer_reset;
 322     dc->props = stm32f2xx_timer_properties;
 323     dc->vmsd = &vmstate_stm32f2xx_timer;
 324 }
 325
 326 static const TypeInfo stm32f2xx_timer_info = {
 327     .name          = TYPE_STM32F2XX_TIMER,
 328     .parent        = TYPE_SYS_BUS_DEVICE,
 329     .instance_size = sizeof(STM32F2XXTimerState),
 330     .instance_init = stm32f2xx_timer_init,
 331     .class_init    = stm32f2xx_timer_class_init,
 332 };
 333
 334 static void stm32f2xx_timer_register_types(void)
 335 {
 336     type_register_static(&stm32f2xx_timer_info);
 337 }
 338
 339 type_init(stm32f2xx_timer_register_types)