include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "exec/memory.h"
   5 #include "sysemu/dma.h"
   6
   7 /* PCI includes legacy ISA access.  */
   8 #include "hw/isa/isa.h"
   9
  10 extern bool pci_available;
  11
  12 /* PCI bus */
  13
  14 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  15 #define PCI_BUS_NUM(x)          (((x) >> 8) & 0xff)
  16 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  17 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  18 #define PCI_BUILD_BDF(bus, devfn)     ((bus << 8) | (devfn))
  19 #define PCI_BDF_TO_DEVFN(x)     ((x) & 0xff)
  20 #define PCI_BUS_MAX             256
  21 #define PCI_DEVFN_MAX           256
  22 #define PCI_SLOT_MAX            32
  23 #define PCI_FUNC_MAX            8
  24
  25 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  26 #include "hw/pci/pci_ids.h"
  27
  28 /* QEMU-specific Vendor and Device ID definitions */
  29
  30 /* IBM (0x1014) */
  31 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  32 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  33
  34 /* Hitachi (0x1054) */
  35 #define PCI_VENDOR_ID_HITACHI            0x1054
  36 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  37
  38 /* Apple (0x106b) */
  39 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  41 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  42 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  43 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  44
  45 /* Realtek (0x10ec) */
  46 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  47
  48 /* Xilinx (0x10ee) */
  49 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  50
  51 /* Marvell (0x11ab) */
  52 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  53
  54 /* QEMU/Bochs VGA (0x1234) */
  55 #define PCI_VENDOR_ID_QEMU               0x1234
  56 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  57 #define PCI_DEVICE_ID_QEMU_IPMI          0x1112
  58
  59 /* VMWare (0x15ad) */
  60 #define PCI_VENDOR_ID_VMWARE             0x15ad
  61 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  62 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  63 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  64 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  65 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  66 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  67 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  68
  69 /* Intel (0x8086) */
  70 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  71 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  72 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  73
  74 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  75 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  76 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  77 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  78
  79 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  80 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  81 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  82 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  83 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  84 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  85 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  86 #define PCI_DEVICE_ID_VIRTIO_VSOCK       0x1012
  87 #define PCI_DEVICE_ID_VIRTIO_PMEM        0x1013
  88 #define PCI_DEVICE_ID_VIRTIO_IOMMU       0x1014
  89 #define PCI_DEVICE_ID_VIRTIO_MEM         0x1015
  90
  91 #define PCI_VENDOR_ID_REDHAT             0x1b36
  92 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  93 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  94 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  95 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  96 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  97 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
  98 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
  99 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
 100 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
 101 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
 102 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE    0x000b
 103 #define PCI_DEVICE_ID_REDHAT_PCIE_RP     0x000c
 104 #define PCI_DEVICE_ID_REDHAT_XHCI        0x000d
 105 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
 106 #define PCI_DEVICE_ID_REDHAT_MDPY        0x000f
 107 #define PCI_DEVICE_ID_REDHAT_NVME        0x0010
 108 #define PCI_DEVICE_ID_REDHAT_PVPANIC     0x0011
 109 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST   0x0012
 110 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
 111
 112 #define FMT_PCIBUS                      PRIx64
 113
 114 typedef uint64_t pcibus_t;
 115
 116 struct PCIHostDeviceAddress {
 117     unsigned int domain;
 118     unsigned int bus;
 119     unsigned int slot;
 120     unsigned int function;
 121 };
 122
 123 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 124                                 uint32_t address, uint32_t data, int len);
 125 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 126                                    uint32_t address, int len);
 127 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 128                                 pcibus_t addr, pcibus_t size, int type);
 129 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 130
 131 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg);
 132 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector);
 133 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector);
 134
 135 typedef struct PCIIORegion {
 136     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 137 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 138     pcibus_t size;
 139     uint8_t type;
 140     MemoryRegion *memory;
 141     MemoryRegion *address_space;
 142 } PCIIORegion;
 143
 144 #define PCI_ROM_SLOT 6
 145 #define PCI_NUM_REGIONS 7
 146
 147 enum {
 148     QEMU_PCI_VGA_MEM,
 149     QEMU_PCI_VGA_IO_LO,
 150     QEMU_PCI_VGA_IO_HI,
 151     QEMU_PCI_VGA_NUM_REGIONS,
 152 };
 153
 154 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 155 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 156 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 157 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 158 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 159 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 160
 161 #include "hw/pci/pci_regs.h"
 162 #include "hw/pci/pcie.h"
 163
 164 /* PCI HEADER_TYPE */
 165 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 166
 167 /* Size of the standard PCI config header */
 168 #define PCI_CONFIG_HEADER_SIZE 0x40
 169 /* Size of the standard PCI config space */
 170 #define PCI_CONFIG_SPACE_SIZE 0x100
 171 /* Size of the standard PCIe config space: 4KB */
 172 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 173
 174 #define PCI_NUM_PINS 4 /* A-D */
 175
 176 /* Bits in cap_present field. */
 177 enum {
 178     QEMU_PCI_CAP_MSI = 0x1,
 179     QEMU_PCI_CAP_MSIX = 0x2,
 180     QEMU_PCI_CAP_EXPRESS = 0x4,
 181
 182     /* multifunction capable device */
 183 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 184     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 185
 186     /* command register SERR bit enabled - unused since QEMU v5.0 */
 187 #define QEMU_PCI_CAP_SERR_BITNR 4
 188     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 189     /* Standard hot plug controller. */
 190 #define QEMU_PCI_SHPC_BITNR 5
 191     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 192 #define QEMU_PCI_SLOTID_BITNR 6
 193     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 194     /* PCI Express capability - Power Controller Present */
 195 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 196     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 197     /* Link active status in endpoint capability is always set */
 198 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
 199     QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
 200 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
 201     QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
 202 #define QEMU_PCIE_CXL_BITNR 10
 203     QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
 204 };
 205
 206 #define TYPE_PCI_DEVICE "pci-device"
 207 typedef struct PCIDeviceClass PCIDeviceClass;
 208 DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass,
 209                      PCI_DEVICE, TYPE_PCI_DEVICE)
 210
 211 /*
 212  * Implemented by devices that can be plugged on CXL buses. In the spec, this is
 213  * actually a "CXL Component, but we name it device to match the PCI naming.
 214  */
 215 #define INTERFACE_CXL_DEVICE "cxl-device"
 216
 217 /* Implemented by devices that can be plugged on PCI Express buses */
 218 #define INTERFACE_PCIE_DEVICE "pci-express-device"
 219
 220 /* Implemented by devices that can be plugged on Conventional PCI buses */
 221 #define INTERFACE_CONVENTIONAL_PCI_DEVICE "conventional-pci-device"
 222
 223 typedef struct PCIINTxRoute {
 224     enum {
 225         PCI_INTX_ENABLED,
 226         PCI_INTX_INVERTED,
 227         PCI_INTX_DISABLED,
 228     } mode;
 229     int irq;
 230 } PCIINTxRoute;
 231
 232 struct PCIDeviceClass {
 233     DeviceClass parent_class;
 234
 235     void (*realize)(PCIDevice *dev, Error **errp);
 236     PCIUnregisterFunc *exit;
 237     PCIConfigReadFunc *config_read;
 238     PCIConfigWriteFunc *config_write;
 239
 240     uint16_t vendor_id;
 241     uint16_t device_id;
 242     uint8_t revision;
 243     uint16_t class_id;
 244     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 245     uint16_t subsystem_id;              /* only for header type = 0 */
 246
 247     /*
 248      * pci-to-pci bridge or normal device.
 249      * This doesn't mean pci host switch.
 250      * When card bus bridge is supported, this would be enhanced.
 251      */
 252     bool is_bridge;
 253
 254     /* rom bar */
 255     const char *romfile;
 256 };
 257
 258 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 259 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 260                                       MSIMessage msg);
 261 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 262 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 263                                       unsigned int vector_start,
 264                                       unsigned int vector_end);
 265
 266 enum PCIReqIDType {
 267     PCI_REQ_ID_INVALID = 0,
 268     PCI_REQ_ID_BDF,
 269     PCI_REQ_ID_SECONDARY_BUS,
 270     PCI_REQ_ID_MAX,
 271 };
 272 typedef enum PCIReqIDType PCIReqIDType;
 273
 274 struct PCIReqIDCache {
 275     PCIDevice *dev;
 276     PCIReqIDType type;
 277 };
 278 typedef struct PCIReqIDCache PCIReqIDCache;
 279
 280 struct PCIDevice {
 281     DeviceState qdev;
 282     bool partially_hotplugged;
 283     bool has_power;
 284
 285     /* PCI config space */
 286     uint8_t *config;
 287
 288     /* Used to enable config checks on load. Note that writable bits are
 289      * never checked even if set in cmask. */
 290     uint8_t *cmask;
 291
 292     /* Used to implement R/W bytes */
 293     uint8_t *wmask;
 294
 295     /* Used to implement RW1C(Write 1 to Clear) bytes */
 296     uint8_t *w1cmask;
 297
 298     /* Used to allocate config space for capabilities. */
 299     uint8_t *used;
 300
 301     /* the following fields are read only */
 302     int32_t devfn;
 303     /* Cached device to fetch requester ID from, to avoid the PCI
 304      * tree walking every time we invoke PCI request (e.g.,
 305      * MSI). For conventional PCI root complex, this field is
 306      * meaningless. */
 307     PCIReqIDCache requester_id_cache;
 308     char name[64];
 309     PCIIORegion io_regions[PCI_NUM_REGIONS];
 310     AddressSpace bus_master_as;
 311     MemoryRegion bus_master_container_region;
 312     MemoryRegion bus_master_enable_region;
 313
 314     /* do not access the following fields */
 315     PCIConfigReadFunc *config_read;
 316     PCIConfigWriteFunc *config_write;
 317
 318     /* Legacy PCI VGA regions */
 319     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 320     bool has_vga;
 321
 322     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 323     uint8_t irq_state;
 324
 325     /* Capability bits */
 326     uint32_t cap_present;
 327
 328     /* Offset of MSI-X capability in config space */
 329     uint8_t msix_cap;
 330
 331     /* MSI-X entries */
 332     int msix_entries_nr;
 333
 334     /* Space to store MSIX table & pending bit array */
 335     uint8_t *msix_table;
 336     uint8_t *msix_pba;
 337
 338     /* May be used by INTx or MSI during interrupt notification */
 339     void *irq_opaque;
 340
 341     MSITriggerFunc *msi_trigger;
 342     MSIPrepareMessageFunc *msi_prepare_message;
 343     MSIxPrepareMessageFunc *msix_prepare_message;
 344
 345     /* MemoryRegion container for msix exclusive BAR setup */
 346     MemoryRegion msix_exclusive_bar;
 347     /* Memory Regions for MSIX table and pending bit entries. */
 348     MemoryRegion msix_table_mmio;
 349     MemoryRegion msix_pba_mmio;
 350     /* Reference-count for entries actually in use by driver. */
 351     unsigned *msix_entry_used;
 352     /* MSIX function mask set or MSIX disabled */
 353     bool msix_function_masked;
 354     /* Version id needed for VMState */
 355     int32_t version_id;
 356
 357     /* Offset of MSI capability in config space */
 358     uint8_t msi_cap;
 359
 360     /* PCI Express */
 361     PCIExpressDevice exp;
 362
 363     /* SHPC */
 364     SHPCDevice *shpc;
 365
 366     /* Location of option rom */
 367     char *romfile;
 368     uint32_t romsize;
 369     bool has_rom;
 370     MemoryRegion rom;
 371     uint32_t rom_bar;
 372
 373     /* INTx routing notifier */
 374     PCIINTxRoutingNotifier intx_routing_notifier;
 375
 376     /* MSI-X notifiers */
 377     MSIVectorUseNotifier msix_vector_use_notifier;
 378     MSIVectorReleaseNotifier msix_vector_release_notifier;
 379     MSIVectorPollNotifier msix_vector_poll_notifier;
 380
 381     /* ID of standby device in net_failover pair */
 382     char *failover_pair_id;
 383     uint32_t acpi_index;
 384 };
 385
 386 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 387                       uint8_t attr, MemoryRegion *memory);
 388 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 389                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 390 void pci_unregister_vga(PCIDevice *pci_dev);
 391 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 392
 393 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 394                        uint8_t offset, uint8_t size,
 395                        Error **errp);
 396
 397 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 398
 399 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 400
 401
 402 uint32_t pci_default_read_config(PCIDevice *d,
 403                                  uint32_t address, int len);
 404 void pci_default_write_config(PCIDevice *d,
 405                               uint32_t address, uint32_t val, int len);
 406 void pci_device_save(PCIDevice *s, QEMUFile *f);
 407 int pci_device_load(PCIDevice *s, QEMUFile *f);
 408 MemoryRegion *pci_address_space(PCIDevice *dev);
 409 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 410
 411 /*
 412  * Should not normally be used by devices. For use by sPAPR target
 413  * where QEMU emulates firmware.
 414  */
 415 int pci_bar(PCIDevice *d, int reg);
 416
 417 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 418 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 419 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 420
 421 #define TYPE_PCI_BUS "PCI"
 422 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
 423 #define TYPE_PCIE_BUS "PCIE"
 424 #define TYPE_CXL_BUS "CXL"
 425
 426 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque);
 427 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque);
 428 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque);
 429
 430 bool pci_bus_is_express(PCIBus *bus);
 431
 432 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
 433                        const char *name,
 434                        MemoryRegion *address_space_mem,
 435                        MemoryRegion *address_space_io,
 436                        uint8_t devfn_min, const char *typename);
 437 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
 438                          MemoryRegion *address_space_mem,
 439                          MemoryRegion *address_space_io,
 440                          uint8_t devfn_min, const char *typename);
 441 void pci_root_bus_cleanup(PCIBus *bus);
 442 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 443                   void *irq_opaque, int nirq);
 444 void pci_bus_irqs_cleanup(PCIBus *bus);
 445 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 446 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 447 static inline int pci_swizzle(int slot, int pin)
 448 {
 449     return (slot + pin) % PCI_NUM_PINS;
 450 }
 451 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 452 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
 453                               pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 454                               void *irq_opaque,
 455                               MemoryRegion *address_space_mem,
 456                               MemoryRegion *address_space_io,
 457                               uint8_t devfn_min, int nirq,
 458                               const char *typename);
 459 void pci_unregister_root_bus(PCIBus *bus);
 460 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 461 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 462 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 463 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 464 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 465                                           PCIINTxRoutingNotifier notifier);
 466 void pci_device_reset(PCIDevice *dev);
 467
 468 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 469                                const char *default_model,
 470                                const char *default_devaddr);
 471
 472 PCIDevice *pci_vga_init(PCIBus *bus);
 473
 474 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
 475 {
 476     return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
 477 }
 478 int pci_bus_num(PCIBus *s);
 479 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
 480 static inline int pci_dev_bus_num(const PCIDevice *dev)
 481 {
 482     return pci_bus_num(pci_get_bus(dev));
 483 }
 484
 485 int pci_bus_numa_node(PCIBus *bus);
 486 void pci_for_each_device(PCIBus *bus, int bus_num,
 487                          pci_bus_dev_fn fn,
 488                          void *opaque);
 489 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
 490                                  pci_bus_dev_fn fn,
 491                                  void *opaque);
 492 void pci_for_each_device_under_bus(PCIBus *bus,
 493                                    pci_bus_dev_fn fn, void *opaque);
 494 void pci_for_each_device_under_bus_reverse(PCIBus *bus,
 495                                            pci_bus_dev_fn fn,
 496                                            void *opaque);
 497 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
 498                                   pci_bus_fn end, void *parent_state);
 499 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
 500
 501 /* Use this wrapper when specific scan order is not required. */
 502 static inline
 503 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque)
 504 {
 505     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 506 }
 507
 508 PCIBus *pci_device_root_bus(const PCIDevice *d);
 509 const char *pci_root_bus_path(PCIDevice *dev);
 510 bool pci_bus_bypass_iommu(PCIBus *bus);
 511 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 512 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 513 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 514
 515 void pci_device_deassert_intx(PCIDevice *dev);
 516
 517 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 518
 519 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 520 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 521
 522 pcibus_t pci_bar_address(PCIDevice *d,
 523                          int reg, uint8_t type, pcibus_t size);
 524
 525 static inline void
 526 pci_set_byte(uint8_t *config, uint8_t val)
 527 {
 528     *config = val;
 529 }
 530
 531 static inline uint8_t
 532 pci_get_byte(const uint8_t *config)
 533 {
 534     return *config;
 535 }
 536
 537 static inline void
 538 pci_set_word(uint8_t *config, uint16_t val)
 539 {
 540     stw_le_p(config, val);
 541 }
 542
 543 static inline uint16_t
 544 pci_get_word(const uint8_t *config)
 545 {
 546     return lduw_le_p(config);
 547 }
 548
 549 static inline void
 550 pci_set_long(uint8_t *config, uint32_t val)
 551 {
 552     stl_le_p(config, val);
 553 }
 554
 555 static inline uint32_t
 556 pci_get_long(const uint8_t *config)
 557 {
 558     return ldl_le_p(config);
 559 }
 560
 561 /*
 562  * PCI capabilities and/or their fields
 563  * are generally DWORD aligned only so
 564  * mechanism used by pci_set/get_quad()
 565  * must be tolerant to unaligned pointers
 566  *
 567  */
 568 static inline void
 569 pci_set_quad(uint8_t *config, uint64_t val)
 570 {
 571     stq_le_p(config, val);
 572 }
 573
 574 static inline uint64_t
 575 pci_get_quad(const uint8_t *config)
 576 {
 577     return ldq_le_p(config);
 578 }
 579
 580 static inline void
 581 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 582 {
 583     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 584 }
 585
 586 static inline void
 587 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 588 {
 589     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 590 }
 591
 592 static inline void
 593 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 594 {
 595     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 596 }
 597
 598 static inline void
 599 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 600 {
 601     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 602 }
 603
 604 static inline void
 605 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 606 {
 607     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 608 }
 609
 610 static inline void
 611 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 612 {
 613     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 614 }
 615
 616 /*
 617  * helper functions to do bit mask operation on configuration space.
 618  * Just to set bit, use test-and-set and discard returned value.
 619  * Just to clear bit, use test-and-clear and discard returned value.
 620  * NOTE: They aren't atomic.
 621  */
 622 static inline uint8_t
 623 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 624 {
 625     uint8_t val = pci_get_byte(config);
 626     pci_set_byte(config, val & ~mask);
 627     return val & mask;
 628 }
 629
 630 static inline uint8_t
 631 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 632 {
 633     uint8_t val = pci_get_byte(config);
 634     pci_set_byte(config, val | mask);
 635     return val & mask;
 636 }
 637
 638 static inline uint16_t
 639 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 640 {
 641     uint16_t val = pci_get_word(config);
 642     pci_set_word(config, val & ~mask);
 643     return val & mask;
 644 }
 645
 646 static inline uint16_t
 647 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 648 {
 649     uint16_t val = pci_get_word(config);
 650     pci_set_word(config, val | mask);
 651     return val & mask;
 652 }
 653
 654 static inline uint32_t
 655 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 656 {
 657     uint32_t val = pci_get_long(config);
 658     pci_set_long(config, val & ~mask);
 659     return val & mask;
 660 }
 661
 662 static inline uint32_t
 663 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 664 {
 665     uint32_t val = pci_get_long(config);
 666     pci_set_long(config, val | mask);
 667     return val & mask;
 668 }
 669
 670 static inline uint64_t
 671 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 672 {
 673     uint64_t val = pci_get_quad(config);
 674     pci_set_quad(config, val & ~mask);
 675     return val & mask;
 676 }
 677
 678 static inline uint64_t
 679 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 680 {
 681     uint64_t val = pci_get_quad(config);
 682     pci_set_quad(config, val | mask);
 683     return val & mask;
 684 }
 685
 686 /* Access a register specified by a mask */
 687 static inline void
 688 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 689 {
 690     uint8_t val = pci_get_byte(config);
 691     uint8_t rval = reg << ctz32(mask);
 692     pci_set_byte(config, (~mask & val) | (mask & rval));
 693 }
 694
 695 static inline void
 696 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 697 {
 698     uint16_t val = pci_get_word(config);
 699     uint16_t rval = reg << ctz32(mask);
 700     pci_set_word(config, (~mask & val) | (mask & rval));
 701 }
 702
 703 static inline void
 704 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 705 {
 706     uint32_t val = pci_get_long(config);
 707     uint32_t rval = reg << ctz32(mask);
 708     pci_set_long(config, (~mask & val) | (mask & rval));
 709 }
 710
 711 static inline void
 712 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 713 {
 714     uint64_t val = pci_get_quad(config);
 715     uint64_t rval = reg << ctz32(mask);
 716     pci_set_quad(config, (~mask & val) | (mask & rval));
 717 }
 718
 719 PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
 720                                     const char *name);
 721 PCIDevice *pci_new(int devfn, const char *name);
 722 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
 723
 724 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 725                                            bool multifunction,
 726                                            const char *name);
 727 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 728
 729 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
 730
 731 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 732 void pci_set_irq(PCIDevice *pci_dev, int level);
 733
 734 static inline int pci_intx(PCIDevice *pci_dev)
 735 {
 736     return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
 737 }
 738
 739 static inline void pci_irq_assert(PCIDevice *pci_dev)
 740 {
 741     pci_set_irq(pci_dev, 1);
 742 }
 743
 744 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 745 {
 746     pci_set_irq(pci_dev, 0);
 747 }
 748
 749 /*
 750  * FIXME: PCI does not work this way.
 751  * All the callers to this method should be fixed.
 752  */
 753 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 754 {
 755     pci_irq_assert(pci_dev);
 756     pci_irq_deassert(pci_dev);
 757 }
 758
 759 static inline int pci_is_cxl(const PCIDevice *d)
 760 {
 761     return d->cap_present & QEMU_PCIE_CAP_CXL;
 762 }
 763
 764 static inline int pci_is_express(const PCIDevice *d)
 765 {
 766     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 767 }
 768
 769 static inline int pci_is_express_downstream_port(const PCIDevice *d)
 770 {
 771     uint8_t type;
 772
 773     if (!pci_is_express(d) || !d->exp.exp_cap) {
 774         return 0;
 775     }
 776
 777     type = pcie_cap_get_type(d);
 778
 779     return type == PCI_EXP_TYPE_DOWNSTREAM || type == PCI_EXP_TYPE_ROOT_PORT;
 780 }
 781
 782 static inline int pci_is_vf(const PCIDevice *d)
 783 {
 784     return d->exp.sriov_vf.pf != NULL;
 785 }
 786
 787 static inline uint32_t pci_config_size(const PCIDevice *d)
 788 {
 789     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 790 }
 791
 792 static inline uint16_t pci_get_bdf(PCIDevice *dev)
 793 {
 794     return PCI_BUILD_BDF(pci_bus_num(pci_get_bus(dev)), dev->devfn);
 795 }
 796
 797 uint16_t pci_requester_id(PCIDevice *dev);
 798
 799 /* DMA access functions */
 800 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 801 {
 802     return &dev->bus_master_as;
 803 }
 804
 805 /**
 806  * pci_dma_rw: Read from or write to an address space from PCI device.
 807  *
 808  * Return a MemTxResult indicating whether the operation succeeded
 809  * or failed (eg unassigned memory, device rejected the transaction,
 810  * IOMMU fault).
 811  *
 812  * @dev: #PCIDevice doing the memory access
 813  * @addr: address within the #PCIDevice address space
 814  * @buf: buffer with the data transferred
 815  * @len: the number of bytes to read or write
 816  * @dir: indicates the transfer direction
 817  */
 818 static inline MemTxResult pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 819                                      void *buf, dma_addr_t len,
 820                                      DMADirection dir, MemTxAttrs attrs)
 821 {
 822     return dma_memory_rw(pci_get_address_space(dev), addr, buf, len,
 823                          dir, attrs);
 824 }
 825
 826 /**
 827  * pci_dma_read: Read from an address space from PCI device.
 828  *
 829  * Return a MemTxResult indicating whether the operation succeeded
 830  * or failed (eg unassigned memory, device rejected the transaction,
 831  * IOMMU fault).  Called within RCU critical section.
 832  *
 833  * @dev: #PCIDevice doing the memory access
 834  * @addr: address within the #PCIDevice address space
 835  * @buf: buffer with the data transferred
 836  * @len: length of the data transferred
 837  */
 838 static inline MemTxResult pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 839                                        void *buf, dma_addr_t len)
 840 {
 841     return pci_dma_rw(dev, addr, buf, len,
 842                       DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED);
 843 }
 844
 845 /**
 846  * pci_dma_write: Write to address space from PCI device.
 847  *
 848  * Return a MemTxResult indicating whether the operation succeeded
 849  * or failed (eg unassigned memory, device rejected the transaction,
 850  * IOMMU fault).
 851  *
 852  * @dev: #PCIDevice doing the memory access
 853  * @addr: address within the #PCIDevice address space
 854  * @buf: buffer with the data transferred
 855  * @len: the number of bytes to write
 856  */
 857 static inline MemTxResult pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 858                                         const void *buf, dma_addr_t len)
 859 {
 860     return pci_dma_rw(dev, addr, (void *) buf, len,
 861                       DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED);
 862 }
 863
 864 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
 865     static inline MemTxResult ld##_l##_pci_dma(PCIDevice *dev, \
 866                                                dma_addr_t addr, \
 867                                                uint##_bits##_t *val, \
 868                                                MemTxAttrs attrs) \
 869     { \
 870         return ld##_l##_dma(pci_get_address_space(dev), addr, val, attrs); \
 871     } \
 872     static inline MemTxResult st##_s##_pci_dma(PCIDevice *dev, \
 873                                                dma_addr_t addr, \
 874                                                uint##_bits##_t val, \
 875                                                MemTxAttrs attrs) \
 876     { \
 877         return st##_s##_dma(pci_get_address_space(dev), addr, val, attrs); \
 878     }
 879
 880 PCI_DMA_DEFINE_LDST(ub, b, 8);
 881 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 882 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 883 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 884 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 885 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 886 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 887
 888 #undef PCI_DMA_DEFINE_LDST
 889
 890 /**
 891  * pci_dma_map: Map device PCI address space range into host virtual address
 892  * @dev: #PCIDevice to be accessed
 893  * @addr: address within that device's address space
 894  * @plen: pointer to length of buffer; updated on return to indicate
 895  *        if only a subset of the requested range has been mapped
 896  * @dir: indicates the transfer direction
 897  *
 898  * Return: A host pointer, or %NULL if the resources needed to
 899  *         perform the mapping are exhausted (in that case *@plen
 900  *         is set to zero).
 901  */
 902 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 903                                 dma_addr_t *plen, DMADirection dir)
 904 {
 905     void *buf;
 906
 907     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir,
 908                          MEMTXATTRS_UNSPECIFIED);
 909     return buf;
 910 }
 911
 912 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 913                                  DMADirection dir, dma_addr_t access_len)
 914 {
 915     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 916 }
 917
 918 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 919                                        int alloc_hint)
 920 {
 921     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 922 }
 923
 924 extern const VMStateDescription vmstate_pci_device;
 925
 926 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 927     .name       = (stringify(_field)),                               \
 928     .size       = sizeof(PCIDevice),                                 \
 929     .vmsd       = &vmstate_pci_device,                               \
 930     .flags      = VMS_STRUCT,                                        \
 931     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 932 }
 933
 934 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 935     .name       = (stringify(_field)),                               \
 936     .size       = sizeof(PCIDevice),                                 \
 937     .vmsd       = &vmstate_pci_device,                               \
 938     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 939     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 940 }
 941
 942 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
 943 void pci_set_power(PCIDevice *pci_dev, bool state);
 944
 945 #endif