2 * Helpers for loads and stores
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
28 //#define DEBUG_CACHE_CONTROL
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
60 #define AM_CHECK(env1) (1)
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
67 #if !defined(CONFIG_USER_ONLY)
68 static void QEMU_NORETURN
do_unaligned_access(CPUSPARCState
*env
,
69 target_ulong addr
, int is_write
,
70 int is_user
, uintptr_t retaddr
);
71 #include "exec/softmmu_exec.h"
72 #define MMUSUFFIX _mmu
76 #include "exec/softmmu_template.h"
79 #include "exec/softmmu_template.h"
82 #include "exec/softmmu_template.h"
85 #include "exec/softmmu_template.h"
88 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
89 /* Calculates TSB pointer value for fault page size 8k or 64k */
90 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register
,
91 uint64_t tag_access_register
,
94 uint64_t tsb_base
= tsb_register
& ~0x1fffULL
;
95 int tsb_split
= (tsb_register
& 0x1000ULL
) ? 1 : 0;
96 int tsb_size
= tsb_register
& 0xf;
98 /* discard lower 13 bits which hold tag access context */
99 uint64_t tag_access_va
= tag_access_register
& ~0x1fffULL
;
101 /* now reorder bits */
102 uint64_t tsb_base_mask
= ~0x1fffULL
;
103 uint64_t va
= tag_access_va
;
105 /* move va bits to correct position */
106 if (page_size
== 8*1024) {
108 } else if (page_size
== 64*1024) {
113 tsb_base_mask
<<= tsb_size
;
116 /* calculate tsb_base mask and adjust va if split is in use */
118 if (page_size
== 8*1024) {
119 va
&= ~(1ULL << (13 + tsb_size
));
120 } else if (page_size
== 64*1024) {
121 va
|= (1ULL << (13 + tsb_size
));
126 return ((tsb_base
& tsb_base_mask
) | (va
& ~tsb_base_mask
)) & ~0xfULL
;
129 /* Calculates tag target register value by reordering bits
130 in tag access register */
131 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register
)
133 return ((tag_access_register
& 0x1fff) << 48) | (tag_access_register
>> 22);
136 static void replace_tlb_entry(SparcTLBEntry
*tlb
,
137 uint64_t tlb_tag
, uint64_t tlb_tte
,
140 target_ulong mask
, size
, va
, offset
;
142 /* flush page range if translation is valid */
143 if (TTE_IS_VALID(tlb
->tte
)) {
144 CPUState
*cs
= CPU(sparc_env_get_cpu(env1
));
146 mask
= 0xffffffffffffe000ULL
;
147 mask
<<= 3 * ((tlb
->tte
>> 61) & 3);
150 va
= tlb
->tag
& mask
;
152 for (offset
= 0; offset
< size
; offset
+= TARGET_PAGE_SIZE
) {
153 tlb_flush_page(cs
, va
+ offset
);
161 static void demap_tlb(SparcTLBEntry
*tlb
, target_ulong demap_addr
,
162 const char *strmmu
, CPUSPARCState
*env1
)
168 int is_demap_context
= (demap_addr
>> 6) & 1;
171 switch ((demap_addr
>> 4) & 3) {
172 case 0: /* primary */
173 context
= env1
->dmmu
.mmu_primary_context
;
175 case 1: /* secondary */
176 context
= env1
->dmmu
.mmu_secondary_context
;
178 case 2: /* nucleus */
181 case 3: /* reserved */
186 for (i
= 0; i
< 64; i
++) {
187 if (TTE_IS_VALID(tlb
[i
].tte
)) {
189 if (is_demap_context
) {
190 /* will remove non-global entries matching context value */
191 if (TTE_IS_GLOBAL(tlb
[i
].tte
) ||
192 !tlb_compare_context(&tlb
[i
], context
)) {
197 will remove any entry matching VA */
198 mask
= 0xffffffffffffe000ULL
;
199 mask
<<= 3 * ((tlb
[i
].tte
>> 61) & 3);
201 if (!compare_masked(demap_addr
, tlb
[i
].tag
, mask
)) {
205 /* entry should be global or matching context value */
206 if (!TTE_IS_GLOBAL(tlb
[i
].tte
) &&
207 !tlb_compare_context(&tlb
[i
], context
)) {
212 replace_tlb_entry(&tlb
[i
], 0, 0, env1
);
214 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu
, i
);
215 dump_mmu(stdout
, fprintf
, env1
);
221 static void replace_tlb_1bit_lru(SparcTLBEntry
*tlb
,
222 uint64_t tlb_tag
, uint64_t tlb_tte
,
223 const char *strmmu
, CPUSPARCState
*env1
)
225 unsigned int i
, replace_used
;
227 /* Try replacing invalid entry */
228 for (i
= 0; i
< 64; i
++) {
229 if (!TTE_IS_VALID(tlb
[i
].tte
)) {
230 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
232 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu
, i
);
233 dump_mmu(stdout
, fprintf
, env1
);
239 /* All entries are valid, try replacing unlocked entry */
241 for (replace_used
= 0; replace_used
< 2; ++replace_used
) {
243 /* Used entries are not replaced on first pass */
245 for (i
= 0; i
< 64; i
++) {
246 if (!TTE_IS_LOCKED(tlb
[i
].tte
) && !TTE_IS_USED(tlb
[i
].tte
)) {
248 replace_tlb_entry(&tlb
[i
], tlb_tag
, tlb_tte
, env1
);
250 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
251 strmmu
, (replace_used
? "used" : "unused"), i
);
252 dump_mmu(stdout
, fprintf
, env1
);
258 /* Now reset used bit and search for unused entries again */
260 for (i
= 0; i
< 64; i
++) {
261 TTE_SET_UNUSED(tlb
[i
].tte
);
266 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu
);
273 static inline target_ulong
address_mask(CPUSPARCState
*env1
, target_ulong addr
)
275 #ifdef TARGET_SPARC64
276 if (AM_CHECK(env1
)) {
277 addr
&= 0xffffffffULL
;
283 /* returns true if access using this ASI is to have address translated by MMU
284 otherwise access is to raw physical address */
285 static inline int is_translating_asi(int asi
)
287 #ifdef TARGET_SPARC64
288 /* Ultrasparc IIi translating asi
289 - note this list is defined by cpu implementation
305 /* TODO: check sparc32 bits */
310 static inline target_ulong
asi_address_mask(CPUSPARCState
*env
,
311 int asi
, target_ulong addr
)
313 if (is_translating_asi(asi
)) {
314 return address_mask(env
, addr
);
320 void helper_check_align(CPUSPARCState
*env
, target_ulong addr
, uint32_t align
)
323 #ifdef DEBUG_UNALIGNED
324 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
325 "\n", addr
, env
->pc
);
327 helper_raise_exception(env
, TT_UNALIGNED
);
331 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
333 static void dump_mxcc(CPUSPARCState
*env
)
335 printf("mxccdata: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
337 env
->mxccdata
[0], env
->mxccdata
[1],
338 env
->mxccdata
[2], env
->mxccdata
[3]);
339 printf("mxccregs: %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
341 " %016" PRIx64
" %016" PRIx64
" %016" PRIx64
" %016" PRIx64
343 env
->mxccregs
[0], env
->mxccregs
[1],
344 env
->mxccregs
[2], env
->mxccregs
[3],
345 env
->mxccregs
[4], env
->mxccregs
[5],
346 env
->mxccregs
[6], env
->mxccregs
[7]);
350 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
351 && defined(DEBUG_ASI)
352 static void dump_asi(const char *txt
, target_ulong addr
, int asi
, int size
,
357 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %02" PRIx64
"\n", txt
,
358 addr
, asi
, r1
& 0xff);
361 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %04" PRIx64
"\n", txt
,
362 addr
, asi
, r1
& 0xffff);
365 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %08" PRIx64
"\n", txt
,
366 addr
, asi
, r1
& 0xffffffff);
369 DPRINTF_ASI("%s "TARGET_FMT_lx
" asi 0x%02x = %016" PRIx64
"\n", txt
,
376 #ifndef TARGET_SPARC64
377 #ifndef CONFIG_USER_ONLY
380 /* Leon3 cache control */
382 static void leon3_cache_control_st(CPUSPARCState
*env
, target_ulong addr
,
383 uint64_t val
, int size
)
385 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64
", size:%d\n",
389 DPRINTF_CACHE_CONTROL("32bits only\n");
394 case 0x00: /* Cache control */
396 /* These values must always be read as zeros */
397 val
&= ~CACHE_CTRL_FD
;
398 val
&= ~CACHE_CTRL_FI
;
399 val
&= ~CACHE_CTRL_IB
;
400 val
&= ~CACHE_CTRL_IP
;
401 val
&= ~CACHE_CTRL_DP
;
403 env
->cache_control
= val
;
405 case 0x04: /* Instruction cache configuration */
406 case 0x08: /* Data cache configuration */
410 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr
);
415 static uint64_t leon3_cache_control_ld(CPUSPARCState
*env
, target_ulong addr
,
421 DPRINTF_CACHE_CONTROL("32bits only\n");
426 case 0x00: /* Cache control */
427 ret
= env
->cache_control
;
430 /* Configuration registers are read and only always keep those
433 case 0x04: /* Instruction cache configuration */
436 case 0x08: /* Data cache configuration */
440 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr
);
443 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64
", size:%d\n",
448 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
451 CPUState
*cs
= CPU(sparc_env_get_cpu(env
));
453 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
454 uint32_t last_addr
= addr
;
457 helper_check_align(env
, addr
, size
- 1);
459 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
461 case 0x00: /* Leon3 Cache Control */
462 case 0x08: /* Leon3 Instruction Cache config */
463 case 0x0C: /* Leon3 Date Cache config */
464 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
465 ret
= leon3_cache_control_ld(env
, addr
, size
);
468 case 0x01c00a00: /* MXCC control register */
470 ret
= env
->mxccregs
[3];
472 qemu_log_mask(LOG_UNIMP
,
473 "%08x: unimplemented access size: %d\n", addr
,
477 case 0x01c00a04: /* MXCC control register */
479 ret
= env
->mxccregs
[3];
481 qemu_log_mask(LOG_UNIMP
,
482 "%08x: unimplemented access size: %d\n", addr
,
486 case 0x01c00c00: /* Module reset register */
488 ret
= env
->mxccregs
[5];
489 /* should we do something here? */
491 qemu_log_mask(LOG_UNIMP
,
492 "%08x: unimplemented access size: %d\n", addr
,
496 case 0x01c00f00: /* MBus port address register */
498 ret
= env
->mxccregs
[7];
500 qemu_log_mask(LOG_UNIMP
,
501 "%08x: unimplemented access size: %d\n", addr
,
506 qemu_log_mask(LOG_UNIMP
,
507 "%08x: unimplemented address, size: %d\n", addr
,
511 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
512 "addr = %08x -> ret = %" PRIx64
","
513 "addr = %08x\n", asi
, size
, sign
, last_addr
, ret
, addr
);
518 case 3: /* MMU probe */
519 case 0x18: /* LEON3 MMU probe */
523 mmulev
= (addr
>> 8) & 15;
527 ret
= mmu_probe(env
, addr
, mmulev
);
529 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64
"\n",
533 case 4: /* read MMU regs */
534 case 0x19: /* LEON3 read MMU regs */
536 int reg
= (addr
>> 8) & 0x1f;
538 ret
= env
->mmuregs
[reg
];
539 if (reg
== 3) { /* Fault status cleared on read */
541 } else if (reg
== 0x13) { /* Fault status read */
542 ret
= env
->mmuregs
[3];
543 } else if (reg
== 0x14) { /* Fault address read */
544 ret
= env
->mmuregs
[4];
546 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64
"\n", reg
, ret
);
549 case 5: /* Turbosparc ITLB Diagnostic */
550 case 6: /* Turbosparc DTLB Diagnostic */
551 case 7: /* Turbosparc IOTLB Diagnostic */
553 case 9: /* Supervisor code access */
556 ret
= cpu_ldub_code(env
, addr
);
559 ret
= cpu_lduw_code(env
, addr
);
563 ret
= cpu_ldl_code(env
, addr
);
566 ret
= cpu_ldq_code(env
, addr
);
570 case 0xa: /* User data access */
573 ret
= cpu_ldub_user(env
, addr
);
576 ret
= cpu_lduw_user(env
, addr
);
580 ret
= cpu_ldl_user(env
, addr
);
583 ret
= cpu_ldq_user(env
, addr
);
587 case 0xb: /* Supervisor data access */
591 ret
= cpu_ldub_kernel(env
, addr
);
594 ret
= cpu_lduw_kernel(env
, addr
);
598 ret
= cpu_ldl_kernel(env
, addr
);
601 ret
= cpu_ldq_kernel(env
, addr
);
605 case 0xc: /* I-cache tag */
606 case 0xd: /* I-cache data */
607 case 0xe: /* D-cache tag */
608 case 0xf: /* D-cache data */
610 case 0x20: /* MMU passthrough */
611 case 0x1c: /* LEON MMU passthrough */
614 ret
= ldub_phys(cs
->as
, addr
);
617 ret
= lduw_phys(cs
->as
, addr
);
621 ret
= ldl_phys(cs
->as
, addr
);
624 ret
= ldq_phys(cs
->as
, addr
);
628 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
631 ret
= ldub_phys(cs
->as
, (hwaddr
)addr
632 | ((hwaddr
)(asi
& 0xf) << 32));
635 ret
= lduw_phys(cs
->as
, (hwaddr
)addr
636 | ((hwaddr
)(asi
& 0xf) << 32));
640 ret
= ldl_phys(cs
->as
, (hwaddr
)addr
641 | ((hwaddr
)(asi
& 0xf) << 32));
644 ret
= ldq_phys(cs
->as
, (hwaddr
)addr
645 | ((hwaddr
)(asi
& 0xf) << 32));
649 case 0x30: /* Turbosparc secondary cache diagnostic */
650 case 0x31: /* Turbosparc RAM snoop */
651 case 0x32: /* Turbosparc page table descriptor diagnostic */
652 case 0x39: /* data cache diagnostic register */
655 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
657 int reg
= (addr
>> 8) & 3;
660 case 0: /* Breakpoint Value (Addr) */
661 ret
= env
->mmubpregs
[reg
];
663 case 1: /* Breakpoint Mask */
664 ret
= env
->mmubpregs
[reg
];
666 case 2: /* Breakpoint Control */
667 ret
= env
->mmubpregs
[reg
];
669 case 3: /* Breakpoint Status */
670 ret
= env
->mmubpregs
[reg
];
671 env
->mmubpregs
[reg
] = 0ULL;
674 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64
"\n", reg
,
678 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
679 ret
= env
->mmubpctrv
;
681 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
682 ret
= env
->mmubpctrc
;
684 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
685 ret
= env
->mmubpctrs
;
687 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
688 ret
= env
->mmubpaction
;
690 case 8: /* User code access, XXX */
692 cpu_unassigned_access(cs
, addr
, false, false, asi
, size
);
712 dump_asi("read ", last_addr
, asi
, size
, ret
);
717 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, uint64_t val
, int asi
,
720 SPARCCPU
*cpu
= sparc_env_get_cpu(env
);
721 CPUState
*cs
= CPU(cpu
);
723 helper_check_align(env
, addr
, size
- 1);
725 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
727 case 0x00: /* Leon3 Cache Control */
728 case 0x08: /* Leon3 Instruction Cache config */
729 case 0x0C: /* Leon3 Date Cache config */
730 if (env
->def
->features
& CPU_FEATURE_CACHE_CTRL
) {
731 leon3_cache_control_st(env
, addr
, val
, size
);
735 case 0x01c00000: /* MXCC stream data register 0 */
737 env
->mxccdata
[0] = val
;
739 qemu_log_mask(LOG_UNIMP
,
740 "%08x: unimplemented access size: %d\n", addr
,
744 case 0x01c00008: /* MXCC stream data register 1 */
746 env
->mxccdata
[1] = val
;
748 qemu_log_mask(LOG_UNIMP
,
749 "%08x: unimplemented access size: %d\n", addr
,
753 case 0x01c00010: /* MXCC stream data register 2 */
755 env
->mxccdata
[2] = val
;
757 qemu_log_mask(LOG_UNIMP
,
758 "%08x: unimplemented access size: %d\n", addr
,
762 case 0x01c00018: /* MXCC stream data register 3 */
764 env
->mxccdata
[3] = val
;
766 qemu_log_mask(LOG_UNIMP
,
767 "%08x: unimplemented access size: %d\n", addr
,
771 case 0x01c00100: /* MXCC stream source */
773 env
->mxccregs
[0] = val
;
775 qemu_log_mask(LOG_UNIMP
,
776 "%08x: unimplemented access size: %d\n", addr
,
779 env
->mxccdata
[0] = ldq_phys(cs
->as
,
780 (env
->mxccregs
[0] & 0xffffffffULL
) +
782 env
->mxccdata
[1] = ldq_phys(cs
->as
,
783 (env
->mxccregs
[0] & 0xffffffffULL
) +
785 env
->mxccdata
[2] = ldq_phys(cs
->as
,
786 (env
->mxccregs
[0] & 0xffffffffULL
) +
788 env
->mxccdata
[3] = ldq_phys(cs
->as
,
789 (env
->mxccregs
[0] & 0xffffffffULL
) +
792 case 0x01c00200: /* MXCC stream destination */
794 env
->mxccregs
[1] = val
;
796 qemu_log_mask(LOG_UNIMP
,
797 "%08x: unimplemented access size: %d\n", addr
,
800 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 0,
802 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 8,
804 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 16,
806 stq_phys(cs
->as
, (env
->mxccregs
[1] & 0xffffffffULL
) + 24,
809 case 0x01c00a00: /* MXCC control register */
811 env
->mxccregs
[3] = val
;
813 qemu_log_mask(LOG_UNIMP
,
814 "%08x: unimplemented access size: %d\n", addr
,
818 case 0x01c00a04: /* MXCC control register */
820 env
->mxccregs
[3] = (env
->mxccregs
[3] & 0xffffffff00000000ULL
)
823 qemu_log_mask(LOG_UNIMP
,
824 "%08x: unimplemented access size: %d\n", addr
,
828 case 0x01c00e00: /* MXCC error register */
829 /* writing a 1 bit clears the error */
831 env
->mxccregs
[6] &= ~val
;
833 qemu_log_mask(LOG_UNIMP
,
834 "%08x: unimplemented access size: %d\n", addr
,
838 case 0x01c00f00: /* MBus port address register */
840 env
->mxccregs
[7] = val
;
842 qemu_log_mask(LOG_UNIMP
,
843 "%08x: unimplemented access size: %d\n", addr
,
848 qemu_log_mask(LOG_UNIMP
,
849 "%08x: unimplemented address, size: %d\n", addr
,
853 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64
"\n",
854 asi
, size
, addr
, val
);
859 case 3: /* MMU flush */
860 case 0x18: /* LEON3 MMU flush */
864 mmulev
= (addr
>> 8) & 15;
865 DPRINTF_MMU("mmu flush level %d\n", mmulev
);
867 case 0: /* flush page */
868 tlb_flush_page(CPU(cpu
), addr
& 0xfffff000);
870 case 1: /* flush segment (256k) */
871 case 2: /* flush region (16M) */
872 case 3: /* flush context (4G) */
873 case 4: /* flush entire */
880 dump_mmu(stdout
, fprintf
, env
);
884 case 4: /* write MMU regs */
885 case 0x19: /* LEON3 write MMU regs */
887 int reg
= (addr
>> 8) & 0x1f;
890 oldreg
= env
->mmuregs
[reg
];
892 case 0: /* Control Register */
893 env
->mmuregs
[reg
] = (env
->mmuregs
[reg
] & 0xff000000) |
895 /* Mappings generated during no-fault mode or MMU
896 disabled mode are invalid in normal mode */
897 if ((oldreg
& (MMU_E
| MMU_NF
| env
->def
->mmu_bm
)) !=
898 (env
->mmuregs
[reg
] & (MMU_E
| MMU_NF
| env
->def
->mmu_bm
))) {
902 case 1: /* Context Table Pointer Register */
903 env
->mmuregs
[reg
] = val
& env
->def
->mmu_ctpr_mask
;
905 case 2: /* Context Register */
906 env
->mmuregs
[reg
] = val
& env
->def
->mmu_cxr_mask
;
907 if (oldreg
!= env
->mmuregs
[reg
]) {
908 /* we flush when the MMU context changes because
909 QEMU has no MMU context support */
913 case 3: /* Synchronous Fault Status Register with Clear */
914 case 4: /* Synchronous Fault Address Register */
916 case 0x10: /* TLB Replacement Control Register */
917 env
->mmuregs
[reg
] = val
& env
->def
->mmu_trcr_mask
;
919 case 0x13: /* Synchronous Fault Status Register with Read
921 env
->mmuregs
[3] = val
& env
->def
->mmu_sfsr_mask
;
923 case 0x14: /* Synchronous Fault Address Register */
924 env
->mmuregs
[4] = val
;
927 env
->mmuregs
[reg
] = val
;
930 if (oldreg
!= env
->mmuregs
[reg
]) {
931 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
932 reg
, oldreg
, env
->mmuregs
[reg
]);
935 dump_mmu(stdout
, fprintf
, env
);
939 case 5: /* Turbosparc ITLB Diagnostic */
940 case 6: /* Turbosparc DTLB Diagnostic */
941 case 7: /* Turbosparc IOTLB Diagnostic */
943 case 0xa: /* User data access */
946 cpu_stb_user(env
, addr
, val
);
949 cpu_stw_user(env
, addr
, val
);
953 cpu_stl_user(env
, addr
, val
);
956 cpu_stq_user(env
, addr
, val
);
960 case 0xb: /* Supervisor data access */
964 cpu_stb_kernel(env
, addr
, val
);
967 cpu_stw_kernel(env
, addr
, val
);
971 cpu_stl_kernel(env
, addr
, val
);
974 cpu_stq_kernel(env
, addr
, val
);
978 case 0xc: /* I-cache tag */
979 case 0xd: /* I-cache data */
980 case 0xe: /* D-cache tag */
981 case 0xf: /* D-cache data */
982 case 0x10: /* I/D-cache flush page */
983 case 0x11: /* I/D-cache flush segment */
984 case 0x12: /* I/D-cache flush region */
985 case 0x13: /* I/D-cache flush context */
986 case 0x14: /* I/D-cache flush user */
988 case 0x17: /* Block copy, sta access */
994 uint32_t src
= val
& ~3, dst
= addr
& ~3, temp
;
996 for (i
= 0; i
< 32; i
+= 4, src
+= 4, dst
+= 4) {
997 temp
= cpu_ldl_kernel(env
, src
);
998 cpu_stl_kernel(env
, dst
, temp
);
1002 case 0x1f: /* Block fill, stda access */
1005 fill 32 bytes with val */
1007 uint32_t dst
= addr
& 7;
1009 for (i
= 0; i
< 32; i
+= 8, dst
+= 8) {
1010 cpu_stq_kernel(env
, dst
, val
);
1014 case 0x20: /* MMU passthrough */
1015 case 0x1c: /* LEON MMU passthrough */
1019 stb_phys(cs
->as
, addr
, val
);
1022 stw_phys(cs
->as
, addr
, val
);
1026 stl_phys(cs
->as
, addr
, val
);
1029 stq_phys(cs
->as
, addr
, val
);
1034 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1038 stb_phys(cs
->as
, (hwaddr
)addr
1039 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1042 stw_phys(cs
->as
, (hwaddr
)addr
1043 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1047 stl_phys(cs
->as
, (hwaddr
)addr
1048 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1051 stq_phys(cs
->as
, (hwaddr
)addr
1052 | ((hwaddr
)(asi
& 0xf) << 32), val
);
1057 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1058 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1059 Turbosparc snoop RAM */
1060 case 0x32: /* store buffer control or Turbosparc page table
1061 descriptor diagnostic */
1062 case 0x36: /* I-cache flash clear */
1063 case 0x37: /* D-cache flash clear */
1065 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1067 int reg
= (addr
>> 8) & 3;
1070 case 0: /* Breakpoint Value (Addr) */
1071 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1073 case 1: /* Breakpoint Mask */
1074 env
->mmubpregs
[reg
] = (val
& 0xfffffffffULL
);
1076 case 2: /* Breakpoint Control */
1077 env
->mmubpregs
[reg
] = (val
& 0x7fULL
);
1079 case 3: /* Breakpoint Status */
1080 env
->mmubpregs
[reg
] = (val
& 0xfULL
);
1083 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg
,
1087 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1088 env
->mmubpctrv
= val
& 0xffffffff;
1090 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1091 env
->mmubpctrc
= val
& 0x3;
1093 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1094 env
->mmubpctrs
= val
& 0x3;
1096 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1097 env
->mmubpaction
= val
& 0x1fff;
1099 case 8: /* User code access, XXX */
1100 case 9: /* Supervisor code access, XXX */
1102 cpu_unassigned_access(CPU(sparc_env_get_cpu(env
)),
1103 addr
, true, false, asi
, size
);
1107 dump_asi("write", addr
, asi
, size
, val
);
1111 #endif /* CONFIG_USER_ONLY */
1112 #else /* TARGET_SPARC64 */
1114 #ifdef CONFIG_USER_ONLY
1115 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
1119 #if defined(DEBUG_ASI)
1120 target_ulong last_addr
= addr
;
1124 helper_raise_exception(env
, TT_PRIV_ACT
);
1127 helper_check_align(env
, addr
, size
- 1);
1128 addr
= asi_address_mask(env
, asi
, addr
);
1131 case 0x82: /* Primary no-fault */
1132 case 0x8a: /* Primary no-fault LE */
1133 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1135 dump_asi("read ", last_addr
, asi
, size
, ret
);
1140 case 0x80: /* Primary */
1141 case 0x88: /* Primary LE */
1145 ret
= ldub_raw(addr
);
1148 ret
= lduw_raw(addr
);
1151 ret
= ldl_raw(addr
);
1155 ret
= ldq_raw(addr
);
1160 case 0x83: /* Secondary no-fault */
1161 case 0x8b: /* Secondary no-fault LE */
1162 if (page_check_range(addr
, size
, PAGE_READ
) == -1) {
1164 dump_asi("read ", last_addr
, asi
, size
, ret
);
1169 case 0x81: /* Secondary */
1170 case 0x89: /* Secondary LE */
1177 /* Convert from little endian */
1179 case 0x88: /* Primary LE */
1180 case 0x89: /* Secondary LE */
1181 case 0x8a: /* Primary no-fault LE */
1182 case 0x8b: /* Secondary no-fault LE */
1200 /* Convert to signed number */
1207 ret
= (int16_t) ret
;
1210 ret
= (int32_t) ret
;
1217 dump_asi("read ", last_addr
, asi
, size
, ret
);
1222 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1226 dump_asi("write", addr
, asi
, size
, val
);
1229 helper_raise_exception(env
, TT_PRIV_ACT
);
1232 helper_check_align(env
, addr
, size
- 1);
1233 addr
= asi_address_mask(env
, asi
, addr
);
1235 /* Convert to little endian */
1237 case 0x88: /* Primary LE */
1238 case 0x89: /* Secondary LE */
1257 case 0x80: /* Primary */
1258 case 0x88: /* Primary LE */
1277 case 0x81: /* Secondary */
1278 case 0x89: /* Secondary LE */
1282 case 0x82: /* Primary no-fault, RO */
1283 case 0x83: /* Secondary no-fault, RO */
1284 case 0x8a: /* Primary no-fault LE, RO */
1285 case 0x8b: /* Secondary no-fault LE, RO */
1287 helper_raise_exception(env
, TT_DATA_ACCESS
);
1292 #else /* CONFIG_USER_ONLY */
1294 uint64_t helper_ld_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
1297 CPUState
*cs
= CPU(sparc_env_get_cpu(env
));
1299 #if defined(DEBUG_ASI)
1300 target_ulong last_addr
= addr
;
1305 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1306 || (cpu_has_hypervisor(env
)
1307 && asi
>= 0x30 && asi
< 0x80
1308 && !(env
->hpstate
& HS_PRIV
))) {
1309 helper_raise_exception(env
, TT_PRIV_ACT
);
1312 helper_check_align(env
, addr
, size
- 1);
1313 addr
= asi_address_mask(env
, asi
, addr
);
1315 /* process nonfaulting loads first */
1316 if ((asi
& 0xf6) == 0x82) {
1319 /* secondary space access has lowest asi bit equal to 1 */
1320 if (env
->pstate
& PS_PRIV
) {
1321 mmu_idx
= (asi
& 1) ? MMU_KERNEL_SECONDARY_IDX
: MMU_KERNEL_IDX
;
1323 mmu_idx
= (asi
& 1) ? MMU_USER_SECONDARY_IDX
: MMU_USER_IDX
;
1326 if (cpu_get_phys_page_nofault(env
, addr
, mmu_idx
) == -1ULL) {
1328 dump_asi("read ", last_addr
, asi
, size
, ret
);
1330 /* env->exception_index is set in get_physical_address_data(). */
1331 helper_raise_exception(env
, cs
->exception_index
);
1334 /* convert nonfaulting load ASIs to normal load ASIs */
1339 case 0x10: /* As if user primary */
1340 case 0x11: /* As if user secondary */
1341 case 0x18: /* As if user primary LE */
1342 case 0x19: /* As if user secondary LE */
1343 case 0x80: /* Primary */
1344 case 0x81: /* Secondary */
1345 case 0x88: /* Primary LE */
1346 case 0x89: /* Secondary LE */
1347 case 0xe2: /* UA2007 Primary block init */
1348 case 0xe3: /* UA2007 Secondary block init */
1349 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1350 if (cpu_hypervisor_mode(env
)) {
1353 ret
= cpu_ldub_hypv(env
, addr
);
1356 ret
= cpu_lduw_hypv(env
, addr
);
1359 ret
= cpu_ldl_hypv(env
, addr
);
1363 ret
= cpu_ldq_hypv(env
, addr
);
1367 /* secondary space access has lowest asi bit equal to 1 */
1371 ret
= cpu_ldub_kernel_secondary(env
, addr
);
1374 ret
= cpu_lduw_kernel_secondary(env
, addr
);
1377 ret
= cpu_ldl_kernel_secondary(env
, addr
);
1381 ret
= cpu_ldq_kernel_secondary(env
, addr
);
1387 ret
= cpu_ldub_kernel(env
, addr
);
1390 ret
= cpu_lduw_kernel(env
, addr
);
1393 ret
= cpu_ldl_kernel(env
, addr
);
1397 ret
= cpu_ldq_kernel(env
, addr
);
1403 /* secondary space access has lowest asi bit equal to 1 */
1407 ret
= cpu_ldub_user_secondary(env
, addr
);
1410 ret
= cpu_lduw_user_secondary(env
, addr
);
1413 ret
= cpu_ldl_user_secondary(env
, addr
);
1417 ret
= cpu_ldq_user_secondary(env
, addr
);
1423 ret
= cpu_ldub_user(env
, addr
);
1426 ret
= cpu_lduw_user(env
, addr
);
1429 ret
= cpu_ldl_user(env
, addr
);
1433 ret
= cpu_ldq_user(env
, addr
);
1439 case 0x14: /* Bypass */
1440 case 0x15: /* Bypass, non-cacheable */
1441 case 0x1c: /* Bypass LE */
1442 case 0x1d: /* Bypass, non-cacheable LE */
1446 ret
= ldub_phys(cs
->as
, addr
);
1449 ret
= lduw_phys(cs
->as
, addr
);
1452 ret
= ldl_phys(cs
->as
, addr
);
1456 ret
= ldq_phys(cs
->as
, addr
);
1461 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1462 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1463 Only ldda allowed */
1464 helper_raise_exception(env
, TT_ILL_INSN
);
1466 case 0x04: /* Nucleus */
1467 case 0x0c: /* Nucleus Little Endian (LE) */
1471 ret
= cpu_ldub_nucleus(env
, addr
);
1474 ret
= cpu_lduw_nucleus(env
, addr
);
1477 ret
= cpu_ldl_nucleus(env
, addr
);
1481 ret
= cpu_ldq_nucleus(env
, addr
);
1486 case 0x4a: /* UPA config */
1489 case 0x45: /* LSU */
1492 case 0x50: /* I-MMU regs */
1494 int reg
= (addr
>> 3) & 0xf;
1497 /* I-TSB Tag Target register */
1498 ret
= ultrasparc_tag_target(env
->immu
.tag_access
);
1500 ret
= env
->immuregs
[reg
];
1505 case 0x51: /* I-MMU 8k TSB pointer */
1507 /* env->immuregs[5] holds I-MMU TSB register value
1508 env->immuregs[6] holds I-MMU Tag Access register value */
1509 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1513 case 0x52: /* I-MMU 64k TSB pointer */
1515 /* env->immuregs[5] holds I-MMU TSB register value
1516 env->immuregs[6] holds I-MMU Tag Access register value */
1517 ret
= ultrasparc_tsb_pointer(env
->immu
.tsb
, env
->immu
.tag_access
,
1521 case 0x55: /* I-MMU data access */
1523 int reg
= (addr
>> 3) & 0x3f;
1525 ret
= env
->itlb
[reg
].tte
;
1528 case 0x56: /* I-MMU tag read */
1530 int reg
= (addr
>> 3) & 0x3f;
1532 ret
= env
->itlb
[reg
].tag
;
1535 case 0x58: /* D-MMU regs */
1537 int reg
= (addr
>> 3) & 0xf;
1540 /* D-TSB Tag Target register */
1541 ret
= ultrasparc_tag_target(env
->dmmu
.tag_access
);
1543 ret
= env
->dmmuregs
[reg
];
1547 case 0x59: /* D-MMU 8k TSB pointer */
1549 /* env->dmmuregs[5] holds D-MMU TSB register value
1550 env->dmmuregs[6] holds D-MMU Tag Access register value */
1551 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1555 case 0x5a: /* D-MMU 64k TSB pointer */
1557 /* env->dmmuregs[5] holds D-MMU TSB register value
1558 env->dmmuregs[6] holds D-MMU Tag Access register value */
1559 ret
= ultrasparc_tsb_pointer(env
->dmmu
.tsb
, env
->dmmu
.tag_access
,
1563 case 0x5d: /* D-MMU data access */
1565 int reg
= (addr
>> 3) & 0x3f;
1567 ret
= env
->dtlb
[reg
].tte
;
1570 case 0x5e: /* D-MMU tag read */
1572 int reg
= (addr
>> 3) & 0x3f;
1574 ret
= env
->dtlb
[reg
].tag
;
1577 case 0x48: /* Interrupt dispatch, RO */
1579 case 0x49: /* Interrupt data receive */
1580 ret
= env
->ivec_status
;
1582 case 0x7f: /* Incoming interrupt vector, RO */
1584 int reg
= (addr
>> 4) & 0x3;
1586 ret
= env
->ivec_data
[reg
];
1590 case 0x46: /* D-cache data */
1591 case 0x47: /* D-cache tag access */
1592 case 0x4b: /* E-cache error enable */
1593 case 0x4c: /* E-cache asynchronous fault status */
1594 case 0x4d: /* E-cache asynchronous fault address */
1595 case 0x4e: /* E-cache tag data */
1596 case 0x66: /* I-cache instruction access */
1597 case 0x67: /* I-cache tag access */
1598 case 0x6e: /* I-cache predecode */
1599 case 0x6f: /* I-cache LRU etc. */
1600 case 0x76: /* E-cache tag */
1601 case 0x7e: /* E-cache tag */
1603 case 0x5b: /* D-MMU data pointer */
1604 case 0x54: /* I-MMU data in, WO */
1605 case 0x57: /* I-MMU demap, WO */
1606 case 0x5c: /* D-MMU data in, WO */
1607 case 0x5f: /* D-MMU demap, WO */
1608 case 0x77: /* Interrupt vector, WO */
1610 cpu_unassigned_access(cs
, addr
, false, false, 1, size
);
1615 /* Convert from little endian */
1617 case 0x0c: /* Nucleus Little Endian (LE) */
1618 case 0x18: /* As if user primary LE */
1619 case 0x19: /* As if user secondary LE */
1620 case 0x1c: /* Bypass LE */
1621 case 0x1d: /* Bypass, non-cacheable LE */
1622 case 0x88: /* Primary LE */
1623 case 0x89: /* Secondary LE */
1641 /* Convert to signed number */
1648 ret
= (int16_t) ret
;
1651 ret
= (int32_t) ret
;
1658 dump_asi("read ", last_addr
, asi
, size
, ret
);
1663 void helper_st_asi(CPUSPARCState
*env
, target_ulong addr
, target_ulong val
,
1666 CPUState
*cs
= CPU(sparc_env_get_cpu(env
));
1668 dump_asi("write", addr
, asi
, size
, val
);
1673 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
1674 || (cpu_has_hypervisor(env
)
1675 && asi
>= 0x30 && asi
< 0x80
1676 && !(env
->hpstate
& HS_PRIV
))) {
1677 helper_raise_exception(env
, TT_PRIV_ACT
);
1680 helper_check_align(env
, addr
, size
- 1);
1681 addr
= asi_address_mask(env
, asi
, addr
);
1683 /* Convert to little endian */
1685 case 0x0c: /* Nucleus Little Endian (LE) */
1686 case 0x18: /* As if user primary LE */
1687 case 0x19: /* As if user secondary LE */
1688 case 0x1c: /* Bypass LE */
1689 case 0x1d: /* Bypass, non-cacheable LE */
1690 case 0x88: /* Primary LE */
1691 case 0x89: /* Secondary LE */
1710 case 0x10: /* As if user primary */
1711 case 0x11: /* As if user secondary */
1712 case 0x18: /* As if user primary LE */
1713 case 0x19: /* As if user secondary LE */
1714 case 0x80: /* Primary */
1715 case 0x81: /* Secondary */
1716 case 0x88: /* Primary LE */
1717 case 0x89: /* Secondary LE */
1718 case 0xe2: /* UA2007 Primary block init */
1719 case 0xe3: /* UA2007 Secondary block init */
1720 if ((asi
& 0x80) && (env
->pstate
& PS_PRIV
)) {
1721 if (cpu_hypervisor_mode(env
)) {
1724 cpu_stb_hypv(env
, addr
, val
);
1727 cpu_stw_hypv(env
, addr
, val
);
1730 cpu_stl_hypv(env
, addr
, val
);
1734 cpu_stq_hypv(env
, addr
, val
);
1738 /* secondary space access has lowest asi bit equal to 1 */
1742 cpu_stb_kernel_secondary(env
, addr
, val
);
1745 cpu_stw_kernel_secondary(env
, addr
, val
);
1748 cpu_stl_kernel_secondary(env
, addr
, val
);
1752 cpu_stq_kernel_secondary(env
, addr
, val
);
1758 cpu_stb_kernel(env
, addr
, val
);
1761 cpu_stw_kernel(env
, addr
, val
);
1764 cpu_stl_kernel(env
, addr
, val
);
1768 cpu_stq_kernel(env
, addr
, val
);
1774 /* secondary space access has lowest asi bit equal to 1 */
1778 cpu_stb_user_secondary(env
, addr
, val
);
1781 cpu_stw_user_secondary(env
, addr
, val
);
1784 cpu_stl_user_secondary(env
, addr
, val
);
1788 cpu_stq_user_secondary(env
, addr
, val
);
1794 cpu_stb_user(env
, addr
, val
);
1797 cpu_stw_user(env
, addr
, val
);
1800 cpu_stl_user(env
, addr
, val
);
1804 cpu_stq_user(env
, addr
, val
);
1810 case 0x14: /* Bypass */
1811 case 0x15: /* Bypass, non-cacheable */
1812 case 0x1c: /* Bypass LE */
1813 case 0x1d: /* Bypass, non-cacheable LE */
1817 stb_phys(cs
->as
, addr
, val
);
1820 stw_phys(cs
->as
, addr
, val
);
1823 stl_phys(cs
->as
, addr
, val
);
1827 stq_phys(cs
->as
, addr
, val
);
1832 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1833 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1834 Only ldda allowed */
1835 helper_raise_exception(env
, TT_ILL_INSN
);
1837 case 0x04: /* Nucleus */
1838 case 0x0c: /* Nucleus Little Endian (LE) */
1842 cpu_stb_nucleus(env
, addr
, val
);
1845 cpu_stw_nucleus(env
, addr
, val
);
1848 cpu_stl_nucleus(env
, addr
, val
);
1852 cpu_stq_nucleus(env
, addr
, val
);
1858 case 0x4a: /* UPA config */
1861 case 0x45: /* LSU */
1866 env
->lsu
= val
& (DMMU_E
| IMMU_E
);
1867 /* Mappings generated during D/I MMU disabled mode are
1868 invalid in normal mode */
1869 if (oldreg
!= env
->lsu
) {
1870 DPRINTF_MMU("LSU change: 0x%" PRIx64
" -> 0x%" PRIx64
"\n",
1873 dump_mmu(stdout
, fprintf
, env
);
1879 case 0x50: /* I-MMU regs */
1881 int reg
= (addr
>> 3) & 0xf;
1884 oldreg
= env
->immuregs
[reg
];
1888 case 1: /* Not in I-MMU */
1892 if ((val
& 1) == 0) {
1893 val
= 0; /* Clear SFSR */
1895 env
->immu
.sfsr
= val
;
1899 case 5: /* TSB access */
1900 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64
" -> 0x%016"
1901 PRIx64
"\n", env
->immu
.tsb
, val
);
1902 env
->immu
.tsb
= val
;
1904 case 6: /* Tag access */
1905 env
->immu
.tag_access
= val
;
1914 if (oldreg
!= env
->immuregs
[reg
]) {
1915 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1916 PRIx64
"\n", reg
, oldreg
, env
->immuregs
[reg
]);
1919 dump_mmu(stdout
, fprintf
, env
);
1923 case 0x54: /* I-MMU data in */
1924 replace_tlb_1bit_lru(env
->itlb
, env
->immu
.tag_access
, val
, "immu", env
);
1926 case 0x55: /* I-MMU data access */
1928 /* TODO: auto demap */
1930 unsigned int i
= (addr
>> 3) & 0x3f;
1932 replace_tlb_entry(&env
->itlb
[i
], env
->immu
.tag_access
, val
, env
);
1935 DPRINTF_MMU("immu data access replaced entry [%i]\n", i
);
1936 dump_mmu(stdout
, fprintf
, env
);
1940 case 0x57: /* I-MMU demap */
1941 demap_tlb(env
->itlb
, addr
, "immu", env
);
1943 case 0x58: /* D-MMU regs */
1945 int reg
= (addr
>> 3) & 0xf;
1948 oldreg
= env
->dmmuregs
[reg
];
1954 if ((val
& 1) == 0) {
1955 val
= 0; /* Clear SFSR, Fault address */
1958 env
->dmmu
.sfsr
= val
;
1960 case 1: /* Primary context */
1961 env
->dmmu
.mmu_primary_context
= val
;
1962 /* can be optimized to only flush MMU_USER_IDX
1963 and MMU_KERNEL_IDX entries */
1966 case 2: /* Secondary context */
1967 env
->dmmu
.mmu_secondary_context
= val
;
1968 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1969 and MMU_KERNEL_SECONDARY_IDX entries */
1972 case 5: /* TSB access */
1973 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64
" -> 0x%016"
1974 PRIx64
"\n", env
->dmmu
.tsb
, val
);
1975 env
->dmmu
.tsb
= val
;
1977 case 6: /* Tag access */
1978 env
->dmmu
.tag_access
= val
;
1980 case 7: /* Virtual Watchpoint */
1981 case 8: /* Physical Watchpoint */
1983 env
->dmmuregs
[reg
] = val
;
1987 if (oldreg
!= env
->dmmuregs
[reg
]) {
1988 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64
" -> 0x%016"
1989 PRIx64
"\n", reg
, oldreg
, env
->dmmuregs
[reg
]);
1992 dump_mmu(stdout
, fprintf
, env
);
1996 case 0x5c: /* D-MMU data in */
1997 replace_tlb_1bit_lru(env
->dtlb
, env
->dmmu
.tag_access
, val
, "dmmu", env
);
1999 case 0x5d: /* D-MMU data access */
2001 unsigned int i
= (addr
>> 3) & 0x3f;
2003 replace_tlb_entry(&env
->dtlb
[i
], env
->dmmu
.tag_access
, val
, env
);
2006 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i
);
2007 dump_mmu(stdout
, fprintf
, env
);
2011 case 0x5f: /* D-MMU demap */
2012 demap_tlb(env
->dtlb
, addr
, "dmmu", env
);
2014 case 0x49: /* Interrupt data receive */
2015 env
->ivec_status
= val
& 0x20;
2017 case 0x46: /* D-cache data */
2018 case 0x47: /* D-cache tag access */
2019 case 0x4b: /* E-cache error enable */
2020 case 0x4c: /* E-cache asynchronous fault status */
2021 case 0x4d: /* E-cache asynchronous fault address */
2022 case 0x4e: /* E-cache tag data */
2023 case 0x66: /* I-cache instruction access */
2024 case 0x67: /* I-cache tag access */
2025 case 0x6e: /* I-cache predecode */
2026 case 0x6f: /* I-cache LRU etc. */
2027 case 0x76: /* E-cache tag */
2028 case 0x7e: /* E-cache tag */
2030 case 0x51: /* I-MMU 8k TSB pointer, RO */
2031 case 0x52: /* I-MMU 64k TSB pointer, RO */
2032 case 0x56: /* I-MMU tag read, RO */
2033 case 0x59: /* D-MMU 8k TSB pointer, RO */
2034 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2035 case 0x5b: /* D-MMU data pointer, RO */
2036 case 0x5e: /* D-MMU tag read, RO */
2037 case 0x48: /* Interrupt dispatch, RO */
2038 case 0x7f: /* Incoming interrupt vector, RO */
2039 case 0x82: /* Primary no-fault, RO */
2040 case 0x83: /* Secondary no-fault, RO */
2041 case 0x8a: /* Primary no-fault LE, RO */
2042 case 0x8b: /* Secondary no-fault LE, RO */
2044 cpu_unassigned_access(cs
, addr
, true, false, 1, size
);
2048 #endif /* CONFIG_USER_ONLY */
2050 void helper_ldda_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int rd
)
2052 if ((asi
< 0x80 && (env
->pstate
& PS_PRIV
) == 0)
2053 || (cpu_has_hypervisor(env
)
2054 && asi
>= 0x30 && asi
< 0x80
2055 && !(env
->hpstate
& HS_PRIV
))) {
2056 helper_raise_exception(env
, TT_PRIV_ACT
);
2059 addr
= asi_address_mask(env
, asi
, addr
);
2062 #if !defined(CONFIG_USER_ONLY)
2063 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2064 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2065 helper_check_align(env
, addr
, 0xf);
2067 env
->gregs
[1] = cpu_ldq_nucleus(env
, addr
+ 8);
2069 bswap64s(&env
->gregs
[1]);
2071 } else if (rd
< 8) {
2072 env
->gregs
[rd
] = cpu_ldq_nucleus(env
, addr
);
2073 env
->gregs
[rd
+ 1] = cpu_ldq_nucleus(env
, addr
+ 8);
2075 bswap64s(&env
->gregs
[rd
]);
2076 bswap64s(&env
->gregs
[rd
+ 1]);
2079 env
->regwptr
[rd
] = cpu_ldq_nucleus(env
, addr
);
2080 env
->regwptr
[rd
+ 1] = cpu_ldq_nucleus(env
, addr
+ 8);
2082 bswap64s(&env
->regwptr
[rd
]);
2083 bswap64s(&env
->regwptr
[rd
+ 1]);
2089 helper_check_align(env
, addr
, 0x3);
2091 env
->gregs
[1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2092 } else if (rd
< 8) {
2093 env
->gregs
[rd
] = helper_ld_asi(env
, addr
, asi
, 4, 0);
2094 env
->gregs
[rd
+ 1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2096 env
->regwptr
[rd
] = helper_ld_asi(env
, addr
, asi
, 4, 0);
2097 env
->regwptr
[rd
+ 1] = helper_ld_asi(env
, addr
+ 4, asi
, 4, 0);
2103 void helper_ldf_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
2109 helper_check_align(env
, addr
, 3);
2110 addr
= asi_address_mask(env
, asi
, addr
);
2113 case 0xf0: /* UA2007/JPS1 Block load primary */
2114 case 0xf1: /* UA2007/JPS1 Block load secondary */
2115 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2116 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2118 helper_raise_exception(env
, TT_ILL_INSN
);
2121 helper_check_align(env
, addr
, 0x3f);
2122 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2123 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
& 0x8f, 8, 0);
2127 case 0x16: /* UA2007 Block load primary, user privilege */
2128 case 0x17: /* UA2007 Block load secondary, user privilege */
2129 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2130 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2131 case 0x70: /* JPS1 Block load primary, user privilege */
2132 case 0x71: /* JPS1 Block load secondary, user privilege */
2133 case 0x78: /* JPS1 Block load primary LE, user privilege */
2134 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2136 helper_raise_exception(env
, TT_ILL_INSN
);
2139 helper_check_align(env
, addr
, 0x3f);
2140 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2141 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
& 0x19, 8, 0);
2152 val
= helper_ld_asi(env
, addr
, asi
, size
, 0);
2154 env
->fpr
[rd
/ 2].l
.lower
= val
;
2156 env
->fpr
[rd
/ 2].l
.upper
= val
;
2160 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
, size
, 0);
2163 env
->fpr
[rd
/ 2].ll
= helper_ld_asi(env
, addr
, asi
, 8, 0);
2164 env
->fpr
[rd
/ 2 + 1].ll
= helper_ld_asi(env
, addr
+ 8, asi
, 8, 0);
2169 void helper_stf_asi(CPUSPARCState
*env
, target_ulong addr
, int asi
, int size
,
2175 helper_check_align(env
, addr
, 3);
2176 addr
= asi_address_mask(env
, asi
, addr
);
2179 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2180 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2181 case 0xf0: /* UA2007/JPS1 Block store primary */
2182 case 0xf1: /* UA2007/JPS1 Block store secondary */
2183 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2184 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2186 helper_raise_exception(env
, TT_ILL_INSN
);
2189 helper_check_align(env
, addr
, 0x3f);
2190 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2191 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
& 0x8f, 8);
2195 case 0x16: /* UA2007 Block load primary, user privilege */
2196 case 0x17: /* UA2007 Block load secondary, user privilege */
2197 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2198 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2199 case 0x70: /* JPS1 Block store primary, user privilege */
2200 case 0x71: /* JPS1 Block store secondary, user privilege */
2201 case 0x78: /* JPS1 Block load primary LE, user privilege */
2202 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2204 helper_raise_exception(env
, TT_ILL_INSN
);
2207 helper_check_align(env
, addr
, 0x3f);
2208 for (i
= 0; i
< 8; i
++, rd
+= 2, addr
+= 8) {
2209 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
& 0x19, 8);
2221 val
= env
->fpr
[rd
/ 2].l
.lower
;
2223 val
= env
->fpr
[rd
/ 2].l
.upper
;
2225 helper_st_asi(env
, addr
, val
, asi
, size
);
2228 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
, size
);
2231 helper_st_asi(env
, addr
, env
->fpr
[rd
/ 2].ll
, asi
, 8);
2232 helper_st_asi(env
, addr
+ 8, env
->fpr
[rd
/ 2 + 1].ll
, asi
, 8);
2237 target_ulong
helper_casx_asi(CPUSPARCState
*env
, target_ulong addr
,
2238 target_ulong val1
, target_ulong val2
,
2243 ret
= helper_ld_asi(env
, addr
, asi
, 8, 0);
2245 helper_st_asi(env
, addr
, val1
, asi
, 8);
2249 #endif /* TARGET_SPARC64 */
2251 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2252 target_ulong
helper_cas_asi(CPUSPARCState
*env
, target_ulong addr
,
2253 target_ulong val1
, target_ulong val2
, uint32_t asi
)
2257 val2
&= 0xffffffffUL
;
2258 ret
= helper_ld_asi(env
, addr
, asi
, 4, 0);
2259 ret
&= 0xffffffffUL
;
2261 helper_st_asi(env
, addr
, val1
& 0xffffffffUL
, asi
, 4);
2265 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2267 void helper_ldqf(CPUSPARCState
*env
, target_ulong addr
, int mem_idx
)
2269 /* XXX add 128 bit load */
2272 helper_check_align(env
, addr
, 7);
2273 #if !defined(CONFIG_USER_ONLY)
2276 u
.ll
.upper
= cpu_ldq_user(env
, addr
);
2277 u
.ll
.lower
= cpu_ldq_user(env
, addr
+ 8);
2280 case MMU_KERNEL_IDX
:
2281 u
.ll
.upper
= cpu_ldq_kernel(env
, addr
);
2282 u
.ll
.lower
= cpu_ldq_kernel(env
, addr
+ 8);
2285 #ifdef TARGET_SPARC64
2287 u
.ll
.upper
= cpu_ldq_hypv(env
, addr
);
2288 u
.ll
.lower
= cpu_ldq_hypv(env
, addr
+ 8);
2293 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx
);
2297 u
.ll
.upper
= ldq_raw(address_mask(env
, addr
));
2298 u
.ll
.lower
= ldq_raw(address_mask(env
, addr
+ 8));
2303 void helper_stqf(CPUSPARCState
*env
, target_ulong addr
, int mem_idx
)
2305 /* XXX add 128 bit store */
2308 helper_check_align(env
, addr
, 7);
2309 #if !defined(CONFIG_USER_ONLY)
2313 cpu_stq_user(env
, addr
, u
.ll
.upper
);
2314 cpu_stq_user(env
, addr
+ 8, u
.ll
.lower
);
2316 case MMU_KERNEL_IDX
:
2318 cpu_stq_kernel(env
, addr
, u
.ll
.upper
);
2319 cpu_stq_kernel(env
, addr
+ 8, u
.ll
.lower
);
2321 #ifdef TARGET_SPARC64
2324 cpu_stq_hypv(env
, addr
, u
.ll
.upper
);
2325 cpu_stq_hypv(env
, addr
+ 8, u
.ll
.lower
);
2329 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx
);
2334 stq_raw(address_mask(env
, addr
), u
.ll
.upper
);
2335 stq_raw(address_mask(env
, addr
+ 8), u
.ll
.lower
);
2339 #if !defined(CONFIG_USER_ONLY)
2340 #ifndef TARGET_SPARC64
2341 void sparc_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2342 bool is_write
, bool is_exec
, int is_asi
,
2345 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2346 CPUSPARCState
*env
= &cpu
->env
;
2349 #ifdef DEBUG_UNASSIGNED
2351 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2352 " asi 0x%02x from " TARGET_FMT_lx
"\n",
2353 is_exec
? "exec" : is_write
? "write" : "read", size
,
2354 size
== 1 ? "" : "s", addr
, is_asi
, env
->pc
);
2356 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2357 " from " TARGET_FMT_lx
"\n",
2358 is_exec
? "exec" : is_write
? "write" : "read", size
,
2359 size
== 1 ? "" : "s", addr
, env
->pc
);
2362 /* Don't overwrite translation and access faults */
2363 fault_type
= (env
->mmuregs
[3] & 0x1c) >> 2;
2364 if ((fault_type
> 4) || (fault_type
== 0)) {
2365 env
->mmuregs
[3] = 0; /* Fault status register */
2367 env
->mmuregs
[3] |= 1 << 16;
2370 env
->mmuregs
[3] |= 1 << 5;
2373 env
->mmuregs
[3] |= 1 << 6;
2376 env
->mmuregs
[3] |= 1 << 7;
2378 env
->mmuregs
[3] |= (5 << 2) | 2;
2379 /* SuperSPARC will never place instruction fault addresses in the FAR */
2381 env
->mmuregs
[4] = addr
; /* Fault address register */
2384 /* overflow (same type fault was not read before another fault) */
2385 if (fault_type
== ((env
->mmuregs
[3] & 0x1c)) >> 2) {
2386 env
->mmuregs
[3] |= 1;
2389 if ((env
->mmuregs
[0] & MMU_E
) && !(env
->mmuregs
[0] & MMU_NF
)) {
2391 helper_raise_exception(env
, TT_CODE_ACCESS
);
2393 helper_raise_exception(env
, TT_DATA_ACCESS
);
2397 /* flush neverland mappings created during no-fault mode,
2398 so the sequential MMU faults report proper fault types */
2399 if (env
->mmuregs
[0] & MMU_NF
) {
2404 void sparc_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2405 bool is_write
, bool is_exec
, int is_asi
,
2408 SPARCCPU
*cpu
= SPARC_CPU(cs
);
2409 CPUSPARCState
*env
= &cpu
->env
;
2411 #ifdef DEBUG_UNASSIGNED
2412 printf("Unassigned mem access to " TARGET_FMT_plx
" from " TARGET_FMT_lx
2413 "\n", addr
, env
->pc
);
2417 helper_raise_exception(env
, TT_CODE_ACCESS
);
2419 helper_raise_exception(env
, TT_DATA_ACCESS
);
2425 #if !defined(CONFIG_USER_ONLY)
2426 static void QEMU_NORETURN
do_unaligned_access(CPUSPARCState
*env
,
2427 target_ulong addr
, int is_write
,
2428 int is_user
, uintptr_t retaddr
)
2430 SPARCCPU
*cpu
= sparc_env_get_cpu(env
);
2431 #ifdef DEBUG_UNALIGNED
2432 printf("Unaligned access to 0x" TARGET_FMT_lx
" from 0x" TARGET_FMT_lx
2433 "\n", addr
, env
->pc
);
2436 cpu_restore_state(CPU(cpu
), retaddr
);
2438 helper_raise_exception(env
, TT_UNALIGNED
);
2441 /* try to fill the TLB and return an exception if error. If retaddr is
2442 NULL, it means that the function was called in C code (i.e. not
2443 from generated code or from helper.c) */
2444 /* XXX: fix it to restore all registers */
2445 void tlb_fill(CPUState
*cs
, target_ulong addr
, int is_write
, int mmu_idx
,
2450 ret
= sparc_cpu_handle_mmu_fault(cs
, addr
, is_write
, mmu_idx
);
2453 cpu_restore_state(cs
, retaddr
);