target-openrisc/sys_helper.c

   1 /*
   2  * OpenRISC system instructions helper routines
   3  *
   4  * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5  *                         Zhizhou Zhang <etouzh@gmail.com>
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "helper.h"
  23
  24 #define TO_SPR(group, number) (((group) << 11) + (number))
  25
  26 void HELPER(mtspr)(CPUOpenRISCState *env,
  27                    target_ulong ra, target_ulong rb, target_ulong offset)
  28 {
  29 #ifndef CONFIG_USER_ONLY
  30     int spr = (ra | offset);
  31     int idx;
  32
  33     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
  34     CPUState *cs = CPU(cpu);
  35
  36     switch (spr) {
  37     case TO_SPR(0, 0): /* VR */
  38         env->vr = rb;
  39         break;
  40
  41     case TO_SPR(0, 16): /* NPC */
  42         env->npc = rb;
  43         break;
  44
  45     case TO_SPR(0, 17): /* SR */
  46         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
  47             (rb & (SR_IME | SR_DME | SR_SM))) {
  48             tlb_flush(env, 1);
  49         }
  50         env->sr = rb;
  51         env->sr |= SR_FO;      /* FO is const equal to 1 */
  52         if (env->sr & SR_DME) {
  53             env->tlb->cpu_openrisc_map_address_data =
  54                 &cpu_openrisc_get_phys_data;
  55         } else {
  56             env->tlb->cpu_openrisc_map_address_data =
  57                 &cpu_openrisc_get_phys_nommu;
  58         }
  59
  60         if (env->sr & SR_IME) {
  61             env->tlb->cpu_openrisc_map_address_code =
  62                 &cpu_openrisc_get_phys_code;
  63         } else {
  64             env->tlb->cpu_openrisc_map_address_code =
  65                 &cpu_openrisc_get_phys_nommu;
  66         }
  67         break;
  68
  69     case TO_SPR(0, 18): /* PPC */
  70         env->ppc = rb;
  71         break;
  72
  73     case TO_SPR(0, 32): /* EPCR */
  74         env->epcr = rb;
  75         break;
  76
  77     case TO_SPR(0, 48): /* EEAR */
  78         env->eear = rb;
  79         break;
  80
  81     case TO_SPR(0, 64): /* ESR */
  82         env->esr = rb;
  83         break;
  84     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
  85         idx = spr - TO_SPR(1, 512);
  86         if (!(rb & 1)) {
  87             tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
  88         }
  89         env->tlb->dtlb[0][idx].mr = rb;
  90         break;
  91
  92     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
  93         idx = spr - TO_SPR(1, 640);
  94         env->tlb->dtlb[0][idx].tr = rb;
  95         break;
  96     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
  97     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
  98     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
  99     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 100     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 101     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 102         break;
 103     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
 104         idx = spr - TO_SPR(2, 512);
 105         if (!(rb & 1)) {
 106             tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
 107         }
 108         env->tlb->itlb[0][idx].mr = rb;
 109         break;
 110
 111     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 112         idx = spr - TO_SPR(2, 640);
 113         env->tlb->itlb[0][idx].tr = rb;
 114         break;
 115     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 116     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 117     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 118     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 119     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 120     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 121         break;
 122     case TO_SPR(9, 0):  /* PICMR */
 123         env->picmr |= rb;
 124         break;
 125     case TO_SPR(9, 2):  /* PICSR */
 126         env->picsr &= ~rb;
 127         break;
 128     case TO_SPR(10, 0): /* TTMR */
 129         {
 130             if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
 131                 switch (rb & TTMR_M) {
 132                 case TIMER_NONE:
 133                     cpu_openrisc_count_stop(cpu);
 134                     break;
 135                 case TIMER_INTR:
 136                 case TIMER_SHOT:
 137                 case TIMER_CONT:
 138                     cpu_openrisc_count_start(cpu);
 139                     break;
 140                 default:
 141                     break;
 142                 }
 143             }
 144
 145             int ip = env->ttmr & TTMR_IP;
 146
 147             if (rb & TTMR_IP) {    /* Keep IP bit.  */
 148                 env->ttmr = (rb & ~TTMR_IP) | ip;
 149             } else {    /* Clear IP bit.  */
 150                 env->ttmr = rb & ~TTMR_IP;
 151                 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 152             }
 153
 154             cpu_openrisc_timer_update(cpu);
 155         }
 156         break;
 157
 158     case TO_SPR(10, 1): /* TTCR */
 159         env->ttcr = rb;
 160         if (env->ttmr & TIMER_NONE) {
 161             return;
 162         }
 163         cpu_openrisc_timer_update(cpu);
 164         break;
 165     default:
 166
 167         break;
 168     }
 169 #endif
 170 }
 171
 172 target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
 173                            target_ulong rd, target_ulong ra, uint32_t offset)
 174 {
 175 #ifndef CONFIG_USER_ONLY
 176     int spr = (ra | offset);
 177     int idx;
 178
 179     OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
 180
 181     switch (spr) {
 182     case TO_SPR(0, 0): /* VR */
 183         return env->vr & SPR_VR;
 184
 185     case TO_SPR(0, 1): /* UPR */
 186         return env->upr;    /* TT, DM, IM, UP present */
 187
 188     case TO_SPR(0, 2): /* CPUCFGR */
 189         return env->cpucfgr;
 190
 191     case TO_SPR(0, 3): /* DMMUCFGR */
 192         return env->dmmucfgr;    /* 1Way, 64 entries */
 193
 194     case TO_SPR(0, 4): /* IMMUCFGR */
 195         return env->immucfgr;
 196
 197     case TO_SPR(0, 16): /* NPC */
 198         return env->npc;
 199
 200     case TO_SPR(0, 17): /* SR */
 201         return env->sr;
 202
 203     case TO_SPR(0, 18): /* PPC */
 204         return env->ppc;
 205
 206     case TO_SPR(0, 32): /* EPCR */
 207         return env->epcr;
 208
 209     case TO_SPR(0, 48): /* EEAR */
 210         return env->eear;
 211
 212     case TO_SPR(0, 64): /* ESR */
 213         return env->esr;
 214
 215     case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
 216         idx = spr - TO_SPR(1, 512);
 217         return env->tlb->dtlb[0][idx].mr;
 218
 219     case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
 220         idx = spr - TO_SPR(1, 640);
 221         return env->tlb->dtlb[0][idx].tr;
 222
 223     case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
 224     case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
 225     case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
 226     case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
 227     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
 228     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
 229         break;
 230
 231     case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
 232         idx = spr - TO_SPR(2, 512);
 233         return env->tlb->itlb[0][idx].mr;
 234
 235     case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
 236         idx = spr - TO_SPR(2, 640);
 237         return env->tlb->itlb[0][idx].tr;
 238
 239     case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
 240     case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
 241     case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
 242     case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
 243     case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
 244     case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
 245         break;
 246
 247     case TO_SPR(9, 0):  /* PICMR */
 248         return env->picmr;
 249
 250     case TO_SPR(9, 2):  /* PICSR */
 251         return env->picsr;
 252
 253     case TO_SPR(10, 0): /* TTMR */
 254         return env->ttmr;
 255
 256     case TO_SPR(10, 1): /* TTCR */
 257         cpu_openrisc_count_update(cpu);
 258         return env->ttcr;
 259
 260     default:
 261         break;
 262     }
 263 #endif
 264
 265 /*If we later need to add tracepoints (or debug printfs) for the return
 266 value, it may be useful to structure the code like this:
 267
 268 target_ulong ret = 0;
 269
 270 switch() {
 271 case x:
 272  ret = y;
 273  break;
 274 case z:
 275  ret = 42;
 276  break;
 277 ...
 278 }
 279
 280 later something like trace_spr_read(ret);
 281
 282 return ret;*/
 283
 284     /* for rd is passed in, if rd unchanged, just keep it back.  */
 285     return rd;
 286 }