hw/ide/cmd646.c

   1 /*
   2  * QEMU IDE Emulation: PCI cmd646 support.
   3  *
   4  * Copyright (c) 2003 Fabrice Bellard
   5  * Copyright (c) 2006 Openedhand Ltd.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include <hw/hw.h>
  26 #include <hw/i386/pc.h>
  27 #include <hw/pci/pci.h>
  28 #include <hw/isa/isa.h>
  29 #include "sysemu/block-backend.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/dma.h"
  32
  33 #include <hw/ide/pci.h>
  34
  35 /* CMD646 specific */
  36 #define CFR             0x50
  37 #define   CFR_INTR_CH0  0x04
  38 #define CNTRL           0x51
  39 #define   CNTRL_EN_CH0  0x04
  40 #define   CNTRL_EN_CH1  0x08
  41 #define ARTTIM23        0x57
  42 #define    ARTTIM23_INTR_CH1    0x10
  43 #define MRDMODE         0x71
  44 #define   MRDMODE_INTR_CH0      0x04
  45 #define   MRDMODE_INTR_CH1      0x08
  46 #define   MRDMODE_BLK_CH0       0x10
  47 #define   MRDMODE_BLK_CH1       0x20
  48 #define UDIDETCR0       0x73
  49 #define UDIDETCR1       0x7B
  50
  51 static void cmd646_update_irq(PCIDevice *pd);
  52
  53 static uint64_t cmd646_cmd_read(void *opaque, hwaddr addr,
  54                                 unsigned size)
  55 {
  56     CMD646BAR *cmd646bar = opaque;
  57
  58     if (addr != 2 || size != 1) {
  59         return ((uint64_t)1 << (size * 8)) - 1;
  60     }
  61     return ide_status_read(cmd646bar->bus, addr + 2);
  62 }
  63
  64 static void cmd646_cmd_write(void *opaque, hwaddr addr,
  65                              uint64_t data, unsigned size)
  66 {
  67     CMD646BAR *cmd646bar = opaque;
  68
  69     if (addr != 2 || size != 1) {
  70         return;
  71     }
  72     ide_cmd_write(cmd646bar->bus, addr + 2, data);
  73 }
  74
  75 static const MemoryRegionOps cmd646_cmd_ops = {
  76     .read = cmd646_cmd_read,
  77     .write = cmd646_cmd_write,
  78     .endianness = DEVICE_LITTLE_ENDIAN,
  79 };
  80
  81 static uint64_t cmd646_data_read(void *opaque, hwaddr addr,
  82                                  unsigned size)
  83 {
  84     CMD646BAR *cmd646bar = opaque;
  85
  86     if (size == 1) {
  87         return ide_ioport_read(cmd646bar->bus, addr);
  88     } else if (addr == 0) {
  89         if (size == 2) {
  90             return ide_data_readw(cmd646bar->bus, addr);
  91         } else {
  92             return ide_data_readl(cmd646bar->bus, addr);
  93         }
  94     }
  95     return ((uint64_t)1 << (size * 8)) - 1;
  96 }
  97
  98 static void cmd646_data_write(void *opaque, hwaddr addr,
  99                              uint64_t data, unsigned size)
 100 {
 101     CMD646BAR *cmd646bar = opaque;
 102
 103     if (size == 1) {
 104         ide_ioport_write(cmd646bar->bus, addr, data);
 105     } else if (addr == 0) {
 106         if (size == 2) {
 107             ide_data_writew(cmd646bar->bus, addr, data);
 108         } else {
 109             ide_data_writel(cmd646bar->bus, addr, data);
 110         }
 111     }
 112 }
 113
 114 static const MemoryRegionOps cmd646_data_ops = {
 115     .read = cmd646_data_read,
 116     .write = cmd646_data_write,
 117     .endianness = DEVICE_LITTLE_ENDIAN,
 118 };
 119
 120 static void setup_cmd646_bar(PCIIDEState *d, int bus_num)
 121 {
 122     IDEBus *bus = &d->bus[bus_num];
 123     CMD646BAR *bar = &d->cmd646_bar[bus_num];
 124
 125     bar->bus = bus;
 126     bar->pci_dev = d;
 127     memory_region_init_io(&bar->cmd, OBJECT(d), &cmd646_cmd_ops, bar,
 128                           "cmd646-cmd", 4);
 129     memory_region_init_io(&bar->data, OBJECT(d), &cmd646_data_ops, bar,
 130                           "cmd646-data", 8);
 131 }
 132
 133 static void cmd646_update_dma_interrupts(PCIDevice *pd)
 134 {
 135     /* Sync DMA interrupt status from UDMA interrupt status */
 136     if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) {
 137         pd->config[CFR] |= CFR_INTR_CH0;
 138     } else {
 139         pd->config[CFR] &= ~CFR_INTR_CH0;
 140     }
 141
 142     if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) {
 143         pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1;
 144     } else {
 145         pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1;
 146     }
 147 }
 148
 149 static void cmd646_update_udma_interrupts(PCIDevice *pd)
 150 {
 151     /* Sync UDMA interrupt status from DMA interrupt status */
 152     if (pd->config[CFR] & CFR_INTR_CH0) {
 153         pd->config[MRDMODE] |= MRDMODE_INTR_CH0;
 154     } else {
 155         pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0;
 156     }
 157
 158     if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) {
 159         pd->config[MRDMODE] |= MRDMODE_INTR_CH1;
 160     } else {
 161         pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1;
 162     }
 163 }
 164
 165 static uint64_t bmdma_read(void *opaque, hwaddr addr,
 166                            unsigned size)
 167 {
 168     BMDMAState *bm = opaque;
 169     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 170     uint32_t val;
 171
 172     if (size != 1) {
 173         return ((uint64_t)1 << (size * 8)) - 1;
 174     }
 175
 176     switch(addr & 3) {
 177     case 0:
 178         val = bm->cmd;
 179         break;
 180     case 1:
 181         val = pci_dev->config[MRDMODE];
 182         break;
 183     case 2:
 184         val = bm->status;
 185         break;
 186     case 3:
 187         if (bm == &bm->pci_dev->bmdma[0]) {
 188             val = pci_dev->config[UDIDETCR0];
 189         } else {
 190             val = pci_dev->config[UDIDETCR1];
 191         }
 192         break;
 193     default:
 194         val = 0xff;
 195         break;
 196     }
 197 #ifdef DEBUG_IDE
 198     printf("bmdma: readb " TARGET_FMT_plx " : 0x%02x\n", addr, val);
 199 #endif
 200     return val;
 201 }
 202
 203 static void bmdma_write(void *opaque, hwaddr addr,
 204                         uint64_t val, unsigned size)
 205 {
 206     BMDMAState *bm = opaque;
 207     PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev);
 208
 209     if (size != 1) {
 210         return;
 211     }
 212
 213 #ifdef DEBUG_IDE
 214     printf("bmdma: writeb " TARGET_FMT_plx " : 0x%" PRIx64 "\n", addr, val);
 215 #endif
 216     switch(addr & 3) {
 217     case 0:
 218         bmdma_cmd_writeb(bm, val);
 219         break;
 220     case 1:
 221         pci_dev->config[MRDMODE] =
 222             (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30);
 223         cmd646_update_dma_interrupts(pci_dev);
 224         cmd646_update_irq(pci_dev);
 225         break;
 226     case 2:
 227         bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
 228         break;
 229     case 3:
 230         if (bm == &bm->pci_dev->bmdma[0]) {
 231             pci_dev->config[UDIDETCR0] = val;
 232         } else {
 233             pci_dev->config[UDIDETCR1] = val;
 234         }
 235         break;
 236     }
 237 }
 238
 239 static const MemoryRegionOps cmd646_bmdma_ops = {
 240     .read = bmdma_read,
 241     .write = bmdma_write,
 242 };
 243
 244 static void bmdma_setup_bar(PCIIDEState *d)
 245 {
 246     BMDMAState *bm;
 247     int i;
 248
 249     memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16);
 250     for(i = 0;i < 2; i++) {
 251         bm = &d->bmdma[i];
 252         memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm,
 253                               "cmd646-bmdma-bus", 4);
 254         memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io);
 255         memory_region_init_io(&bm->addr_ioport, OBJECT(d),
 256                               &bmdma_addr_ioport_ops, bm,
 257                               "cmd646-bmdma-ioport", 4);
 258         memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport);
 259     }
 260 }
 261
 262 static void cmd646_update_irq(PCIDevice *pd)
 263 {
 264     int pci_level;
 265
 266     pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) &&
 267                  !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
 268         ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
 269          !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
 270     pci_set_irq(pd, pci_level);
 271 }
 272
 273 /* the PCI irq level is the logical OR of the two channels */
 274 static void cmd646_set_irq(void *opaque, int channel, int level)
 275 {
 276     PCIIDEState *d = opaque;
 277     PCIDevice *pd = PCI_DEVICE(d);
 278     int irq_mask;
 279
 280     irq_mask = MRDMODE_INTR_CH0 << channel;
 281     if (level) {
 282         pd->config[MRDMODE] |= irq_mask;
 283     } else {
 284         pd->config[MRDMODE] &= ~irq_mask;
 285     }
 286     cmd646_update_dma_interrupts(pd);
 287     cmd646_update_irq(pd);
 288 }
 289
 290 static void cmd646_reset(void *opaque)
 291 {
 292     PCIIDEState *d = opaque;
 293     unsigned int i;
 294
 295     for (i = 0; i < 2; i++) {
 296         ide_bus_reset(&d->bus[i]);
 297     }
 298 }
 299
 300 static uint32_t cmd646_pci_config_read(PCIDevice *d,
 301                                        uint32_t address, int len)
 302 {
 303     return pci_default_read_config(d, address, len);
 304 }
 305
 306 static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val,
 307                                     int l)
 308 {
 309     uint32_t i;
 310
 311     pci_default_write_config(d, addr, val, l);
 312
 313     for (i = addr; i < addr + l; i++) {
 314         switch (i) {
 315         case CFR:
 316         case ARTTIM23:
 317             cmd646_update_udma_interrupts(d);
 318             break;
 319         case MRDMODE:
 320             cmd646_update_dma_interrupts(d);
 321             break;
 322         }
 323     }
 324
 325     cmd646_update_irq(d);
 326 }
 327
 328 /* CMD646 PCI IDE controller */
 329 static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
 330 {
 331     PCIIDEState *d = PCI_IDE(dev);
 332     uint8_t *pci_conf = dev->config;
 333     qemu_irq *irq;
 334     int i;
 335
 336     pci_conf[PCI_CLASS_PROG] = 0x8f;
 337
 338     pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0
 339     if (d->secondary) {
 340         /* XXX: if not enabled, really disable the seconday IDE controller */
 341         pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */
 342     }
 343
 344     /* Set write-to-clear interrupt bits */
 345     dev->wmask[CFR] = 0x0;
 346     dev->w1cmask[CFR] = CFR_INTR_CH0;
 347     dev->wmask[ARTTIM23] = 0x0;
 348     dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1;
 349     dev->wmask[MRDMODE] = 0x0;
 350     dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1;
 351
 352     setup_cmd646_bar(d, 0);
 353     setup_cmd646_bar(d, 1);
 354     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].data);
 355     pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[0].cmd);
 356     pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].data);
 357     pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd646_bar[1].cmd);
 358     bmdma_setup_bar(d);
 359     pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar);
 360
 361     /* TODO: RST# value should be 0 */
 362     pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1
 363
 364     irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
 365     for (i = 0; i < 2; i++) {
 366         ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2);
 367         ide_init2(&d->bus[i], irq[i]);
 368
 369         bmdma_init(&d->bus[i], &d->bmdma[i], d);
 370         d->bmdma[i].bus = &d->bus[i];
 371         ide_register_restart_cb(&d->bus[i]);
 372     }
 373
 374     vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d);
 375     qemu_register_reset(cmd646_reset, d);
 376 }
 377
 378 static void pci_cmd646_ide_exitfn(PCIDevice *dev)
 379 {
 380     PCIIDEState *d = PCI_IDE(dev);
 381     unsigned i;
 382
 383     for (i = 0; i < 2; ++i) {
 384         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io);
 385         memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport);
 386     }
 387 }
 388
 389 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
 390                          int secondary_ide_enabled)
 391 {
 392     PCIDevice *dev;
 393
 394     dev = pci_create(bus, -1, "cmd646-ide");
 395     qdev_prop_set_uint32(&dev->qdev, "secondary", secondary_ide_enabled);
 396     qdev_init_nofail(&dev->qdev);
 397
 398     pci_ide_create_devs(dev, hd_table);
 399 }
 400
 401 static Property cmd646_ide_properties[] = {
 402     DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0),
 403     DEFINE_PROP_END_OF_LIST(),
 404 };
 405
 406 static void cmd646_ide_class_init(ObjectClass *klass, void *data)
 407 {
 408     DeviceClass *dc = DEVICE_CLASS(klass);
 409     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 410
 411     k->realize = pci_cmd646_ide_realize;
 412     k->exit = pci_cmd646_ide_exitfn;
 413     k->vendor_id = PCI_VENDOR_ID_CMD;
 414     k->device_id = PCI_DEVICE_ID_CMD_646;
 415     k->revision = 0x07;
 416     k->class_id = PCI_CLASS_STORAGE_IDE;
 417     k->config_read = cmd646_pci_config_read;
 418     k->config_write = cmd646_pci_config_write;
 419     dc->props = cmd646_ide_properties;
 420 }
 421
 422 static const TypeInfo cmd646_ide_info = {
 423     .name          = "cmd646-ide",
 424     .parent        = TYPE_PCI_IDE,
 425     .class_init    = cmd646_ide_class_init,
 426 };
 427
 428 static void cmd646_ide_register_types(void)
 429 {
 430     type_register_static(&cmd646_ide_info);
 431 }
 432
 433 type_init(cmd646_ide_register_types)