2 * QEMU PowerPC XIVE interrupt controller model
5 * The POWER9 processor comes with a new interrupt controller, called
6 * XIVE as "eXternal Interrupt Virtualization Engine".
8 * = Overall architecture
11 * XIVE Interrupt Controller
12 * +------------------------------------+ IPIs
13 * | +---------+ +---------+ +--------+ | +-------+
14 * | |VC | |CQ | |PC |----> | CORES |
15 * | | esb | | | | |----> | |
16 * | | eas | | Bridge | | tctx |----> | |
17 * | |SC end | | | | nvt | | | |
18 * +------+ | +---------+ +----+----+ +--------+ | +-+-+-+-+
19 * | RAM | +------------------|-----------------+ | | |
22 * | | +--------------------v------------------------v-v-v--+ other
23 * | <--+ Power Bus +--> chips
24 * | esb | +---------+-----------------------+------------------+
26 * | end | +--|------+ |
27 * | nvt | +----+----+ | +----+----+
28 * +------+ |SC | | |SC |
30 * | PQ-bits | | | PQ-bits |
31 * | local |-+ | in VC |
32 * +---------+ +---------+
35 * SC: Source Controller (aka. IVSE)
36 * VC: Virtualization Controller (aka. IVRE)
37 * PC: Presentation Controller (aka. IVPE)
38 * CQ: Common Queue (Bridge)
40 * PQ-bits: 2 bits source state machine (P:pending Q:queued)
41 * esb: Event State Buffer (Array of PQ bits in an IVSE)
42 * eas: Event Assignment Structure
43 * end: Event Notification Descriptor
44 * nvt: Notification Virtual Target
45 * tctx: Thread interrupt Context
48 * The XIVE IC is composed of three sub-engines :
50 * - Interrupt Virtualization Source Engine (IVSE), or Source
51 * Controller (SC). These are found in PCI PHBs, in the PSI host
52 * bridge controller, but also inside the main controller for the
53 * core IPIs and other sub-chips (NX, CAP, NPU) of the
54 * chip/processor. They are configured to feed the IVRE with events.
56 * - Interrupt Virtualization Routing Engine (IVRE) or Virtualization
57 * Controller (VC). Its job is to match an event source with an
58 * Event Notification Descriptor (END).
60 * - Interrupt Virtualization Presentation Engine (IVPE) or
61 * Presentation Controller (PC). It maintains the interrupt context
62 * state of each thread and handles the delivery of the external
63 * exception to the thread.
65 * In XIVE 1.0, the sub-engines used to be referred as:
67 * SC Source Controller
68 * VC Virtualization Controller
69 * PC Presentation Controller
70 * CQ Common Queue (PowerBUS Bridge)
73 * = XIVE internal tables
75 * Each of the sub-engines uses a set of tables to redirect exceptions
76 * from event sources to CPU threads.
80 * or +------>|entries|
85 * +-------------------------------------------------+
87 * Hypervisor +------+ +---+--+ +---+--+ +------+
88 * Memory | ESB | | EAT | | ENDT | | NVTT |
89 * (skiboot) +----+-+ +----+-+ +----+-+ +------+
92 * +-------------------------------------------------+
95 * +----|--|--------|--|--------|--|-+ +-|-----+ +------+
96 * | | | | | | | | | | tctx| |Thread|
97 * IPI or --> | + v + v + v |---| + .. |-----> |
98 * HW events --> | | | | | |
99 * IVSE | IVRE | | IVPE | +------+
100 * +---------------------------------+ +-------+
104 * The IVSE have a 2-bits state machine, P for pending and Q for queued,
105 * for each source that allows events to be triggered. They are stored in
106 * an Event State Buffer (ESB) array and can be controlled by MMIOs.
108 * If the event is let through, the IVRE looks up in the Event Assignment
109 * Structure (EAS) table for an Event Notification Descriptor (END)
110 * configured for the source. Each Event Notification Descriptor defines
111 * a notification path to a CPU and an in-memory Event Queue, in which
112 * will be enqueued an EQ data for the OS to pull.
114 * The IVPE determines if a Notification Virtual Target (NVT) can
115 * handle the event by scanning the thread contexts of the VCPUs
116 * dispatched on the processor HW threads. It maintains the state of
117 * the thread interrupt context (TCTX) of each thread in a NVT table.
121 * Description In XIVE 1.0, used to be referred as
123 * EAS Event Assignment Structure IVE Interrupt Virt. Entry
124 * EAT Event Assignment Table IVT Interrupt Virt. Table
125 * ENDT Event Notif. Descriptor Table EQDT Event Queue Desc. Table
126 * EQ Event Queue same
127 * ESB Event State Buffer SBE State Bit Entry
128 * NVT Notif. Virtual Target VPD Virtual Processor Desc.
129 * NVTT Notif. Virtual Target Table VPDT Virtual Processor Desc. Table
130 * TCTX Thread interrupt Context
133 * Copyright (c) 2017-2018, IBM Corporation.
135 * This code is licensed under the GPL version 2 or later. See the
136 * COPYING file in the top-level directory.
143 #include "sysemu/kvm.h"
144 #include "hw/qdev-core.h"
145 #include "hw/sysbus.h"
146 #include "hw/ppc/xive_regs.h"
149 * XIVE Notifier (Interface between Source and Router)
152 typedef struct XiveNotifier
{
156 #define TYPE_XIVE_NOTIFIER "xive-notifier"
157 #define XIVE_NOTIFIER(obj) \
158 OBJECT_CHECK(XiveNotifier, (obj), TYPE_XIVE_NOTIFIER)
159 #define XIVE_NOTIFIER_CLASS(klass) \
160 OBJECT_CLASS_CHECK(XiveNotifierClass, (klass), TYPE_XIVE_NOTIFIER)
161 #define XIVE_NOTIFIER_GET_CLASS(obj) \
162 OBJECT_GET_CLASS(XiveNotifierClass, (obj), TYPE_XIVE_NOTIFIER)
164 typedef struct XiveNotifierClass
{
165 InterfaceClass parent
;
166 void (*notify
)(XiveNotifier
*xn
, uint32_t lisn
);
170 * XIVE Interrupt Source
173 #define TYPE_XIVE_SOURCE "xive-source"
174 #define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE)
177 * XIVE Interrupt Source characteristics, which define how the ESB are
180 #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
181 #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
183 typedef struct XiveSource
{
188 unsigned long *lsi_map
;
190 /* PQ bits and LSI assertion bit */
193 /* ESB memory region */
196 MemoryRegion esb_mmio
;
200 MemoryRegion esb_mmio_kvm
;
206 * ESB MMIO setting. Can be one page, for both source triggering and
207 * source management, or two different pages. See below for magic
210 #define XIVE_ESB_4K 12 /* PSI HB only */
211 #define XIVE_ESB_4K_2PAGE 13
212 #define XIVE_ESB_64K 16
213 #define XIVE_ESB_64K_2PAGE 17
215 static inline bool xive_source_esb_has_2page(XiveSource
*xsrc
)
217 return xsrc
->esb_shift
== XIVE_ESB_64K_2PAGE
||
218 xsrc
->esb_shift
== XIVE_ESB_4K_2PAGE
;
221 /* The trigger page is always the first/even page */
222 static inline hwaddr
xive_source_esb_page(XiveSource
*xsrc
, uint32_t srcno
)
224 assert(srcno
< xsrc
->nr_irqs
);
225 return (1ull << xsrc
->esb_shift
) * srcno
;
228 /* In a two pages ESB MMIO setting, the odd page is for management */
229 static inline hwaddr
xive_source_esb_mgmt(XiveSource
*xsrc
, int srcno
)
231 hwaddr addr
= xive_source_esb_page(xsrc
, srcno
);
233 if (xive_source_esb_has_2page(xsrc
)) {
234 addr
+= (1 << (xsrc
->esb_shift
- 1));
241 * Each interrupt source has a 2-bit state machine which can be
242 * controlled by MMIO. P indicates that an interrupt is pending (has
243 * been sent to a queue and is waiting for an EOI). Q indicates that
244 * the interrupt has been triggered while pending.
246 * This acts as a coalescing mechanism in order to guarantee that a
247 * given interrupt only occurs at most once in a queue.
249 * When doing an EOI, the Q bit will indicate if the interrupt
250 * needs to be re-triggered.
252 #define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */
253 #define XIVE_ESB_VAL_P 0x2
254 #define XIVE_ESB_VAL_Q 0x1
256 #define XIVE_ESB_RESET 0x0
257 #define XIVE_ESB_PENDING XIVE_ESB_VAL_P
258 #define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
259 #define XIVE_ESB_OFF XIVE_ESB_VAL_Q
262 * "magic" Event State Buffer (ESB) MMIO offsets.
264 * The following offsets into the ESB MMIO allow to read or manipulate
265 * the PQ bits. They must be used with an 8-byte load instruction.
266 * They all return the previous state of the interrupt (atomically).
268 * Additionally, some ESB pages support doing an EOI via a store and
269 * some ESBs support doing a trigger via a separate trigger page.
271 #define XIVE_ESB_STORE_EOI 0x400 /* Store */
272 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */
273 #define XIVE_ESB_GET 0x800 /* Load */
274 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
275 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
276 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
277 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
279 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
);
280 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
);
282 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
,
285 static inline bool xive_source_irq_is_lsi(XiveSource
*xsrc
, uint32_t srcno
)
287 assert(srcno
< xsrc
->nr_irqs
);
288 return test_bit(srcno
, xsrc
->lsi_map
);
291 static inline void xive_source_irq_set_lsi(XiveSource
*xsrc
, uint32_t srcno
)
293 assert(srcno
< xsrc
->nr_irqs
);
294 bitmap_set(xsrc
->lsi_map
, srcno
, 1);
297 void xive_source_set_irq(void *opaque
, int srcno
, int val
);
300 * XIVE Thread interrupt Management (TM) context
303 #define TYPE_XIVE_TCTX "xive-tctx"
304 #define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
307 * XIVE Thread interrupt Management register rings :
309 * QW-0 User event-based exception state
310 * QW-1 O/S OS context for priority management, interrupt acks
311 * QW-2 Pool hypervisor pool context for virtual processors dispatched
312 * QW-3 Physical physical thread context and security context
314 #define XIVE_TM_RING_COUNT 4
315 #define XIVE_TM_RING_SIZE 0x10
317 typedef struct XiveTCTX
{
318 DeviceState parent_obj
;
324 uint8_t regs
[XIVE_TM_RING_COUNT
* XIVE_TM_RING_SIZE
];
331 typedef struct XiveRouter
{
335 #define TYPE_XIVE_ROUTER "xive-router"
336 #define XIVE_ROUTER(obj) \
337 OBJECT_CHECK(XiveRouter, (obj), TYPE_XIVE_ROUTER)
338 #define XIVE_ROUTER_CLASS(klass) \
339 OBJECT_CLASS_CHECK(XiveRouterClass, (klass), TYPE_XIVE_ROUTER)
340 #define XIVE_ROUTER_GET_CLASS(obj) \
341 OBJECT_GET_CLASS(XiveRouterClass, (obj), TYPE_XIVE_ROUTER)
343 typedef struct XiveRouterClass
{
344 SysBusDeviceClass parent
;
346 /* XIVE table accessors */
347 int (*get_eas
)(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
349 int (*get_end
)(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
351 int (*write_end
)(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
352 XiveEND
*end
, uint8_t word_number
);
353 int (*get_nvt
)(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
355 int (*write_nvt
)(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
356 XiveNVT
*nvt
, uint8_t word_number
);
357 XiveTCTX
*(*get_tctx
)(XiveRouter
*xrtr
, CPUState
*cs
);
360 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
);
362 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
364 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
366 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
367 XiveEND
*end
, uint8_t word_number
);
368 int xive_router_get_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
370 int xive_router_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
371 XiveNVT
*nvt
, uint8_t word_number
);
372 XiveTCTX
*xive_router_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
);
373 void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
);
379 #define TYPE_XIVE_END_SOURCE "xive-end-source"
380 #define XIVE_END_SOURCE(obj) \
381 OBJECT_CHECK(XiveENDSource, (obj), TYPE_XIVE_END_SOURCE)
383 typedef struct XiveENDSource
{
389 /* ESB memory region */
391 MemoryRegion esb_mmio
;
397 * For legacy compatibility, the exceptions define up to 256 different
398 * priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
399 * and the least favored level 0xFF.
401 #define XIVE_PRIORITY_MAX 7
403 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
);
404 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
);
407 * XIVE Thread Interrupt Management Aera (TIMA)
409 * This region gives access to the registers of the thread interrupt
410 * management context. It is four page wide, each page providing a
411 * different view of the registers. The page with the lower offset is
412 * the most privileged and gives access to the entire context.
414 #define XIVE_TM_HW_PAGE 0x0
415 #define XIVE_TM_HV_PAGE 0x1
416 #define XIVE_TM_OS_PAGE 0x2
417 #define XIVE_TM_USER_PAGE 0x3
419 extern const MemoryRegionOps xive_tm_ops
;
420 void xive_tctx_tm_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
422 uint64_t xive_tctx_tm_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
);
424 void xive_tctx_pic_print_info(XiveTCTX
*tctx
, Monitor
*mon
);
425 Object
*xive_tctx_create(Object
*cpu
, XiveRouter
*xrtr
, Error
**errp
);
427 static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk
, uint32_t nvt_idx
)
429 return (nvt_blk
<< 19) | nvt_idx
;
433 * KVM XIVE device helpers
436 void kvmppc_xive_source_reset_one(XiveSource
*xsrc
, int srcno
, Error
**errp
);
437 void kvmppc_xive_source_set_irq(void *opaque
, int srcno
, int val
);
438 void kvmppc_xive_cpu_connect(XiveTCTX
*tctx
, Error
**errp
);
439 void kvmppc_xive_cpu_synchronize_state(XiveTCTX
*tctx
, Error
**errp
);
440 void kvmppc_xive_cpu_get_state(XiveTCTX
*tctx
, Error
**errp
);
441 void kvmppc_xive_cpu_set_state(XiveTCTX
*tctx
, Error
**errp
);
443 #endif /* PPC_XIVE_H */