3 #include "exec/gdbstub.h"
5 #include "qemu/host-utils.h"
6 #include "sysemu/arch_init.h"
7 #include "sysemu/sysemu.h"
8 #include "qemu/bitops.h"
9 #include "qemu/crc32c.h"
10 #include <zlib.h> /* For crc32 */
12 #ifndef CONFIG_USER_ONLY
13 #include "exec/softmmu_exec.h"
15 static inline int get_phys_addr(CPUARMState
*env
, target_ulong address
,
16 int access_type
, int is_user
,
17 hwaddr
*phys_ptr
, int *prot
,
18 target_ulong
*page_size
);
20 /* Definitions for the PMCCNTR and PMCR registers */
26 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
30 /* VFP data registers are always little-endian. */
31 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
33 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
36 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
37 /* Aliases for Q regs. */
40 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
41 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
45 switch (reg
- nregs
) {
46 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
47 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
48 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
53 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
57 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
59 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
62 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
65 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
66 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
70 switch (reg
- nregs
) {
71 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
72 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
73 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
78 static int aarch64_fpu_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
82 /* 128 bit FP register */
83 stfq_le_p(buf
, env
->vfp
.regs
[reg
* 2]);
84 stfq_le_p(buf
+ 8, env
->vfp
.regs
[reg
* 2 + 1]);
88 stl_p(buf
, vfp_get_fpsr(env
));
92 stl_p(buf
, vfp_get_fpcr(env
));
99 static int aarch64_fpu_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
103 /* 128 bit FP register */
104 env
->vfp
.regs
[reg
* 2] = ldfq_le_p(buf
);
105 env
->vfp
.regs
[reg
* 2 + 1] = ldfq_le_p(buf
+ 8);
109 vfp_set_fpsr(env
, ldl_p(buf
));
113 vfp_set_fpcr(env
, ldl_p(buf
));
120 static uint64_t raw_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
122 if (cpreg_field_is_64bit(ri
)) {
123 return CPREG_FIELD64(env
, ri
);
125 return CPREG_FIELD32(env
, ri
);
129 static void raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
132 if (cpreg_field_is_64bit(ri
)) {
133 CPREG_FIELD64(env
, ri
) = value
;
135 CPREG_FIELD32(env
, ri
) = value
;
139 static uint64_t read_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
141 /* Raw read of a coprocessor register (as needed for migration, etc). */
142 if (ri
->type
& ARM_CP_CONST
) {
143 return ri
->resetvalue
;
144 } else if (ri
->raw_readfn
) {
145 return ri
->raw_readfn(env
, ri
);
146 } else if (ri
->readfn
) {
147 return ri
->readfn(env
, ri
);
149 return raw_read(env
, ri
);
153 static void write_raw_cp_reg(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
156 /* Raw write of a coprocessor register (as needed for migration, etc).
157 * Note that constant registers are treated as write-ignored; the
158 * caller should check for success by whether a readback gives the
161 if (ri
->type
& ARM_CP_CONST
) {
163 } else if (ri
->raw_writefn
) {
164 ri
->raw_writefn(env
, ri
, v
);
165 } else if (ri
->writefn
) {
166 ri
->writefn(env
, ri
, v
);
168 raw_write(env
, ri
, v
);
172 bool write_cpustate_to_list(ARMCPU
*cpu
)
174 /* Write the coprocessor state from cpu->env to the (index,value) list. */
178 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
179 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
180 const ARMCPRegInfo
*ri
;
182 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
187 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
190 cpu
->cpreg_values
[i
] = read_raw_cp_reg(&cpu
->env
, ri
);
195 bool write_list_to_cpustate(ARMCPU
*cpu
)
200 for (i
= 0; i
< cpu
->cpreg_array_len
; i
++) {
201 uint32_t regidx
= kvm_to_cpreg_id(cpu
->cpreg_indexes
[i
]);
202 uint64_t v
= cpu
->cpreg_values
[i
];
203 const ARMCPRegInfo
*ri
;
205 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
210 if (ri
->type
& ARM_CP_NO_MIGRATE
) {
213 /* Write value and confirm it reads back as written
214 * (to catch read-only registers and partially read-only
215 * registers where the incoming migration value doesn't match)
217 write_raw_cp_reg(&cpu
->env
, ri
, v
);
218 if (read_raw_cp_reg(&cpu
->env
, ri
) != v
) {
225 static void add_cpreg_to_list(gpointer key
, gpointer opaque
)
227 ARMCPU
*cpu
= opaque
;
229 const ARMCPRegInfo
*ri
;
231 regidx
= *(uint32_t *)key
;
232 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
234 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
235 cpu
->cpreg_indexes
[cpu
->cpreg_array_len
] = cpreg_to_kvm_id(regidx
);
236 /* The value array need not be initialized at this point */
237 cpu
->cpreg_array_len
++;
241 static void count_cpreg(gpointer key
, gpointer opaque
)
243 ARMCPU
*cpu
= opaque
;
245 const ARMCPRegInfo
*ri
;
247 regidx
= *(uint32_t *)key
;
248 ri
= get_arm_cp_reginfo(cpu
->cp_regs
, regidx
);
250 if (!(ri
->type
& ARM_CP_NO_MIGRATE
)) {
251 cpu
->cpreg_array_len
++;
255 static gint
cpreg_key_compare(gconstpointer a
, gconstpointer b
)
257 uint64_t aidx
= cpreg_to_kvm_id(*(uint32_t *)a
);
258 uint64_t bidx
= cpreg_to_kvm_id(*(uint32_t *)b
);
269 static void cpreg_make_keylist(gpointer key
, gpointer value
, gpointer udata
)
271 GList
**plist
= udata
;
273 *plist
= g_list_prepend(*plist
, key
);
276 void init_cpreg_list(ARMCPU
*cpu
)
278 /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
279 * Note that we require cpreg_tuples[] to be sorted by key ID.
284 g_hash_table_foreach(cpu
->cp_regs
, cpreg_make_keylist
, &keys
);
286 keys
= g_list_sort(keys
, cpreg_key_compare
);
288 cpu
->cpreg_array_len
= 0;
290 g_list_foreach(keys
, count_cpreg
, cpu
);
292 arraylen
= cpu
->cpreg_array_len
;
293 cpu
->cpreg_indexes
= g_new(uint64_t, arraylen
);
294 cpu
->cpreg_values
= g_new(uint64_t, arraylen
);
295 cpu
->cpreg_vmstate_indexes
= g_new(uint64_t, arraylen
);
296 cpu
->cpreg_vmstate_values
= g_new(uint64_t, arraylen
);
297 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
298 cpu
->cpreg_array_len
= 0;
300 g_list_foreach(keys
, add_cpreg_to_list
, cpu
);
302 assert(cpu
->cpreg_array_len
== arraylen
);
307 /* Return true if extended addresses are enabled.
308 * This is always the case if our translation regime is 64 bit,
309 * but depends on TTBCR.EAE for 32 bit.
311 static inline bool extended_addresses_enabled(CPUARMState
*env
)
313 return arm_el_is_aa64(env
, 1)
314 || ((arm_feature(env
, ARM_FEATURE_LPAE
)
315 && (env
->cp15
.c2_control
& (1U << 31))));
318 static void dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
320 ARMCPU
*cpu
= arm_env_get_cpu(env
);
322 env
->cp15
.c3
= value
;
323 tlb_flush(CPU(cpu
), 1); /* Flush TLB as domain not tracked in TLB */
326 static void fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
328 ARMCPU
*cpu
= arm_env_get_cpu(env
);
330 if (env
->cp15
.c13_fcse
!= value
) {
331 /* Unlike real hardware the qemu TLB uses virtual addresses,
332 * not modified virtual addresses, so this causes a TLB flush.
334 tlb_flush(CPU(cpu
), 1);
335 env
->cp15
.c13_fcse
= value
;
339 static void contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
342 ARMCPU
*cpu
= arm_env_get_cpu(env
);
344 if (env
->cp15
.contextidr_el1
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)
345 && !extended_addresses_enabled(env
)) {
346 /* For VMSA (when not using the LPAE long descriptor page table
347 * format) this register includes the ASID, so do a TLB flush.
348 * For PMSA it is purely a process ID and no action is needed.
350 tlb_flush(CPU(cpu
), 1);
352 env
->cp15
.contextidr_el1
= value
;
355 static void tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
358 /* Invalidate all (TLBIALL) */
359 ARMCPU
*cpu
= arm_env_get_cpu(env
);
361 tlb_flush(CPU(cpu
), 1);
364 static void tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
367 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
368 ARMCPU
*cpu
= arm_env_get_cpu(env
);
370 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
373 static void tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
376 /* Invalidate by ASID (TLBIASID) */
377 ARMCPU
*cpu
= arm_env_get_cpu(env
);
379 tlb_flush(CPU(cpu
), value
== 0);
382 static void tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
385 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
386 ARMCPU
*cpu
= arm_env_get_cpu(env
);
388 tlb_flush_page(CPU(cpu
), value
& TARGET_PAGE_MASK
);
391 static const ARMCPRegInfo cp_reginfo
[] = {
392 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
393 * version" bits will read as a reserved value, which should cause
394 * Linux to not try to use the debug hardware.
396 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
397 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
398 /* MMU Domain access control / MPU write buffer control */
399 { .name
= "DACR", .cp
= 15,
400 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
401 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
402 .resetvalue
= 0, .writefn
= dacr_write
, .raw_writefn
= raw_write
, },
403 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
404 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
405 .resetvalue
= 0, .writefn
= fcse_write
, .raw_writefn
= raw_write
, },
406 { .name
= "CONTEXTIDR", .state
= ARM_CP_STATE_BOTH
,
407 .opc0
= 3, .opc1
= 0, .crn
= 13, .crm
= 0, .opc2
= 1,
409 .fieldoffset
= offsetof(CPUARMState
, cp15
.contextidr_el1
),
410 .resetvalue
= 0, .writefn
= contextidr_write
, .raw_writefn
= raw_write
, },
411 /* ??? This covers not just the impdef TLB lockdown registers but also
412 * some v7VMSA registers relating to TEX remap, so it is overly broad.
414 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
415 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
416 /* MMU TLB control. Note that the wildcarding means we cover not just
417 * the unified TLB ops but also the dside/iside/inner-shareable variants.
419 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
420 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
,
421 .type
= ARM_CP_NO_MIGRATE
},
422 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
423 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
,
424 .type
= ARM_CP_NO_MIGRATE
},
425 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
426 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
,
427 .type
= ARM_CP_NO_MIGRATE
},
428 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
429 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
,
430 .type
= ARM_CP_NO_MIGRATE
},
431 /* Cache maintenance ops; some of this space may be overridden later. */
432 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
433 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
434 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
438 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
439 /* Not all pre-v6 cores implemented this WFI, so this is slightly
442 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
443 .access
= PL1_W
, .type
= ARM_CP_WFI
},
447 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
448 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
449 * is UNPREDICTABLE; we choose to NOP as most implementations do).
451 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
452 .access
= PL1_W
, .type
= ARM_CP_WFI
},
453 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
454 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
455 * OMAPCP will override this space.
457 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
458 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
460 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
461 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
463 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
464 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
465 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
470 static void cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
473 if (env
->cp15
.c1_coproc
!= value
) {
474 env
->cp15
.c1_coproc
= value
;
475 /* ??? Is this safe when called from within a TB? */
480 static const ARMCPRegInfo v6_cp_reginfo
[] = {
481 /* prefetch by MVA in v6, NOP in v7 */
482 { .name
= "MVA_prefetch",
483 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
484 .access
= PL1_W
, .type
= ARM_CP_NOP
},
485 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
486 .access
= PL0_W
, .type
= ARM_CP_NOP
},
487 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
488 .access
= PL0_W
, .type
= ARM_CP_NOP
},
489 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
490 .access
= PL0_W
, .type
= ARM_CP_NOP
},
491 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
493 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.far_el1
),
495 /* Watchpoint Fault Address Register : should actually only be present
496 * for 1136, 1176, 11MPCore.
498 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
499 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
500 { .name
= "CPACR", .state
= ARM_CP_STATE_BOTH
, .opc0
= 3,
501 .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
502 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
503 .resetvalue
= 0, .writefn
= cpacr_write
},
507 static CPAccessResult
pmreg_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
509 /* Performance monitor registers user accessibility is controlled
512 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
513 return CP_ACCESS_TRAP
;
518 #ifndef CONFIG_USER_ONLY
519 static void pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
522 /* Don't computer the number of ticks in user mode */
525 temp_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
526 get_ticks_per_sec() / 1000000;
528 if (env
->cp15
.c9_pmcr
& PMCRE
) {
529 /* If the counter is enabled */
530 if (env
->cp15
.c9_pmcr
& PMCRD
) {
531 /* Increment once every 64 processor clock cycles */
532 env
->cp15
.c15_ccnt
= (temp_ticks
/64) - env
->cp15
.c15_ccnt
;
534 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
539 /* The counter has been reset */
540 env
->cp15
.c15_ccnt
= 0;
543 /* only the DP, X, D and E bits are writable */
544 env
->cp15
.c9_pmcr
&= ~0x39;
545 env
->cp15
.c9_pmcr
|= (value
& 0x39);
547 if (env
->cp15
.c9_pmcr
& PMCRE
) {
548 if (env
->cp15
.c9_pmcr
& PMCRD
) {
549 /* Increment once every 64 processor clock cycles */
552 env
->cp15
.c15_ccnt
= temp_ticks
- env
->cp15
.c15_ccnt
;
556 static uint64_t pmccntr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
558 uint32_t total_ticks
;
560 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
561 /* Counter is disabled, do not change value */
562 return env
->cp15
.c15_ccnt
;
565 total_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
566 get_ticks_per_sec() / 1000000;
568 if (env
->cp15
.c9_pmcr
& PMCRD
) {
569 /* Increment once every 64 processor clock cycles */
572 return total_ticks
- env
->cp15
.c15_ccnt
;
575 static void pmccntr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
578 uint32_t total_ticks
;
580 if (!(env
->cp15
.c9_pmcr
& PMCRE
)) {
581 /* Counter is disabled, set the absolute value */
582 env
->cp15
.c15_ccnt
= value
;
586 total_ticks
= qemu_clock_get_us(QEMU_CLOCK_VIRTUAL
) *
587 get_ticks_per_sec() / 1000000;
589 if (env
->cp15
.c9_pmcr
& PMCRD
) {
590 /* Increment once every 64 processor clock cycles */
593 env
->cp15
.c15_ccnt
= total_ticks
- value
;
597 static void pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
601 env
->cp15
.c9_pmcnten
|= value
;
604 static void pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
608 env
->cp15
.c9_pmcnten
&= ~value
;
611 static void pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
614 env
->cp15
.c9_pmovsr
&= ~value
;
617 static void pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
620 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
623 static void pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
626 env
->cp15
.c9_pmuserenr
= value
& 1;
629 static void pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
632 /* We have no event counters so only the C bit can be changed */
634 env
->cp15
.c9_pminten
|= value
;
637 static void pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
641 env
->cp15
.c9_pminten
&= ~value
;
644 static void vbar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
647 /* Note that even though the AArch64 view of this register has bits
648 * [10:0] all RES0 we can only mask the bottom 5, to comply with the
649 * architectural requirements for bits which are RES0 only in some
650 * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
651 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
653 env
->cp15
.c12_vbar
= value
& ~0x1Ful
;
656 static uint64_t ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
658 ARMCPU
*cpu
= arm_env_get_cpu(env
);
659 return cpu
->ccsidr
[env
->cp15
.c0_cssel
];
662 static void csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
665 env
->cp15
.c0_cssel
= value
& 0xf;
668 static const ARMCPRegInfo v7_cp_reginfo
[] = {
669 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
672 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
673 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
674 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
675 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
676 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
677 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
678 .access
= PL1_W
, .type
= ARM_CP_NOP
},
679 /* Performance monitors are implementation defined in v7,
680 * but with an ARM recommended set of registers, which we
681 * follow (although we don't actually implement any counters)
683 * Performance registers fall into three categories:
684 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
685 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
686 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
687 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
688 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
690 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
691 .access
= PL0_RW
, .resetvalue
= 0,
692 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
693 .writefn
= pmcntenset_write
,
694 .accessfn
= pmreg_access
,
695 .raw_writefn
= raw_write
},
696 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
697 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
698 .accessfn
= pmreg_access
,
699 .writefn
= pmcntenclr_write
,
700 .type
= ARM_CP_NO_MIGRATE
},
701 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
702 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
703 .accessfn
= pmreg_access
,
704 .writefn
= pmovsr_write
,
705 .raw_writefn
= raw_write
},
706 /* Unimplemented so WI. */
707 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
708 .access
= PL0_W
, .accessfn
= pmreg_access
, .type
= ARM_CP_NOP
},
709 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
710 * We choose to RAZ/WI.
712 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
713 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
714 .accessfn
= pmreg_access
},
715 #ifndef CONFIG_USER_ONLY
716 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
717 .access
= PL0_RW
, .resetvalue
= 0, .type
= ARM_CP_IO
,
718 .readfn
= pmccntr_read
, .writefn
= pmccntr_write
,
719 .accessfn
= pmreg_access
},
721 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
723 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
724 .accessfn
= pmreg_access
, .writefn
= pmxevtyper_write
,
725 .raw_writefn
= raw_write
},
726 /* Unimplemented, RAZ/WI. */
727 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
728 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0,
729 .accessfn
= pmreg_access
},
730 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
731 .access
= PL0_R
| PL1_RW
,
732 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
734 .writefn
= pmuserenr_write
, .raw_writefn
= raw_write
},
735 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
737 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
739 .writefn
= pmintenset_write
, .raw_writefn
= raw_write
},
740 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
741 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
742 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
743 .resetvalue
= 0, .writefn
= pmintenclr_write
, },
744 { .name
= "VBAR", .state
= ARM_CP_STATE_BOTH
,
745 .opc0
= 3, .crn
= 12, .crm
= 0, .opc1
= 0, .opc2
= 0,
746 .access
= PL1_RW
, .writefn
= vbar_write
,
747 .fieldoffset
= offsetof(CPUARMState
, cp15
.c12_vbar
),
749 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
750 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
752 { .name
= "CCSIDR", .state
= ARM_CP_STATE_BOTH
,
753 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
754 .access
= PL1_R
, .readfn
= ccsidr_read
, .type
= ARM_CP_NO_MIGRATE
},
755 { .name
= "CSSELR", .state
= ARM_CP_STATE_BOTH
,
756 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
757 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
758 .writefn
= csselr_write
, .resetvalue
= 0 },
759 /* Auxiliary ID register: this actually has an IMPDEF value but for now
760 * just RAZ for all cores:
762 { .name
= "AIDR", .state
= ARM_CP_STATE_BOTH
,
763 .opc0
= 3, .opc1
= 1, .crn
= 0, .crm
= 0, .opc2
= 7,
764 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
765 /* MAIR can just read-as-written because we don't implement caches
766 * and so don't need to care about memory attributes.
768 { .name
= "MAIR_EL1", .state
= ARM_CP_STATE_AA64
,
769 .opc0
= 3, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0,
770 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.mair_el1
),
772 /* For non-long-descriptor page tables these are PRRR and NMRR;
773 * regardless they still act as reads-as-written for QEMU.
774 * The override is necessary because of the overly-broad TLB_LOCKDOWN
777 { .name
= "MAIR0", .state
= ARM_CP_STATE_AA32
, .type
= ARM_CP_OVERRIDE
,
778 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 0, .access
= PL1_RW
,
779 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.mair_el1
),
780 .resetfn
= arm_cp_reset_ignore
},
781 { .name
= "MAIR1", .state
= ARM_CP_STATE_AA32
, .type
= ARM_CP_OVERRIDE
,
782 .cp
= 15, .opc1
= 0, .crn
= 10, .crm
= 2, .opc2
= 1, .access
= PL1_RW
,
783 .fieldoffset
= offsetofhigh32(CPUARMState
, cp15
.mair_el1
),
784 .resetfn
= arm_cp_reset_ignore
},
788 static void teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
795 static CPAccessResult
teehbr_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
797 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
798 return CP_ACCESS_TRAP
;
803 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
804 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
805 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
807 .writefn
= teecr_write
},
808 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
809 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
810 .accessfn
= teehbr_access
, .resetvalue
= 0 },
814 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
815 { .name
= "TPIDR_EL0", .state
= ARM_CP_STATE_AA64
,
816 .opc0
= 3, .opc1
= 3, .opc2
= 2, .crn
= 13, .crm
= 0,
818 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el0
), .resetvalue
= 0 },
819 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
821 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.tpidr_el0
),
822 .resetfn
= arm_cp_reset_ignore
},
823 { .name
= "TPIDRRO_EL0", .state
= ARM_CP_STATE_AA64
,
824 .opc0
= 3, .opc1
= 3, .opc2
= 3, .crn
= 13, .crm
= 0,
825 .access
= PL0_R
|PL1_W
,
826 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidrro_el0
), .resetvalue
= 0 },
827 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
828 .access
= PL0_R
|PL1_W
,
829 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.tpidrro_el0
),
830 .resetfn
= arm_cp_reset_ignore
},
831 { .name
= "TPIDR_EL1", .state
= ARM_CP_STATE_BOTH
,
832 .opc0
= 3, .opc1
= 0, .opc2
= 4, .crn
= 13, .crm
= 0,
834 .fieldoffset
= offsetof(CPUARMState
, cp15
.tpidr_el1
), .resetvalue
= 0 },
838 #ifndef CONFIG_USER_ONLY
840 static CPAccessResult
gt_cntfrq_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
842 /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
843 if (arm_current_pl(env
) == 0 && !extract32(env
->cp15
.c14_cntkctl
, 0, 2)) {
844 return CP_ACCESS_TRAP
;
849 static CPAccessResult
gt_counter_access(CPUARMState
*env
, int timeridx
)
851 /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
852 if (arm_current_pl(env
) == 0 &&
853 !extract32(env
->cp15
.c14_cntkctl
, timeridx
, 1)) {
854 return CP_ACCESS_TRAP
;
859 static CPAccessResult
gt_timer_access(CPUARMState
*env
, int timeridx
)
861 /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
862 * EL0[PV]TEN is zero.
864 if (arm_current_pl(env
) == 0 &&
865 !extract32(env
->cp15
.c14_cntkctl
, 9 - timeridx
, 1)) {
866 return CP_ACCESS_TRAP
;
871 static CPAccessResult
gt_pct_access(CPUARMState
*env
,
872 const ARMCPRegInfo
*ri
)
874 return gt_counter_access(env
, GTIMER_PHYS
);
877 static CPAccessResult
gt_vct_access(CPUARMState
*env
,
878 const ARMCPRegInfo
*ri
)
880 return gt_counter_access(env
, GTIMER_VIRT
);
883 static CPAccessResult
gt_ptimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
885 return gt_timer_access(env
, GTIMER_PHYS
);
888 static CPAccessResult
gt_vtimer_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
890 return gt_timer_access(env
, GTIMER_VIRT
);
893 static uint64_t gt_get_countervalue(CPUARMState
*env
)
895 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / GTIMER_SCALE
;
898 static void gt_recalc_timer(ARMCPU
*cpu
, int timeridx
)
900 ARMGenericTimer
*gt
= &cpu
->env
.cp15
.c14_timer
[timeridx
];
903 /* Timer enabled: calculate and set current ISTATUS, irq, and
904 * reset timer to when ISTATUS next has to change
906 uint64_t count
= gt_get_countervalue(&cpu
->env
);
907 /* Note that this must be unsigned 64 bit arithmetic: */
908 int istatus
= count
>= gt
->cval
;
911 gt
->ctl
= deposit32(gt
->ctl
, 2, 1, istatus
);
912 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
913 (istatus
&& !(gt
->ctl
& 2)));
915 /* Next transition is when count rolls back over to zero */
916 nexttick
= UINT64_MAX
;
918 /* Next transition is when we hit cval */
921 /* Note that the desired next expiry time might be beyond the
922 * signed-64-bit range of a QEMUTimer -- in this case we just
923 * set the timer for as far in the future as possible. When the
924 * timer expires we will reset the timer for any remaining period.
926 if (nexttick
> INT64_MAX
/ GTIMER_SCALE
) {
927 nexttick
= INT64_MAX
/ GTIMER_SCALE
;
929 timer_mod(cpu
->gt_timer
[timeridx
], nexttick
);
931 /* Timer disabled: ISTATUS and timer output always clear */
933 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
], 0);
934 timer_del(cpu
->gt_timer
[timeridx
]);
938 static void gt_cnt_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
940 ARMCPU
*cpu
= arm_env_get_cpu(env
);
941 int timeridx
= ri
->opc1
& 1;
943 timer_del(cpu
->gt_timer
[timeridx
]);
946 static uint64_t gt_cnt_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
948 return gt_get_countervalue(env
);
951 static void gt_cval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
954 int timeridx
= ri
->opc1
& 1;
956 env
->cp15
.c14_timer
[timeridx
].cval
= value
;
957 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
960 static uint64_t gt_tval_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
962 int timeridx
= ri
->crm
& 1;
964 return (uint32_t)(env
->cp15
.c14_timer
[timeridx
].cval
-
965 gt_get_countervalue(env
));
968 static void gt_tval_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
971 int timeridx
= ri
->crm
& 1;
973 env
->cp15
.c14_timer
[timeridx
].cval
= gt_get_countervalue(env
) +
974 + sextract64(value
, 0, 32);
975 gt_recalc_timer(arm_env_get_cpu(env
), timeridx
);
978 static void gt_ctl_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
981 ARMCPU
*cpu
= arm_env_get_cpu(env
);
982 int timeridx
= ri
->crm
& 1;
983 uint32_t oldval
= env
->cp15
.c14_timer
[timeridx
].ctl
;
985 env
->cp15
.c14_timer
[timeridx
].ctl
= value
& 3;
986 if ((oldval
^ value
) & 1) {
988 gt_recalc_timer(cpu
, timeridx
);
989 } else if ((oldval
& value
) & 2) {
990 /* IMASK toggled: don't need to recalculate,
991 * just set the interrupt line based on ISTATUS
993 qemu_set_irq(cpu
->gt_timer_outputs
[timeridx
],
994 (oldval
& 4) && (value
& 2));
998 void arm_gt_ptimer_cb(void *opaque
)
1000 ARMCPU
*cpu
= opaque
;
1002 gt_recalc_timer(cpu
, GTIMER_PHYS
);
1005 void arm_gt_vtimer_cb(void *opaque
)
1007 ARMCPU
*cpu
= opaque
;
1009 gt_recalc_timer(cpu
, GTIMER_VIRT
);
1012 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1013 /* Note that CNTFRQ is purely reads-as-written for the benefit
1014 * of software; writing it doesn't actually change the timer frequency.
1015 * Our reset value matches the fixed frequency we implement the timer at.
1017 { .name
= "CNTFRQ", .cp
= 15, .crn
= 14, .crm
= 0, .opc1
= 0, .opc2
= 0,
1018 .type
= ARM_CP_NO_MIGRATE
,
1019 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1020 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c14_cntfrq
),
1021 .resetfn
= arm_cp_reset_ignore
,
1023 { .name
= "CNTFRQ_EL0", .state
= ARM_CP_STATE_AA64
,
1024 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 0,
1025 .access
= PL1_RW
| PL0_R
, .accessfn
= gt_cntfrq_access
,
1026 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntfrq
),
1027 .resetvalue
= (1000 * 1000 * 1000) / GTIMER_SCALE
,
1029 /* overall control: mostly access permissions */
1030 { .name
= "CNTKCTL", .state
= ARM_CP_STATE_BOTH
,
1031 .opc0
= 3, .opc1
= 0, .crn
= 14, .crm
= 1, .opc2
= 0,
1033 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_cntkctl
),
1036 /* per-timer control */
1037 { .name
= "CNTP_CTL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 1,
1038 .type
= ARM_CP_IO
| ARM_CP_NO_MIGRATE
, .access
= PL1_RW
| PL0_R
,
1039 .accessfn
= gt_ptimer_access
,
1040 .fieldoffset
= offsetoflow32(CPUARMState
,
1041 cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1042 .resetfn
= arm_cp_reset_ignore
,
1043 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1045 { .name
= "CNTP_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1046 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 1,
1047 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1048 .accessfn
= gt_ptimer_access
,
1049 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].ctl
),
1051 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1053 { .name
= "CNTV_CTL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 1,
1054 .type
= ARM_CP_IO
| ARM_CP_NO_MIGRATE
, .access
= PL1_RW
| PL0_R
,
1055 .accessfn
= gt_vtimer_access
,
1056 .fieldoffset
= offsetoflow32(CPUARMState
,
1057 cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1058 .resetfn
= arm_cp_reset_ignore
,
1059 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1061 { .name
= "CNTV_CTL_EL0", .state
= ARM_CP_STATE_AA64
,
1062 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 1,
1063 .type
= ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1064 .accessfn
= gt_vtimer_access
,
1065 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].ctl
),
1067 .writefn
= gt_ctl_write
, .raw_writefn
= raw_write
,
1069 /* TimerValue views: a 32 bit downcounting view of the underlying state */
1070 { .name
= "CNTP_TVAL", .cp
= 15, .crn
= 14, .crm
= 2, .opc1
= 0, .opc2
= 0,
1071 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1072 .accessfn
= gt_ptimer_access
,
1073 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1075 { .name
= "CNTP_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1076 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 0,
1077 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1078 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1080 { .name
= "CNTV_TVAL", .cp
= 15, .crn
= 14, .crm
= 3, .opc1
= 0, .opc2
= 0,
1081 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1082 .accessfn
= gt_vtimer_access
,
1083 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1085 { .name
= "CNTV_TVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1086 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 0,
1087 .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
, .access
= PL1_RW
| PL0_R
,
1088 .readfn
= gt_tval_read
, .writefn
= gt_tval_write
,
1090 /* The counter itself */
1091 { .name
= "CNTPCT", .cp
= 15, .crm
= 14, .opc1
= 0,
1092 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1093 .accessfn
= gt_pct_access
,
1094 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1096 { .name
= "CNTPCT_EL0", .state
= ARM_CP_STATE_AA64
,
1097 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 1,
1098 .access
= PL0_R
, .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1099 .accessfn
= gt_pct_access
,
1100 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1102 { .name
= "CNTVCT", .cp
= 15, .crm
= 14, .opc1
= 1,
1103 .access
= PL0_R
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1104 .accessfn
= gt_vct_access
,
1105 .readfn
= gt_cnt_read
, .resetfn
= arm_cp_reset_ignore
,
1107 { .name
= "CNTVCT_EL0", .state
= ARM_CP_STATE_AA64
,
1108 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 0, .opc2
= 2,
1109 .access
= PL0_R
, .type
= ARM_CP_NO_MIGRATE
| ARM_CP_IO
,
1110 .accessfn
= gt_vct_access
,
1111 .readfn
= gt_cnt_read
, .resetfn
= gt_cnt_reset
,
1113 /* Comparison value, indicating when the timer goes off */
1114 { .name
= "CNTP_CVAL", .cp
= 15, .crm
= 14, .opc1
= 2,
1115 .access
= PL1_RW
| PL0_R
,
1116 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_MIGRATE
,
1117 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1118 .accessfn
= gt_ptimer_access
, .resetfn
= arm_cp_reset_ignore
,
1119 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1121 { .name
= "CNTP_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1122 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 2, .opc2
= 2,
1123 .access
= PL1_RW
| PL0_R
,
1125 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_PHYS
].cval
),
1126 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1127 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1129 { .name
= "CNTV_CVAL", .cp
= 15, .crm
= 14, .opc1
= 3,
1130 .access
= PL1_RW
| PL0_R
,
1131 .type
= ARM_CP_64BIT
| ARM_CP_IO
| ARM_CP_NO_MIGRATE
,
1132 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1133 .accessfn
= gt_vtimer_access
, .resetfn
= arm_cp_reset_ignore
,
1134 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1136 { .name
= "CNTV_CVAL_EL0", .state
= ARM_CP_STATE_AA64
,
1137 .opc0
= 3, .opc1
= 3, .crn
= 14, .crm
= 3, .opc2
= 2,
1138 .access
= PL1_RW
| PL0_R
,
1140 .fieldoffset
= offsetof(CPUARMState
, cp15
.c14_timer
[GTIMER_VIRT
].cval
),
1141 .resetvalue
= 0, .accessfn
= gt_vtimer_access
,
1142 .writefn
= gt_cval_write
, .raw_writefn
= raw_write
,
1148 /* In user-mode none of the generic timer registers are accessible,
1149 * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1150 * so instead just don't register any of them.
1152 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
1158 static void par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1160 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1161 env
->cp15
.c7_par
= value
;
1162 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
1163 env
->cp15
.c7_par
= value
& 0xfffff6ff;
1165 env
->cp15
.c7_par
= value
& 0xfffff1ff;
1169 #ifndef CONFIG_USER_ONLY
1170 /* get_phys_addr() isn't present for user-mode-only targets */
1172 static CPAccessResult
ats_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1175 /* Other states are only available with TrustZone; in
1176 * a non-TZ implementation these registers don't exist
1177 * at all, which is an Uncategorized trap. This underdecoding
1178 * is safe because the reginfo is NO_MIGRATE.
1180 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1182 return CP_ACCESS_OK
;
1185 static void ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1188 target_ulong page_size
;
1190 int ret
, is_user
= ri
->opc2
& 2;
1191 int access_type
= ri
->opc2
& 1;
1193 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
1194 &phys_addr
, &prot
, &page_size
);
1195 if (extended_addresses_enabled(env
)) {
1196 /* ret is a DFSR/IFSR value for the long descriptor
1197 * translation table format, but with WnR always clear.
1198 * Convert it to a 64-bit PAR.
1200 uint64_t par64
= (1 << 11); /* LPAE bit always set */
1202 par64
|= phys_addr
& ~0xfffULL
;
1203 /* We don't set the ATTR or SH fields in the PAR. */
1206 par64
|= (ret
& 0x3f) << 1; /* FS */
1207 /* Note that S2WLK and FSTAGE are always zero, because we don't
1208 * implement virtualization and therefore there can't be a stage 2
1212 env
->cp15
.c7_par
= par64
;
1213 env
->cp15
.c7_par_hi
= par64
>> 32;
1215 /* ret is a DFSR/IFSR value for the short descriptor
1216 * translation table format (with WnR always clear).
1217 * Convert it to a 32-bit PAR.
1220 /* We do not set any attribute bits in the PAR */
1221 if (page_size
== (1 << 24)
1222 && arm_feature(env
, ARM_FEATURE_V7
)) {
1223 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
1225 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
1228 env
->cp15
.c7_par
= ((ret
& (1 << 10)) >> 5) |
1229 ((ret
& (1 << 12)) >> 6) |
1230 ((ret
& 0xf) << 1) | 1;
1232 env
->cp15
.c7_par_hi
= 0;
1237 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
1238 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
1239 .access
= PL1_RW
, .resetvalue
= 0,
1240 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
1241 .writefn
= par_write
},
1242 #ifndef CONFIG_USER_ONLY
1243 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
1244 .access
= PL1_W
, .accessfn
= ats_access
,
1245 .writefn
= ats_write
, .type
= ARM_CP_NO_MIGRATE
},
1250 /* Return basic MPU access permission bits. */
1251 static uint32_t simple_mpu_ap_bits(uint32_t val
)
1258 for (i
= 0; i
< 16; i
+= 2) {
1259 ret
|= (val
>> i
) & mask
;
1265 /* Pad basic MPU access permission bits to extended format. */
1266 static uint32_t extended_mpu_ap_bits(uint32_t val
)
1273 for (i
= 0; i
< 16; i
+= 2) {
1274 ret
|= (val
& mask
) << i
;
1280 static void pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1283 env
->cp15
.pmsav5_data_ap
= extended_mpu_ap_bits(value
);
1286 static uint64_t pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1288 return simple_mpu_ap_bits(env
->cp15
.pmsav5_data_ap
);
1291 static void pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1294 env
->cp15
.pmsav5_insn_ap
= extended_mpu_ap_bits(value
);
1297 static uint64_t pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1299 return simple_mpu_ap_bits(env
->cp15
.pmsav5_insn_ap
);
1302 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
1303 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1304 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1305 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
1307 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
1308 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1309 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1310 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
1312 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
1313 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
1315 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_data_ap
),
1317 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
1319 .fieldoffset
= offsetof(CPUARMState
, cp15
.pmsav5_insn_ap
),
1321 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1323 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
1324 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1326 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
1327 /* Protection region base and size registers */
1328 { .name
= "946_PRBS0", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0,
1329 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1330 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[0]) },
1331 { .name
= "946_PRBS1", .cp
= 15, .crn
= 6, .crm
= 1, .opc1
= 0,
1332 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1333 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[1]) },
1334 { .name
= "946_PRBS2", .cp
= 15, .crn
= 6, .crm
= 2, .opc1
= 0,
1335 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1336 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[2]) },
1337 { .name
= "946_PRBS3", .cp
= 15, .crn
= 6, .crm
= 3, .opc1
= 0,
1338 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1339 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[3]) },
1340 { .name
= "946_PRBS4", .cp
= 15, .crn
= 6, .crm
= 4, .opc1
= 0,
1341 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1342 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[4]) },
1343 { .name
= "946_PRBS5", .cp
= 15, .crn
= 6, .crm
= 5, .opc1
= 0,
1344 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1345 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[5]) },
1346 { .name
= "946_PRBS6", .cp
= 15, .crn
= 6, .crm
= 6, .opc1
= 0,
1347 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1348 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[6]) },
1349 { .name
= "946_PRBS7", .cp
= 15, .crn
= 6, .crm
= 7, .opc1
= 0,
1350 .opc2
= CP_ANY
, .access
= PL1_RW
, .resetvalue
= 0,
1351 .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_region
[7]) },
1355 static void vmsa_ttbcr_raw_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1358 int maskshift
= extract32(value
, 0, 3);
1360 if (arm_feature(env
, ARM_FEATURE_LPAE
) && (value
& (1 << 31))) {
1361 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
1365 /* Note that we always calculate c2_mask and c2_base_mask, but
1366 * they are only used for short-descriptor tables (ie if EAE is 0);
1367 * for long-descriptor tables the TTBCR fields are used differently
1368 * and the c2_mask and c2_base_mask values are meaningless.
1370 env
->cp15
.c2_control
= value
;
1371 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> maskshift
);
1372 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> maskshift
);
1375 static void vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1378 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1380 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1381 /* With LPAE the TTBCR could result in a change of ASID
1382 * via the TTBCR.A1 bit, so do a TLB flush.
1384 tlb_flush(CPU(cpu
), 1);
1386 vmsa_ttbcr_raw_write(env
, ri
, value
);
1389 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1391 env
->cp15
.c2_base_mask
= 0xffffc000u
;
1392 env
->cp15
.c2_control
= 0;
1393 env
->cp15
.c2_mask
= 0;
1396 static void vmsa_tcr_el1_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1399 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1401 /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1402 tlb_flush(CPU(cpu
), 1);
1403 env
->cp15
.c2_control
= value
;
1406 static void vmsa_ttbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1409 /* 64 bit accesses to the TTBRs can change the ASID and so we
1410 * must flush the TLB.
1412 if (cpreg_field_is_64bit(ri
)) {
1413 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1415 tlb_flush(CPU(cpu
), 1);
1417 raw_write(env
, ri
, value
);
1420 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
1421 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
1422 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
,
1423 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el1
),
1424 .resetfn
= arm_cp_reset_ignore
, },
1425 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
1427 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifsr_el2
), .resetvalue
= 0, },
1428 { .name
= "ESR_EL1", .state
= ARM_CP_STATE_AA64
,
1429 .opc0
= 3, .crn
= 5, .crm
= 2, .opc1
= 0, .opc2
= 0,
1431 .fieldoffset
= offsetof(CPUARMState
, cp15
.esr_el1
), .resetvalue
= 0, },
1432 { .name
= "TTBR0_EL1", .state
= ARM_CP_STATE_BOTH
,
1433 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
1434 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el1
),
1435 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0 },
1436 { .name
= "TTBR1_EL1", .state
= ARM_CP_STATE_BOTH
,
1437 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
1438 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el1
),
1439 .writefn
= vmsa_ttbr_write
, .resetvalue
= 0 },
1440 { .name
= "TCR_EL1", .state
= ARM_CP_STATE_AA64
,
1441 .opc0
= 3, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1442 .access
= PL1_RW
, .writefn
= vmsa_tcr_el1_write
,
1443 .resetfn
= vmsa_ttbcr_reset
, .raw_writefn
= raw_write
,
1444 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
1445 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
1446 .access
= PL1_RW
, .type
= ARM_CP_NO_MIGRATE
, .writefn
= vmsa_ttbcr_write
,
1447 .resetfn
= arm_cp_reset_ignore
, .raw_writefn
= vmsa_ttbcr_raw_write
,
1448 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.c2_control
) },
1449 /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1450 { .name
= "FAR_EL1", .state
= ARM_CP_STATE_BOTH
,
1451 .opc0
= 3, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
1452 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.far_el1
),
1457 static void omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1460 env
->cp15
.c15_ticonfig
= value
& 0xe7;
1461 /* The OS_TYPE bit in this register changes the reported CPUID! */
1462 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
1463 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
1466 static void omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1469 env
->cp15
.c15_threadid
= value
& 0xffff;
1472 static void omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1475 /* Wait-for-interrupt (deprecated) */
1476 cpu_interrupt(CPU(arm_env_get_cpu(env
)), CPU_INTERRUPT_HALT
);
1479 static void omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1482 /* On OMAP there are registers indicating the max/min index of dcache lines
1483 * containing a dirty line; cache flush operations have to reset these.
1485 env
->cp15
.c15_i_max
= 0x000;
1486 env
->cp15
.c15_i_min
= 0xff0;
1489 static const ARMCPRegInfo omap_cp_reginfo
[] = {
1490 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
1491 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
1492 .fieldoffset
= offsetoflow32(CPUARMState
, cp15
.esr_el1
),
1494 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
1495 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
1496 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
1498 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
1499 .writefn
= omap_ticonfig_write
},
1500 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
1502 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
1503 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
1504 .access
= PL1_RW
, .resetvalue
= 0xff0,
1505 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
1506 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
1508 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
1509 .writefn
= omap_threadid_write
},
1510 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
1511 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1512 .type
= ARM_CP_NO_MIGRATE
,
1513 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
1514 /* TODO: Peripheral port remap register:
1515 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1516 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1519 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
1520 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
1521 .type
= ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
,
1522 .writefn
= omap_cachemaint_write
},
1523 { .name
= "C9", .cp
= 15, .crn
= 9,
1524 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
1525 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
1529 static void xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1533 if (env
->cp15
.c15_cpar
!= value
) {
1534 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1536 env
->cp15
.c15_cpar
= value
;
1540 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
1541 { .name
= "XSCALE_CPAR",
1542 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
1543 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
1544 .writefn
= xscale_cpar_write
, },
1545 { .name
= "XSCALE_AUXCR",
1546 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
1547 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
1552 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
1553 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1554 * implementation of this implementation-defined space.
1555 * Ideally this should eventually disappear in favour of actually
1556 * implementing the correct behaviour for all cores.
1558 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
1559 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1561 .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
| ARM_CP_OVERRIDE
,
1566 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
1567 /* Cache status: RAZ because we have no cache so it's always clean */
1568 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
1569 .access
= PL1_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1574 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
1575 /* We never have a a block transfer operation in progress */
1576 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
1577 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1579 /* The cache ops themselves: these all NOP for QEMU */
1580 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
1581 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1582 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
1583 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1584 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
1585 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1586 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
1587 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1588 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
1589 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1590 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
1591 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
1595 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
1596 /* The cache test-and-clean instructions always return (1 << 30)
1597 * to indicate that there are no dirty cache lines.
1599 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
1600 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1601 .resetvalue
= (1 << 30) },
1602 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
1603 .access
= PL0_R
, .type
= ARM_CP_CONST
| ARM_CP_NO_MIGRATE
,
1604 .resetvalue
= (1 << 30) },
1608 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
1609 /* Ignore ReadBuffer accesses */
1610 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
1611 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
1612 .access
= PL1_RW
, .resetvalue
= 0,
1613 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
| ARM_CP_NO_MIGRATE
},
1617 static uint64_t mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1619 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
1620 uint32_t mpidr
= cs
->cpu_index
;
1621 /* We don't support setting cluster ID ([8..11]) (known as Aff1
1622 * in later ARM ARM versions), or any of the higher affinity level fields,
1623 * so these bits always RAZ.
1625 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
1626 mpidr
|= (1U << 31);
1627 /* Cores which are uniprocessor (non-coherent)
1628 * but still implement the MP extensions set
1629 * bit 30. (For instance, A9UP.) However we do
1630 * not currently model any of those cores.
1636 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
1637 { .name
= "MPIDR", .state
= ARM_CP_STATE_BOTH
,
1638 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
1639 .access
= PL1_R
, .readfn
= mpidr_read
, .type
= ARM_CP_NO_MIGRATE
},
1643 static uint64_t par64_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1645 return ((uint64_t)env
->cp15
.c7_par_hi
<< 32) | env
->cp15
.c7_par
;
1648 static void par64_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1651 env
->cp15
.c7_par_hi
= value
>> 32;
1652 env
->cp15
.c7_par
= value
;
1655 static void par64_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1657 env
->cp15
.c7_par_hi
= 0;
1658 env
->cp15
.c7_par
= 0;
1661 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
1662 /* NOP AMAIR0/1: the override is because these clash with the rather
1663 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1665 { .name
= "AMAIR0", .state
= ARM_CP_STATE_BOTH
,
1666 .opc0
= 3, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
1667 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1669 /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1670 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
1671 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1673 /* 64 bit access versions of the (dummy) debug registers */
1674 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
1675 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1676 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
1677 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1678 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
1679 .access
= PL1_RW
, .type
= ARM_CP_64BIT
,
1680 .readfn
= par64_read
, .writefn
= par64_write
, .resetfn
= par64_reset
},
1681 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
1682 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
,
1683 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr0_el1
),
1684 .writefn
= vmsa_ttbr_write
, .resetfn
= arm_cp_reset_ignore
},
1685 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
1686 .access
= PL1_RW
, .type
= ARM_CP_64BIT
| ARM_CP_NO_MIGRATE
,
1687 .fieldoffset
= offsetof(CPUARMState
, cp15
.ttbr1_el1
),
1688 .writefn
= vmsa_ttbr_write
, .resetfn
= arm_cp_reset_ignore
},
1692 static uint64_t aa64_fpcr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1694 return vfp_get_fpcr(env
);
1697 static void aa64_fpcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1700 vfp_set_fpcr(env
, value
);
1703 static uint64_t aa64_fpsr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1705 return vfp_get_fpsr(env
);
1708 static void aa64_fpsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1711 vfp_set_fpsr(env
, value
);
1714 static CPAccessResult
aa64_daif_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1716 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UMA
)) {
1717 return CP_ACCESS_TRAP
;
1719 return CP_ACCESS_OK
;
1722 static void aa64_daif_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1725 env
->daif
= value
& PSTATE_DAIF
;
1728 static CPAccessResult
aa64_cacheop_access(CPUARMState
*env
,
1729 const ARMCPRegInfo
*ri
)
1731 /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1732 * SCTLR_EL1.UCI is set.
1734 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UCI
)) {
1735 return CP_ACCESS_TRAP
;
1737 return CP_ACCESS_OK
;
1740 static void tlbi_aa64_va_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1743 /* Invalidate by VA (AArch64 version) */
1744 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1745 uint64_t pageaddr
= value
<< 12;
1746 tlb_flush_page(CPU(cpu
), pageaddr
);
1749 static void tlbi_aa64_vaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1752 /* Invalidate by VA, all ASIDs (AArch64 version) */
1753 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1754 uint64_t pageaddr
= value
<< 12;
1755 tlb_flush_page(CPU(cpu
), pageaddr
);
1758 static void tlbi_aa64_asid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1761 /* Invalidate by ASID (AArch64 version) */
1762 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1763 int asid
= extract64(value
, 48, 16);
1764 tlb_flush(CPU(cpu
), asid
== 0);
1767 static CPAccessResult
aa64_zva_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1769 /* We don't implement EL2, so the only control on DC ZVA is the
1770 * bit in the SCTLR which can prohibit access for EL0.
1772 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_DZE
)) {
1773 return CP_ACCESS_TRAP
;
1775 return CP_ACCESS_OK
;
1778 static uint64_t aa64_dczid_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1780 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1781 int dzp_bit
= 1 << 4;
1783 /* DZP indicates whether DC ZVA access is allowed */
1784 if (aa64_zva_access(env
, NULL
) != CP_ACCESS_OK
) {
1787 return cpu
->dcz_blocksize
| dzp_bit
;
1790 static CPAccessResult
sp_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1792 if (!env
->pstate
& PSTATE_SP
) {
1793 /* Access to SP_EL0 is undefined if it's being used as
1794 * the stack pointer.
1796 return CP_ACCESS_TRAP_UNCATEGORIZED
;
1798 return CP_ACCESS_OK
;
1801 static uint64_t spsel_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1803 return env
->pstate
& PSTATE_SP
;
1806 static void spsel_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t val
)
1808 update_spsel(env
, val
);
1811 static const ARMCPRegInfo v8_cp_reginfo
[] = {
1812 /* Minimal set of EL0-visible registers. This will need to be expanded
1813 * significantly for system emulation of AArch64 CPUs.
1815 { .name
= "NZCV", .state
= ARM_CP_STATE_AA64
,
1816 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 2,
1817 .access
= PL0_RW
, .type
= ARM_CP_NZCV
},
1818 { .name
= "DAIF", .state
= ARM_CP_STATE_AA64
,
1819 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 2,
1820 .type
= ARM_CP_NO_MIGRATE
,
1821 .access
= PL0_RW
, .accessfn
= aa64_daif_access
,
1822 .fieldoffset
= offsetof(CPUARMState
, daif
),
1823 .writefn
= aa64_daif_write
, .resetfn
= arm_cp_reset_ignore
},
1824 { .name
= "FPCR", .state
= ARM_CP_STATE_AA64
,
1825 .opc0
= 3, .opc1
= 3, .opc2
= 0, .crn
= 4, .crm
= 4,
1826 .access
= PL0_RW
, .readfn
= aa64_fpcr_read
, .writefn
= aa64_fpcr_write
},
1827 { .name
= "FPSR", .state
= ARM_CP_STATE_AA64
,
1828 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 4, .crm
= 4,
1829 .access
= PL0_RW
, .readfn
= aa64_fpsr_read
, .writefn
= aa64_fpsr_write
},
1830 { .name
= "DCZID_EL0", .state
= ARM_CP_STATE_AA64
,
1831 .opc0
= 3, .opc1
= 3, .opc2
= 7, .crn
= 0, .crm
= 0,
1832 .access
= PL0_R
, .type
= ARM_CP_NO_MIGRATE
,
1833 .readfn
= aa64_dczid_read
},
1834 { .name
= "DC_ZVA", .state
= ARM_CP_STATE_AA64
,
1835 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 4, .opc2
= 1,
1836 .access
= PL0_W
, .type
= ARM_CP_DC_ZVA
,
1837 #ifndef CONFIG_USER_ONLY
1838 /* Avoid overhead of an access check that always passes in user-mode */
1839 .accessfn
= aa64_zva_access
,
1842 { .name
= "CURRENTEL", .state
= ARM_CP_STATE_AA64
,
1843 .opc0
= 3, .opc1
= 0, .opc2
= 2, .crn
= 4, .crm
= 2,
1844 .access
= PL1_R
, .type
= ARM_CP_CURRENTEL
},
1845 /* Cache ops: all NOPs since we don't emulate caches */
1846 { .name
= "IC_IALLUIS", .state
= ARM_CP_STATE_AA64
,
1847 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 1, .opc2
= 0,
1848 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1849 { .name
= "IC_IALLU", .state
= ARM_CP_STATE_AA64
,
1850 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 5, .opc2
= 0,
1851 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1852 { .name
= "IC_IVAU", .state
= ARM_CP_STATE_AA64
,
1853 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 5, .opc2
= 1,
1854 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1855 .accessfn
= aa64_cacheop_access
},
1856 { .name
= "DC_IVAC", .state
= ARM_CP_STATE_AA64
,
1857 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 1,
1858 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1859 { .name
= "DC_ISW", .state
= ARM_CP_STATE_AA64
,
1860 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 6, .opc2
= 2,
1861 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1862 { .name
= "DC_CVAC", .state
= ARM_CP_STATE_AA64
,
1863 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 10, .opc2
= 1,
1864 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1865 .accessfn
= aa64_cacheop_access
},
1866 { .name
= "DC_CSW", .state
= ARM_CP_STATE_AA64
,
1867 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 10, .opc2
= 2,
1868 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1869 { .name
= "DC_CVAU", .state
= ARM_CP_STATE_AA64
,
1870 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 11, .opc2
= 1,
1871 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1872 .accessfn
= aa64_cacheop_access
},
1873 { .name
= "DC_CIVAC", .state
= ARM_CP_STATE_AA64
,
1874 .opc0
= 1, .opc1
= 3, .crn
= 7, .crm
= 14, .opc2
= 1,
1875 .access
= PL0_W
, .type
= ARM_CP_NOP
,
1876 .accessfn
= aa64_cacheop_access
},
1877 { .name
= "DC_CISW", .state
= ARM_CP_STATE_AA64
,
1878 .opc0
= 1, .opc1
= 0, .crn
= 7, .crm
= 14, .opc2
= 2,
1879 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1880 /* TLBI operations */
1881 { .name
= "TLBI_VMALLE1IS", .state
= ARM_CP_STATE_AA64
,
1882 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 0,
1883 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1884 .writefn
= tlbiall_write
},
1885 { .name
= "TLBI_VAE1IS", .state
= ARM_CP_STATE_AA64
,
1886 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 1,
1887 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1888 .writefn
= tlbi_aa64_va_write
},
1889 { .name
= "TLBI_ASIDE1IS", .state
= ARM_CP_STATE_AA64
,
1890 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 2,
1891 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1892 .writefn
= tlbi_aa64_asid_write
},
1893 { .name
= "TLBI_VAAE1IS", .state
= ARM_CP_STATE_AA64
,
1894 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 3,
1895 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1896 .writefn
= tlbi_aa64_vaa_write
},
1897 { .name
= "TLBI_VALE1IS", .state
= ARM_CP_STATE_AA64
,
1898 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 5,
1899 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1900 .writefn
= tlbi_aa64_va_write
},
1901 { .name
= "TLBI_VAALE1IS", .state
= ARM_CP_STATE_AA64
,
1902 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 3, .opc2
= 7,
1903 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1904 .writefn
= tlbi_aa64_vaa_write
},
1905 { .name
= "TLBI_VMALLE1", .state
= ARM_CP_STATE_AA64
,
1906 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 0,
1907 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1908 .writefn
= tlbiall_write
},
1909 { .name
= "TLBI_VAE1", .state
= ARM_CP_STATE_AA64
,
1910 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 1,
1911 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1912 .writefn
= tlbi_aa64_va_write
},
1913 { .name
= "TLBI_ASIDE1", .state
= ARM_CP_STATE_AA64
,
1914 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 2,
1915 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1916 .writefn
= tlbi_aa64_asid_write
},
1917 { .name
= "TLBI_VAAE1", .state
= ARM_CP_STATE_AA64
,
1918 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 3,
1919 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1920 .writefn
= tlbi_aa64_vaa_write
},
1921 { .name
= "TLBI_VALE1", .state
= ARM_CP_STATE_AA64
,
1922 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 5,
1923 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1924 .writefn
= tlbi_aa64_va_write
},
1925 { .name
= "TLBI_VAALE1", .state
= ARM_CP_STATE_AA64
,
1926 .opc0
= 1, .opc2
= 0, .crn
= 8, .crm
= 7, .opc2
= 7,
1927 .access
= PL1_W
, .type
= ARM_CP_NO_MIGRATE
,
1928 .writefn
= tlbi_aa64_vaa_write
},
1929 /* Dummy implementation of monitor debug system control register:
1930 * we don't support debug.
1932 { .name
= "MDSCR_EL1", .state
= ARM_CP_STATE_AA64
,
1933 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
1934 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1935 /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
1936 { .name
= "OSLAR_EL1", .state
= ARM_CP_STATE_AA64
,
1937 .opc0
= 2, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 4,
1938 .access
= PL1_W
, .type
= ARM_CP_NOP
},
1939 { .name
= "ELR_EL1", .state
= ARM_CP_STATE_AA64
,
1940 .type
= ARM_CP_NO_MIGRATE
,
1941 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 1,
1942 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, elr_el1
) },
1943 { .name
= "SPSR_EL1", .state
= ARM_CP_STATE_AA64
,
1944 .type
= ARM_CP_NO_MIGRATE
,
1945 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 0, .opc2
= 0,
1946 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, banked_spsr
[0]) },
1947 /* We rely on the access checks not allowing the guest to write to the
1948 * state field when SPSel indicates that it's being used as the stack
1951 { .name
= "SP_EL0", .state
= ARM_CP_STATE_AA64
,
1952 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 1, .opc2
= 0,
1953 .access
= PL1_RW
, .accessfn
= sp_el0_access
,
1954 .type
= ARM_CP_NO_MIGRATE
,
1955 .fieldoffset
= offsetof(CPUARMState
, sp_el
[0]) },
1956 { .name
= "SPSel", .state
= ARM_CP_STATE_AA64
,
1957 .opc0
= 3, .opc1
= 0, .crn
= 4, .crm
= 2, .opc2
= 0,
1958 .type
= ARM_CP_NO_MIGRATE
,
1959 .access
= PL1_RW
, .readfn
= spsel_read
, .writefn
= spsel_write
},
1963 static void sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1966 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1968 env
->cp15
.c1_sys
= value
;
1969 /* ??? Lots of these bits are not implemented. */
1970 /* This may enable/disable the MMU, so do a TLB flush. */
1971 tlb_flush(CPU(cpu
), 1);
1974 static CPAccessResult
ctr_el0_access(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
1976 /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
1977 * but the AArch32 CTR has its own reginfo struct)
1979 if (arm_current_pl(env
) == 0 && !(env
->cp15
.c1_sys
& SCTLR_UCT
)) {
1980 return CP_ACCESS_TRAP
;
1982 return CP_ACCESS_OK
;
1985 static void define_aarch64_debug_regs(ARMCPU
*cpu
)
1987 /* Define breakpoint and watchpoint registers. These do nothing
1988 * but read as written, for now.
1992 for (i
= 0; i
< 16; i
++) {
1993 ARMCPRegInfo dbgregs
[] = {
1994 { .name
= "DBGBVR", .state
= ARM_CP_STATE_AA64
,
1995 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 4,
1997 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbvr
[i
]) },
1998 { .name
= "DBGBCR", .state
= ARM_CP_STATE_AA64
,
1999 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 5,
2001 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgbcr
[i
]) },
2002 { .name
= "DBGWVR", .state
= ARM_CP_STATE_AA64
,
2003 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 6,
2005 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwvr
[i
]) },
2006 { .name
= "DBGWCR", .state
= ARM_CP_STATE_AA64
,
2007 .opc0
= 2, .opc1
= 0, .crn
= 0, .crm
= i
, .opc2
= 7,
2009 .fieldoffset
= offsetof(CPUARMState
, cp15
.dbgwcr
[i
]) },
2012 define_arm_cp_regs(cpu
, dbgregs
);
2016 void register_cp_regs_for_features(ARMCPU
*cpu
)
2018 /* Register all the coprocessor registers based on feature bits */
2019 CPUARMState
*env
= &cpu
->env
;
2020 if (arm_feature(env
, ARM_FEATURE_M
)) {
2021 /* M profile has no coprocessor registers */
2025 define_arm_cp_regs(cpu
, cp_reginfo
);
2026 if (arm_feature(env
, ARM_FEATURE_V6
)) {
2027 /* The ID registers all have impdef reset values */
2028 ARMCPRegInfo v6_idregs
[] = {
2029 { .name
= "ID_PFR0", .state
= ARM_CP_STATE_BOTH
,
2030 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 0,
2031 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2032 .resetvalue
= cpu
->id_pfr0
},
2033 { .name
= "ID_PFR1", .state
= ARM_CP_STATE_BOTH
,
2034 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 1,
2035 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2036 .resetvalue
= cpu
->id_pfr1
},
2037 { .name
= "ID_DFR0", .state
= ARM_CP_STATE_BOTH
,
2038 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 2,
2039 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2040 .resetvalue
= cpu
->id_dfr0
},
2041 { .name
= "ID_AFR0", .state
= ARM_CP_STATE_BOTH
,
2042 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 3,
2043 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2044 .resetvalue
= cpu
->id_afr0
},
2045 { .name
= "ID_MMFR0", .state
= ARM_CP_STATE_BOTH
,
2046 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 4,
2047 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2048 .resetvalue
= cpu
->id_mmfr0
},
2049 { .name
= "ID_MMFR1", .state
= ARM_CP_STATE_BOTH
,
2050 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 5,
2051 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2052 .resetvalue
= cpu
->id_mmfr1
},
2053 { .name
= "ID_MMFR2", .state
= ARM_CP_STATE_BOTH
,
2054 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 6,
2055 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2056 .resetvalue
= cpu
->id_mmfr2
},
2057 { .name
= "ID_MMFR3", .state
= ARM_CP_STATE_BOTH
,
2058 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 1, .opc2
= 7,
2059 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2060 .resetvalue
= cpu
->id_mmfr3
},
2061 { .name
= "ID_ISAR0", .state
= ARM_CP_STATE_BOTH
,
2062 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 0,
2063 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2064 .resetvalue
= cpu
->id_isar0
},
2065 { .name
= "ID_ISAR1", .state
= ARM_CP_STATE_BOTH
,
2066 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 1,
2067 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2068 .resetvalue
= cpu
->id_isar1
},
2069 { .name
= "ID_ISAR2", .state
= ARM_CP_STATE_BOTH
,
2070 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 2,
2071 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2072 .resetvalue
= cpu
->id_isar2
},
2073 { .name
= "ID_ISAR3", .state
= ARM_CP_STATE_BOTH
,
2074 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 3,
2075 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2076 .resetvalue
= cpu
->id_isar3
},
2077 { .name
= "ID_ISAR4", .state
= ARM_CP_STATE_BOTH
,
2078 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 4,
2079 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2080 .resetvalue
= cpu
->id_isar4
},
2081 { .name
= "ID_ISAR5", .state
= ARM_CP_STATE_BOTH
,
2082 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 2, .opc2
= 5,
2083 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2084 .resetvalue
= cpu
->id_isar5
},
2085 /* 6..7 are as yet unallocated and must RAZ */
2086 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
2087 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
2089 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
2090 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
2094 define_arm_cp_regs(cpu
, v6_idregs
);
2095 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
2097 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
2099 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
2100 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
2102 if (arm_feature(env
, ARM_FEATURE_V7
)) {
2103 /* v7 performance monitor control register: same implementor
2104 * field as main ID register, and we implement only the cycle
2107 #ifndef CONFIG_USER_ONLY
2108 ARMCPRegInfo pmcr
= {
2109 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
2110 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
2112 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
2113 .accessfn
= pmreg_access
, .writefn
= pmcr_write
,
2114 .raw_writefn
= raw_write
,
2116 define_one_arm_cp_reg(cpu
, &pmcr
);
2118 ARMCPRegInfo clidr
= {
2119 .name
= "CLIDR", .state
= ARM_CP_STATE_BOTH
,
2120 .opc0
= 3, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
2121 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
2123 define_one_arm_cp_reg(cpu
, &clidr
);
2124 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
2126 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
2128 if (arm_feature(env
, ARM_FEATURE_V8
)) {
2129 /* AArch64 ID registers, which all have impdef reset values */
2130 ARMCPRegInfo v8_idregs
[] = {
2131 { .name
= "ID_AA64PFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2132 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 0,
2133 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2134 .resetvalue
= cpu
->id_aa64pfr0
},
2135 { .name
= "ID_AA64PFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2136 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 4, .opc2
= 1,
2137 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2138 .resetvalue
= cpu
->id_aa64pfr1
},
2139 { .name
= "ID_AA64DFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2140 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 0,
2141 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2142 /* We mask out the PMUVer field, beacuse we don't currently
2143 * implement the PMU. Not advertising it prevents the guest
2144 * from trying to use it and getting UNDEFs on registers we
2147 .resetvalue
= cpu
->id_aa64dfr0
& ~0xf00 },
2148 { .name
= "ID_AA64DFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2149 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 1,
2150 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2151 .resetvalue
= cpu
->id_aa64dfr1
},
2152 { .name
= "ID_AA64AFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2153 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 4,
2154 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2155 .resetvalue
= cpu
->id_aa64afr0
},
2156 { .name
= "ID_AA64AFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2157 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 5, .opc2
= 5,
2158 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2159 .resetvalue
= cpu
->id_aa64afr1
},
2160 { .name
= "ID_AA64ISAR0_EL1", .state
= ARM_CP_STATE_AA64
,
2161 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 0,
2162 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2163 .resetvalue
= cpu
->id_aa64isar0
},
2164 { .name
= "ID_AA64ISAR1_EL1", .state
= ARM_CP_STATE_AA64
,
2165 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 6, .opc2
= 1,
2166 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2167 .resetvalue
= cpu
->id_aa64isar1
},
2168 { .name
= "ID_AA64MMFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2169 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 0,
2170 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2171 .resetvalue
= cpu
->id_aa64mmfr0
},
2172 { .name
= "ID_AA64MMFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2173 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 7, .opc2
= 1,
2174 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2175 .resetvalue
= cpu
->id_aa64mmfr1
},
2176 { .name
= "MVFR0_EL1", .state
= ARM_CP_STATE_AA64
,
2177 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 0,
2178 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2179 .resetvalue
= cpu
->mvfr0
},
2180 { .name
= "MVFR1_EL1", .state
= ARM_CP_STATE_AA64
,
2181 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 1,
2182 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2183 .resetvalue
= cpu
->mvfr1
},
2184 { .name
= "MVFR2_EL1", .state
= ARM_CP_STATE_AA64
,
2185 .opc0
= 3, .opc1
= 0, .crn
= 0, .crm
= 3, .opc2
= 2,
2186 .access
= PL1_R
, .type
= ARM_CP_CONST
,
2187 .resetvalue
= cpu
->mvfr2
},
2190 define_arm_cp_regs(cpu
, v8_idregs
);
2191 define_arm_cp_regs(cpu
, v8_cp_reginfo
);
2192 define_aarch64_debug_regs(cpu
);
2194 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2195 /* These are the MPU registers prior to PMSAv6. Any new
2196 * PMSA core later than the ARM946 will require that we
2197 * implement the PMSAv6 or PMSAv7 registers, which are
2198 * completely different.
2200 assert(!arm_feature(env
, ARM_FEATURE_V6
));
2201 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
2203 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
2205 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
2206 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
2208 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
2209 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
2211 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
2212 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
2214 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
2215 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
2217 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
2218 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
2220 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
2221 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
2223 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
2224 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
2226 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
2227 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
2229 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2230 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
2232 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
2233 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
2235 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
2236 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
2238 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2239 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2240 * be read-only (ie write causes UNDEF exception).
2243 ARMCPRegInfo id_cp_reginfo
[] = {
2244 /* Note that the MIDR isn't a simple constant register because
2245 * of the TI925 behaviour where writes to another register can
2246 * cause the MIDR value to change.
2248 * Unimplemented registers in the c15 0 0 0 space default to
2249 * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2250 * and friends override accordingly.
2253 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= CP_ANY
,
2254 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
2255 .writefn
= arm_cp_write_ignore
, .raw_writefn
= raw_write
,
2256 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
),
2257 .type
= ARM_CP_OVERRIDE
},
2258 { .name
= "MIDR_EL1", .state
= ARM_CP_STATE_AA64
,
2259 .opc0
= 3, .opc1
= 0, .opc2
= 0, .crn
= 0, .crm
= 0,
2260 .access
= PL1_R
, .resetvalue
= cpu
->midr
, .type
= ARM_CP_CONST
},
2262 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
2263 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
2264 { .name
= "CTR_EL0", .state
= ARM_CP_STATE_AA64
,
2265 .opc0
= 3, .opc1
= 3, .opc2
= 1, .crn
= 0, .crm
= 0,
2266 .access
= PL0_R
, .accessfn
= ctr_el0_access
,
2267 .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
2269 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
2270 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2272 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
2273 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2274 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2276 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
2277 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2279 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
2280 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2282 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
2283 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2285 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
2286 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2288 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
2289 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2292 ARMCPRegInfo crn0_wi_reginfo
= {
2293 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
2294 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
2295 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
2297 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
2298 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
2300 /* Register the blanket "writes ignored" value first to cover the
2301 * whole space. Then update the specific ID registers to allow write
2302 * access, so that they ignore writes rather than causing them to
2305 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
2306 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
2310 define_arm_cp_regs(cpu
, id_cp_reginfo
);
2313 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
2314 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
2317 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
2318 ARMCPRegInfo auxcr
= {
2319 .name
= "ACTLR_EL1", .state
= ARM_CP_STATE_BOTH
,
2320 .opc0
= 3, .opc1
= 0, .crn
= 1, .crm
= 0, .opc2
= 1,
2321 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
2322 .resetvalue
= cpu
->reset_auxcr
2324 define_one_arm_cp_reg(cpu
, &auxcr
);
2327 if (arm_feature(env
, ARM_FEATURE_CBAR
)) {
2328 ARMCPRegInfo cbar
= {
2329 .name
= "CBAR", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 4, .opc2
= 0,
2330 .access
= PL1_R
|PL3_W
, .resetvalue
= cpu
->reset_cbar
,
2331 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_config_base_address
)
2333 define_one_arm_cp_reg(cpu
, &cbar
);
2336 /* Generic registers whose values depend on the implementation */
2338 ARMCPRegInfo sctlr
= {
2339 .name
= "SCTLR", .state
= ARM_CP_STATE_BOTH
,
2340 .opc0
= 3, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
2341 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
2342 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
,
2343 .raw_writefn
= raw_write
,
2345 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2346 /* Normally we would always end the TB on an SCTLR write, but Linux
2347 * arch/arm/mach-pxa/sleep.S expects two instructions following
2348 * an MMU enable to execute from cache. Imitate this behaviour.
2350 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
2352 define_one_arm_cp_reg(cpu
, &sctlr
);
2356 ARMCPU
*cpu_arm_init(const char *cpu_model
)
2358 return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU
, cpu_model
));
2361 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
2363 CPUState
*cs
= CPU(cpu
);
2364 CPUARMState
*env
= &cpu
->env
;
2366 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
2367 gdb_register_coprocessor(cs
, aarch64_fpu_gdb_get_reg
,
2368 aarch64_fpu_gdb_set_reg
,
2369 34, "aarch64-fpu.xml", 0);
2370 } else if (arm_feature(env
, ARM_FEATURE_NEON
)) {
2371 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2372 51, "arm-neon.xml", 0);
2373 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
2374 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2375 35, "arm-vfp3.xml", 0);
2376 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
2377 gdb_register_coprocessor(cs
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
2378 19, "arm-vfp.xml", 0);
2382 /* Sort alphabetically by type name, except for "any". */
2383 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
2385 ObjectClass
*class_a
= (ObjectClass
*)a
;
2386 ObjectClass
*class_b
= (ObjectClass
*)b
;
2387 const char *name_a
, *name_b
;
2389 name_a
= object_class_get_name(class_a
);
2390 name_b
= object_class_get_name(class_b
);
2391 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
2393 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
2396 return strcmp(name_a
, name_b
);
2400 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
2402 ObjectClass
*oc
= data
;
2403 CPUListState
*s
= user_data
;
2404 const char *typename
;
2407 typename
= object_class_get_name(oc
);
2408 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
2409 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
2414 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2418 .cpu_fprintf
= cpu_fprintf
,
2422 list
= object_class_get_list(TYPE_ARM_CPU
, false);
2423 list
= g_slist_sort(list
, arm_cpu_list_compare
);
2424 (*cpu_fprintf
)(f
, "Available CPUs:\n");
2425 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
2428 /* The 'host' CPU type is dynamically registered only if KVM is
2429 * enabled, so we have to special-case it here:
2431 (*cpu_fprintf
)(f
, " host (only available in KVM mode)\n");
2435 static void arm_cpu_add_definition(gpointer data
, gpointer user_data
)
2437 ObjectClass
*oc
= data
;
2438 CpuDefinitionInfoList
**cpu_list
= user_data
;
2439 CpuDefinitionInfoList
*entry
;
2440 CpuDefinitionInfo
*info
;
2441 const char *typename
;
2443 typename
= object_class_get_name(oc
);
2444 info
= g_malloc0(sizeof(*info
));
2445 info
->name
= g_strndup(typename
,
2446 strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
2448 entry
= g_malloc0(sizeof(*entry
));
2449 entry
->value
= info
;
2450 entry
->next
= *cpu_list
;
2454 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2456 CpuDefinitionInfoList
*cpu_list
= NULL
;
2459 list
= object_class_get_list(TYPE_ARM_CPU
, false);
2460 g_slist_foreach(list
, arm_cpu_add_definition
, &cpu_list
);
2466 static void add_cpreg_to_hashtable(ARMCPU
*cpu
, const ARMCPRegInfo
*r
,
2467 void *opaque
, int state
,
2468 int crm
, int opc1
, int opc2
)
2470 /* Private utility function for define_one_arm_cp_reg_with_opaque():
2471 * add a single reginfo struct to the hash table.
2473 uint32_t *key
= g_new(uint32_t, 1);
2474 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
2475 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
2476 if (r
->state
== ARM_CP_STATE_BOTH
&& state
== ARM_CP_STATE_AA32
) {
2477 /* The AArch32 view of a shared register sees the lower 32 bits
2478 * of a 64 bit backing field. It is not migratable as the AArch64
2479 * view handles that. AArch64 also handles reset.
2480 * We assume it is a cp15 register.
2483 r2
->type
|= ARM_CP_NO_MIGRATE
;
2484 r2
->resetfn
= arm_cp_reset_ignore
;
2485 #ifdef HOST_WORDS_BIGENDIAN
2486 if (r2
->fieldoffset
) {
2487 r2
->fieldoffset
+= sizeof(uint32_t);
2491 if (state
== ARM_CP_STATE_AA64
) {
2492 /* To allow abbreviation of ARMCPRegInfo
2493 * definitions, we treat cp == 0 as equivalent to
2494 * the value for "standard guest-visible sysreg".
2497 r2
->cp
= CP_REG_ARM64_SYSREG_CP
;
2499 *key
= ENCODE_AA64_CP_REG(r2
->cp
, r2
->crn
, crm
,
2500 r2
->opc0
, opc1
, opc2
);
2502 *key
= ENCODE_CP_REG(r2
->cp
, is64
, r2
->crn
, crm
, opc1
, opc2
);
2505 r2
->opaque
= opaque
;
2507 /* reginfo passed to helpers is correct for the actual access,
2508 * and is never ARM_CP_STATE_BOTH:
2511 /* Make sure reginfo passed to helpers for wildcarded regs
2512 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2517 /* By convention, for wildcarded registers only the first
2518 * entry is used for migration; the others are marked as
2519 * NO_MIGRATE so we don't try to transfer the register
2520 * multiple times. Special registers (ie NOP/WFI) are
2523 if ((r
->type
& ARM_CP_SPECIAL
) ||
2524 ((r
->crm
== CP_ANY
) && crm
!= 0) ||
2525 ((r
->opc1
== CP_ANY
) && opc1
!= 0) ||
2526 ((r
->opc2
== CP_ANY
) && opc2
!= 0)) {
2527 r2
->type
|= ARM_CP_NO_MIGRATE
;
2530 /* Overriding of an existing definition must be explicitly
2533 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
2534 ARMCPRegInfo
*oldreg
;
2535 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
2536 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
2537 fprintf(stderr
, "Register redefined: cp=%d %d bit "
2538 "crn=%d crm=%d opc1=%d opc2=%d, "
2539 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
2540 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
2541 oldreg
->name
, r2
->name
);
2542 g_assert_not_reached();
2545 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
2549 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
2550 const ARMCPRegInfo
*r
, void *opaque
)
2552 /* Define implementations of coprocessor registers.
2553 * We store these in a hashtable because typically
2554 * there are less than 150 registers in a space which
2555 * is 16*16*16*8*8 = 262144 in size.
2556 * Wildcarding is supported for the crm, opc1 and opc2 fields.
2557 * If a register is defined twice then the second definition is
2558 * used, so this can be used to define some generic registers and
2559 * then override them with implementation specific variations.
2560 * At least one of the original and the second definition should
2561 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2562 * against accidental use.
2564 * The state field defines whether the register is to be
2565 * visible in the AArch32 or AArch64 execution state. If the
2566 * state is set to ARM_CP_STATE_BOTH then we synthesise a
2567 * reginfo structure for the AArch32 view, which sees the lower
2568 * 32 bits of the 64 bit register.
2570 * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2571 * be wildcarded. AArch64 registers are always considered to be 64
2572 * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2573 * the register, if any.
2575 int crm
, opc1
, opc2
, state
;
2576 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
2577 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
2578 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
2579 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
2580 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
2581 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
2582 /* 64 bit registers have only CRm and Opc1 fields */
2583 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
2584 /* op0 only exists in the AArch64 encodings */
2585 assert((r
->state
!= ARM_CP_STATE_AA32
) || (r
->opc0
== 0));
2586 /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2587 assert((r
->state
!= ARM_CP_STATE_AA64
) || !(r
->type
& ARM_CP_64BIT
));
2588 /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2589 * encodes a minimum access level for the register. We roll this
2590 * runtime check into our general permission check code, so check
2591 * here that the reginfo's specified permissions are strict enough
2592 * to encompass the generic architectural permission check.
2594 if (r
->state
!= ARM_CP_STATE_AA32
) {
2597 case 0: case 1: case 2:
2610 /* unallocated encoding, so not possible */
2618 /* min_EL EL1, secure mode only (we don't check the latter) */
2622 /* broken reginfo with out-of-range opc1 */
2626 /* assert our permissions are not too lax (stricter is fine) */
2627 assert((r
->access
& ~mask
) == 0);
2630 /* Check that the register definition has enough info to handle
2631 * reads and writes if they are permitted.
2633 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
2634 if (r
->access
& PL3_R
) {
2635 assert(r
->fieldoffset
|| r
->readfn
);
2637 if (r
->access
& PL3_W
) {
2638 assert(r
->fieldoffset
|| r
->writefn
);
2641 /* Bad type field probably means missing sentinel at end of reg list */
2642 assert(cptype_valid(r
->type
));
2643 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
2644 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
2645 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
2646 for (state
= ARM_CP_STATE_AA32
;
2647 state
<= ARM_CP_STATE_AA64
; state
++) {
2648 if (r
->state
!= state
&& r
->state
!= ARM_CP_STATE_BOTH
) {
2651 add_cpreg_to_hashtable(cpu
, r
, opaque
, state
,
2659 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
2660 const ARMCPRegInfo
*regs
, void *opaque
)
2662 /* Define a whole list of registers */
2663 const ARMCPRegInfo
*r
;
2664 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
2665 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
2669 const ARMCPRegInfo
*get_arm_cp_reginfo(GHashTable
*cpregs
, uint32_t encoded_cp
)
2671 return g_hash_table_lookup(cpregs
, &encoded_cp
);
2674 void arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
2677 /* Helper coprocessor write function for write-ignore registers */
2680 uint64_t arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2682 /* Helper coprocessor write function for read-as-zero registers */
2686 void arm_cp_reset_ignore(CPUARMState
*env
, const ARMCPRegInfo
*opaque
)
2688 /* Helper coprocessor reset function for do-nothing-on-reset registers */
2691 static int bad_mode_switch(CPUARMState
*env
, int mode
)
2693 /* Return true if it is not valid for us to switch to
2694 * this CPU mode (ie all the UNPREDICTABLE cases in
2695 * the ARM ARM CPSRWriteByInstr pseudocode).
2698 case ARM_CPU_MODE_USR
:
2699 case ARM_CPU_MODE_SYS
:
2700 case ARM_CPU_MODE_SVC
:
2701 case ARM_CPU_MODE_ABT
:
2702 case ARM_CPU_MODE_UND
:
2703 case ARM_CPU_MODE_IRQ
:
2704 case ARM_CPU_MODE_FIQ
:
2711 uint32_t cpsr_read(CPUARMState
*env
)
2714 ZF
= (env
->ZF
== 0);
2715 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
2716 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
2717 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
2718 | ((env
->condexec_bits
& 0xfc) << 8)
2719 | (env
->GE
<< 16) | (env
->daif
& CPSR_AIF
);
2722 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
2724 if (mask
& CPSR_NZCV
) {
2725 env
->ZF
= (~val
) & CPSR_Z
;
2727 env
->CF
= (val
>> 29) & 1;
2728 env
->VF
= (val
<< 3) & 0x80000000;
2731 env
->QF
= ((val
& CPSR_Q
) != 0);
2733 env
->thumb
= ((val
& CPSR_T
) != 0);
2734 if (mask
& CPSR_IT_0_1
) {
2735 env
->condexec_bits
&= ~3;
2736 env
->condexec_bits
|= (val
>> 25) & 3;
2738 if (mask
& CPSR_IT_2_7
) {
2739 env
->condexec_bits
&= 3;
2740 env
->condexec_bits
|= (val
>> 8) & 0xfc;
2742 if (mask
& CPSR_GE
) {
2743 env
->GE
= (val
>> 16) & 0xf;
2746 env
->daif
&= ~(CPSR_AIF
& mask
);
2747 env
->daif
|= val
& CPSR_AIF
& mask
;
2749 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
2750 if (bad_mode_switch(env
, val
& CPSR_M
)) {
2751 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2752 * We choose to ignore the attempt and leave the CPSR M field
2757 switch_mode(env
, val
& CPSR_M
);
2760 mask
&= ~CACHED_CPSR_BITS
;
2761 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
2764 /* Sign/zero extend */
2765 uint32_t HELPER(sxtb16
)(uint32_t x
)
2768 res
= (uint16_t)(int8_t)x
;
2769 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
2773 uint32_t HELPER(uxtb16
)(uint32_t x
)
2776 res
= (uint16_t)(uint8_t)x
;
2777 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
2781 uint32_t HELPER(clz
)(uint32_t x
)
2786 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
2790 if (num
== INT_MIN
&& den
== -1)
2795 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
2802 uint32_t HELPER(rbit
)(uint32_t x
)
2804 x
= ((x
& 0xff000000) >> 24)
2805 | ((x
& 0x00ff0000) >> 8)
2806 | ((x
& 0x0000ff00) << 8)
2807 | ((x
& 0x000000ff) << 24);
2808 x
= ((x
& 0xf0f0f0f0) >> 4)
2809 | ((x
& 0x0f0f0f0f) << 4);
2810 x
= ((x
& 0x88888888) >> 3)
2811 | ((x
& 0x44444444) >> 1)
2812 | ((x
& 0x22222222) << 1)
2813 | ((x
& 0x11111111) << 3);
2817 #if defined(CONFIG_USER_ONLY)
2819 void arm_cpu_do_interrupt(CPUState
*cs
)
2821 cs
->exception_index
= -1;
2824 int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
, int rw
,
2827 ARMCPU
*cpu
= ARM_CPU(cs
);
2828 CPUARMState
*env
= &cpu
->env
;
2830 env
->exception
.vaddress
= address
;
2832 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
2834 cs
->exception_index
= EXCP_DATA_ABORT
;
2839 /* These should probably raise undefined insn exceptions. */
2840 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2842 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2844 cpu_abort(CPU(cpu
), "v7m_msr %d\n", reg
);
2847 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2849 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2851 cpu_abort(CPU(cpu
), "v7m_mrs %d\n", reg
);
2855 void switch_mode(CPUARMState
*env
, int mode
)
2857 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2859 if (mode
!= ARM_CPU_MODE_USR
) {
2860 cpu_abort(CPU(cpu
), "Tried to switch out of user mode\n");
2864 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2866 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2868 cpu_abort(CPU(cpu
), "banked r13 write\n");
2871 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2873 ARMCPU
*cpu
= arm_env_get_cpu(env
);
2875 cpu_abort(CPU(cpu
), "banked r13 read\n");
2881 /* Map CPU modes onto saved register banks. */
2882 int bank_number(int mode
)
2885 case ARM_CPU_MODE_USR
:
2886 case ARM_CPU_MODE_SYS
:
2888 case ARM_CPU_MODE_SVC
:
2890 case ARM_CPU_MODE_ABT
:
2892 case ARM_CPU_MODE_UND
:
2894 case ARM_CPU_MODE_IRQ
:
2896 case ARM_CPU_MODE_FIQ
:
2899 hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode
);
2902 void switch_mode(CPUARMState
*env
, int mode
)
2907 old_mode
= env
->uncached_cpsr
& CPSR_M
;
2908 if (mode
== old_mode
)
2911 if (old_mode
== ARM_CPU_MODE_FIQ
) {
2912 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
2913 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
2914 } else if (mode
== ARM_CPU_MODE_FIQ
) {
2915 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
2916 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
2919 i
= bank_number(old_mode
);
2920 env
->banked_r13
[i
] = env
->regs
[13];
2921 env
->banked_r14
[i
] = env
->regs
[14];
2922 env
->banked_spsr
[i
] = env
->spsr
;
2924 i
= bank_number(mode
);
2925 env
->regs
[13] = env
->banked_r13
[i
];
2926 env
->regs
[14] = env
->banked_r14
[i
];
2927 env
->spsr
= env
->banked_spsr
[i
];
2930 static void v7m_push(CPUARMState
*env
, uint32_t val
)
2932 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
2935 stl_phys(cs
->as
, env
->regs
[13], val
);
2938 static uint32_t v7m_pop(CPUARMState
*env
)
2940 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
2943 val
= ldl_phys(cs
->as
, env
->regs
[13]);
2948 /* Switch to V7M main or process stack pointer. */
2949 static void switch_v7m_sp(CPUARMState
*env
, int process
)
2952 if (env
->v7m
.current_sp
!= process
) {
2953 tmp
= env
->v7m
.other_sp
;
2954 env
->v7m
.other_sp
= env
->regs
[13];
2955 env
->regs
[13] = tmp
;
2956 env
->v7m
.current_sp
= process
;
2960 static void do_v7m_exception_exit(CPUARMState
*env
)
2965 type
= env
->regs
[15];
2966 if (env
->v7m
.exception
!= 0)
2967 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
2969 /* Switch to the target stack. */
2970 switch_v7m_sp(env
, (type
& 4) != 0);
2971 /* Pop registers. */
2972 env
->regs
[0] = v7m_pop(env
);
2973 env
->regs
[1] = v7m_pop(env
);
2974 env
->regs
[2] = v7m_pop(env
);
2975 env
->regs
[3] = v7m_pop(env
);
2976 env
->regs
[12] = v7m_pop(env
);
2977 env
->regs
[14] = v7m_pop(env
);
2978 env
->regs
[15] = v7m_pop(env
);
2979 xpsr
= v7m_pop(env
);
2980 xpsr_write(env
, xpsr
, 0xfffffdff);
2981 /* Undo stack alignment. */
2984 /* ??? The exception return type specifies Thread/Handler mode. However
2985 this is also implied by the xPSR value. Not sure what to do
2986 if there is a mismatch. */
2987 /* ??? Likewise for mismatches between the CONTROL register and the stack
2991 void arm_v7m_cpu_do_interrupt(CPUState
*cs
)
2993 ARMCPU
*cpu
= ARM_CPU(cs
);
2994 CPUARMState
*env
= &cpu
->env
;
2995 uint32_t xpsr
= xpsr_read(env
);
2999 arm_log_exception(cs
->exception_index
);
3002 if (env
->v7m
.current_sp
)
3004 if (env
->v7m
.exception
== 0)
3007 /* For exceptions we just mark as pending on the NVIC, and let that
3009 /* TODO: Need to escalate if the current priority is higher than the
3010 one we're raising. */
3011 switch (cs
->exception_index
) {
3013 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
3016 /* The PC already points to the next instruction. */
3017 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
3019 case EXCP_PREFETCH_ABORT
:
3020 case EXCP_DATA_ABORT
:
3021 /* TODO: if we implemented the MPU registers, this is where we
3022 * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3024 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
3027 if (semihosting_enabled
) {
3029 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
3032 env
->regs
[0] = do_arm_semihosting(env
);
3033 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
3037 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
3040 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
3042 case EXCP_EXCEPTION_EXIT
:
3043 do_v7m_exception_exit(env
);
3046 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
3047 return; /* Never happens. Keep compiler happy. */
3050 /* Align stack pointer. */
3051 /* ??? Should only do this if Configuration Control Register
3052 STACKALIGN bit is set. */
3053 if (env
->regs
[13] & 4) {
3057 /* Switch to the handler mode. */
3058 v7m_push(env
, xpsr
);
3059 v7m_push(env
, env
->regs
[15]);
3060 v7m_push(env
, env
->regs
[14]);
3061 v7m_push(env
, env
->regs
[12]);
3062 v7m_push(env
, env
->regs
[3]);
3063 v7m_push(env
, env
->regs
[2]);
3064 v7m_push(env
, env
->regs
[1]);
3065 v7m_push(env
, env
->regs
[0]);
3066 switch_v7m_sp(env
, 0);
3068 env
->condexec_bits
= 0;
3070 addr
= ldl_phys(cs
->as
, env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
3071 env
->regs
[15] = addr
& 0xfffffffe;
3072 env
->thumb
= addr
& 1;
3075 /* Handle a CPU exception. */
3076 void arm_cpu_do_interrupt(CPUState
*cs
)
3078 ARMCPU
*cpu
= ARM_CPU(cs
);
3079 CPUARMState
*env
= &cpu
->env
;
3087 arm_log_exception(cs
->exception_index
);
3089 /* TODO: Vectored interrupt controller. */
3090 switch (cs
->exception_index
) {
3092 new_mode
= ARM_CPU_MODE_UND
;
3101 if (semihosting_enabled
) {
3102 /* Check for semihosting interrupt. */
3104 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
3107 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
3110 /* Only intercept calls from privileged modes, to provide some
3111 semblance of security. */
3112 if (((mask
== 0x123456 && !env
->thumb
)
3113 || (mask
== 0xab && env
->thumb
))
3114 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
3115 env
->regs
[0] = do_arm_semihosting(env
);
3116 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
3120 new_mode
= ARM_CPU_MODE_SVC
;
3123 /* The PC already points to the next instruction. */
3127 /* See if this is a semihosting syscall. */
3128 if (env
->thumb
&& semihosting_enabled
) {
3129 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
3131 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
3133 env
->regs
[0] = do_arm_semihosting(env
);
3134 qemu_log_mask(CPU_LOG_INT
, "...handled as semihosting call\n");
3138 env
->exception
.fsr
= 2;
3139 /* Fall through to prefetch abort. */
3140 case EXCP_PREFETCH_ABORT
:
3141 env
->cp15
.ifsr_el2
= env
->exception
.fsr
;
3142 env
->cp15
.far_el1
= deposit64(env
->cp15
.far_el1
, 32, 32,
3143 env
->exception
.vaddress
);
3144 qemu_log_mask(CPU_LOG_INT
, "...with IFSR 0x%x IFAR 0x%x\n",
3145 env
->cp15
.ifsr_el2
, (uint32_t)env
->exception
.vaddress
);
3146 new_mode
= ARM_CPU_MODE_ABT
;
3148 mask
= CPSR_A
| CPSR_I
;
3151 case EXCP_DATA_ABORT
:
3152 env
->cp15
.esr_el1
= env
->exception
.fsr
;
3153 env
->cp15
.far_el1
= deposit64(env
->cp15
.far_el1
, 0, 32,
3154 env
->exception
.vaddress
);
3155 qemu_log_mask(CPU_LOG_INT
, "...with DFSR 0x%x DFAR 0x%x\n",
3156 (uint32_t)env
->cp15
.esr_el1
,
3157 (uint32_t)env
->exception
.vaddress
);
3158 new_mode
= ARM_CPU_MODE_ABT
;
3160 mask
= CPSR_A
| CPSR_I
;
3164 new_mode
= ARM_CPU_MODE_IRQ
;
3166 /* Disable IRQ and imprecise data aborts. */
3167 mask
= CPSR_A
| CPSR_I
;
3171 new_mode
= ARM_CPU_MODE_FIQ
;
3173 /* Disable FIQ, IRQ and imprecise data aborts. */
3174 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
3178 cpu_abort(cs
, "Unhandled exception 0x%x\n", cs
->exception_index
);
3179 return; /* Never happens. Keep compiler happy. */
3182 if (env
->cp15
.c1_sys
& SCTLR_V
) {
3183 /* when enabled, base address cannot be remapped. */
3186 /* ARM v7 architectures provide a vector base address register to remap
3187 * the interrupt vector table.
3188 * This register is only followed in non-monitor mode, and has a secure
3189 * and un-secure copy. Since the cpu is always in a un-secure operation
3190 * and is never in monitor mode this feature is always active.
3191 * Note: only bits 31:5 are valid.
3193 addr
+= env
->cp15
.c12_vbar
;
3195 switch_mode (env
, new_mode
);
3196 env
->spsr
= cpsr_read(env
);
3197 /* Clear IT bits. */
3198 env
->condexec_bits
= 0;
3199 /* Switch to the new mode, and to the correct instruction set. */
3200 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
3202 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3203 * and we should just guard the thumb mode on V4 */
3204 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
3205 env
->thumb
= (env
->cp15
.c1_sys
& SCTLR_TE
) != 0;
3207 env
->regs
[14] = env
->regs
[15] + offset
;
3208 env
->regs
[15] = addr
;
3209 cs
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
3212 /* Check section/page access permissions.
3213 Returns the page protection flags, or zero if the access is not
3215 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
3216 int access_type
, int is_user
)
3220 if (domain_prot
== 3) {
3221 return PAGE_READ
| PAGE_WRITE
;
3224 if (access_type
== 1)
3227 prot_ro
= PAGE_READ
;
3231 if (arm_feature(env
, ARM_FEATURE_V7
)) {
3234 if (access_type
== 1)
3236 switch (env
->cp15
.c1_sys
& (SCTLR_S
| SCTLR_R
)) {
3238 return is_user
? 0 : PAGE_READ
;
3245 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
3250 return PAGE_READ
| PAGE_WRITE
;
3252 return PAGE_READ
| PAGE_WRITE
;
3253 case 4: /* Reserved. */
3256 return is_user
? 0 : prot_ro
;
3260 if (!arm_feature (env
, ARM_FEATURE_V6K
))
3268 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
3272 if (address
& env
->cp15
.c2_mask
)
3273 table
= env
->cp15
.ttbr1_el1
& 0xffffc000;
3275 table
= env
->cp15
.ttbr0_el1
& env
->cp15
.c2_base_mask
;
3277 table
|= (address
>> 18) & 0x3ffc;
3281 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
3282 int is_user
, hwaddr
*phys_ptr
,
3283 int *prot
, target_ulong
*page_size
)
3285 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3295 /* Pagetable walk. */
3296 /* Lookup l1 descriptor. */
3297 table
= get_level1_table_address(env
, address
);
3298 desc
= ldl_phys(cs
->as
, table
);
3300 domain
= (desc
>> 5) & 0x0f;
3301 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
3303 /* Section translation fault. */
3307 if (domain_prot
== 0 || domain_prot
== 2) {
3309 code
= 9; /* Section domain fault. */
3311 code
= 11; /* Page domain fault. */
3316 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
3317 ap
= (desc
>> 10) & 3;
3319 *page_size
= 1024 * 1024;
3321 /* Lookup l2 entry. */
3323 /* Coarse pagetable. */
3324 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
3326 /* Fine pagetable. */
3327 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
3329 desc
= ldl_phys(cs
->as
, table
);
3331 case 0: /* Page translation fault. */
3334 case 1: /* 64k page. */
3335 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
3336 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
3337 *page_size
= 0x10000;
3339 case 2: /* 4k page. */
3340 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3341 ap
= (desc
>> (4 + ((address
>> 9) & 6))) & 3;
3342 *page_size
= 0x1000;
3344 case 3: /* 1k page. */
3346 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
3347 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3349 /* Page translation fault. */
3354 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
3356 ap
= (desc
>> 4) & 3;
3360 /* Never happens, but compiler isn't smart enough to tell. */
3365 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
3367 /* Access permission fault. */
3371 *phys_ptr
= phys_addr
;
3374 return code
| (domain
<< 4);
3377 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
3378 int is_user
, hwaddr
*phys_ptr
,
3379 int *prot
, target_ulong
*page_size
)
3381 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3393 /* Pagetable walk. */
3394 /* Lookup l1 descriptor. */
3395 table
= get_level1_table_address(env
, address
);
3396 desc
= ldl_phys(cs
->as
, table
);
3398 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
3399 /* Section translation fault, or attempt to use the encoding
3400 * which is Reserved on implementations without PXN.
3405 if ((type
== 1) || !(desc
& (1 << 18))) {
3406 /* Page or Section. */
3407 domain
= (desc
>> 5) & 0x0f;
3409 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
3410 if (domain_prot
== 0 || domain_prot
== 2) {
3412 code
= 9; /* Section domain fault. */
3414 code
= 11; /* Page domain fault. */
3419 if (desc
& (1 << 18)) {
3421 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
3422 *page_size
= 0x1000000;
3425 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
3426 *page_size
= 0x100000;
3428 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
3429 xn
= desc
& (1 << 4);
3433 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
3434 pxn
= (desc
>> 2) & 1;
3436 /* Lookup l2 entry. */
3437 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
3438 desc
= ldl_phys(cs
->as
, table
);
3439 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
3441 case 0: /* Page translation fault. */
3444 case 1: /* 64k page. */
3445 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
3446 xn
= desc
& (1 << 15);
3447 *page_size
= 0x10000;
3449 case 2: case 3: /* 4k page. */
3450 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
3452 *page_size
= 0x1000;
3455 /* Never happens, but compiler isn't smart enough to tell. */
3460 if (domain_prot
== 3) {
3461 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3463 if (pxn
&& !is_user
) {
3466 if (xn
&& access_type
== 2)
3469 /* The simplified model uses AP[0] as an access control bit. */
3470 if ((env
->cp15
.c1_sys
& SCTLR_AFE
) && (ap
& 1) == 0) {
3471 /* Access flag fault. */
3472 code
= (code
== 15) ? 6 : 3;
3475 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
3477 /* Access permission fault. */
3484 *phys_ptr
= phys_addr
;
3487 return code
| (domain
<< 4);
3490 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3491 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3494 translation_fault
= 1,
3496 permission_fault
= 3,
3499 static int get_phys_addr_lpae(CPUARMState
*env
, target_ulong address
,
3500 int access_type
, int is_user
,
3501 hwaddr
*phys_ptr
, int *prot
,
3502 target_ulong
*page_size_ptr
)
3504 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
3505 /* Read an LPAE long-descriptor translation table. */
3506 MMUFaultType fault_type
= translation_fault
;
3513 hwaddr descaddr
, descmask
;
3514 uint32_t tableattrs
;
3515 target_ulong page_size
;
3517 int32_t granule_sz
= 9;
3518 int32_t va_size
= 32;
3521 if (arm_el_is_aa64(env
, 1)) {
3523 if (extract64(address
, 55, 1))
3524 tbi
= extract64(env
->cp15
.c2_control
, 38, 1);
3526 tbi
= extract64(env
->cp15
.c2_control
, 37, 1);
3530 /* Determine whether this address is in the region controlled by
3531 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3532 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3533 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3535 uint32_t t0sz
= extract32(env
->cp15
.c2_control
, 0, 6);
3536 if (arm_el_is_aa64(env
, 1)) {
3537 t0sz
= MIN(t0sz
, 39);
3538 t0sz
= MAX(t0sz
, 16);
3540 uint32_t t1sz
= extract32(env
->cp15
.c2_control
, 16, 6);
3541 if (arm_el_is_aa64(env
, 1)) {
3542 t1sz
= MIN(t1sz
, 39);
3543 t1sz
= MAX(t1sz
, 16);
3545 if (t0sz
&& !extract64(address
, va_size
- t0sz
, t0sz
- tbi
)) {
3546 /* there is a ttbr0 region and we are in it (high bits all zero) */
3548 } else if (t1sz
&& !extract64(~address
, va_size
- t1sz
, t1sz
- tbi
)) {
3549 /* there is a ttbr1 region and we are in it (high bits all one) */
3552 /* ttbr0 region is "everything not in the ttbr1 region" */
3555 /* ttbr1 region is "everything not in the ttbr0 region" */
3558 /* in the gap between the two regions, this is a Translation fault */
3559 fault_type
= translation_fault
;
3563 /* Note that QEMU ignores shareability and cacheability attributes,
3564 * so we don't need to do anything with the SH, ORGN, IRGN fields
3565 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
3566 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3567 * implement any ASID-like capability so we can ignore it (instead
3568 * we will always flush the TLB any time the ASID is changed).
3570 if (ttbr_select
== 0) {
3571 ttbr
= env
->cp15
.ttbr0_el1
;
3572 epd
= extract32(env
->cp15
.c2_control
, 7, 1);
3575 tg
= extract32(env
->cp15
.c2_control
, 14, 2);
3576 if (tg
== 1) { /* 64KB pages */
3579 if (tg
== 2) { /* 16KB pages */
3583 ttbr
= env
->cp15
.ttbr1_el1
;
3584 epd
= extract32(env
->cp15
.c2_control
, 23, 1);
3587 tg
= extract32(env
->cp15
.c2_control
, 30, 2);
3588 if (tg
== 3) { /* 64KB pages */
3591 if (tg
== 1) { /* 16KB pages */
3597 /* Translation table walk disabled => Translation fault on TLB miss */
3601 /* The starting level depends on the virtual address size which can be
3602 * up to 48-bits and the translation granule size.
3604 if ((va_size
- tsz
) > (granule_sz
* 4 + 3)) {
3606 } else if ((va_size
- tsz
) > (granule_sz
* 3 + 3)) {
3612 /* Clear the vaddr bits which aren't part of the within-region address,
3613 * so that we don't have to special case things when calculating the
3614 * first descriptor address.
3617 address
&= (1ULL << (va_size
- tsz
)) - 1;
3620 descmask
= (1ULL << (granule_sz
+ 3)) - 1;
3622 /* Now we can extract the actual base address from the TTBR */
3623 descaddr
= extract64(ttbr
, 0, 48);
3624 descaddr
&= ~((1ULL << (va_size
- tsz
- (granule_sz
* (4 - level
)))) - 1);
3628 uint64_t descriptor
;
3630 descaddr
|= (address
>> (granule_sz
* (4 - level
))) & descmask
;
3632 descriptor
= ldq_phys(cs
->as
, descaddr
);
3633 if (!(descriptor
& 1) ||
3634 (!(descriptor
& 2) && (level
== 3))) {
3635 /* Invalid, or the Reserved level 3 encoding */
3638 descaddr
= descriptor
& 0xfffffff000ULL
;
3640 if ((descriptor
& 2) && (level
< 3)) {
3641 /* Table entry. The top five bits are attributes which may
3642 * propagate down through lower levels of the table (and
3643 * which are all arranged so that 0 means "no effect", so
3644 * we can gather them up by ORing in the bits at each level).
3646 tableattrs
|= extract64(descriptor
, 59, 5);
3650 /* Block entry at level 1 or 2, or page entry at level 3.
3651 * These are basically the same thing, although the number
3652 * of bits we pull in from the vaddr varies.
3654 page_size
= (1 << ((granule_sz
* (4 - level
)) + 3));
3655 descaddr
|= (address
& (page_size
- 1));
3656 /* Extract attributes from the descriptor and merge with table attrs */
3657 if (arm_feature(env
, ARM_FEATURE_V8
)) {
3658 attrs
= extract64(descriptor
, 2, 10)
3659 | (extract64(descriptor
, 53, 11) << 10);
3661 attrs
= extract64(descriptor
, 2, 10)
3662 | (extract64(descriptor
, 52, 12) << 10);
3664 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
3665 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
3666 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3667 * means "force PL1 access only", which means forcing AP[1] to 0.
3669 if (extract32(tableattrs
, 2, 1)) {
3672 /* Since we're always in the Non-secure state, NSTable is ignored. */
3675 /* Here descaddr is the final physical address, and attributes
3678 fault_type
= access_fault
;
3679 if ((attrs
& (1 << 8)) == 0) {
3683 fault_type
= permission_fault
;
3684 if (is_user
&& !(attrs
& (1 << 4))) {
3685 /* Unprivileged access not enabled */
3688 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3689 if (attrs
& (1 << 12) || (!is_user
&& (attrs
& (1 << 11)))) {
3691 if (access_type
== 2) {
3694 *prot
&= ~PAGE_EXEC
;
3696 if (attrs
& (1 << 5)) {
3697 /* Write access forbidden */
3698 if (access_type
== 1) {
3701 *prot
&= ~PAGE_WRITE
;
3704 *phys_ptr
= descaddr
;
3705 *page_size_ptr
= page_size
;
3709 /* Long-descriptor format IFSR/DFSR value */
3710 return (1 << 9) | (fault_type
<< 2) | level
;
3713 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
3714 int access_type
, int is_user
,
3715 hwaddr
*phys_ptr
, int *prot
)
3721 *phys_ptr
= address
;
3722 for (n
= 7; n
>= 0; n
--) {
3723 base
= env
->cp15
.c6_region
[n
];
3724 if ((base
& 1) == 0)
3726 mask
= 1 << ((base
>> 1) & 0x1f);
3727 /* Keep this shift separate from the above to avoid an
3728 (undefined) << 32. */
3729 mask
= (mask
<< 1) - 1;
3730 if (((base
^ address
) & ~mask
) == 0)
3736 if (access_type
== 2) {
3737 mask
= env
->cp15
.pmsav5_insn_ap
;
3739 mask
= env
->cp15
.pmsav5_data_ap
;
3741 mask
= (mask
>> (n
* 4)) & 0xf;
3748 *prot
= PAGE_READ
| PAGE_WRITE
;
3753 *prot
|= PAGE_WRITE
;
3756 *prot
= PAGE_READ
| PAGE_WRITE
;
3767 /* Bad permission. */
3774 /* get_phys_addr - get the physical address for this virtual address
3776 * Find the physical address corresponding to the given virtual address,
3777 * by doing a translation table walk on MMU based systems or using the
3778 * MPU state on MPU based systems.
3780 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3781 * prot and page_size are not filled in, and the return value provides
3782 * information on why the translation aborted, in the format of a
3783 * DFSR/IFSR fault register, with the following caveats:
3784 * * we honour the short vs long DFSR format differences.
3785 * * the WnR bit is never set (the caller must do this).
3786 * * for MPU based systems we don't bother to return a full FSR format
3790 * @address: virtual address to get physical address for
3791 * @access_type: 0 for read, 1 for write, 2 for execute
3792 * @is_user: 0 for privileged access, 1 for user
3793 * @phys_ptr: set to the physical address corresponding to the virtual address
3794 * @prot: set to the permissions for the page containing phys_ptr
3795 * @page_size: set to the size of the page containing phys_ptr
3797 static inline int get_phys_addr(CPUARMState
*env
, target_ulong address
,
3798 int access_type
, int is_user
,
3799 hwaddr
*phys_ptr
, int *prot
,
3800 target_ulong
*page_size
)
3802 /* Fast Context Switch Extension. */
3803 if (address
< 0x02000000)
3804 address
+= env
->cp15
.c13_fcse
;
3806 if ((env
->cp15
.c1_sys
& SCTLR_M
) == 0) {
3807 /* MMU/MPU disabled. */
3808 *phys_ptr
= address
;
3809 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
3810 *page_size
= TARGET_PAGE_SIZE
;
3812 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
3813 *page_size
= TARGET_PAGE_SIZE
;
3814 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
3816 } else if (extended_addresses_enabled(env
)) {
3817 return get_phys_addr_lpae(env
, address
, access_type
, is_user
, phys_ptr
,
3819 } else if (env
->cp15
.c1_sys
& SCTLR_XP
) {
3820 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
3823 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
3828 int arm_cpu_handle_mmu_fault(CPUState
*cs
, vaddr address
,
3829 int access_type
, int mmu_idx
)
3831 ARMCPU
*cpu
= ARM_CPU(cs
);
3832 CPUARMState
*env
= &cpu
->env
;
3834 target_ulong page_size
;
3838 bool same_el
= (arm_current_pl(env
) != 0);
3840 is_user
= mmu_idx
== MMU_USER_IDX
;
3841 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
3844 /* Map a single [sub]page. */
3845 phys_addr
&= ~(hwaddr
)0x3ff;
3846 address
&= ~(target_ulong
)0x3ff;
3847 tlb_set_page(cs
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
3851 /* AArch64 syndrome does not have an LPAE bit */
3852 syn
= ret
& ~(1 << 9);
3854 /* For insn and data aborts we assume there is no instruction syndrome
3855 * information; this is always true for exceptions reported to EL1.
3857 if (access_type
== 2) {
3858 syn
= syn_insn_abort(same_el
, 0, 0, syn
);
3859 cs
->exception_index
= EXCP_PREFETCH_ABORT
;
3861 syn
= syn_data_abort(same_el
, 0, 0, 0, access_type
== 1, syn
);
3862 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
)) {
3865 cs
->exception_index
= EXCP_DATA_ABORT
;
3868 env
->exception
.syndrome
= syn
;
3869 env
->exception
.vaddress
= address
;
3870 env
->exception
.fsr
= ret
;
3874 hwaddr
arm_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
3876 ARMCPU
*cpu
= ARM_CPU(cs
);
3878 target_ulong page_size
;
3882 ret
= get_phys_addr(&cpu
->env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
3891 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
3893 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
3894 env
->regs
[13] = val
;
3896 env
->banked_r13
[bank_number(mode
)] = val
;
3900 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
3902 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
3903 return env
->regs
[13];
3905 return env
->banked_r13
[bank_number(mode
)];
3909 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
3911 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3915 return xpsr_read(env
) & 0xf8000000;
3917 return xpsr_read(env
) & 0xf80001ff;
3919 return xpsr_read(env
) & 0xff00fc00;
3921 return xpsr_read(env
) & 0xff00fdff;
3923 return xpsr_read(env
) & 0x000001ff;
3925 return xpsr_read(env
) & 0x0700fc00;
3927 return xpsr_read(env
) & 0x0700edff;
3929 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
3931 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
3932 case 16: /* PRIMASK */
3933 return (env
->daif
& PSTATE_I
) != 0;
3934 case 17: /* BASEPRI */
3935 case 18: /* BASEPRI_MAX */
3936 return env
->v7m
.basepri
;
3937 case 19: /* FAULTMASK */
3938 return (env
->daif
& PSTATE_F
) != 0;
3939 case 20: /* CONTROL */
3940 return env
->v7m
.control
;
3942 /* ??? For debugging only. */
3943 cpu_abort(CPU(cpu
), "Unimplemented system register read (%d)\n", reg
);
3948 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
3950 ARMCPU
*cpu
= arm_env_get_cpu(env
);
3954 xpsr_write(env
, val
, 0xf8000000);
3957 xpsr_write(env
, val
, 0xf8000000);
3960 xpsr_write(env
, val
, 0xfe00fc00);
3963 xpsr_write(env
, val
, 0xfe00fc00);
3966 /* IPSR bits are readonly. */
3969 xpsr_write(env
, val
, 0x0600fc00);
3972 xpsr_write(env
, val
, 0x0600fc00);
3975 if (env
->v7m
.current_sp
)
3976 env
->v7m
.other_sp
= val
;
3978 env
->regs
[13] = val
;
3981 if (env
->v7m
.current_sp
)
3982 env
->regs
[13] = val
;
3984 env
->v7m
.other_sp
= val
;
3986 case 16: /* PRIMASK */
3988 env
->daif
|= PSTATE_I
;
3990 env
->daif
&= ~PSTATE_I
;
3993 case 17: /* BASEPRI */
3994 env
->v7m
.basepri
= val
& 0xff;
3996 case 18: /* BASEPRI_MAX */
3998 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
3999 env
->v7m
.basepri
= val
;
4001 case 19: /* FAULTMASK */
4003 env
->daif
|= PSTATE_F
;
4005 env
->daif
&= ~PSTATE_F
;
4008 case 20: /* CONTROL */
4009 env
->v7m
.control
= val
& 3;
4010 switch_v7m_sp(env
, (val
& 2) != 0);
4013 /* ??? For debugging only. */
4014 cpu_abort(CPU(cpu
), "Unimplemented system register write (%d)\n", reg
);
4021 void HELPER(dc_zva
)(CPUARMState
*env
, uint64_t vaddr_in
)
4023 /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4024 * Note that we do not implement the (architecturally mandated)
4025 * alignment fault for attempts to use this on Device memory
4026 * (which matches the usual QEMU behaviour of not implementing either
4027 * alignment faults or any memory attribute handling).
4030 ARMCPU
*cpu
= arm_env_get_cpu(env
);
4031 uint64_t blocklen
= 4 << cpu
->dcz_blocksize
;
4032 uint64_t vaddr
= vaddr_in
& ~(blocklen
- 1);
4034 #ifndef CONFIG_USER_ONLY
4036 /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4037 * the block size so we might have to do more than one TLB lookup.
4038 * We know that in fact for any v8 CPU the page size is at least 4K
4039 * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4040 * 1K as an artefact of legacy v5 subpage support being present in the
4041 * same QEMU executable.
4043 int maxidx
= DIV_ROUND_UP(blocklen
, TARGET_PAGE_SIZE
);
4044 void *hostaddr
[maxidx
];
4047 for (try = 0; try < 2; try++) {
4049 for (i
= 0; i
< maxidx
; i
++) {
4050 hostaddr
[i
] = tlb_vaddr_to_host(env
,
4051 vaddr
+ TARGET_PAGE_SIZE
* i
,
4052 1, cpu_mmu_index(env
));
4058 /* If it's all in the TLB it's fair game for just writing to;
4059 * we know we don't need to update dirty status, etc.
4061 for (i
= 0; i
< maxidx
- 1; i
++) {
4062 memset(hostaddr
[i
], 0, TARGET_PAGE_SIZE
);
4064 memset(hostaddr
[i
], 0, blocklen
- (i
* TARGET_PAGE_SIZE
));
4067 /* OK, try a store and see if we can populate the tlb. This
4068 * might cause an exception if the memory isn't writable,
4069 * in which case we will longjmp out of here. We must for
4070 * this purpose use the actual register value passed to us
4071 * so that we get the fault address right.
4073 helper_ret_stb_mmu(env
, vaddr_in
, 0, cpu_mmu_index(env
), GETRA());
4074 /* Now we can populate the other TLB entries, if any */
4075 for (i
= 0; i
< maxidx
; i
++) {
4076 uint64_t va
= vaddr
+ TARGET_PAGE_SIZE
* i
;
4077 if (va
!= (vaddr_in
& TARGET_PAGE_MASK
)) {
4078 helper_ret_stb_mmu(env
, va
, 0, cpu_mmu_index(env
), GETRA());
4083 /* Slow path (probably attempt to do this to an I/O device or
4084 * similar, or clearing of a block of code we have translations
4085 * cached for). Just do a series of byte writes as the architecture
4086 * demands. It's not worth trying to use a cpu_physical_memory_map(),
4087 * memset(), unmap() sequence here because:
4088 * + we'd need to account for the blocksize being larger than a page
4089 * + the direct-RAM access case is almost always going to be dealt
4090 * with in the fastpath code above, so there's no speed benefit
4091 * + we would have to deal with the map returning NULL because the
4092 * bounce buffer was in use
4094 for (i
= 0; i
< blocklen
; i
++) {
4095 helper_ret_stb_mmu(env
, vaddr
+ i
, 0, cpu_mmu_index(env
), GETRA());
4099 memset(g2h(vaddr
), 0, blocklen
);
4103 /* Note that signed overflow is undefined in C. The following routines are
4104 careful to use unsigned types where modulo arithmetic is required.
4105 Failure to do so _will_ break on newer gcc. */
4107 /* Signed saturating arithmetic. */
4109 /* Perform 16-bit signed saturating addition. */
4110 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
4115 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
4124 /* Perform 8-bit signed saturating addition. */
4125 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
4130 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
4139 /* Perform 16-bit signed saturating subtraction. */
4140 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
4145 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
4154 /* Perform 8-bit signed saturating subtraction. */
4155 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
4160 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
4169 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4170 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4171 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
4172 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
4175 #include "op_addsub.h"
4177 /* Unsigned saturating arithmetic. */
4178 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
4187 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
4195 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
4204 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
4212 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4213 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4214 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
4215 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
4218 #include "op_addsub.h"
4220 /* Signed modulo arithmetic. */
4221 #define SARITH16(a, b, n, op) do { \
4223 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4224 RESULT(sum, n, 16); \
4226 ge |= 3 << (n * 2); \
4229 #define SARITH8(a, b, n, op) do { \
4231 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4232 RESULT(sum, n, 8); \
4238 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4239 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4240 #define ADD8(a, b, n) SARITH8(a, b, n, +)
4241 #define SUB8(a, b, n) SARITH8(a, b, n, -)
4245 #include "op_addsub.h"
4247 /* Unsigned modulo arithmetic. */
4248 #define ADD16(a, b, n) do { \
4250 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4251 RESULT(sum, n, 16); \
4252 if ((sum >> 16) == 1) \
4253 ge |= 3 << (n * 2); \
4256 #define ADD8(a, b, n) do { \
4258 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4259 RESULT(sum, n, 8); \
4260 if ((sum >> 8) == 1) \
4264 #define SUB16(a, b, n) do { \
4266 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4267 RESULT(sum, n, 16); \
4268 if ((sum >> 16) == 0) \
4269 ge |= 3 << (n * 2); \
4272 #define SUB8(a, b, n) do { \
4274 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4275 RESULT(sum, n, 8); \
4276 if ((sum >> 8) == 0) \
4283 #include "op_addsub.h"
4285 /* Halved signed arithmetic. */
4286 #define ADD16(a, b, n) \
4287 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4288 #define SUB16(a, b, n) \
4289 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4290 #define ADD8(a, b, n) \
4291 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4292 #define SUB8(a, b, n) \
4293 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4296 #include "op_addsub.h"
4298 /* Halved unsigned arithmetic. */
4299 #define ADD16(a, b, n) \
4300 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4301 #define SUB16(a, b, n) \
4302 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4303 #define ADD8(a, b, n) \
4304 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4305 #define SUB8(a, b, n) \
4306 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4309 #include "op_addsub.h"
4311 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
4319 /* Unsigned sum of absolute byte differences. */
4320 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
4323 sum
= do_usad(a
, b
);
4324 sum
+= do_usad(a
>> 8, b
>> 8);
4325 sum
+= do_usad(a
>> 16, b
>>16);
4326 sum
+= do_usad(a
>> 24, b
>> 24);
4330 /* For ARMv6 SEL instruction. */
4331 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
4344 return (a
& mask
) | (b
& ~mask
);
4347 /* VFP support. We follow the convention used for VFP instructions:
4348 Single precision routines have a "s" suffix, double precision a
4351 /* Convert host exception flags to vfp form. */
4352 static inline int vfp_exceptbits_from_host(int host_bits
)
4354 int target_bits
= 0;
4356 if (host_bits
& float_flag_invalid
)
4358 if (host_bits
& float_flag_divbyzero
)
4360 if (host_bits
& float_flag_overflow
)
4362 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
4364 if (host_bits
& float_flag_inexact
)
4365 target_bits
|= 0x10;
4366 if (host_bits
& float_flag_input_denormal
)
4367 target_bits
|= 0x80;
4371 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
4376 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
4377 | (env
->vfp
.vec_len
<< 16)
4378 | (env
->vfp
.vec_stride
<< 20);
4379 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
4380 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
4381 fpscr
|= vfp_exceptbits_from_host(i
);
4385 uint32_t vfp_get_fpscr(CPUARMState
*env
)
4387 return HELPER(vfp_get_fpscr
)(env
);
4390 /* Convert vfp exception flags to target form. */
4391 static inline int vfp_exceptbits_to_host(int target_bits
)
4395 if (target_bits
& 1)
4396 host_bits
|= float_flag_invalid
;
4397 if (target_bits
& 2)
4398 host_bits
|= float_flag_divbyzero
;
4399 if (target_bits
& 4)
4400 host_bits
|= float_flag_overflow
;
4401 if (target_bits
& 8)
4402 host_bits
|= float_flag_underflow
;
4403 if (target_bits
& 0x10)
4404 host_bits
|= float_flag_inexact
;
4405 if (target_bits
& 0x80)
4406 host_bits
|= float_flag_input_denormal
;
4410 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
4415 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
4416 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
4417 env
->vfp
.vec_len
= (val
>> 16) & 7;
4418 env
->vfp
.vec_stride
= (val
>> 20) & 3;
4421 if (changed
& (3 << 22)) {
4422 i
= (val
>> 22) & 3;
4424 case FPROUNDING_TIEEVEN
:
4425 i
= float_round_nearest_even
;
4427 case FPROUNDING_POSINF
:
4430 case FPROUNDING_NEGINF
:
4431 i
= float_round_down
;
4433 case FPROUNDING_ZERO
:
4434 i
= float_round_to_zero
;
4437 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
4439 if (changed
& (1 << 24)) {
4440 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
4441 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
4443 if (changed
& (1 << 25))
4444 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
4446 i
= vfp_exceptbits_to_host(val
);
4447 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
4448 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
4451 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
4453 HELPER(vfp_set_fpscr
)(env
, val
);
4456 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4458 #define VFP_BINOP(name) \
4459 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4461 float_status *fpst = fpstp; \
4462 return float32_ ## name(a, b, fpst); \
4464 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4466 float_status *fpst = fpstp; \
4467 return float64_ ## name(a, b, fpst); \
4479 float32
VFP_HELPER(neg
, s
)(float32 a
)
4481 return float32_chs(a
);
4484 float64
VFP_HELPER(neg
, d
)(float64 a
)
4486 return float64_chs(a
);
4489 float32
VFP_HELPER(abs
, s
)(float32 a
)
4491 return float32_abs(a
);
4494 float64
VFP_HELPER(abs
, d
)(float64 a
)
4496 return float64_abs(a
);
4499 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
4501 return float32_sqrt(a
, &env
->vfp
.fp_status
);
4504 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
4506 return float64_sqrt(a
, &env
->vfp
.fp_status
);
4509 /* XXX: check quiet/signaling case */
4510 #define DO_VFP_cmp(p, type) \
4511 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4514 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4515 case 0: flags = 0x6; break; \
4516 case -1: flags = 0x8; break; \
4517 case 1: flags = 0x2; break; \
4518 default: case 2: flags = 0x3; break; \
4520 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4521 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4523 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4526 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4527 case 0: flags = 0x6; break; \
4528 case -1: flags = 0x8; break; \
4529 case 1: flags = 0x2; break; \
4530 default: case 2: flags = 0x3; break; \
4532 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4533 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4535 DO_VFP_cmp(s
, float32
)
4536 DO_VFP_cmp(d
, float64
)
4539 /* Integer to float and float to integer conversions */
4541 #define CONV_ITOF(name, fsz, sign) \
4542 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4544 float_status *fpst = fpstp; \
4545 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4548 #define CONV_FTOI(name, fsz, sign, round) \
4549 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4551 float_status *fpst = fpstp; \
4552 if (float##fsz##_is_any_nan(x)) { \
4553 float_raise(float_flag_invalid, fpst); \
4556 return float##fsz##_to_##sign##int32##round(x, fpst); \
4559 #define FLOAT_CONVS(name, p, fsz, sign) \
4560 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4561 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4562 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4564 FLOAT_CONVS(si
, s
, 32, )
4565 FLOAT_CONVS(si
, d
, 64, )
4566 FLOAT_CONVS(ui
, s
, 32, u
)
4567 FLOAT_CONVS(ui
, d
, 64, u
)
4573 /* floating point conversion */
4574 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
4576 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
4577 /* ARM requires that S<->D conversion of any kind of NaN generates
4578 * a quiet NaN by forcing the most significant frac bit to 1.
4580 return float64_maybe_silence_nan(r
);
4583 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
4585 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
4586 /* ARM requires that S<->D conversion of any kind of NaN generates
4587 * a quiet NaN by forcing the most significant frac bit to 1.
4589 return float32_maybe_silence_nan(r
);
4592 /* VFP3 fixed point conversion. */
4593 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4594 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
4597 float_status *fpst = fpstp; \
4599 tmp = itype##_to_##float##fsz(x, fpst); \
4600 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4603 /* Notice that we want only input-denormal exception flags from the
4604 * scalbn operation: the other possible flags (overflow+inexact if
4605 * we overflow to infinity, output-denormal) aren't correct for the
4606 * complete scale-and-convert operation.
4608 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4609 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4613 float_status *fpst = fpstp; \
4614 int old_exc_flags = get_float_exception_flags(fpst); \
4616 if (float##fsz##_is_any_nan(x)) { \
4617 float_raise(float_flag_invalid, fpst); \
4620 tmp = float##fsz##_scalbn(x, shift, fpst); \
4621 old_exc_flags |= get_float_exception_flags(fpst) \
4622 & float_flag_input_denormal; \
4623 set_float_exception_flags(old_exc_flags, fpst); \
4624 return float##fsz##_to_##itype##round(tmp, fpst); \
4627 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
4628 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4629 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4630 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4632 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
4633 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4634 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4636 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
4637 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
4638 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
4639 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
4640 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
4641 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
4642 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
4643 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
4644 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
4645 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
4646 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
4647 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
4649 #undef VFP_CONV_FIX_FLOAT
4650 #undef VFP_CONV_FLOAT_FIX_ROUND
4652 /* Set the current fp rounding mode and return the old one.
4653 * The argument is a softfloat float_round_ value.
4655 uint32_t HELPER(set_rmode
)(uint32_t rmode
, CPUARMState
*env
)
4657 float_status
*fp_status
= &env
->vfp
.fp_status
;
4659 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
4660 set_float_rounding_mode(rmode
, fp_status
);
4665 /* Set the current fp rounding mode in the standard fp status and return
4666 * the old one. This is for NEON instructions that need to change the
4667 * rounding mode but wish to use the standard FPSCR values for everything
4668 * else. Always set the rounding mode back to the correct value after
4670 * The argument is a softfloat float_round_ value.
4672 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
4674 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
4676 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
4677 set_float_rounding_mode(rmode
, fp_status
);
4682 /* Half precision conversions. */
4683 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
4685 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
4686 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
4688 return float32_maybe_silence_nan(r
);
4693 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
4695 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
4696 float16 r
= float32_to_float16(a
, ieee
, s
);
4698 r
= float16_maybe_silence_nan(r
);
4700 return float16_val(r
);
4703 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
4705 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
4708 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
4710 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
4713 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
4715 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
4718 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
4720 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
4723 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, CPUARMState
*env
)
4725 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
4726 float64 r
= float16_to_float64(make_float16(a
), ieee
, &env
->vfp
.fp_status
);
4728 return float64_maybe_silence_nan(r
);
4733 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, CPUARMState
*env
)
4735 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
4736 float16 r
= float64_to_float16(a
, ieee
, &env
->vfp
.fp_status
);
4738 r
= float16_maybe_silence_nan(r
);
4740 return float16_val(r
);
4743 #define float32_two make_float32(0x40000000)
4744 #define float32_three make_float32(0x40400000)
4745 #define float32_one_point_five make_float32(0x3fc00000)
4747 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
4749 float_status
*s
= &env
->vfp
.standard_fp_status
;
4750 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
4751 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
4752 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
4753 float_raise(float_flag_input_denormal
, s
);
4757 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
4760 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
4762 float_status
*s
= &env
->vfp
.standard_fp_status
;
4764 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
4765 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
4766 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
4767 float_raise(float_flag_input_denormal
, s
);
4769 return float32_one_point_five
;
4771 product
= float32_mul(a
, b
, s
);
4772 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
4777 /* Constants 256 and 512 are used in some helpers; we avoid relying on
4778 * int->float conversions at run-time. */
4779 #define float64_256 make_float64(0x4070000000000000LL)
4780 #define float64_512 make_float64(0x4080000000000000LL)
4781 #define float32_maxnorm make_float32(0x7f7fffff)
4782 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
4784 /* Reciprocal functions
4786 * The algorithm that must be used to calculate the estimate
4787 * is specified by the ARM ARM, see FPRecipEstimate()
4790 static float64
recip_estimate(float64 a
, float_status
*real_fp_status
)
4792 /* These calculations mustn't set any fp exception flags,
4793 * so we use a local copy of the fp_status.
4795 float_status dummy_status
= *real_fp_status
;
4796 float_status
*s
= &dummy_status
;
4797 /* q = (int)(a * 512.0) */
4798 float64 q
= float64_mul(float64_512
, a
, s
);
4799 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
4801 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4802 q
= int64_to_float64(q_int
, s
);
4803 q
= float64_add(q
, float64_half
, s
);
4804 q
= float64_div(q
, float64_512
, s
);
4805 q
= float64_div(float64_one
, q
, s
);
4807 /* s = (int)(256.0 * r + 0.5) */
4808 q
= float64_mul(q
, float64_256
, s
);
4809 q
= float64_add(q
, float64_half
, s
);
4810 q_int
= float64_to_int64_round_to_zero(q
, s
);
4812 /* return (double)s / 256.0 */
4813 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
4816 /* Common wrapper to call recip_estimate */
4817 static float64
call_recip_estimate(float64 num
, int off
, float_status
*fpst
)
4819 uint64_t val64
= float64_val(num
);
4820 uint64_t frac
= extract64(val64
, 0, 52);
4821 int64_t exp
= extract64(val64
, 52, 11);
4823 float64 scaled
, estimate
;
4825 /* Generate the scaled number for the estimate function */
4827 if (extract64(frac
, 51, 1) == 0) {
4829 frac
= extract64(frac
, 0, 50) << 2;
4831 frac
= extract64(frac
, 0, 51) << 1;
4835 /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
4836 scaled
= make_float64((0x3feULL
<< 52)
4837 | extract64(frac
, 44, 8) << 44);
4839 estimate
= recip_estimate(scaled
, fpst
);
4841 /* Build new result */
4842 val64
= float64_val(estimate
);
4843 sbit
= 0x8000000000000000ULL
& val64
;
4845 frac
= extract64(val64
, 0, 52);
4848 frac
= 1ULL << 51 | extract64(frac
, 1, 51);
4849 } else if (exp
== -1) {
4850 frac
= 1ULL << 50 | extract64(frac
, 2, 50);
4854 return make_float64(sbit
| (exp
<< 52) | frac
);
4857 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
4859 switch (fpst
->float_rounding_mode
) {
4860 case float_round_nearest_even
: /* Round to Nearest */
4862 case float_round_up
: /* Round to +Inf */
4864 case float_round_down
: /* Round to -Inf */
4866 case float_round_to_zero
: /* Round to Zero */
4870 g_assert_not_reached();
4873 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
4875 float_status
*fpst
= fpstp
;
4876 float32 f32
= float32_squash_input_denormal(input
, fpst
);
4877 uint32_t f32_val
= float32_val(f32
);
4878 uint32_t f32_sbit
= 0x80000000ULL
& f32_val
;
4879 int32_t f32_exp
= extract32(f32_val
, 23, 8);
4880 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
4886 if (float32_is_any_nan(f32
)) {
4888 if (float32_is_signaling_nan(f32
)) {
4889 float_raise(float_flag_invalid
, fpst
);
4890 nan
= float32_maybe_silence_nan(f32
);
4892 if (fpst
->default_nan_mode
) {
4893 nan
= float32_default_nan
;
4896 } else if (float32_is_infinity(f32
)) {
4897 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
4898 } else if (float32_is_zero(f32
)) {
4899 float_raise(float_flag_divbyzero
, fpst
);
4900 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
4901 } else if ((f32_val
& ~(1ULL << 31)) < (1ULL << 21)) {
4902 /* Abs(value) < 2.0^-128 */
4903 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
4904 if (round_to_inf(fpst
, f32_sbit
)) {
4905 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
4907 return float32_set_sign(float32_maxnorm
, float32_is_neg(f32
));
4909 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
4910 float_raise(float_flag_underflow
, fpst
);
4911 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
4915 f64
= make_float64(((int64_t)(f32_exp
) << 52) | (int64_t)(f32_frac
) << 29);
4916 r64
= call_recip_estimate(f64
, 253, fpst
);
4917 r64_val
= float64_val(r64
);
4918 r64_exp
= extract64(r64_val
, 52, 11);
4919 r64_frac
= extract64(r64_val
, 0, 52);
4921 /* result = sign : result_exp<7:0> : fraction<51:29>; */
4922 return make_float32(f32_sbit
|
4923 (r64_exp
& 0xff) << 23 |
4924 extract64(r64_frac
, 29, 24));
4927 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
4929 float_status
*fpst
= fpstp
;
4930 float64 f64
= float64_squash_input_denormal(input
, fpst
);
4931 uint64_t f64_val
= float64_val(f64
);
4932 uint64_t f64_sbit
= 0x8000000000000000ULL
& f64_val
;
4933 int64_t f64_exp
= extract64(f64_val
, 52, 11);
4939 /* Deal with any special cases */
4940 if (float64_is_any_nan(f64
)) {
4942 if (float64_is_signaling_nan(f64
)) {
4943 float_raise(float_flag_invalid
, fpst
);
4944 nan
= float64_maybe_silence_nan(f64
);
4946 if (fpst
->default_nan_mode
) {
4947 nan
= float64_default_nan
;
4950 } else if (float64_is_infinity(f64
)) {
4951 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
4952 } else if (float64_is_zero(f64
)) {
4953 float_raise(float_flag_divbyzero
, fpst
);
4954 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
4955 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
4956 /* Abs(value) < 2.0^-1024 */
4957 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
4958 if (round_to_inf(fpst
, f64_sbit
)) {
4959 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
4961 return float64_set_sign(float64_maxnorm
, float64_is_neg(f64
));
4963 } else if (f64_exp
>= 1023 && fpst
->flush_to_zero
) {
4964 float_raise(float_flag_underflow
, fpst
);
4965 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
4968 r64
= call_recip_estimate(f64
, 2045, fpst
);
4969 r64_val
= float64_val(r64
);
4970 r64_exp
= extract64(r64_val
, 52, 11);
4971 r64_frac
= extract64(r64_val
, 0, 52);
4973 /* result = sign : result_exp<10:0> : fraction<51:0> */
4974 return make_float64(f64_sbit
|
4975 ((r64_exp
& 0x7ff) << 52) |
4979 /* The algorithm that must be used to calculate the estimate
4980 * is specified by the ARM ARM.
4982 static float64
recip_sqrt_estimate(float64 a
, float_status
*real_fp_status
)
4984 /* These calculations mustn't set any fp exception flags,
4985 * so we use a local copy of the fp_status.
4987 float_status dummy_status
= *real_fp_status
;
4988 float_status
*s
= &dummy_status
;
4992 if (float64_lt(a
, float64_half
, s
)) {
4993 /* range 0.25 <= a < 0.5 */
4995 /* a in units of 1/512 rounded down */
4996 /* q0 = (int)(a * 512.0); */
4997 q
= float64_mul(float64_512
, a
, s
);
4998 q_int
= float64_to_int64_round_to_zero(q
, s
);
5000 /* reciprocal root r */
5001 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
5002 q
= int64_to_float64(q_int
, s
);
5003 q
= float64_add(q
, float64_half
, s
);
5004 q
= float64_div(q
, float64_512
, s
);
5005 q
= float64_sqrt(q
, s
);
5006 q
= float64_div(float64_one
, q
, s
);
5008 /* range 0.5 <= a < 1.0 */
5010 /* a in units of 1/256 rounded down */
5011 /* q1 = (int)(a * 256.0); */
5012 q
= float64_mul(float64_256
, a
, s
);
5013 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
5015 /* reciprocal root r */
5016 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5017 q
= int64_to_float64(q_int
, s
);
5018 q
= float64_add(q
, float64_half
, s
);
5019 q
= float64_div(q
, float64_256
, s
);
5020 q
= float64_sqrt(q
, s
);
5021 q
= float64_div(float64_one
, q
, s
);
5023 /* r in units of 1/256 rounded to nearest */
5024 /* s = (int)(256.0 * r + 0.5); */
5026 q
= float64_mul(q
, float64_256
,s
);
5027 q
= float64_add(q
, float64_half
, s
);
5028 q_int
= float64_to_int64_round_to_zero(q
, s
);
5030 /* return (double)s / 256.0;*/
5031 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
5034 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
5036 float_status
*s
= fpstp
;
5037 float32 f32
= float32_squash_input_denormal(input
, s
);
5038 uint32_t val
= float32_val(f32
);
5039 uint32_t f32_sbit
= 0x80000000 & val
;
5040 int32_t f32_exp
= extract32(val
, 23, 8);
5041 uint32_t f32_frac
= extract32(val
, 0, 23);
5047 if (float32_is_any_nan(f32
)) {
5049 if (float32_is_signaling_nan(f32
)) {
5050 float_raise(float_flag_invalid
, s
);
5051 nan
= float32_maybe_silence_nan(f32
);
5053 if (s
->default_nan_mode
) {
5054 nan
= float32_default_nan
;
5057 } else if (float32_is_zero(f32
)) {
5058 float_raise(float_flag_divbyzero
, s
);
5059 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
5060 } else if (float32_is_neg(f32
)) {
5061 float_raise(float_flag_invalid
, s
);
5062 return float32_default_nan
;
5063 } else if (float32_is_infinity(f32
)) {
5064 return float32_zero
;
5067 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5068 * preserving the parity of the exponent. */
5070 f64_frac
= ((uint64_t) f32_frac
) << 29;
5072 while (extract64(f64_frac
, 51, 1) == 0) {
5073 f64_frac
= f64_frac
<< 1;
5074 f32_exp
= f32_exp
-1;
5076 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
5079 if (extract64(f32_exp
, 0, 1) == 0) {
5080 f64
= make_float64(((uint64_t) f32_sbit
) << 32
5084 f64
= make_float64(((uint64_t) f32_sbit
) << 32
5089 result_exp
= (380 - f32_exp
) / 2;
5091 f64
= recip_sqrt_estimate(f64
, s
);
5093 val64
= float64_val(f64
);
5095 val
= ((result_exp
& 0xff) << 23)
5096 | ((val64
>> 29) & 0x7fffff);
5097 return make_float32(val
);
5100 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
5102 float_status
*s
= fpstp
;
5103 float64 f64
= float64_squash_input_denormal(input
, s
);
5104 uint64_t val
= float64_val(f64
);
5105 uint64_t f64_sbit
= 0x8000000000000000ULL
& val
;
5106 int64_t f64_exp
= extract64(val
, 52, 11);
5107 uint64_t f64_frac
= extract64(val
, 0, 52);
5109 uint64_t result_frac
;
5111 if (float64_is_any_nan(f64
)) {
5113 if (float64_is_signaling_nan(f64
)) {
5114 float_raise(float_flag_invalid
, s
);
5115 nan
= float64_maybe_silence_nan(f64
);
5117 if (s
->default_nan_mode
) {
5118 nan
= float64_default_nan
;
5121 } else if (float64_is_zero(f64
)) {
5122 float_raise(float_flag_divbyzero
, s
);
5123 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
5124 } else if (float64_is_neg(f64
)) {
5125 float_raise(float_flag_invalid
, s
);
5126 return float64_default_nan
;
5127 } else if (float64_is_infinity(f64
)) {
5128 return float64_zero
;
5131 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5132 * preserving the parity of the exponent. */
5135 while (extract64(f64_frac
, 51, 1) == 0) {
5136 f64_frac
= f64_frac
<< 1;
5137 f64_exp
= f64_exp
- 1;
5139 f64_frac
= extract64(f64_frac
, 0, 51) << 1;
5142 if (extract64(f64_exp
, 0, 1) == 0) {
5143 f64
= make_float64(f64_sbit
5147 f64
= make_float64(f64_sbit
5152 result_exp
= (3068 - f64_exp
) / 2;
5154 f64
= recip_sqrt_estimate(f64
, s
);
5156 result_frac
= extract64(float64_val(f64
), 0, 52);
5158 return make_float64(f64_sbit
|
5159 ((result_exp
& 0x7ff) << 52) |
5163 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
5165 float_status
*s
= fpstp
;
5168 if ((a
& 0x80000000) == 0) {
5172 f64
= make_float64((0x3feULL
<< 52)
5173 | ((int64_t)(a
& 0x7fffffff) << 21));
5175 f64
= recip_estimate(f64
, s
);
5177 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
5180 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
5182 float_status
*fpst
= fpstp
;
5185 if ((a
& 0xc0000000) == 0) {
5189 if (a
& 0x80000000) {
5190 f64
= make_float64((0x3feULL
<< 52)
5191 | ((uint64_t)(a
& 0x7fffffff) << 21));
5192 } else { /* bits 31-30 == '01' */
5193 f64
= make_float64((0x3fdULL
<< 52)
5194 | ((uint64_t)(a
& 0x3fffffff) << 22));
5197 f64
= recip_sqrt_estimate(f64
, fpst
);
5199 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
5202 /* VFPv4 fused multiply-accumulate */
5203 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
5205 float_status
*fpst
= fpstp
;
5206 return float32_muladd(a
, b
, c
, 0, fpst
);
5209 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
5211 float_status
*fpst
= fpstp
;
5212 return float64_muladd(a
, b
, c
, 0, fpst
);
5215 /* ARMv8 round to integral */
5216 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
5218 return float32_round_to_int(x
, fp_status
);
5221 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
5223 return float64_round_to_int(x
, fp_status
);
5226 float32
HELPER(rints
)(float32 x
, void *fp_status
)
5228 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
5231 ret
= float32_round_to_int(x
, fp_status
);
5233 /* Suppress any inexact exceptions the conversion produced */
5234 if (!(old_flags
& float_flag_inexact
)) {
5235 new_flags
= get_float_exception_flags(fp_status
);
5236 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
5242 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
5244 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
5247 ret
= float64_round_to_int(x
, fp_status
);
5249 new_flags
= get_float_exception_flags(fp_status
);
5251 /* Suppress any inexact exceptions the conversion produced */
5252 if (!(old_flags
& float_flag_inexact
)) {
5253 new_flags
= get_float_exception_flags(fp_status
);
5254 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
5260 /* Convert ARM rounding mode to softfloat */
5261 int arm_rmode_to_sf(int rmode
)
5264 case FPROUNDING_TIEAWAY
:
5265 rmode
= float_round_ties_away
;
5267 case FPROUNDING_ODD
:
5268 /* FIXME: add support for TIEAWAY and ODD */
5269 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
5271 case FPROUNDING_TIEEVEN
:
5273 rmode
= float_round_nearest_even
;
5275 case FPROUNDING_POSINF
:
5276 rmode
= float_round_up
;
5278 case FPROUNDING_NEGINF
:
5279 rmode
= float_round_down
;
5281 case FPROUNDING_ZERO
:
5282 rmode
= float_round_to_zero
;
5288 static void crc_init_buffer(uint8_t *buf
, uint32_t val
, uint32_t bytes
)
5293 buf
[0] = val
& 0xff;
5294 } else if (bytes
== 2) {
5295 buf
[0] = val
& 0xff;
5296 buf
[1] = (val
>> 8) & 0xff;
5298 buf
[0] = val
& 0xff;
5299 buf
[1] = (val
>> 8) & 0xff;
5300 buf
[2] = (val
>> 16) & 0xff;
5301 buf
[3] = (val
>> 24) & 0xff;
5305 uint32_t HELPER(crc32
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
5309 crc_init_buffer(buf
, val
, bytes
);
5311 /* zlib crc32 converts the accumulator and output to one's complement. */
5312 return crc32(acc
^ 0xffffffff, buf
, bytes
) ^ 0xffffffff;
5315 uint32_t HELPER(crc32c
)(uint32_t acc
, uint32_t val
, uint32_t bytes
)
5319 crc_init_buffer(buf
, val
, bytes
);
5321 /* Linux crc32c converts the output to one's complement. */
5322 return crc32c(acc
, buf
, bytes
) ^ 0xffffffff;