?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
block: Forbid bdrv_set_aio_context outside BQL
[qemu.git] / target-ppc / translate.c
blob88c18e37b3de3220b135620954c3ed8c576ac8e2
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25 #include "exec/cpu_ldst.h"
26
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29
30 #include "trace-tcg.h"
31
32
33 #define CPU_SINGLE_STEP 0x1
34 #define CPU_BRANCH_STEP 0x2
35 #define GDBSTUB_SINGLE_STEP 0x4
36
37 /* Include definitions for instructions classes and implementations flags */
38 //#define PPC_DEBUG_DISAS
39 //#define DO_PPC_STATISTICS
40
41 #ifdef PPC_DEBUG_DISAS
42 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
43 #else
44 # define LOG_DISAS(...) do { } while (0)
45 #endif
46 /*****************************************************************************/
47 /* Code translation helpers */
48
49 /* global register indexes */
50 static TCGv_ptr cpu_env;
51 static char cpu_reg_names[10*3 + 22*4 /* GPR */
52 + 10*4 + 22*5 /* SPE GPRh */
53 + 10*4 + 22*5 /* FPR */
54 + 2*(10*6 + 22*7) /* AVRh, AVRl */
55 + 10*5 + 22*6 /* VSR */
56 + 8*5 /* CRF */];
57 static TCGv cpu_gpr[32];
58 static TCGv cpu_gprh[32];
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i64 cpu_vsr[32];
62 static TCGv_i32 cpu_crf[8];
63 static TCGv cpu_nip;
64 static TCGv cpu_msr;
65 static TCGv cpu_ctr;
66 static TCGv cpu_lr;
67 #if defined(TARGET_PPC64)
68 static TCGv cpu_cfar;
69 #endif
70 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
71 static TCGv cpu_reserve;
72 static TCGv cpu_fpscr;
73 static TCGv_i32 cpu_access_type;
74
75 #include "exec/gen-icount.h"
76
77 void ppc_translate_init(void)
78 {
79 int i;
80 char* p;
81 size_t cpu_reg_names_size;
82 static int done_init = 0;
83
84 if (done_init)
85 return;
86
87 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
88
89 p = cpu_reg_names;
90 cpu_reg_names_size = sizeof(cpu_reg_names);
91
92 for (i = 0; i < 8; i++) {
93 snprintf(p, cpu_reg_names_size, "crf%d", i);
94 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
95 offsetof(CPUPPCState, crf[i]), p);
96 p += 5;
97 cpu_reg_names_size -= 5;
98 }
99
100 for (i = 0; i < 32; i++) {
101 snprintf(p, cpu_reg_names_size, "r%d", i);
102 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUPPCState, gpr[i]), p);
104 p += (i < 10) ? 3 : 4;
105 cpu_reg_names_size -= (i < 10) ? 3 : 4;
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111
112 snprintf(p, cpu_reg_names_size, "fp%d", i);
113 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
114 offsetof(CPUPPCState, fpr[i]), p);
115 p += (i < 10) ? 4 : 5;
116 cpu_reg_names_size -= (i < 10) ? 4 : 5;
117
118 snprintf(p, cpu_reg_names_size, "avr%dH", i);
119 #ifdef HOST_WORDS_BIGENDIAN
120 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
121 offsetof(CPUPPCState, avr[i].u64[0]), p);
122 #else
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[1]), p);
125 #endif
126 p += (i < 10) ? 6 : 7;
127 cpu_reg_names_size -= (i < 10) ? 6 : 7;
128
129 snprintf(p, cpu_reg_names_size, "avr%dL", i);
130 #ifdef HOST_WORDS_BIGENDIAN
131 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
132 offsetof(CPUPPCState, avr[i].u64[1]), p);
133 #else
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[0]), p);
136 #endif
137 p += (i < 10) ? 6 : 7;
138 cpu_reg_names_size -= (i < 10) ? 6 : 7;
139 snprintf(p, cpu_reg_names_size, "vsr%d", i);
140 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
141 offsetof(CPUPPCState, vsr[i]), p);
142 p += (i < 10) ? 5 : 6;
143 cpu_reg_names_size -= (i < 10) ? 5 : 6;
144 }
145
146 cpu_nip = tcg_global_mem_new(TCG_AREG0,
147 offsetof(CPUPPCState, nip), "nip");
148
149 cpu_msr = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, msr), "msr");
151
152 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, ctr), "ctr");
154
155 cpu_lr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, lr), "lr");
157
158 #if defined(TARGET_PPC64)
159 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, cfar), "cfar");
161 #endif
162
163 cpu_xer = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, xer), "xer");
165 cpu_so = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, so), "SO");
167 cpu_ov = tcg_global_mem_new(TCG_AREG0,
168 offsetof(CPUPPCState, ov), "OV");
169 cpu_ca = tcg_global_mem_new(TCG_AREG0,
170 offsetof(CPUPPCState, ca), "CA");
171
172 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, reserve_addr),
174 "reserve_addr");
175
176 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
177 offsetof(CPUPPCState, fpscr), "fpscr");
178
179 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
180 offsetof(CPUPPCState, access_type), "access_type");
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 bool pr, hv;
193 int mem_idx;
194 int access_type;
195 /* Translation flags */
196 int le_mode;
197 TCGMemOp default_tcg_memop_mask;
198 #if defined(TARGET_PPC64)
199 int sf_mode;
200 int has_cfar;
201 #endif
202 int fpu_enabled;
203 int altivec_enabled;
204 int vsx_enabled;
205 int spe_enabled;
206 int tm_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 };
212
213 /* Return true iff byteswap is needed in a scalar memop */
214 static inline bool need_byteswap(const DisasContext *ctx)
215 {
216 #if defined(TARGET_WORDS_BIGENDIAN)
217 return ctx->le_mode;
218 #else
219 return !ctx->le_mode;
220 #endif
221 }
222
223 /* True when active word size < size of target_long. */
224 #ifdef TARGET_PPC64
225 # define NARROW_MODE(C) (!(C)->sf_mode)
226 #else
227 # define NARROW_MODE(C) 0
228 #endif
229
230 struct opc_handler_t {
231 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
232 uint32_t inval1;
233 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
234 uint32_t inval2;
235 /* instruction type */
236 uint64_t type;
237 /* extended instruction type */
238 uint64_t type2;
239 /* handler */
240 void (*handler)(DisasContext *ctx);
241 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
242 const char *oname;
243 #endif
244 #if defined(DO_PPC_STATISTICS)
245 uint64_t count;
246 #endif
247 };
248
249 static inline void gen_reset_fpstatus(void)
250 {
251 gen_helper_reset_fpstatus(cpu_env);
252 }
253
254 static inline void gen_compute_fprf(TCGv_i64 arg)
255 {
256 gen_helper_compute_fprf(cpu_env, arg);
257 gen_helper_float_check_status(cpu_env);
258 }
259
260 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
261 {
262 if (ctx->access_type != access_type) {
263 tcg_gen_movi_i32(cpu_access_type, access_type);
264 ctx->access_type = access_type;
265 }
266 }
267
268 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
269 {
270 if (NARROW_MODE(ctx)) {
271 nip = (uint32_t)nip;
272 }
273 tcg_gen_movi_tl(cpu_nip, nip);
274 }
275
276 void gen_update_current_nip(void *opaque)
277 {
278 DisasContext *ctx = opaque;
279
280 tcg_gen_movi_tl(cpu_nip, ctx->nip);
281 }
282
283 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
284 {
285 TCGv_i32 t0, t1;
286 if (ctx->exception == POWERPC_EXCP_NONE) {
287 gen_update_nip(ctx, ctx->nip);
288 }
289 t0 = tcg_const_i32(excp);
290 t1 = tcg_const_i32(error);
291 gen_helper_raise_exception_err(cpu_env, t0, t1);
292 tcg_temp_free_i32(t0);
293 tcg_temp_free_i32(t1);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
298 {
299 TCGv_i32 t0;
300 if (ctx->exception == POWERPC_EXCP_NONE) {
301 gen_update_nip(ctx, ctx->nip);
302 }
303 t0 = tcg_const_i32(excp);
304 gen_helper_raise_exception(cpu_env, t0);
305 tcg_temp_free_i32(t0);
306 ctx->exception = (excp);
307 }
308
309 static inline void gen_debug_exception(DisasContext *ctx)
310 {
311 TCGv_i32 t0;
312
313 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
314 (ctx->exception != POWERPC_EXCP_SYNC)) {
315 gen_update_nip(ctx, ctx->nip);
316 }
317 t0 = tcg_const_i32(EXCP_DEBUG);
318 gen_helper_raise_exception(cpu_env, t0);
319 tcg_temp_free_i32(t0);
320 }
321
322 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
323 {
324 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
325 }
326
327 /* Stop translation */
328 static inline void gen_stop_exception(DisasContext *ctx)
329 {
330 gen_update_nip(ctx, ctx->nip);
331 ctx->exception = POWERPC_EXCP_STOP;
332 }
333
334 #ifndef CONFIG_USER_ONLY
335 /* No need to update nip here, as execution flow will change */
336 static inline void gen_sync_exception(DisasContext *ctx)
337 {
338 ctx->exception = POWERPC_EXCP_SYNC;
339 }
340 #endif
341
342 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
344
345 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
346 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
347
348 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
350
351 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
352 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
353
354 typedef struct opcode_t {
355 unsigned char opc1, opc2, opc3;
356 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
357 unsigned char pad[5];
358 #else
359 unsigned char pad[1];
360 #endif
361 opc_handler_t handler;
362 const char *oname;
363 } opcode_t;
364
365 /*****************************************************************************/
366 /*** Instruction decoding ***/
367 #define EXTRACT_HELPER(name, shift, nb) \
368 static inline uint32_t name(uint32_t opcode) \
369 { \
370 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
371 }
372
373 #define EXTRACT_SHELPER(name, shift, nb) \
374 static inline int32_t name(uint32_t opcode) \
375 { \
376 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
377 }
378
379 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
380 static inline uint32_t name(uint32_t opcode) \
381 { \
382 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
383 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
384 }
385 /* Opcode part 1 */
386 EXTRACT_HELPER(opc1, 26, 6);
387 /* Opcode part 2 */
388 EXTRACT_HELPER(opc2, 1, 5);
389 /* Opcode part 3 */
390 EXTRACT_HELPER(opc3, 6, 5);
391 /* Update Cr0 flags */
392 EXTRACT_HELPER(Rc, 0, 1);
393 /* Update Cr6 flags (Altivec) */
394 EXTRACT_HELPER(Rc21, 10, 1);
395 /* Destination */
396 EXTRACT_HELPER(rD, 21, 5);
397 /* Source */
398 EXTRACT_HELPER(rS, 21, 5);
399 /* First operand */
400 EXTRACT_HELPER(rA, 16, 5);
401 /* Second operand */
402 EXTRACT_HELPER(rB, 11, 5);
403 /* Third operand */
404 EXTRACT_HELPER(rC, 6, 5);
405 /*** Get CRn ***/
406 EXTRACT_HELPER(crfD, 23, 3);
407 EXTRACT_HELPER(crfS, 18, 3);
408 EXTRACT_HELPER(crbD, 21, 5);
409 EXTRACT_HELPER(crbA, 16, 5);
410 EXTRACT_HELPER(crbB, 11, 5);
411 /* SPR / TBL */
412 EXTRACT_HELPER(_SPR, 11, 10);
413 static inline uint32_t SPR(uint32_t opcode)
414 {
415 uint32_t sprn = _SPR(opcode);
416
417 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
418 }
419 /*** Get constants ***/
420 /* 16 bits signed immediate value */
421 EXTRACT_SHELPER(SIMM, 0, 16);
422 /* 16 bits unsigned immediate value */
423 EXTRACT_HELPER(UIMM, 0, 16);
424 /* 5 bits signed immediate value */
425 EXTRACT_HELPER(SIMM5, 16, 5);
426 /* 5 bits signed immediate value */
427 EXTRACT_HELPER(UIMM5, 16, 5);
428 /* Bit count */
429 EXTRACT_HELPER(NB, 11, 5);
430 /* Shift count */
431 EXTRACT_HELPER(SH, 11, 5);
432 /* Vector shift count */
433 EXTRACT_HELPER(VSH, 6, 4);
434 /* Mask start */
435 EXTRACT_HELPER(MB, 6, 5);
436 /* Mask end */
437 EXTRACT_HELPER(ME, 1, 5);
438 /* Trap operand */
439 EXTRACT_HELPER(TO, 21, 5);
440
441 EXTRACT_HELPER(CRM, 12, 8);
442
443 #ifndef CONFIG_USER_ONLY
444 EXTRACT_HELPER(SR, 16, 4);
445 #endif
446
447 /* mtfsf/mtfsfi */
448 EXTRACT_HELPER(FPBF, 23, 3);
449 EXTRACT_HELPER(FPIMM, 12, 4);
450 EXTRACT_HELPER(FPL, 25, 1);
451 EXTRACT_HELPER(FPFLM, 17, 8);
452 EXTRACT_HELPER(FPW, 16, 1);
453
454 /*** Jump target decoding ***/
455 /* Immediate address */
456 static inline target_ulong LI(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0x03FFFFFC;
459 }
460
461 static inline uint32_t BD(uint32_t opcode)
462 {
463 return (opcode >> 0) & 0xFFFC;
464 }
465
466 EXTRACT_HELPER(BO, 21, 5);
467 EXTRACT_HELPER(BI, 16, 5);
468 /* Absolute/relative address */
469 EXTRACT_HELPER(AA, 1, 1);
470 /* Link */
471 EXTRACT_HELPER(LK, 0, 1);
472
473 /* DFP Z22-form */
474 EXTRACT_HELPER(DCM, 10, 6)
475
476 /* DFP Z23-form */
477 EXTRACT_HELPER(RMC, 9, 2)
478
479 /* Create a mask between <start> and <end> bits */
480 static inline target_ulong MASK(uint32_t start, uint32_t end)
481 {
482 target_ulong ret;
483
484 #if defined(TARGET_PPC64)
485 if (likely(start == 0)) {
486 ret = UINT64_MAX << (63 - end);
487 } else if (likely(end == 63)) {
488 ret = UINT64_MAX >> start;
489 }
490 #else
491 if (likely(start == 0)) {
492 ret = UINT32_MAX << (31 - end);
493 } else if (likely(end == 31)) {
494 ret = UINT32_MAX >> start;
495 }
496 #endif
497 else {
498 ret = (((target_ulong)(-1ULL)) >> (start)) ^
499 (((target_ulong)(-1ULL) >> (end)) >> 1);
500 if (unlikely(start > end))
501 return ~ret;
502 }
503
504 return ret;
505 }
506
507 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
508 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
509 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
510 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
511 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
512 EXTRACT_HELPER(DM, 8, 2);
513 EXTRACT_HELPER(UIM, 16, 2);
514 EXTRACT_HELPER(SHW, 8, 2);
515 EXTRACT_HELPER(SP, 19, 2);
516 /*****************************************************************************/
517 /* PowerPC instructions table */
518
519 #if defined(DO_PPC_STATISTICS)
520 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
521 { \
522 .opc1 = op1, \
523 .opc2 = op2, \
524 .opc3 = op3, \
525 .pad = { 0, }, \
526 .handler = { \
527 .inval1 = invl, \
528 .type = _typ, \
529 .type2 = _typ2, \
530 .handler = &gen_##name, \
531 .oname = stringify(name), \
532 }, \
533 .oname = stringify(name), \
534 }
535 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
536 { \
537 .opc1 = op1, \
538 .opc2 = op2, \
539 .opc3 = op3, \
540 .pad = { 0, }, \
541 .handler = { \
542 .inval1 = invl1, \
543 .inval2 = invl2, \
544 .type = _typ, \
545 .type2 = _typ2, \
546 .handler = &gen_##name, \
547 .oname = stringify(name), \
548 }, \
549 .oname = stringify(name), \
550 }
551 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
552 { \
553 .opc1 = op1, \
554 .opc2 = op2, \
555 .opc3 = op3, \
556 .pad = { 0, }, \
557 .handler = { \
558 .inval1 = invl, \
559 .type = _typ, \
560 .type2 = _typ2, \
561 .handler = &gen_##name, \
562 .oname = onam, \
563 }, \
564 .oname = onam, \
565 }
566 #else
567 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
568 { \
569 .opc1 = op1, \
570 .opc2 = op2, \
571 .opc3 = op3, \
572 .pad = { 0, }, \
573 .handler = { \
574 .inval1 = invl, \
575 .type = _typ, \
576 .type2 = _typ2, \
577 .handler = &gen_##name, \
578 }, \
579 .oname = stringify(name), \
580 }
581 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
582 { \
583 .opc1 = op1, \
584 .opc2 = op2, \
585 .opc3 = op3, \
586 .pad = { 0, }, \
587 .handler = { \
588 .inval1 = invl1, \
589 .inval2 = invl2, \
590 .type = _typ, \
591 .type2 = _typ2, \
592 .handler = &gen_##name, \
593 }, \
594 .oname = stringify(name), \
595 }
596 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
597 { \
598 .opc1 = op1, \
599 .opc2 = op2, \
600 .opc3 = op3, \
601 .pad = { 0, }, \
602 .handler = { \
603 .inval1 = invl, \
604 .type = _typ, \
605 .type2 = _typ2, \
606 .handler = &gen_##name, \
607 }, \
608 .oname = onam, \
609 }
610 #endif
611
612 /* SPR load/store helpers */
613 static inline void gen_load_spr(TCGv t, int reg)
614 {
615 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
616 }
617
618 static inline void gen_store_spr(int reg, TCGv t)
619 {
620 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
621 }
622
623 /* Invalid instruction */
624 static void gen_invalid(DisasContext *ctx)
625 {
626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
627 }
628
629 static opc_handler_t invalid_handler = {
630 .inval1 = 0xFFFFFFFF,
631 .inval2 = 0xFFFFFFFF,
632 .type = PPC_NONE,
633 .type2 = PPC_NONE,
634 .handler = gen_invalid,
635 };
636
637 /*** Integer comparison ***/
638
639 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
640 {
641 TCGv t0 = tcg_temp_new();
642 TCGv_i32 t1 = tcg_temp_new_i32();
643
644 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
645
646 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
647 tcg_gen_trunc_tl_i32(t1, t0);
648 tcg_gen_shli_i32(t1, t1, CRF_LT);
649 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
650
651 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
652 tcg_gen_trunc_tl_i32(t1, t0);
653 tcg_gen_shli_i32(t1, t1, CRF_GT);
654 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
655
656 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
657 tcg_gen_trunc_tl_i32(t1, t0);
658 tcg_gen_shli_i32(t1, t1, CRF_EQ);
659 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
660
661 tcg_temp_free(t0);
662 tcg_temp_free_i32(t1);
663 }
664
665 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
666 {
667 TCGv t0 = tcg_const_tl(arg1);
668 gen_op_cmp(arg0, t0, s, crf);
669 tcg_temp_free(t0);
670 }
671
672 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
673 {
674 TCGv t0, t1;
675 t0 = tcg_temp_new();
676 t1 = tcg_temp_new();
677 if (s) {
678 tcg_gen_ext32s_tl(t0, arg0);
679 tcg_gen_ext32s_tl(t1, arg1);
680 } else {
681 tcg_gen_ext32u_tl(t0, arg0);
682 tcg_gen_ext32u_tl(t1, arg1);
683 }
684 gen_op_cmp(t0, t1, s, crf);
685 tcg_temp_free(t1);
686 tcg_temp_free(t0);
687 }
688
689 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
690 {
691 TCGv t0 = tcg_const_tl(arg1);
692 gen_op_cmp32(arg0, t0, s, crf);
693 tcg_temp_free(t0);
694 }
695
696 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
697 {
698 if (NARROW_MODE(ctx)) {
699 gen_op_cmpi32(reg, 0, 1, 0);
700 } else {
701 gen_op_cmpi(reg, 0, 1, 0);
702 }
703 }
704
705 /* cmp */
706 static void gen_cmp(DisasContext *ctx)
707 {
708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
709 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
710 1, crfD(ctx->opcode));
711 } else {
712 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
713 1, crfD(ctx->opcode));
714 }
715 }
716
717 /* cmpi */
718 static void gen_cmpi(DisasContext *ctx)
719 {
720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
721 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
722 1, crfD(ctx->opcode));
723 } else {
724 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
725 1, crfD(ctx->opcode));
726 }
727 }
728
729 /* cmpl */
730 static void gen_cmpl(DisasContext *ctx)
731 {
732 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
733 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
734 0, crfD(ctx->opcode));
735 } else {
736 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
737 0, crfD(ctx->opcode));
738 }
739 }
740
741 /* cmpli */
742 static void gen_cmpli(DisasContext *ctx)
743 {
744 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
745 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
746 0, crfD(ctx->opcode));
747 } else {
748 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
749 0, crfD(ctx->opcode));
750 }
751 }
752
753 /* isel (PowerPC 2.03 specification) */
754 static void gen_isel(DisasContext *ctx)
755 {
756 int l1, l2;
757 uint32_t bi = rC(ctx->opcode);
758 uint32_t mask;
759 TCGv_i32 t0;
760
761 l1 = gen_new_label();
762 l2 = gen_new_label();
763
764 mask = 0x08 >> (bi & 0x03);
765 t0 = tcg_temp_new_i32();
766 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
767 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
768 if (rA(ctx->opcode) == 0)
769 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
770 else
771 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
772 tcg_gen_br(l2);
773 gen_set_label(l1);
774 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
775 gen_set_label(l2);
776 tcg_temp_free_i32(t0);
777 }
778
779 /* cmpb: PowerPC 2.05 specification */
780 static void gen_cmpb(DisasContext *ctx)
781 {
782 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
783 cpu_gpr[rB(ctx->opcode)]);
784 }
785
786 /*** Integer arithmetic ***/
787
788 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
789 TCGv arg1, TCGv arg2, int sub)
790 {
791 TCGv t0 = tcg_temp_new();
792
793 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
794 tcg_gen_xor_tl(t0, arg1, arg2);
795 if (sub) {
796 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
797 } else {
798 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
799 }
800 tcg_temp_free(t0);
801 if (NARROW_MODE(ctx)) {
802 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
803 }
804 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
805 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
806 }
807
808 /* Common add function */
809 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
810 TCGv arg2, bool add_ca, bool compute_ca,
811 bool compute_ov, bool compute_rc0)
812 {
813 TCGv t0 = ret;
814
815 if (compute_ca || compute_ov) {
816 t0 = tcg_temp_new();
817 }
818
819 if (compute_ca) {
820 if (NARROW_MODE(ctx)) {
821 /* Caution: a non-obvious corner case of the spec is that we
822 must produce the *entire* 64-bit addition, but produce the
823 carry into bit 32. */
824 TCGv t1 = tcg_temp_new();
825 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
826 tcg_gen_add_tl(t0, arg1, arg2);
827 if (add_ca) {
828 tcg_gen_add_tl(t0, t0, cpu_ca);
829 }
830 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
831 tcg_temp_free(t1);
832 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
833 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
834 } else {
835 TCGv zero = tcg_const_tl(0);
836 if (add_ca) {
837 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
838 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
839 } else {
840 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
841 }
842 tcg_temp_free(zero);
843 }
844 } else {
845 tcg_gen_add_tl(t0, arg1, arg2);
846 if (add_ca) {
847 tcg_gen_add_tl(t0, t0, cpu_ca);
848 }
849 }
850
851 if (compute_ov) {
852 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
853 }
854 if (unlikely(compute_rc0)) {
855 gen_set_Rc0(ctx, t0);
856 }
857
858 if (!TCGV_EQUAL(t0, ret)) {
859 tcg_gen_mov_tl(ret, t0);
860 tcg_temp_free(t0);
861 }
862 }
863 /* Add functions with two operands */
864 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
865 static void glue(gen_, name)(DisasContext *ctx) \
866 { \
867 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
868 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
869 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
870 }
871 /* Add functions with one operand and one immediate */
872 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
873 add_ca, compute_ca, compute_ov) \
874 static void glue(gen_, name)(DisasContext *ctx) \
875 { \
876 TCGv t0 = tcg_const_tl(const_val); \
877 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
878 cpu_gpr[rA(ctx->opcode)], t0, \
879 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
880 tcg_temp_free(t0); \
881 }
882
883 /* add add. addo addo. */
884 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
885 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
886 /* addc addc. addco addco. */
887 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
888 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
889 /* adde adde. addeo addeo. */
890 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
891 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
892 /* addme addme. addmeo addmeo. */
893 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
894 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
895 /* addze addze. addzeo addzeo.*/
896 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
897 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
898 /* addi */
899 static void gen_addi(DisasContext *ctx)
900 {
901 target_long simm = SIMM(ctx->opcode);
902
903 if (rA(ctx->opcode) == 0) {
904 /* li case */
905 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
906 } else {
907 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
908 cpu_gpr[rA(ctx->opcode)], simm);
909 }
910 }
911 /* addic addic.*/
912 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
913 {
914 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
915 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
916 c, 0, 1, 0, compute_rc0);
917 tcg_temp_free(c);
918 }
919
920 static void gen_addic(DisasContext *ctx)
921 {
922 gen_op_addic(ctx, 0);
923 }
924
925 static void gen_addic_(DisasContext *ctx)
926 {
927 gen_op_addic(ctx, 1);
928 }
929
930 /* addis */
931 static void gen_addis(DisasContext *ctx)
932 {
933 target_long simm = SIMM(ctx->opcode);
934
935 if (rA(ctx->opcode) == 0) {
936 /* lis case */
937 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
938 } else {
939 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
940 cpu_gpr[rA(ctx->opcode)], simm << 16);
941 }
942 }
943
944 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
945 TCGv arg2, int sign, int compute_ov)
946 {
947 int l1 = gen_new_label();
948 int l2 = gen_new_label();
949 TCGv_i32 t0 = tcg_temp_local_new_i32();
950 TCGv_i32 t1 = tcg_temp_local_new_i32();
951
952 tcg_gen_trunc_tl_i32(t0, arg1);
953 tcg_gen_trunc_tl_i32(t1, arg2);
954 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
955 if (sign) {
956 int l3 = gen_new_label();
957 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
958 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
959 gen_set_label(l3);
960 tcg_gen_div_i32(t0, t0, t1);
961 } else {
962 tcg_gen_divu_i32(t0, t0, t1);
963 }
964 if (compute_ov) {
965 tcg_gen_movi_tl(cpu_ov, 0);
966 }
967 tcg_gen_br(l2);
968 gen_set_label(l1);
969 if (sign) {
970 tcg_gen_sari_i32(t0, t0, 31);
971 } else {
972 tcg_gen_movi_i32(t0, 0);
973 }
974 if (compute_ov) {
975 tcg_gen_movi_tl(cpu_ov, 1);
976 tcg_gen_movi_tl(cpu_so, 1);
977 }
978 gen_set_label(l2);
979 tcg_gen_extu_i32_tl(ret, t0);
980 tcg_temp_free_i32(t0);
981 tcg_temp_free_i32(t1);
982 if (unlikely(Rc(ctx->opcode) != 0))
983 gen_set_Rc0(ctx, ret);
984 }
985 /* Div functions */
986 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
987 static void glue(gen_, name)(DisasContext *ctx) \
988 { \
989 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
990 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
991 sign, compute_ov); \
992 }
993 /* divwu divwu. divwuo divwuo. */
994 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
995 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
996 /* divw divw. divwo divwo. */
997 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
998 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
999
1000 /* div[wd]eu[o][.] */
1001 #define GEN_DIVE(name, hlpr, compute_ov) \
1002 static void gen_##name(DisasContext *ctx) \
1003 { \
1004 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1005 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1006 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1007 tcg_temp_free_i32(t0); \
1008 if (unlikely(Rc(ctx->opcode) != 0)) { \
1009 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1010 } \
1011 }
1012
1013 GEN_DIVE(divweu, divweu, 0);
1014 GEN_DIVE(divweuo, divweu, 1);
1015 GEN_DIVE(divwe, divwe, 0);
1016 GEN_DIVE(divweo, divwe, 1);
1017
1018 #if defined(TARGET_PPC64)
1019 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1020 TCGv arg2, int sign, int compute_ov)
1021 {
1022 int l1 = gen_new_label();
1023 int l2 = gen_new_label();
1024
1025 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1026 if (sign) {
1027 int l3 = gen_new_label();
1028 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1029 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1030 gen_set_label(l3);
1031 tcg_gen_div_i64(ret, arg1, arg2);
1032 } else {
1033 tcg_gen_divu_i64(ret, arg1, arg2);
1034 }
1035 if (compute_ov) {
1036 tcg_gen_movi_tl(cpu_ov, 0);
1037 }
1038 tcg_gen_br(l2);
1039 gen_set_label(l1);
1040 if (sign) {
1041 tcg_gen_sari_i64(ret, arg1, 63);
1042 } else {
1043 tcg_gen_movi_i64(ret, 0);
1044 }
1045 if (compute_ov) {
1046 tcg_gen_movi_tl(cpu_ov, 1);
1047 tcg_gen_movi_tl(cpu_so, 1);
1048 }
1049 gen_set_label(l2);
1050 if (unlikely(Rc(ctx->opcode) != 0))
1051 gen_set_Rc0(ctx, ret);
1052 }
1053 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1054 static void glue(gen_, name)(DisasContext *ctx) \
1055 { \
1056 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1057 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1058 sign, compute_ov); \
1059 }
1060 /* divwu divwu. divwuo divwuo. */
1061 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1062 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1063 /* divw divw. divwo divwo. */
1064 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1065 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1066
1067 GEN_DIVE(divdeu, divdeu, 0);
1068 GEN_DIVE(divdeuo, divdeu, 1);
1069 GEN_DIVE(divde, divde, 0);
1070 GEN_DIVE(divdeo, divde, 1);
1071 #endif
1072
1073 /* mulhw mulhw. */
1074 static void gen_mulhw(DisasContext *ctx)
1075 {
1076 TCGv_i32 t0 = tcg_temp_new_i32();
1077 TCGv_i32 t1 = tcg_temp_new_i32();
1078
1079 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1080 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1081 tcg_gen_muls2_i32(t0, t1, t0, t1);
1082 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1083 tcg_temp_free_i32(t0);
1084 tcg_temp_free_i32(t1);
1085 if (unlikely(Rc(ctx->opcode) != 0))
1086 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1087 }
1088
1089 /* mulhwu mulhwu. */
1090 static void gen_mulhwu(DisasContext *ctx)
1091 {
1092 TCGv_i32 t0 = tcg_temp_new_i32();
1093 TCGv_i32 t1 = tcg_temp_new_i32();
1094
1095 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1096 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1097 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1098 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1099 tcg_temp_free_i32(t0);
1100 tcg_temp_free_i32(t1);
1101 if (unlikely(Rc(ctx->opcode) != 0))
1102 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1103 }
1104
1105 /* mullw mullw. */
1106 static void gen_mullw(DisasContext *ctx)
1107 {
1108 #if defined(TARGET_PPC64)
1109 TCGv_i64 t0, t1;
1110 t0 = tcg_temp_new_i64();
1111 t1 = tcg_temp_new_i64();
1112 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1113 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1114 tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1115 tcg_temp_free(t0);
1116 tcg_temp_free(t1);
1117 #else
1118 tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1119 cpu_gpr[rB(ctx->opcode)]);
1120 #endif
1121 if (unlikely(Rc(ctx->opcode) != 0))
1122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1123 }
1124
1125 /* mullwo mullwo. */
1126 static void gen_mullwo(DisasContext *ctx)
1127 {
1128 TCGv_i32 t0 = tcg_temp_new_i32();
1129 TCGv_i32 t1 = tcg_temp_new_i32();
1130
1131 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1132 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1133 tcg_gen_muls2_i32(t0, t1, t0, t1);
1134 #if defined(TARGET_PPC64)
1135 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1136 #else
1137 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1138 #endif
1139
1140 tcg_gen_sari_i32(t0, t0, 31);
1141 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1142 tcg_gen_extu_i32_tl(cpu_ov, t0);
1143 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1144
1145 tcg_temp_free_i32(t0);
1146 tcg_temp_free_i32(t1);
1147 if (unlikely(Rc(ctx->opcode) != 0))
1148 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1149 }
1150
1151 /* mulli */
1152 static void gen_mulli(DisasContext *ctx)
1153 {
1154 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1155 SIMM(ctx->opcode));
1156 }
1157
1158 #if defined(TARGET_PPC64)
1159 /* mulhd mulhd. */
1160 static void gen_mulhd(DisasContext *ctx)
1161 {
1162 TCGv lo = tcg_temp_new();
1163 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1164 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1165 tcg_temp_free(lo);
1166 if (unlikely(Rc(ctx->opcode) != 0)) {
1167 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1168 }
1169 }
1170
1171 /* mulhdu mulhdu. */
1172 static void gen_mulhdu(DisasContext *ctx)
1173 {
1174 TCGv lo = tcg_temp_new();
1175 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1176 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1177 tcg_temp_free(lo);
1178 if (unlikely(Rc(ctx->opcode) != 0)) {
1179 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1180 }
1181 }
1182
1183 /* mulld mulld. */
1184 static void gen_mulld(DisasContext *ctx)
1185 {
1186 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1187 cpu_gpr[rB(ctx->opcode)]);
1188 if (unlikely(Rc(ctx->opcode) != 0))
1189 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1190 }
1191
1192 /* mulldo mulldo. */
1193 static void gen_mulldo(DisasContext *ctx)
1194 {
1195 TCGv_i64 t0 = tcg_temp_new_i64();
1196 TCGv_i64 t1 = tcg_temp_new_i64();
1197
1198 tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1199 cpu_gpr[rB(ctx->opcode)]);
1200 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1201
1202 tcg_gen_sari_i64(t0, t0, 63);
1203 tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1204 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1205
1206 tcg_temp_free_i64(t0);
1207 tcg_temp_free_i64(t1);
1208
1209 if (unlikely(Rc(ctx->opcode) != 0)) {
1210 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1211 }
1212 }
1213 #endif
1214
1215 /* Common subf function */
1216 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1217 TCGv arg2, bool add_ca, bool compute_ca,
1218 bool compute_ov, bool compute_rc0)
1219 {
1220 TCGv t0 = ret;
1221
1222 if (compute_ca || compute_ov) {
1223 t0 = tcg_temp_new();
1224 }
1225
1226 if (compute_ca) {
1227 /* dest = ~arg1 + arg2 [+ ca]. */
1228 if (NARROW_MODE(ctx)) {
1229 /* Caution: a non-obvious corner case of the spec is that we
1230 must produce the *entire* 64-bit addition, but produce the
1231 carry into bit 32. */
1232 TCGv inv1 = tcg_temp_new();
1233 TCGv t1 = tcg_temp_new();
1234 tcg_gen_not_tl(inv1, arg1);
1235 if (add_ca) {
1236 tcg_gen_add_tl(t0, arg2, cpu_ca);
1237 } else {
1238 tcg_gen_addi_tl(t0, arg2, 1);
1239 }
1240 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1241 tcg_gen_add_tl(t0, t0, inv1);
1242 tcg_temp_free(inv1);
1243 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1244 tcg_temp_free(t1);
1245 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1246 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1247 } else if (add_ca) {
1248 TCGv zero, inv1 = tcg_temp_new();
1249 tcg_gen_not_tl(inv1, arg1);
1250 zero = tcg_const_tl(0);
1251 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1252 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1253 tcg_temp_free(zero);
1254 tcg_temp_free(inv1);
1255 } else {
1256 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1257 tcg_gen_sub_tl(t0, arg2, arg1);
1258 }
1259 } else if (add_ca) {
1260 /* Since we're ignoring carry-out, we can simplify the
1261 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1262 tcg_gen_sub_tl(t0, arg2, arg1);
1263 tcg_gen_add_tl(t0, t0, cpu_ca);
1264 tcg_gen_subi_tl(t0, t0, 1);
1265 } else {
1266 tcg_gen_sub_tl(t0, arg2, arg1);
1267 }
1268
1269 if (compute_ov) {
1270 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1271 }
1272 if (unlikely(compute_rc0)) {
1273 gen_set_Rc0(ctx, t0);
1274 }
1275
1276 if (!TCGV_EQUAL(t0, ret)) {
1277 tcg_gen_mov_tl(ret, t0);
1278 tcg_temp_free(t0);
1279 }
1280 }
1281 /* Sub functions with Two operands functions */
1282 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1283 static void glue(gen_, name)(DisasContext *ctx) \
1284 { \
1285 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1286 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1287 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1288 }
1289 /* Sub functions with one operand and one immediate */
1290 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1291 add_ca, compute_ca, compute_ov) \
1292 static void glue(gen_, name)(DisasContext *ctx) \
1293 { \
1294 TCGv t0 = tcg_const_tl(const_val); \
1295 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1296 cpu_gpr[rA(ctx->opcode)], t0, \
1297 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1298 tcg_temp_free(t0); \
1299 }
1300 /* subf subf. subfo subfo. */
1301 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1302 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1303 /* subfc subfc. subfco subfco. */
1304 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1305 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1306 /* subfe subfe. subfeo subfo. */
1307 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1308 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1309 /* subfme subfme. subfmeo subfmeo. */
1310 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1311 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1312 /* subfze subfze. subfzeo subfzeo.*/
1313 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1314 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1315
1316 /* subfic */
1317 static void gen_subfic(DisasContext *ctx)
1318 {
1319 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1320 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1321 c, 0, 1, 0, 0);
1322 tcg_temp_free(c);
1323 }
1324
1325 /* neg neg. nego nego. */
1326 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1327 {
1328 TCGv zero = tcg_const_tl(0);
1329 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1330 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1331 tcg_temp_free(zero);
1332 }
1333
1334 static void gen_neg(DisasContext *ctx)
1335 {
1336 gen_op_arith_neg(ctx, 0);
1337 }
1338
1339 static void gen_nego(DisasContext *ctx)
1340 {
1341 gen_op_arith_neg(ctx, 1);
1342 }
1343
1344 /*** Integer logical ***/
1345 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1346 static void glue(gen_, name)(DisasContext *ctx) \
1347 { \
1348 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1349 cpu_gpr[rB(ctx->opcode)]); \
1350 if (unlikely(Rc(ctx->opcode) != 0)) \
1351 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1352 }
1353
1354 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1355 static void glue(gen_, name)(DisasContext *ctx) \
1356 { \
1357 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1358 if (unlikely(Rc(ctx->opcode) != 0)) \
1359 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1360 }
1361
1362 /* and & and. */
1363 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1364 /* andc & andc. */
1365 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1366
1367 /* andi. */
1368 static void gen_andi_(DisasContext *ctx)
1369 {
1370 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1371 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1372 }
1373
1374 /* andis. */
1375 static void gen_andis_(DisasContext *ctx)
1376 {
1377 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1378 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1379 }
1380
1381 /* cntlzw */
1382 static void gen_cntlzw(DisasContext *ctx)
1383 {
1384 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1385 if (unlikely(Rc(ctx->opcode) != 0))
1386 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1387 }
1388 /* eqv & eqv. */
1389 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1390 /* extsb & extsb. */
1391 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1392 /* extsh & extsh. */
1393 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1394 /* nand & nand. */
1395 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1396 /* nor & nor. */
1397 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1398
1399 /* or & or. */
1400 static void gen_or(DisasContext *ctx)
1401 {
1402 int rs, ra, rb;
1403
1404 rs = rS(ctx->opcode);
1405 ra = rA(ctx->opcode);
1406 rb = rB(ctx->opcode);
1407 /* Optimisation for mr. ri case */
1408 if (rs != ra || rs != rb) {
1409 if (rs != rb)
1410 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1411 else
1412 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1413 if (unlikely(Rc(ctx->opcode) != 0))
1414 gen_set_Rc0(ctx, cpu_gpr[ra]);
1415 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1416 gen_set_Rc0(ctx, cpu_gpr[rs]);
1417 #if defined(TARGET_PPC64)
1418 } else {
1419 int prio = 0;
1420
1421 switch (rs) {
1422 case 1:
1423 /* Set process priority to low */
1424 prio = 2;
1425 break;
1426 case 6:
1427 /* Set process priority to medium-low */
1428 prio = 3;
1429 break;
1430 case 2:
1431 /* Set process priority to normal */
1432 prio = 4;
1433 break;
1434 #if !defined(CONFIG_USER_ONLY)
1435 case 31:
1436 if (!ctx->pr) {
1437 /* Set process priority to very low */
1438 prio = 1;
1439 }
1440 break;
1441 case 5:
1442 if (!ctx->pr) {
1443 /* Set process priority to medium-hight */
1444 prio = 5;
1445 }
1446 break;
1447 case 3:
1448 if (!ctx->pr) {
1449 /* Set process priority to high */
1450 prio = 6;
1451 }
1452 break;
1453 case 7:
1454 if (ctx->hv) {
1455 /* Set process priority to very high */
1456 prio = 7;
1457 }
1458 break;
1459 #endif
1460 default:
1461 /* nop */
1462 break;
1463 }
1464 if (prio) {
1465 TCGv t0 = tcg_temp_new();
1466 gen_load_spr(t0, SPR_PPR);
1467 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1468 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1469 gen_store_spr(SPR_PPR, t0);
1470 tcg_temp_free(t0);
1471 }
1472 #endif
1473 }
1474 }
1475 /* orc & orc. */
1476 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1477
1478 /* xor & xor. */
1479 static void gen_xor(DisasContext *ctx)
1480 {
1481 /* Optimisation for "set to zero" case */
1482 if (rS(ctx->opcode) != rB(ctx->opcode))
1483 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1484 else
1485 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1486 if (unlikely(Rc(ctx->opcode) != 0))
1487 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1488 }
1489
1490 /* ori */
1491 static void gen_ori(DisasContext *ctx)
1492 {
1493 target_ulong uimm = UIMM(ctx->opcode);
1494
1495 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1496 /* NOP */
1497 /* XXX: should handle special NOPs for POWER series */
1498 return;
1499 }
1500 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1501 }
1502
1503 /* oris */
1504 static void gen_oris(DisasContext *ctx)
1505 {
1506 target_ulong uimm = UIMM(ctx->opcode);
1507
1508 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1509 /* NOP */
1510 return;
1511 }
1512 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1513 }
1514
1515 /* xori */
1516 static void gen_xori(DisasContext *ctx)
1517 {
1518 target_ulong uimm = UIMM(ctx->opcode);
1519
1520 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1521 /* NOP */
1522 return;
1523 }
1524 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1525 }
1526
1527 /* xoris */
1528 static void gen_xoris(DisasContext *ctx)
1529 {
1530 target_ulong uimm = UIMM(ctx->opcode);
1531
1532 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1533 /* NOP */
1534 return;
1535 }
1536 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1537 }
1538
1539 /* popcntb : PowerPC 2.03 specification */
1540 static void gen_popcntb(DisasContext *ctx)
1541 {
1542 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1543 }
1544
1545 static void gen_popcntw(DisasContext *ctx)
1546 {
1547 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1548 }
1549
1550 #if defined(TARGET_PPC64)
1551 /* popcntd: PowerPC 2.06 specification */
1552 static void gen_popcntd(DisasContext *ctx)
1553 {
1554 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1555 }
1556 #endif
1557
1558 /* prtyw: PowerPC 2.05 specification */
1559 static void gen_prtyw(DisasContext *ctx)
1560 {
1561 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1562 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1563 TCGv t0 = tcg_temp_new();
1564 tcg_gen_shri_tl(t0, rs, 16);
1565 tcg_gen_xor_tl(ra, rs, t0);
1566 tcg_gen_shri_tl(t0, ra, 8);
1567 tcg_gen_xor_tl(ra, ra, t0);
1568 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1569 tcg_temp_free(t0);
1570 }
1571
1572 #if defined(TARGET_PPC64)
1573 /* prtyd: PowerPC 2.05 specification */
1574 static void gen_prtyd(DisasContext *ctx)
1575 {
1576 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1577 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1578 TCGv t0 = tcg_temp_new();
1579 tcg_gen_shri_tl(t0, rs, 32);
1580 tcg_gen_xor_tl(ra, rs, t0);
1581 tcg_gen_shri_tl(t0, ra, 16);
1582 tcg_gen_xor_tl(ra, ra, t0);
1583 tcg_gen_shri_tl(t0, ra, 8);
1584 tcg_gen_xor_tl(ra, ra, t0);
1585 tcg_gen_andi_tl(ra, ra, 1);
1586 tcg_temp_free(t0);
1587 }
1588 #endif
1589
1590 #if defined(TARGET_PPC64)
1591 /* bpermd */
1592 static void gen_bpermd(DisasContext *ctx)
1593 {
1594 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1595 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1596 }
1597 #endif
1598
1599 #if defined(TARGET_PPC64)
1600 /* extsw & extsw. */
1601 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1602
1603 /* cntlzd */
1604 static void gen_cntlzd(DisasContext *ctx)
1605 {
1606 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1607 if (unlikely(Rc(ctx->opcode) != 0))
1608 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1609 }
1610 #endif
1611
1612 /*** Integer rotate ***/
1613
1614 /* rlwimi & rlwimi. */
1615 static void gen_rlwimi(DisasContext *ctx)
1616 {
1617 uint32_t mb, me, sh;
1618
1619 mb = MB(ctx->opcode);
1620 me = ME(ctx->opcode);
1621 sh = SH(ctx->opcode);
1622 if (likely(sh == (31-me) && mb <= me)) {
1623 tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1624 cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1625 } else {
1626 target_ulong mask;
1627 TCGv t1;
1628 TCGv t0 = tcg_temp_new();
1629 #if defined(TARGET_PPC64)
1630 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1631 cpu_gpr[rS(ctx->opcode)], 32, 32);
1632 tcg_gen_rotli_i64(t0, t0, sh);
1633 #else
1634 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1635 #endif
1636 #if defined(TARGET_PPC64)
1637 mb += 32;
1638 me += 32;
1639 #endif
1640 mask = MASK(mb, me);
1641 t1 = tcg_temp_new();
1642 tcg_gen_andi_tl(t0, t0, mask);
1643 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1644 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1645 tcg_temp_free(t0);
1646 tcg_temp_free(t1);
1647 }
1648 if (unlikely(Rc(ctx->opcode) != 0))
1649 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1650 }
1651
1652 /* rlwinm & rlwinm. */
1653 static void gen_rlwinm(DisasContext *ctx)
1654 {
1655 uint32_t mb, me, sh;
1656
1657 sh = SH(ctx->opcode);
1658 mb = MB(ctx->opcode);
1659 me = ME(ctx->opcode);
1660
1661 if (likely(mb == 0 && me == (31 - sh))) {
1662 if (likely(sh == 0)) {
1663 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1664 } else {
1665 TCGv t0 = tcg_temp_new();
1666 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1667 tcg_gen_shli_tl(t0, t0, sh);
1668 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1669 tcg_temp_free(t0);
1670 }
1671 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1672 TCGv t0 = tcg_temp_new();
1673 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1674 tcg_gen_shri_tl(t0, t0, mb);
1675 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1676 tcg_temp_free(t0);
1677 } else if (likely(mb == 0 && me == 31)) {
1678 TCGv_i32 t0 = tcg_temp_new_i32();
1679 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1680 tcg_gen_rotli_i32(t0, t0, sh);
1681 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1682 tcg_temp_free_i32(t0);
1683 } else {
1684 TCGv t0 = tcg_temp_new();
1685 #if defined(TARGET_PPC64)
1686 tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1687 cpu_gpr[rS(ctx->opcode)], 32, 32);
1688 tcg_gen_rotli_i64(t0, t0, sh);
1689 #else
1690 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1691 #endif
1692 #if defined(TARGET_PPC64)
1693 mb += 32;
1694 me += 32;
1695 #endif
1696 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1697 tcg_temp_free(t0);
1698 }
1699 if (unlikely(Rc(ctx->opcode) != 0))
1700 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1701 }
1702
1703 /* rlwnm & rlwnm. */
1704 static void gen_rlwnm(DisasContext *ctx)
1705 {
1706 uint32_t mb, me;
1707 mb = MB(ctx->opcode);
1708 me = ME(ctx->opcode);
1709
1710 if (likely(mb == 0 && me == 31)) {
1711 TCGv_i32 t0, t1;
1712 t0 = tcg_temp_new_i32();
1713 t1 = tcg_temp_new_i32();
1714 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1715 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1716 tcg_gen_andi_i32(t0, t0, 0x1f);
1717 tcg_gen_rotl_i32(t1, t1, t0);
1718 tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1719 tcg_temp_free_i32(t0);
1720 tcg_temp_free_i32(t1);
1721 } else {
1722 TCGv t0;
1723 #if defined(TARGET_PPC64)
1724 TCGv t1;
1725 #endif
1726
1727 t0 = tcg_temp_new();
1728 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1729 #if defined(TARGET_PPC64)
1730 t1 = tcg_temp_new_i64();
1731 tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1732 cpu_gpr[rS(ctx->opcode)], 32, 32);
1733 tcg_gen_rotl_i64(t0, t1, t0);
1734 tcg_temp_free_i64(t1);
1735 #else
1736 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1737 #endif
1738 if (unlikely(mb != 0 || me != 31)) {
1739 #if defined(TARGET_PPC64)
1740 mb += 32;
1741 me += 32;
1742 #endif
1743 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1744 } else {
1745 tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1746 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1747 }
1748 tcg_temp_free(t0);
1749 }
1750 if (unlikely(Rc(ctx->opcode) != 0))
1751 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1752 }
1753
1754 #if defined(TARGET_PPC64)
1755 #define GEN_PPC64_R2(name, opc1, opc2) \
1756 static void glue(gen_, name##0)(DisasContext *ctx) \
1757 { \
1758 gen_##name(ctx, 0); \
1759 } \
1760 \
1761 static void glue(gen_, name##1)(DisasContext *ctx) \
1762 { \
1763 gen_##name(ctx, 1); \
1764 }
1765 #define GEN_PPC64_R4(name, opc1, opc2) \
1766 static void glue(gen_, name##0)(DisasContext *ctx) \
1767 { \
1768 gen_##name(ctx, 0, 0); \
1769 } \
1770 \
1771 static void glue(gen_, name##1)(DisasContext *ctx) \
1772 { \
1773 gen_##name(ctx, 0, 1); \
1774 } \
1775 \
1776 static void glue(gen_, name##2)(DisasContext *ctx) \
1777 { \
1778 gen_##name(ctx, 1, 0); \
1779 } \
1780 \
1781 static void glue(gen_, name##3)(DisasContext *ctx) \
1782 { \
1783 gen_##name(ctx, 1, 1); \
1784 }
1785
1786 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1787 uint32_t sh)
1788 {
1789 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1790 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1791 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1792 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1793 } else {
1794 TCGv t0 = tcg_temp_new();
1795 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1796 if (likely(mb == 0 && me == 63)) {
1797 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1798 } else {
1799 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1800 }
1801 tcg_temp_free(t0);
1802 }
1803 if (unlikely(Rc(ctx->opcode) != 0))
1804 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1805 }
1806 /* rldicl - rldicl. */
1807 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1808 {
1809 uint32_t sh, mb;
1810
1811 sh = SH(ctx->opcode) | (shn << 5);
1812 mb = MB(ctx->opcode) | (mbn << 5);
1813 gen_rldinm(ctx, mb, 63, sh);
1814 }
1815 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1816 /* rldicr - rldicr. */
1817 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1818 {
1819 uint32_t sh, me;
1820
1821 sh = SH(ctx->opcode) | (shn << 5);
1822 me = MB(ctx->opcode) | (men << 5);
1823 gen_rldinm(ctx, 0, me, sh);
1824 }
1825 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1826 /* rldic - rldic. */
1827 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1828 {
1829 uint32_t sh, mb;
1830
1831 sh = SH(ctx->opcode) | (shn << 5);
1832 mb = MB(ctx->opcode) | (mbn << 5);
1833 gen_rldinm(ctx, mb, 63 - sh, sh);
1834 }
1835 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1836
1837 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1838 {
1839 TCGv t0;
1840
1841 t0 = tcg_temp_new();
1842 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1843 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1844 if (unlikely(mb != 0 || me != 63)) {
1845 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1846 } else {
1847 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1848 }
1849 tcg_temp_free(t0);
1850 if (unlikely(Rc(ctx->opcode) != 0))
1851 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1852 }
1853
1854 /* rldcl - rldcl. */
1855 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1856 {
1857 uint32_t mb;
1858
1859 mb = MB(ctx->opcode) | (mbn << 5);
1860 gen_rldnm(ctx, mb, 63);
1861 }
1862 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1863 /* rldcr - rldcr. */
1864 static inline void gen_rldcr(DisasContext *ctx, int men)
1865 {
1866 uint32_t me;
1867
1868 me = MB(ctx->opcode) | (men << 5);
1869 gen_rldnm(ctx, 0, me);
1870 }
1871 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1872 /* rldimi - rldimi. */
1873 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1874 {
1875 uint32_t sh, mb, me;
1876
1877 sh = SH(ctx->opcode) | (shn << 5);
1878 mb = MB(ctx->opcode) | (mbn << 5);
1879 me = 63 - sh;
1880 if (unlikely(sh == 0 && mb == 0)) {
1881 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1882 } else {
1883 TCGv t0, t1;
1884 target_ulong mask;
1885
1886 t0 = tcg_temp_new();
1887 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1888 t1 = tcg_temp_new();
1889 mask = MASK(mb, me);
1890 tcg_gen_andi_tl(t0, t0, mask);
1891 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1892 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1893 tcg_temp_free(t0);
1894 tcg_temp_free(t1);
1895 }
1896 if (unlikely(Rc(ctx->opcode) != 0))
1897 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1898 }
1899 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1900 #endif
1901
1902 /*** Integer shift ***/
1903
1904 /* slw & slw. */
1905 static void gen_slw(DisasContext *ctx)
1906 {
1907 TCGv t0, t1;
1908
1909 t0 = tcg_temp_new();
1910 /* AND rS with a mask that is 0 when rB >= 0x20 */
1911 #if defined(TARGET_PPC64)
1912 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1913 tcg_gen_sari_tl(t0, t0, 0x3f);
1914 #else
1915 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1916 tcg_gen_sari_tl(t0, t0, 0x1f);
1917 #endif
1918 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1919 t1 = tcg_temp_new();
1920 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1921 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1922 tcg_temp_free(t1);
1923 tcg_temp_free(t0);
1924 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1925 if (unlikely(Rc(ctx->opcode) != 0))
1926 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1927 }
1928
1929 /* sraw & sraw. */
1930 static void gen_sraw(DisasContext *ctx)
1931 {
1932 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1933 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1934 if (unlikely(Rc(ctx->opcode) != 0))
1935 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1936 }
1937
1938 /* srawi & srawi. */
1939 static void gen_srawi(DisasContext *ctx)
1940 {
1941 int sh = SH(ctx->opcode);
1942 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1943 TCGv src = cpu_gpr[rS(ctx->opcode)];
1944 if (sh == 0) {
1945 tcg_gen_ext32s_tl(dst, src);
1946 tcg_gen_movi_tl(cpu_ca, 0);
1947 } else {
1948 TCGv t0;
1949 tcg_gen_ext32s_tl(dst, src);
1950 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1951 t0 = tcg_temp_new();
1952 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1953 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1954 tcg_temp_free(t0);
1955 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1956 tcg_gen_sari_tl(dst, dst, sh);
1957 }
1958 if (unlikely(Rc(ctx->opcode) != 0)) {
1959 gen_set_Rc0(ctx, dst);
1960 }
1961 }
1962
1963 /* srw & srw. */
1964 static void gen_srw(DisasContext *ctx)
1965 {
1966 TCGv t0, t1;
1967
1968 t0 = tcg_temp_new();
1969 /* AND rS with a mask that is 0 when rB >= 0x20 */
1970 #if defined(TARGET_PPC64)
1971 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1972 tcg_gen_sari_tl(t0, t0, 0x3f);
1973 #else
1974 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1975 tcg_gen_sari_tl(t0, t0, 0x1f);
1976 #endif
1977 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1978 tcg_gen_ext32u_tl(t0, t0);
1979 t1 = tcg_temp_new();
1980 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1981 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1982 tcg_temp_free(t1);
1983 tcg_temp_free(t0);
1984 if (unlikely(Rc(ctx->opcode) != 0))
1985 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1986 }
1987
1988 #if defined(TARGET_PPC64)
1989 /* sld & sld. */
1990 static void gen_sld(DisasContext *ctx)
1991 {
1992 TCGv t0, t1;
1993
1994 t0 = tcg_temp_new();
1995 /* AND rS with a mask that is 0 when rB >= 0x40 */
1996 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1997 tcg_gen_sari_tl(t0, t0, 0x3f);
1998 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1999 t1 = tcg_temp_new();
2000 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2001 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2002 tcg_temp_free(t1);
2003 tcg_temp_free(t0);
2004 if (unlikely(Rc(ctx->opcode) != 0))
2005 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2006 }
2007
2008 /* srad & srad. */
2009 static void gen_srad(DisasContext *ctx)
2010 {
2011 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2012 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2013 if (unlikely(Rc(ctx->opcode) != 0))
2014 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2015 }
2016 /* sradi & sradi. */
2017 static inline void gen_sradi(DisasContext *ctx, int n)
2018 {
2019 int sh = SH(ctx->opcode) + (n << 5);
2020 TCGv dst = cpu_gpr[rA(ctx->opcode)];
2021 TCGv src = cpu_gpr[rS(ctx->opcode)];
2022 if (sh == 0) {
2023 tcg_gen_mov_tl(dst, src);
2024 tcg_gen_movi_tl(cpu_ca, 0);
2025 } else {
2026 TCGv t0;
2027 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2028 t0 = tcg_temp_new();
2029 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2030 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2031 tcg_temp_free(t0);
2032 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2033 tcg_gen_sari_tl(dst, src, sh);
2034 }
2035 if (unlikely(Rc(ctx->opcode) != 0)) {
2036 gen_set_Rc0(ctx, dst);
2037 }
2038 }
2039
2040 static void gen_sradi0(DisasContext *ctx)
2041 {
2042 gen_sradi(ctx, 0);
2043 }
2044
2045 static void gen_sradi1(DisasContext *ctx)
2046 {
2047 gen_sradi(ctx, 1);
2048 }
2049
2050 /* srd & srd. */
2051 static void gen_srd(DisasContext *ctx)
2052 {
2053 TCGv t0, t1;
2054
2055 t0 = tcg_temp_new();
2056 /* AND rS with a mask that is 0 when rB >= 0x40 */
2057 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2058 tcg_gen_sari_tl(t0, t0, 0x3f);
2059 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2060 t1 = tcg_temp_new();
2061 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2062 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2063 tcg_temp_free(t1);
2064 tcg_temp_free(t0);
2065 if (unlikely(Rc(ctx->opcode) != 0))
2066 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2067 }
2068 #endif
2069
2070 #if defined(TARGET_PPC64)
2071 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2072 {
2073 TCGv_i32 tmp = tcg_temp_new_i32();
2074 tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2075 tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2076 tcg_temp_free_i32(tmp);
2077 }
2078 #else
2079 static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2080 {
2081 tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2082 }
2083 #endif
2084
2085 /*** Floating-Point arithmetic ***/
2086 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2087 static void gen_f##name(DisasContext *ctx) \
2088 { \
2089 if (unlikely(!ctx->fpu_enabled)) { \
2090 gen_exception(ctx, POWERPC_EXCP_FPU); \
2091 return; \
2092 } \
2093 /* NIP cannot be restored if the memory exception comes from an helper */ \
2094 gen_update_nip(ctx, ctx->nip - 4); \
2095 gen_reset_fpstatus(); \
2096 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2097 cpu_fpr[rA(ctx->opcode)], \
2098 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2099 if (isfloat) { \
2100 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2101 cpu_fpr[rD(ctx->opcode)]); \
2102 } \
2103 if (set_fprf) { \
2104 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2105 } \
2106 if (unlikely(Rc(ctx->opcode) != 0)) { \
2107 gen_set_cr1_from_fpscr(ctx); \
2108 } \
2109 }
2110
2111 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2112 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2113 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2114
2115 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2116 static void gen_f##name(DisasContext *ctx) \
2117 { \
2118 if (unlikely(!ctx->fpu_enabled)) { \
2119 gen_exception(ctx, POWERPC_EXCP_FPU); \
2120 return; \
2121 } \
2122 /* NIP cannot be restored if the memory exception comes from an helper */ \
2123 gen_update_nip(ctx, ctx->nip - 4); \
2124 gen_reset_fpstatus(); \
2125 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2126 cpu_fpr[rA(ctx->opcode)], \
2127 cpu_fpr[rB(ctx->opcode)]); \
2128 if (isfloat) { \
2129 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2130 cpu_fpr[rD(ctx->opcode)]); \
2131 } \
2132 if (set_fprf) { \
2133 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2134 } \
2135 if (unlikely(Rc(ctx->opcode) != 0)) { \
2136 gen_set_cr1_from_fpscr(ctx); \
2137 } \
2138 }
2139 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2140 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2141 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2142
2143 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2144 static void gen_f##name(DisasContext *ctx) \
2145 { \
2146 if (unlikely(!ctx->fpu_enabled)) { \
2147 gen_exception(ctx, POWERPC_EXCP_FPU); \
2148 return; \
2149 } \
2150 /* NIP cannot be restored if the memory exception comes from an helper */ \
2151 gen_update_nip(ctx, ctx->nip - 4); \
2152 gen_reset_fpstatus(); \
2153 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2154 cpu_fpr[rA(ctx->opcode)], \
2155 cpu_fpr[rC(ctx->opcode)]); \
2156 if (isfloat) { \
2157 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2158 cpu_fpr[rD(ctx->opcode)]); \
2159 } \
2160 if (set_fprf) { \
2161 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2162 } \
2163 if (unlikely(Rc(ctx->opcode) != 0)) { \
2164 gen_set_cr1_from_fpscr(ctx); \
2165 } \
2166 }
2167 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2168 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2169 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2170
2171 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2172 static void gen_f##name(DisasContext *ctx) \
2173 { \
2174 if (unlikely(!ctx->fpu_enabled)) { \
2175 gen_exception(ctx, POWERPC_EXCP_FPU); \
2176 return; \
2177 } \
2178 /* NIP cannot be restored if the memory exception comes from an helper */ \
2179 gen_update_nip(ctx, ctx->nip - 4); \
2180 gen_reset_fpstatus(); \
2181 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2182 cpu_fpr[rB(ctx->opcode)]); \
2183 if (set_fprf) { \
2184 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2185 } \
2186 if (unlikely(Rc(ctx->opcode) != 0)) { \
2187 gen_set_cr1_from_fpscr(ctx); \
2188 } \
2189 }
2190
2191 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2192 static void gen_f##name(DisasContext *ctx) \
2193 { \
2194 if (unlikely(!ctx->fpu_enabled)) { \
2195 gen_exception(ctx, POWERPC_EXCP_FPU); \
2196 return; \
2197 } \
2198 /* NIP cannot be restored if the memory exception comes from an helper */ \
2199 gen_update_nip(ctx, ctx->nip - 4); \
2200 gen_reset_fpstatus(); \
2201 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2202 cpu_fpr[rB(ctx->opcode)]); \
2203 if (set_fprf) { \
2204 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
2205 } \
2206 if (unlikely(Rc(ctx->opcode) != 0)) { \
2207 gen_set_cr1_from_fpscr(ctx); \
2208 } \
2209 }
2210
2211 /* fadd - fadds */
2212 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2213 /* fdiv - fdivs */
2214 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2215 /* fmul - fmuls */
2216 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2217
2218 /* fre */
2219 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2220
2221 /* fres */
2222 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2223
2224 /* frsqrte */
2225 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2226
2227 /* frsqrtes */
2228 static void gen_frsqrtes(DisasContext *ctx)
2229 {
2230 if (unlikely(!ctx->fpu_enabled)) {
2231 gen_exception(ctx, POWERPC_EXCP_FPU);
2232 return;
2233 }
2234 /* NIP cannot be restored if the memory exception comes from an helper */
2235 gen_update_nip(ctx, ctx->nip - 4);
2236 gen_reset_fpstatus();
2237 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2238 cpu_fpr[rB(ctx->opcode)]);
2239 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2240 cpu_fpr[rD(ctx->opcode)]);
2241 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2242 if (unlikely(Rc(ctx->opcode) != 0)) {
2243 gen_set_cr1_from_fpscr(ctx);
2244 }
2245 }
2246
2247 /* fsel */
2248 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2249 /* fsub - fsubs */
2250 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2251 /* Optional: */
2252
2253 /* fsqrt */
2254 static void gen_fsqrt(DisasContext *ctx)
2255 {
2256 if (unlikely(!ctx->fpu_enabled)) {
2257 gen_exception(ctx, POWERPC_EXCP_FPU);
2258 return;
2259 }
2260 /* NIP cannot be restored if the memory exception comes from an helper */
2261 gen_update_nip(ctx, ctx->nip - 4);
2262 gen_reset_fpstatus();
2263 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2264 cpu_fpr[rB(ctx->opcode)]);
2265 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2266 if (unlikely(Rc(ctx->opcode) != 0)) {
2267 gen_set_cr1_from_fpscr(ctx);
2268 }
2269 }
2270
2271 static void gen_fsqrts(DisasContext *ctx)
2272 {
2273 if (unlikely(!ctx->fpu_enabled)) {
2274 gen_exception(ctx, POWERPC_EXCP_FPU);
2275 return;
2276 }
2277 /* NIP cannot be restored if the memory exception comes from an helper */
2278 gen_update_nip(ctx, ctx->nip - 4);
2279 gen_reset_fpstatus();
2280 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2281 cpu_fpr[rB(ctx->opcode)]);
2282 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2283 cpu_fpr[rD(ctx->opcode)]);
2284 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2285 if (unlikely(Rc(ctx->opcode) != 0)) {
2286 gen_set_cr1_from_fpscr(ctx);
2287 }
2288 }
2289
2290 /*** Floating-Point multiply-and-add ***/
2291 /* fmadd - fmadds */
2292 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2293 /* fmsub - fmsubs */
2294 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2295 /* fnmadd - fnmadds */
2296 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2297 /* fnmsub - fnmsubs */
2298 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2299
2300 /*** Floating-Point round & convert ***/
2301 /* fctiw */
2302 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2303 /* fctiwu */
2304 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2305 /* fctiwz */
2306 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2307 /* fctiwuz */
2308 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2309 /* frsp */
2310 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2311 /* fcfid */
2312 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2313 /* fcfids */
2314 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2315 /* fcfidu */
2316 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2317 /* fcfidus */
2318 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2319 /* fctid */
2320 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2321 /* fctidu */
2322 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2323 /* fctidz */
2324 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2325 /* fctidu */
2326 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2327
2328 /* frin */
2329 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2330 /* friz */
2331 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2332 /* frip */
2333 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2334 /* frim */
2335 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2336
2337 static void gen_ftdiv(DisasContext *ctx)
2338 {
2339 if (unlikely(!ctx->fpu_enabled)) {
2340 gen_exception(ctx, POWERPC_EXCP_FPU);
2341 return;
2342 }
2343 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2344 cpu_fpr[rB(ctx->opcode)]);
2345 }
2346
2347 static void gen_ftsqrt(DisasContext *ctx)
2348 {
2349 if (unlikely(!ctx->fpu_enabled)) {
2350 gen_exception(ctx, POWERPC_EXCP_FPU);
2351 return;
2352 }
2353 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2354 }
2355
2356
2357
2358 /*** Floating-Point compare ***/
2359
2360 /* fcmpo */
2361 static void gen_fcmpo(DisasContext *ctx)
2362 {
2363 TCGv_i32 crf;
2364 if (unlikely(!ctx->fpu_enabled)) {
2365 gen_exception(ctx, POWERPC_EXCP_FPU);
2366 return;
2367 }
2368 /* NIP cannot be restored if the memory exception comes from an helper */
2369 gen_update_nip(ctx, ctx->nip - 4);
2370 gen_reset_fpstatus();
2371 crf = tcg_const_i32(crfD(ctx->opcode));
2372 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2373 cpu_fpr[rB(ctx->opcode)], crf);
2374 tcg_temp_free_i32(crf);
2375 gen_helper_float_check_status(cpu_env);
2376 }
2377
2378 /* fcmpu */
2379 static void gen_fcmpu(DisasContext *ctx)
2380 {
2381 TCGv_i32 crf;
2382 if (unlikely(!ctx->fpu_enabled)) {
2383 gen_exception(ctx, POWERPC_EXCP_FPU);
2384 return;
2385 }
2386 /* NIP cannot be restored if the memory exception comes from an helper */
2387 gen_update_nip(ctx, ctx->nip - 4);
2388 gen_reset_fpstatus();
2389 crf = tcg_const_i32(crfD(ctx->opcode));
2390 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2391 cpu_fpr[rB(ctx->opcode)], crf);
2392 tcg_temp_free_i32(crf);
2393 gen_helper_float_check_status(cpu_env);
2394 }
2395
2396 /*** Floating-point move ***/
2397 /* fabs */
2398 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2399 static void gen_fabs(DisasContext *ctx)
2400 {
2401 if (unlikely(!ctx->fpu_enabled)) {
2402 gen_exception(ctx, POWERPC_EXCP_FPU);
2403 return;
2404 }
2405 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2406 ~(1ULL << 63));
2407 if (unlikely(Rc(ctx->opcode))) {
2408 gen_set_cr1_from_fpscr(ctx);
2409 }
2410 }
2411
2412 /* fmr - fmr. */
2413 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2414 static void gen_fmr(DisasContext *ctx)
2415 {
2416 if (unlikely(!ctx->fpu_enabled)) {
2417 gen_exception(ctx, POWERPC_EXCP_FPU);
2418 return;
2419 }
2420 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2421 if (unlikely(Rc(ctx->opcode))) {
2422 gen_set_cr1_from_fpscr(ctx);
2423 }
2424 }
2425
2426 /* fnabs */
2427 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2428 static void gen_fnabs(DisasContext *ctx)
2429 {
2430 if (unlikely(!ctx->fpu_enabled)) {
2431 gen_exception(ctx, POWERPC_EXCP_FPU);
2432 return;
2433 }
2434 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2435 1ULL << 63);
2436 if (unlikely(Rc(ctx->opcode))) {
2437 gen_set_cr1_from_fpscr(ctx);
2438 }
2439 }
2440
2441 /* fneg */
2442 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2443 static void gen_fneg(DisasContext *ctx)
2444 {
2445 if (unlikely(!ctx->fpu_enabled)) {
2446 gen_exception(ctx, POWERPC_EXCP_FPU);
2447 return;
2448 }
2449 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2450 1ULL << 63);
2451 if (unlikely(Rc(ctx->opcode))) {
2452 gen_set_cr1_from_fpscr(ctx);
2453 }
2454 }
2455
2456 /* fcpsgn: PowerPC 2.05 specification */
2457 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2458 static void gen_fcpsgn(DisasContext *ctx)
2459 {
2460 if (unlikely(!ctx->fpu_enabled)) {
2461 gen_exception(ctx, POWERPC_EXCP_FPU);
2462 return;
2463 }
2464 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2465 cpu_fpr[rB(ctx->opcode)], 0, 63);
2466 if (unlikely(Rc(ctx->opcode))) {
2467 gen_set_cr1_from_fpscr(ctx);
2468 }
2469 }
2470
2471 static void gen_fmrgew(DisasContext *ctx)
2472 {
2473 TCGv_i64 b0;
2474 if (unlikely(!ctx->fpu_enabled)) {
2475 gen_exception(ctx, POWERPC_EXCP_FPU);
2476 return;
2477 }
2478 b0 = tcg_temp_new_i64();
2479 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2480 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2481 b0, 0, 32);
2482 tcg_temp_free_i64(b0);
2483 }
2484
2485 static void gen_fmrgow(DisasContext *ctx)
2486 {
2487 if (unlikely(!ctx->fpu_enabled)) {
2488 gen_exception(ctx, POWERPC_EXCP_FPU);
2489 return;
2490 }
2491 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2492 cpu_fpr[rB(ctx->opcode)],
2493 cpu_fpr[rA(ctx->opcode)],
2494 32, 32);
2495 }
2496
2497 /*** Floating-Point status & ctrl register ***/
2498
2499 /* mcrfs */
2500 static void gen_mcrfs(DisasContext *ctx)
2501 {
2502 TCGv tmp = tcg_temp_new();
2503 int bfa;
2504
2505 if (unlikely(!ctx->fpu_enabled)) {
2506 gen_exception(ctx, POWERPC_EXCP_FPU);
2507 return;
2508 }
2509 bfa = 4 * (7 - crfS(ctx->opcode));
2510 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2511 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2512 tcg_temp_free(tmp);
2513 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2514 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2515 }
2516
2517 /* mffs */
2518 static void gen_mffs(DisasContext *ctx)
2519 {
2520 if (unlikely(!ctx->fpu_enabled)) {
2521 gen_exception(ctx, POWERPC_EXCP_FPU);
2522 return;
2523 }
2524 gen_reset_fpstatus();
2525 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2526 if (unlikely(Rc(ctx->opcode))) {
2527 gen_set_cr1_from_fpscr(ctx);
2528 }
2529 }
2530
2531 /* mtfsb0 */
2532 static void gen_mtfsb0(DisasContext *ctx)
2533 {
2534 uint8_t crb;
2535
2536 if (unlikely(!ctx->fpu_enabled)) {
2537 gen_exception(ctx, POWERPC_EXCP_FPU);
2538 return;
2539 }
2540 crb = 31 - crbD(ctx->opcode);
2541 gen_reset_fpstatus();
2542 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2543 TCGv_i32 t0;
2544 /* NIP cannot be restored if the memory exception comes from an helper */
2545 gen_update_nip(ctx, ctx->nip - 4);
2546 t0 = tcg_const_i32(crb);
2547 gen_helper_fpscr_clrbit(cpu_env, t0);
2548 tcg_temp_free_i32(t0);
2549 }
2550 if (unlikely(Rc(ctx->opcode) != 0)) {
2551 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2552 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2553 }
2554 }
2555
2556 /* mtfsb1 */
2557 static void gen_mtfsb1(DisasContext *ctx)
2558 {
2559 uint8_t crb;
2560
2561 if (unlikely(!ctx->fpu_enabled)) {
2562 gen_exception(ctx, POWERPC_EXCP_FPU);
2563 return;
2564 }
2565 crb = 31 - crbD(ctx->opcode);
2566 gen_reset_fpstatus();
2567 /* XXX: we pretend we can only do IEEE floating-point computations */
2568 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2569 TCGv_i32 t0;
2570 /* NIP cannot be restored if the memory exception comes from an helper */
2571 gen_update_nip(ctx, ctx->nip - 4);
2572 t0 = tcg_const_i32(crb);
2573 gen_helper_fpscr_setbit(cpu_env, t0);
2574 tcg_temp_free_i32(t0);
2575 }
2576 if (unlikely(Rc(ctx->opcode) != 0)) {
2577 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2578 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2579 }
2580 /* We can raise a differed exception */
2581 gen_helper_float_check_status(cpu_env);
2582 }
2583
2584 /* mtfsf */
2585 static void gen_mtfsf(DisasContext *ctx)
2586 {
2587 TCGv_i32 t0;
2588 int flm, l, w;
2589
2590 if (unlikely(!ctx->fpu_enabled)) {
2591 gen_exception(ctx, POWERPC_EXCP_FPU);
2592 return;
2593 }
2594 flm = FPFLM(ctx->opcode);
2595 l = FPL(ctx->opcode);
2596 w = FPW(ctx->opcode);
2597 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2598 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2599 return;
2600 }
2601 /* NIP cannot be restored if the memory exception comes from an helper */
2602 gen_update_nip(ctx, ctx->nip - 4);
2603 gen_reset_fpstatus();
2604 if (l) {
2605 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2606 } else {
2607 t0 = tcg_const_i32(flm << (w * 8));
2608 }
2609 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2610 tcg_temp_free_i32(t0);
2611 if (unlikely(Rc(ctx->opcode) != 0)) {
2612 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2613 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2614 }
2615 /* We can raise a differed exception */
2616 gen_helper_float_check_status(cpu_env);
2617 }
2618
2619 /* mtfsfi */
2620 static void gen_mtfsfi(DisasContext *ctx)
2621 {
2622 int bf, sh, w;
2623 TCGv_i64 t0;
2624 TCGv_i32 t1;
2625
2626 if (unlikely(!ctx->fpu_enabled)) {
2627 gen_exception(ctx, POWERPC_EXCP_FPU);
2628 return;
2629 }
2630 w = FPW(ctx->opcode);
2631 bf = FPBF(ctx->opcode);
2632 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2633 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2634 return;
2635 }
2636 sh = (8 * w) + 7 - bf;
2637 /* NIP cannot be restored if the memory exception comes from an helper */
2638 gen_update_nip(ctx, ctx->nip - 4);
2639 gen_reset_fpstatus();
2640 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2641 t1 = tcg_const_i32(1 << sh);
2642 gen_helper_store_fpscr(cpu_env, t0, t1);
2643 tcg_temp_free_i64(t0);
2644 tcg_temp_free_i32(t1);
2645 if (unlikely(Rc(ctx->opcode) != 0)) {
2646 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2647 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2648 }
2649 /* We can raise a differed exception */
2650 gen_helper_float_check_status(cpu_env);
2651 }
2652
2653 /*** Addressing modes ***/
2654 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2655 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2656 target_long maskl)
2657 {
2658 target_long simm = SIMM(ctx->opcode);
2659
2660 simm &= ~maskl;
2661 if (rA(ctx->opcode) == 0) {
2662 if (NARROW_MODE(ctx)) {
2663 simm = (uint32_t)simm;
2664 }
2665 tcg_gen_movi_tl(EA, simm);
2666 } else if (likely(simm != 0)) {
2667 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2668 if (NARROW_MODE(ctx)) {
2669 tcg_gen_ext32u_tl(EA, EA);
2670 }
2671 } else {
2672 if (NARROW_MODE(ctx)) {
2673 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2674 } else {
2675 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2676 }
2677 }
2678 }
2679
2680 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2681 {
2682 if (rA(ctx->opcode) == 0) {
2683 if (NARROW_MODE(ctx)) {
2684 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2685 } else {
2686 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2687 }
2688 } else {
2689 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2690 if (NARROW_MODE(ctx)) {
2691 tcg_gen_ext32u_tl(EA, EA);
2692 }
2693 }
2694 }
2695
2696 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2697 {
2698 if (rA(ctx->opcode) == 0) {
2699 tcg_gen_movi_tl(EA, 0);
2700 } else if (NARROW_MODE(ctx)) {
2701 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2702 } else {
2703 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2704 }
2705 }
2706
2707 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2708 target_long val)
2709 {
2710 tcg_gen_addi_tl(ret, arg1, val);
2711 if (NARROW_MODE(ctx)) {
2712 tcg_gen_ext32u_tl(ret, ret);
2713 }
2714 }
2715
2716 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2717 {
2718 int l1 = gen_new_label();
2719 TCGv t0 = tcg_temp_new();
2720 TCGv_i32 t1, t2;
2721 /* NIP cannot be restored if the memory exception comes from an helper */
2722 gen_update_nip(ctx, ctx->nip - 4);
2723 tcg_gen_andi_tl(t0, EA, mask);
2724 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2725 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2726 t2 = tcg_const_i32(0);
2727 gen_helper_raise_exception_err(cpu_env, t1, t2);
2728 tcg_temp_free_i32(t1);
2729 tcg_temp_free_i32(t2);
2730 gen_set_label(l1);
2731 tcg_temp_free(t0);
2732 }
2733
2734 /*** Integer load ***/
2735 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2736 {
2737 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2738 }
2739
2740 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2741 {
2742 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2743 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2744 }
2745
2746 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2747 {
2748 TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2749 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2750 }
2751
2752 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2753 {
2754 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2755 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2756 }
2757
2758 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2759 {
2760 TCGv tmp = tcg_temp_new();
2761 gen_qemu_ld32u(ctx, tmp, addr);
2762 tcg_gen_extu_tl_i64(val, tmp);
2763 tcg_temp_free(tmp);
2764 }
2765
2766 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2767 {
2768 TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2769 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2770 }
2771
2772 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2773 {
2774 TCGv tmp = tcg_temp_new();
2775 gen_qemu_ld32s(ctx, tmp, addr);
2776 tcg_gen_ext_tl_i64(val, tmp);
2777 tcg_temp_free(tmp);
2778 }
2779
2780 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2781 {
2782 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2783 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2784 }
2785
2786 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2787 {
2788 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2789 }
2790
2791 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2792 {
2793 TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2794 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2795 }
2796
2797 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2798 {
2799 TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2800 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2801 }
2802
2803 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2804 {
2805 TCGv tmp = tcg_temp_new();
2806 tcg_gen_trunc_i64_tl(tmp, val);
2807 gen_qemu_st32(ctx, tmp, addr);
2808 tcg_temp_free(tmp);
2809 }
2810
2811 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2812 {
2813 TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2814 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2815 }
2816
2817 #define GEN_LD(name, ldop, opc, type) \
2818 static void glue(gen_, name)(DisasContext *ctx) \
2819 { \
2820 TCGv EA; \
2821 gen_set_access_type(ctx, ACCESS_INT); \
2822 EA = tcg_temp_new(); \
2823 gen_addr_imm_index(ctx, EA, 0); \
2824 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2825 tcg_temp_free(EA); \
2826 }
2827
2828 #define GEN_LDU(name, ldop, opc, type) \
2829 static void glue(gen_, name##u)(DisasContext *ctx) \
2830 { \
2831 TCGv EA; \
2832 if (unlikely(rA(ctx->opcode) == 0 || \
2833 rA(ctx->opcode) == rD(ctx->opcode))) { \
2834 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2835 return; \
2836 } \
2837 gen_set_access_type(ctx, ACCESS_INT); \
2838 EA = tcg_temp_new(); \
2839 if (type == PPC_64B) \
2840 gen_addr_imm_index(ctx, EA, 0x03); \
2841 else \
2842 gen_addr_imm_index(ctx, EA, 0); \
2843 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2844 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2845 tcg_temp_free(EA); \
2846 }
2847
2848 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2849 static void glue(gen_, name##ux)(DisasContext *ctx) \
2850 { \
2851 TCGv EA; \
2852 if (unlikely(rA(ctx->opcode) == 0 || \
2853 rA(ctx->opcode) == rD(ctx->opcode))) { \
2854 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2855 return; \
2856 } \
2857 gen_set_access_type(ctx, ACCESS_INT); \
2858 EA = tcg_temp_new(); \
2859 gen_addr_reg_index(ctx, EA); \
2860 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2861 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2862 tcg_temp_free(EA); \
2863 }
2864
2865 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2866 static void glue(gen_, name##x)(DisasContext *ctx) \
2867 { \
2868 TCGv EA; \
2869 gen_set_access_type(ctx, ACCESS_INT); \
2870 EA = tcg_temp_new(); \
2871 gen_addr_reg_index(ctx, EA); \
2872 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2873 tcg_temp_free(EA); \
2874 }
2875 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2876 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2877
2878 #define GEN_LDS(name, ldop, op, type) \
2879 GEN_LD(name, ldop, op | 0x20, type); \
2880 GEN_LDU(name, ldop, op | 0x21, type); \
2881 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2882 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2883
2884 /* lbz lbzu lbzux lbzx */
2885 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2886 /* lha lhau lhaux lhax */
2887 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2888 /* lhz lhzu lhzux lhzx */
2889 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2890 /* lwz lwzu lwzux lwzx */
2891 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2892 #if defined(TARGET_PPC64)
2893 /* lwaux */
2894 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2895 /* lwax */
2896 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2897 /* ldux */
2898 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2899 /* ldx */
2900 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2901
2902 static void gen_ld(DisasContext *ctx)
2903 {
2904 TCGv EA;
2905 if (Rc(ctx->opcode)) {
2906 if (unlikely(rA(ctx->opcode) == 0 ||
2907 rA(ctx->opcode) == rD(ctx->opcode))) {
2908 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2909 return;
2910 }
2911 }
2912 gen_set_access_type(ctx, ACCESS_INT);
2913 EA = tcg_temp_new();
2914 gen_addr_imm_index(ctx, EA, 0x03);
2915 if (ctx->opcode & 0x02) {
2916 /* lwa (lwau is undefined) */
2917 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2918 } else {
2919 /* ld - ldu */
2920 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2921 }
2922 if (Rc(ctx->opcode))
2923 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2924 tcg_temp_free(EA);
2925 }
2926
2927 /* lq */
2928 static void gen_lq(DisasContext *ctx)
2929 {
2930 int ra, rd;
2931 TCGv EA;
2932
2933 /* lq is a legal user mode instruction starting in ISA 2.07 */
2934 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2935 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2936
2937 if (!legal_in_user_mode && ctx->pr) {
2938 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2939 return;
2940 }
2941
2942 if (!le_is_supported && ctx->le_mode) {
2943 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2944 return;
2945 }
2946
2947 ra = rA(ctx->opcode);
2948 rd = rD(ctx->opcode);
2949 if (unlikely((rd & 1) || rd == ra)) {
2950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2951 return;
2952 }
2953
2954 gen_set_access_type(ctx, ACCESS_INT);
2955 EA = tcg_temp_new();
2956 gen_addr_imm_index(ctx, EA, 0x0F);
2957
2958 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2959 64-bit byteswap already. */
2960 if (unlikely(ctx->le_mode)) {
2961 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2962 gen_addr_add(ctx, EA, EA, 8);
2963 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2964 } else {
2965 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2966 gen_addr_add(ctx, EA, EA, 8);
2967 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2968 }
2969 tcg_temp_free(EA);
2970 }
2971 #endif
2972
2973 /*** Integer store ***/
2974 #define GEN_ST(name, stop, opc, type) \
2975 static void glue(gen_, name)(DisasContext *ctx) \
2976 { \
2977 TCGv EA; \
2978 gen_set_access_type(ctx, ACCESS_INT); \
2979 EA = tcg_temp_new(); \
2980 gen_addr_imm_index(ctx, EA, 0); \
2981 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2982 tcg_temp_free(EA); \
2983 }
2984
2985 #define GEN_STU(name, stop, opc, type) \
2986 static void glue(gen_, stop##u)(DisasContext *ctx) \
2987 { \
2988 TCGv EA; \
2989 if (unlikely(rA(ctx->opcode) == 0)) { \
2990 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2991 return; \
2992 } \
2993 gen_set_access_type(ctx, ACCESS_INT); \
2994 EA = tcg_temp_new(); \
2995 if (type == PPC_64B) \
2996 gen_addr_imm_index(ctx, EA, 0x03); \
2997 else \
2998 gen_addr_imm_index(ctx, EA, 0); \
2999 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3000 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3001 tcg_temp_free(EA); \
3002 }
3003
3004 #define GEN_STUX(name, stop, opc2, opc3, type) \
3005 static void glue(gen_, name##ux)(DisasContext *ctx) \
3006 { \
3007 TCGv EA; \
3008 if (unlikely(rA(ctx->opcode) == 0)) { \
3009 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3010 return; \
3011 } \
3012 gen_set_access_type(ctx, ACCESS_INT); \
3013 EA = tcg_temp_new(); \
3014 gen_addr_reg_index(ctx, EA); \
3015 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3016 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3017 tcg_temp_free(EA); \
3018 }
3019
3020 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
3021 static void glue(gen_, name##x)(DisasContext *ctx) \
3022 { \
3023 TCGv EA; \
3024 gen_set_access_type(ctx, ACCESS_INT); \
3025 EA = tcg_temp_new(); \
3026 gen_addr_reg_index(ctx, EA); \
3027 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
3028 tcg_temp_free(EA); \
3029 }
3030 #define GEN_STX(name, stop, opc2, opc3, type) \
3031 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3032
3033 #define GEN_STS(name, stop, op, type) \
3034 GEN_ST(name, stop, op | 0x20, type); \
3035 GEN_STU(name, stop, op | 0x21, type); \
3036 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
3037 GEN_STX(name, stop, 0x17, op | 0x00, type)
3038
3039 /* stb stbu stbux stbx */
3040 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3041 /* sth sthu sthux sthx */
3042 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3043 /* stw stwu stwux stwx */
3044 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3045 #if defined(TARGET_PPC64)
3046 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3047 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3048
3049 static void gen_std(DisasContext *ctx)
3050 {
3051 int rs;
3052 TCGv EA;
3053
3054 rs = rS(ctx->opcode);
3055 if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3056
3057 bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3058 bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3059
3060 if (!legal_in_user_mode && ctx->pr) {
3061 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3062 return;
3063 }
3064
3065 if (!le_is_supported && ctx->le_mode) {
3066 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3067 return;
3068 }
3069
3070 if (unlikely(rs & 1)) {
3071 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3072 return;
3073 }
3074 gen_set_access_type(ctx, ACCESS_INT);
3075 EA = tcg_temp_new();
3076 gen_addr_imm_index(ctx, EA, 0x03);
3077
3078 /* We only need to swap high and low halves. gen_qemu_st64 does
3079 necessary 64-bit byteswap already. */
3080 if (unlikely(ctx->le_mode)) {
3081 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3082 gen_addr_add(ctx, EA, EA, 8);
3083 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3084 } else {
3085 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3086 gen_addr_add(ctx, EA, EA, 8);
3087 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3088 }
3089 tcg_temp_free(EA);
3090 } else {
3091 /* std / stdu*/
3092 if (Rc(ctx->opcode)) {
3093 if (unlikely(rA(ctx->opcode) == 0)) {
3094 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3095 return;
3096 }
3097 }
3098 gen_set_access_type(ctx, ACCESS_INT);
3099 EA = tcg_temp_new();
3100 gen_addr_imm_index(ctx, EA, 0x03);
3101 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3102 if (Rc(ctx->opcode))
3103 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3104 tcg_temp_free(EA);
3105 }
3106 }
3107 #endif
3108 /*** Integer load and store with byte reverse ***/
3109
3110 /* lhbrx */
3111 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3112 {
3113 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3114 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3115 }
3116 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3117
3118 /* lwbrx */
3119 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3120 {
3121 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3122 tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3123 }
3124 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3125
3126 #if defined(TARGET_PPC64)
3127 /* ldbrx */
3128 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3129 {
3130 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3131 tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3132 }
3133 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3134 #endif /* TARGET_PPC64 */
3135
3136 /* sthbrx */
3137 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3138 {
3139 TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3140 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3141 }
3142 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3143
3144 /* stwbrx */
3145 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3146 {
3147 TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3148 tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3149 }
3150 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3151
3152 #if defined(TARGET_PPC64)
3153 /* stdbrx */
3154 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3155 {
3156 TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3157 tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3158 }
3159 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3160 #endif /* TARGET_PPC64 */
3161
3162 /*** Integer load and store multiple ***/
3163
3164 /* lmw */
3165 static void gen_lmw(DisasContext *ctx)
3166 {
3167 TCGv t0;
3168 TCGv_i32 t1;
3169 gen_set_access_type(ctx, ACCESS_INT);
3170 /* NIP cannot be restored if the memory exception comes from an helper */
3171 gen_update_nip(ctx, ctx->nip - 4);
3172 t0 = tcg_temp_new();
3173 t1 = tcg_const_i32(rD(ctx->opcode));
3174 gen_addr_imm_index(ctx, t0, 0);
3175 gen_helper_lmw(cpu_env, t0, t1);
3176 tcg_temp_free(t0);
3177 tcg_temp_free_i32(t1);
3178 }
3179
3180 /* stmw */
3181 static void gen_stmw(DisasContext *ctx)
3182 {
3183 TCGv t0;
3184 TCGv_i32 t1;
3185 gen_set_access_type(ctx, ACCESS_INT);
3186 /* NIP cannot be restored if the memory exception comes from an helper */
3187 gen_update_nip(ctx, ctx->nip - 4);
3188 t0 = tcg_temp_new();
3189 t1 = tcg_const_i32(rS(ctx->opcode));
3190 gen_addr_imm_index(ctx, t0, 0);
3191 gen_helper_stmw(cpu_env, t0, t1);
3192 tcg_temp_free(t0);
3193 tcg_temp_free_i32(t1);
3194 }
3195
3196 /*** Integer load and store strings ***/
3197
3198 /* lswi */
3199 /* PowerPC32 specification says we must generate an exception if
3200 * rA is in the range of registers to be loaded.
3201 * In an other hand, IBM says this is valid, but rA won't be loaded.
3202 * For now, I'll follow the spec...
3203 */
3204 static void gen_lswi(DisasContext *ctx)
3205 {
3206 TCGv t0;
3207 TCGv_i32 t1, t2;
3208 int nb = NB(ctx->opcode);
3209 int start = rD(ctx->opcode);
3210 int ra = rA(ctx->opcode);
3211 int nr;
3212
3213 if (nb == 0)
3214 nb = 32;
3215 nr = nb / 4;
3216 if (unlikely(((start + nr) > 32 &&
3217 start <= ra && (start + nr - 32) > ra) ||
3218 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3219 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3220 return;
3221 }
3222 gen_set_access_type(ctx, ACCESS_INT);
3223 /* NIP cannot be restored if the memory exception comes from an helper */
3224 gen_update_nip(ctx, ctx->nip - 4);
3225 t0 = tcg_temp_new();
3226 gen_addr_register(ctx, t0);
3227 t1 = tcg_const_i32(nb);
3228 t2 = tcg_const_i32(start);
3229 gen_helper_lsw(cpu_env, t0, t1, t2);
3230 tcg_temp_free(t0);
3231 tcg_temp_free_i32(t1);
3232 tcg_temp_free_i32(t2);
3233 }
3234
3235 /* lswx */
3236 static void gen_lswx(DisasContext *ctx)
3237 {
3238 TCGv t0;
3239 TCGv_i32 t1, t2, t3;
3240 gen_set_access_type(ctx, ACCESS_INT);
3241 /* NIP cannot be restored if the memory exception comes from an helper */
3242 gen_update_nip(ctx, ctx->nip - 4);
3243 t0 = tcg_temp_new();
3244 gen_addr_reg_index(ctx, t0);
3245 t1 = tcg_const_i32(rD(ctx->opcode));
3246 t2 = tcg_const_i32(rA(ctx->opcode));
3247 t3 = tcg_const_i32(rB(ctx->opcode));
3248 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3249 tcg_temp_free(t0);
3250 tcg_temp_free_i32(t1);
3251 tcg_temp_free_i32(t2);
3252 tcg_temp_free_i32(t3);
3253 }
3254
3255 /* stswi */
3256 static void gen_stswi(DisasContext *ctx)
3257 {
3258 TCGv t0;
3259 TCGv_i32 t1, t2;
3260 int nb = NB(ctx->opcode);
3261 gen_set_access_type(ctx, ACCESS_INT);
3262 /* NIP cannot be restored if the memory exception comes from an helper */
3263 gen_update_nip(ctx, ctx->nip - 4);
3264 t0 = tcg_temp_new();
3265 gen_addr_register(ctx, t0);
3266 if (nb == 0)
3267 nb = 32;
3268 t1 = tcg_const_i32(nb);
3269 t2 = tcg_const_i32(rS(ctx->opcode));
3270 gen_helper_stsw(cpu_env, t0, t1, t2);
3271 tcg_temp_free(t0);
3272 tcg_temp_free_i32(t1);
3273 tcg_temp_free_i32(t2);
3274 }
3275
3276 /* stswx */
3277 static void gen_stswx(DisasContext *ctx)
3278 {
3279 TCGv t0;
3280 TCGv_i32 t1, t2;
3281 gen_set_access_type(ctx, ACCESS_INT);
3282 /* NIP cannot be restored if the memory exception comes from an helper */
3283 gen_update_nip(ctx, ctx->nip - 4);
3284 t0 = tcg_temp_new();
3285 gen_addr_reg_index(ctx, t0);
3286 t1 = tcg_temp_new_i32();
3287 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3288 tcg_gen_andi_i32(t1, t1, 0x7F);
3289 t2 = tcg_const_i32(rS(ctx->opcode));
3290 gen_helper_stsw(cpu_env, t0, t1, t2);
3291 tcg_temp_free(t0);
3292 tcg_temp_free_i32(t1);
3293 tcg_temp_free_i32(t2);
3294 }
3295
3296 /*** Memory synchronisation ***/
3297 /* eieio */
3298 static void gen_eieio(DisasContext *ctx)
3299 {
3300 }
3301
3302 /* isync */
3303 static void gen_isync(DisasContext *ctx)
3304 {
3305 gen_stop_exception(ctx);
3306 }
3307
3308 #define LARX(name, len, loadop) \
3309 static void gen_##name(DisasContext *ctx) \
3310 { \
3311 TCGv t0; \
3312 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3313 gen_set_access_type(ctx, ACCESS_RES); \
3314 t0 = tcg_temp_local_new(); \
3315 gen_addr_reg_index(ctx, t0); \
3316 if ((len) > 1) { \
3317 gen_check_align(ctx, t0, (len)-1); \
3318 } \
3319 gen_qemu_##loadop(ctx, gpr, t0); \
3320 tcg_gen_mov_tl(cpu_reserve, t0); \
3321 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3322 tcg_temp_free(t0); \
3323 }
3324
3325 /* lwarx */
3326 LARX(lbarx, 1, ld8u);
3327 LARX(lharx, 2, ld16u);
3328 LARX(lwarx, 4, ld32u);
3329
3330
3331 #if defined(CONFIG_USER_ONLY)
3332 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3333 int reg, int size)
3334 {
3335 TCGv t0 = tcg_temp_new();
3336 uint32_t save_exception = ctx->exception;
3337
3338 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3339 tcg_gen_movi_tl(t0, (size << 5) | reg);
3340 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3341 tcg_temp_free(t0);
3342 gen_update_nip(ctx, ctx->nip-4);
3343 ctx->exception = POWERPC_EXCP_BRANCH;
3344 gen_exception(ctx, POWERPC_EXCP_STCX);
3345 ctx->exception = save_exception;
3346 }
3347 #else
3348 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3349 int reg, int size)
3350 {
3351 int l1;
3352
3353 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3354 l1 = gen_new_label();
3355 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3356 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3357 #if defined(TARGET_PPC64)
3358 if (size == 8) {
3359 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3360 } else
3361 #endif
3362 if (size == 4) {
3363 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3364 } else if (size == 2) {
3365 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3366 #if defined(TARGET_PPC64)
3367 } else if (size == 16) {
3368 TCGv gpr1, gpr2 , EA8;
3369 if (unlikely(ctx->le_mode)) {
3370 gpr1 = cpu_gpr[reg+1];
3371 gpr2 = cpu_gpr[reg];
3372 } else {
3373 gpr1 = cpu_gpr[reg];
3374 gpr2 = cpu_gpr[reg+1];
3375 }
3376 gen_qemu_st64(ctx, gpr1, EA);
3377 EA8 = tcg_temp_local_new();
3378 gen_addr_add(ctx, EA8, EA, 8);
3379 gen_qemu_st64(ctx, gpr2, EA8);
3380 tcg_temp_free(EA8);
3381 #endif
3382 } else {
3383 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3384 }
3385 gen_set_label(l1);
3386 tcg_gen_movi_tl(cpu_reserve, -1);
3387 }
3388 #endif
3389
3390 #define STCX(name, len) \
3391 static void gen_##name(DisasContext *ctx) \
3392 { \
3393 TCGv t0; \
3394 if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3395 gen_inval_exception(ctx, \
3396 POWERPC_EXCP_INVAL_INVAL); \
3397 return; \
3398 } \
3399 gen_set_access_type(ctx, ACCESS_RES); \
3400 t0 = tcg_temp_local_new(); \
3401 gen_addr_reg_index(ctx, t0); \
3402 if (len > 1) { \
3403 gen_check_align(ctx, t0, (len)-1); \
3404 } \
3405 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3406 tcg_temp_free(t0); \
3407 }
3408
3409 STCX(stbcx_, 1);
3410 STCX(sthcx_, 2);
3411 STCX(stwcx_, 4);
3412
3413 #if defined(TARGET_PPC64)
3414 /* ldarx */
3415 LARX(ldarx, 8, ld64);
3416
3417 /* lqarx */
3418 static void gen_lqarx(DisasContext *ctx)
3419 {
3420 TCGv EA;
3421 int rd = rD(ctx->opcode);
3422 TCGv gpr1, gpr2;
3423
3424 if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3425 (rd == rB(ctx->opcode)))) {
3426 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3427 return;
3428 }
3429
3430 gen_set_access_type(ctx, ACCESS_RES);
3431 EA = tcg_temp_local_new();
3432 gen_addr_reg_index(ctx, EA);
3433 gen_check_align(ctx, EA, 15);
3434 if (unlikely(ctx->le_mode)) {
3435 gpr1 = cpu_gpr[rd+1];
3436 gpr2 = cpu_gpr[rd];
3437 } else {
3438 gpr1 = cpu_gpr[rd];
3439 gpr2 = cpu_gpr[rd+1];
3440 }
3441 gen_qemu_ld64(ctx, gpr1, EA);
3442 tcg_gen_mov_tl(cpu_reserve, EA);
3443
3444 gen_addr_add(ctx, EA, EA, 8);
3445 gen_qemu_ld64(ctx, gpr2, EA);
3446
3447 tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3448 tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3449
3450 tcg_temp_free(EA);
3451 }
3452
3453 /* stdcx. */
3454 STCX(stdcx_, 8);
3455 STCX(stqcx_, 16);
3456 #endif /* defined(TARGET_PPC64) */
3457
3458 /* sync */
3459 static void gen_sync(DisasContext *ctx)
3460 {
3461 }
3462
3463 /* wait */
3464 static void gen_wait(DisasContext *ctx)
3465 {
3466 TCGv_i32 t0 = tcg_temp_new_i32();
3467 tcg_gen_st_i32(t0, cpu_env,
3468 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3469 tcg_temp_free_i32(t0);
3470 /* Stop translation, as the CPU is supposed to sleep from now */
3471 gen_exception_err(ctx, EXCP_HLT, 1);
3472 }
3473
3474 /*** Floating-point load ***/
3475 #define GEN_LDF(name, ldop, opc, type) \
3476 static void glue(gen_, name)(DisasContext *ctx) \
3477 { \
3478 TCGv EA; \
3479 if (unlikely(!ctx->fpu_enabled)) { \
3480 gen_exception(ctx, POWERPC_EXCP_FPU); \
3481 return; \
3482 } \
3483 gen_set_access_type(ctx, ACCESS_FLOAT); \
3484 EA = tcg_temp_new(); \
3485 gen_addr_imm_index(ctx, EA, 0); \
3486 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3487 tcg_temp_free(EA); \
3488 }
3489
3490 #define GEN_LDUF(name, ldop, opc, type) \
3491 static void glue(gen_, name##u)(DisasContext *ctx) \
3492 { \
3493 TCGv EA; \
3494 if (unlikely(!ctx->fpu_enabled)) { \
3495 gen_exception(ctx, POWERPC_EXCP_FPU); \
3496 return; \
3497 } \
3498 if (unlikely(rA(ctx->opcode) == 0)) { \
3499 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3500 return; \
3501 } \
3502 gen_set_access_type(ctx, ACCESS_FLOAT); \
3503 EA = tcg_temp_new(); \
3504 gen_addr_imm_index(ctx, EA, 0); \
3505 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3506 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3507 tcg_temp_free(EA); \
3508 }
3509
3510 #define GEN_LDUXF(name, ldop, opc, type) \
3511 static void glue(gen_, name##ux)(DisasContext *ctx) \
3512 { \
3513 TCGv EA; \
3514 if (unlikely(!ctx->fpu_enabled)) { \
3515 gen_exception(ctx, POWERPC_EXCP_FPU); \
3516 return; \
3517 } \
3518 if (unlikely(rA(ctx->opcode) == 0)) { \
3519 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3520 return; \
3521 } \
3522 gen_set_access_type(ctx, ACCESS_FLOAT); \
3523 EA = tcg_temp_new(); \
3524 gen_addr_reg_index(ctx, EA); \
3525 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3526 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3527 tcg_temp_free(EA); \
3528 }
3529
3530 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3531 static void glue(gen_, name##x)(DisasContext *ctx) \
3532 { \
3533 TCGv EA; \
3534 if (unlikely(!ctx->fpu_enabled)) { \
3535 gen_exception(ctx, POWERPC_EXCP_FPU); \
3536 return; \
3537 } \
3538 gen_set_access_type(ctx, ACCESS_FLOAT); \
3539 EA = tcg_temp_new(); \
3540 gen_addr_reg_index(ctx, EA); \
3541 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3542 tcg_temp_free(EA); \
3543 }
3544
3545 #define GEN_LDFS(name, ldop, op, type) \
3546 GEN_LDF(name, ldop, op | 0x20, type); \
3547 GEN_LDUF(name, ldop, op | 0x21, type); \
3548 GEN_LDUXF(name, ldop, op | 0x01, type); \
3549 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3550
3551 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3552 {
3553 TCGv t0 = tcg_temp_new();
3554 TCGv_i32 t1 = tcg_temp_new_i32();
3555 gen_qemu_ld32u(ctx, t0, arg2);
3556 tcg_gen_trunc_tl_i32(t1, t0);
3557 tcg_temp_free(t0);
3558 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3559 tcg_temp_free_i32(t1);
3560 }
3561
3562 /* lfd lfdu lfdux lfdx */
3563 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3564 /* lfs lfsu lfsux lfsx */
3565 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3566
3567 /* lfdp */
3568 static void gen_lfdp(DisasContext *ctx)
3569 {
3570 TCGv EA;
3571 if (unlikely(!ctx->fpu_enabled)) {
3572 gen_exception(ctx, POWERPC_EXCP_FPU);
3573 return;
3574 }
3575 gen_set_access_type(ctx, ACCESS_FLOAT);
3576 EA = tcg_temp_new();
3577 gen_addr_imm_index(ctx, EA, 0);
3578 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3579 64-bit byteswap already. */
3580 if (unlikely(ctx->le_mode)) {
3581 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3582 tcg_gen_addi_tl(EA, EA, 8);
3583 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3584 } else {
3585 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3586 tcg_gen_addi_tl(EA, EA, 8);
3587 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3588 }
3589 tcg_temp_free(EA);
3590 }
3591
3592 /* lfdpx */
3593 static void gen_lfdpx(DisasContext *ctx)
3594 {
3595 TCGv EA;
3596 if (unlikely(!ctx->fpu_enabled)) {
3597 gen_exception(ctx, POWERPC_EXCP_FPU);
3598 return;
3599 }
3600 gen_set_access_type(ctx, ACCESS_FLOAT);
3601 EA = tcg_temp_new();
3602 gen_addr_reg_index(ctx, EA);
3603 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3604 64-bit byteswap already. */
3605 if (unlikely(ctx->le_mode)) {
3606 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3607 tcg_gen_addi_tl(EA, EA, 8);
3608 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3609 } else {
3610 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3611 tcg_gen_addi_tl(EA, EA, 8);
3612 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3613 }
3614 tcg_temp_free(EA);
3615 }
3616
3617 /* lfiwax */
3618 static void gen_lfiwax(DisasContext *ctx)
3619 {
3620 TCGv EA;
3621 TCGv t0;
3622 if (unlikely(!ctx->fpu_enabled)) {
3623 gen_exception(ctx, POWERPC_EXCP_FPU);
3624 return;
3625 }
3626 gen_set_access_type(ctx, ACCESS_FLOAT);
3627 EA = tcg_temp_new();
3628 t0 = tcg_temp_new();
3629 gen_addr_reg_index(ctx, EA);
3630 gen_qemu_ld32s(ctx, t0, EA);
3631 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3632 tcg_temp_free(EA);
3633 tcg_temp_free(t0);
3634 }
3635
3636 /* lfiwzx */
3637 static void gen_lfiwzx(DisasContext *ctx)
3638 {
3639 TCGv EA;
3640 if (unlikely(!ctx->fpu_enabled)) {
3641 gen_exception(ctx, POWERPC_EXCP_FPU);
3642 return;
3643 }
3644 gen_set_access_type(ctx, ACCESS_FLOAT);
3645 EA = tcg_temp_new();
3646 gen_addr_reg_index(ctx, EA);
3647 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3648 tcg_temp_free(EA);
3649 }
3650 /*** Floating-point store ***/
3651 #define GEN_STF(name, stop, opc, type) \
3652 static void glue(gen_, name)(DisasContext *ctx) \
3653 { \
3654 TCGv EA; \
3655 if (unlikely(!ctx->fpu_enabled)) { \
3656 gen_exception(ctx, POWERPC_EXCP_FPU); \
3657 return; \
3658 } \
3659 gen_set_access_type(ctx, ACCESS_FLOAT); \
3660 EA = tcg_temp_new(); \
3661 gen_addr_imm_index(ctx, EA, 0); \
3662 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3663 tcg_temp_free(EA); \
3664 }
3665
3666 #define GEN_STUF(name, stop, opc, type) \
3667 static void glue(gen_, name##u)(DisasContext *ctx) \
3668 { \
3669 TCGv EA; \
3670 if (unlikely(!ctx->fpu_enabled)) { \
3671 gen_exception(ctx, POWERPC_EXCP_FPU); \
3672 return; \
3673 } \
3674 if (unlikely(rA(ctx->opcode) == 0)) { \
3675 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3676 return; \
3677 } \
3678 gen_set_access_type(ctx, ACCESS_FLOAT); \
3679 EA = tcg_temp_new(); \
3680 gen_addr_imm_index(ctx, EA, 0); \
3681 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3682 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3683 tcg_temp_free(EA); \
3684 }
3685
3686 #define GEN_STUXF(name, stop, opc, type) \
3687 static void glue(gen_, name##ux)(DisasContext *ctx) \
3688 { \
3689 TCGv EA; \
3690 if (unlikely(!ctx->fpu_enabled)) { \
3691 gen_exception(ctx, POWERPC_EXCP_FPU); \
3692 return; \
3693 } \
3694 if (unlikely(rA(ctx->opcode) == 0)) { \
3695 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3696 return; \
3697 } \
3698 gen_set_access_type(ctx, ACCESS_FLOAT); \
3699 EA = tcg_temp_new(); \
3700 gen_addr_reg_index(ctx, EA); \
3701 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3702 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3703 tcg_temp_free(EA); \
3704 }
3705
3706 #define GEN_STXF(name, stop, opc2, opc3, type) \
3707 static void glue(gen_, name##x)(DisasContext *ctx) \
3708 { \
3709 TCGv EA; \
3710 if (unlikely(!ctx->fpu_enabled)) { \
3711 gen_exception(ctx, POWERPC_EXCP_FPU); \
3712 return; \
3713 } \
3714 gen_set_access_type(ctx, ACCESS_FLOAT); \
3715 EA = tcg_temp_new(); \
3716 gen_addr_reg_index(ctx, EA); \
3717 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3718 tcg_temp_free(EA); \
3719 }
3720
3721 #define GEN_STFS(name, stop, op, type) \
3722 GEN_STF(name, stop, op | 0x20, type); \
3723 GEN_STUF(name, stop, op | 0x21, type); \
3724 GEN_STUXF(name, stop, op | 0x01, type); \
3725 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3726
3727 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3728 {
3729 TCGv_i32 t0 = tcg_temp_new_i32();
3730 TCGv t1 = tcg_temp_new();
3731 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3732 tcg_gen_extu_i32_tl(t1, t0);
3733 tcg_temp_free_i32(t0);
3734 gen_qemu_st32(ctx, t1, arg2);
3735 tcg_temp_free(t1);
3736 }
3737
3738 /* stfd stfdu stfdux stfdx */
3739 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3740 /* stfs stfsu stfsux stfsx */
3741 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3742
3743 /* stfdp */
3744 static void gen_stfdp(DisasContext *ctx)
3745 {
3746 TCGv EA;
3747 if (unlikely(!ctx->fpu_enabled)) {
3748 gen_exception(ctx, POWERPC_EXCP_FPU);
3749 return;
3750 }
3751 gen_set_access_type(ctx, ACCESS_FLOAT);
3752 EA = tcg_temp_new();
3753 gen_addr_imm_index(ctx, EA, 0);
3754 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3755 64-bit byteswap already. */
3756 if (unlikely(ctx->le_mode)) {
3757 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3758 tcg_gen_addi_tl(EA, EA, 8);
3759 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3760 } else {
3761 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3762 tcg_gen_addi_tl(EA, EA, 8);
3763 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3764 }
3765 tcg_temp_free(EA);
3766 }
3767
3768 /* stfdpx */
3769 static void gen_stfdpx(DisasContext *ctx)
3770 {
3771 TCGv EA;
3772 if (unlikely(!ctx->fpu_enabled)) {
3773 gen_exception(ctx, POWERPC_EXCP_FPU);
3774 return;
3775 }
3776 gen_set_access_type(ctx, ACCESS_FLOAT);
3777 EA = tcg_temp_new();
3778 gen_addr_reg_index(ctx, EA);
3779 /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3780 64-bit byteswap already. */
3781 if (unlikely(ctx->le_mode)) {
3782 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3783 tcg_gen_addi_tl(EA, EA, 8);
3784 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3785 } else {
3786 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3787 tcg_gen_addi_tl(EA, EA, 8);
3788 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3789 }
3790 tcg_temp_free(EA);
3791 }
3792
3793 /* Optional: */
3794 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3795 {
3796 TCGv t0 = tcg_temp_new();
3797 tcg_gen_trunc_i64_tl(t0, arg1),
3798 gen_qemu_st32(ctx, t0, arg2);
3799 tcg_temp_free(t0);
3800 }
3801 /* stfiwx */
3802 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3803
3804 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3805 {
3806 #if defined(TARGET_PPC64)
3807 if (ctx->has_cfar)
3808 tcg_gen_movi_tl(cpu_cfar, nip);
3809 #endif
3810 }
3811
3812 /*** Branch ***/
3813 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3814 {
3815 TranslationBlock *tb;
3816 tb = ctx->tb;
3817 if (NARROW_MODE(ctx)) {
3818 dest = (uint32_t) dest;
3819 }
3820 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3821 likely(!ctx->singlestep_enabled)) {
3822 tcg_gen_goto_tb(n);
3823 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3824 tcg_gen_exit_tb((uintptr_t)tb + n);
3825 } else {
3826 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3827 if (unlikely(ctx->singlestep_enabled)) {
3828 if ((ctx->singlestep_enabled &
3829 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3830 (ctx->exception == POWERPC_EXCP_BRANCH ||
3831 ctx->exception == POWERPC_EXCP_TRACE)) {
3832 target_ulong tmp = ctx->nip;
3833 ctx->nip = dest;
3834 gen_exception(ctx, POWERPC_EXCP_TRACE);
3835 ctx->nip = tmp;
3836 }
3837 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3838 gen_debug_exception(ctx);
3839 }
3840 }
3841 tcg_gen_exit_tb(0);
3842 }
3843 }
3844
3845 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3846 {
3847 if (NARROW_MODE(ctx)) {
3848 nip = (uint32_t)nip;
3849 }
3850 tcg_gen_movi_tl(cpu_lr, nip);
3851 }
3852
3853 /* b ba bl bla */
3854 static void gen_b(DisasContext *ctx)
3855 {
3856 target_ulong li, target;
3857
3858 ctx->exception = POWERPC_EXCP_BRANCH;
3859 /* sign extend LI */
3860 li = LI(ctx->opcode);
3861 li = (li ^ 0x02000000) - 0x02000000;
3862 if (likely(AA(ctx->opcode) == 0)) {
3863 target = ctx->nip + li - 4;
3864 } else {
3865 target = li;
3866 }
3867 if (LK(ctx->opcode)) {
3868 gen_setlr(ctx, ctx->nip);
3869 }
3870 gen_update_cfar(ctx, ctx->nip);
3871 gen_goto_tb(ctx, 0, target);
3872 }
3873
3874 #define BCOND_IM 0
3875 #define BCOND_LR 1
3876 #define BCOND_CTR 2
3877 #define BCOND_TAR 3
3878
3879 static inline void gen_bcond(DisasContext *ctx, int type)
3880 {
3881 uint32_t bo = BO(ctx->opcode);
3882 int l1;
3883 TCGv target;
3884
3885 ctx->exception = POWERPC_EXCP_BRANCH;
3886 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3887 target = tcg_temp_local_new();
3888 if (type == BCOND_CTR)
3889 tcg_gen_mov_tl(target, cpu_ctr);
3890 else if (type == BCOND_TAR)
3891 gen_load_spr(target, SPR_TAR);
3892 else
3893 tcg_gen_mov_tl(target, cpu_lr);
3894 } else {
3895 TCGV_UNUSED(target);
3896 }
3897 if (LK(ctx->opcode))
3898 gen_setlr(ctx, ctx->nip);
3899 l1 = gen_new_label();
3900 if ((bo & 0x4) == 0) {
3901 /* Decrement and test CTR */
3902 TCGv temp = tcg_temp_new();
3903 if (unlikely(type == BCOND_CTR)) {
3904 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3905 return;
3906 }
3907 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3908 if (NARROW_MODE(ctx)) {
3909 tcg_gen_ext32u_tl(temp, cpu_ctr);
3910 } else {
3911 tcg_gen_mov_tl(temp, cpu_ctr);
3912 }
3913 if (bo & 0x2) {
3914 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3915 } else {
3916 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3917 }
3918 tcg_temp_free(temp);
3919 }
3920 if ((bo & 0x10) == 0) {
3921 /* Test CR */
3922 uint32_t bi = BI(ctx->opcode);
3923 uint32_t mask = 0x08 >> (bi & 0x03);
3924 TCGv_i32 temp = tcg_temp_new_i32();
3925
3926 if (bo & 0x8) {
3927 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3928 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3929 } else {
3930 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3931 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3932 }
3933 tcg_temp_free_i32(temp);
3934 }
3935 gen_update_cfar(ctx, ctx->nip);
3936 if (type == BCOND_IM) {
3937 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3938 if (likely(AA(ctx->opcode) == 0)) {
3939 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3940 } else {
3941 gen_goto_tb(ctx, 0, li);
3942 }
3943 gen_set_label(l1);
3944 gen_goto_tb(ctx, 1, ctx->nip);
3945 } else {
3946 if (NARROW_MODE(ctx)) {
3947 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3948 } else {
3949 tcg_gen_andi_tl(cpu_nip, target, ~3);
3950 }
3951 tcg_gen_exit_tb(0);
3952 gen_set_label(l1);
3953 gen_update_nip(ctx, ctx->nip);
3954 tcg_gen_exit_tb(0);
3955 }
3956 if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3957 tcg_temp_free(target);
3958 }
3959 }
3960
3961 static void gen_bc(DisasContext *ctx)
3962 {
3963 gen_bcond(ctx, BCOND_IM);
3964 }
3965
3966 static void gen_bcctr(DisasContext *ctx)
3967 {
3968 gen_bcond(ctx, BCOND_CTR);
3969 }
3970
3971 static void gen_bclr(DisasContext *ctx)
3972 {
3973 gen_bcond(ctx, BCOND_LR);
3974 }
3975
3976 static void gen_bctar(DisasContext *ctx)
3977 {
3978 gen_bcond(ctx, BCOND_TAR);
3979 }
3980
3981 /*** Condition register logical ***/
3982 #define GEN_CRLOGIC(name, tcg_op, opc) \
3983 static void glue(gen_, name)(DisasContext *ctx) \
3984 { \
3985 uint8_t bitmask; \
3986 int sh; \
3987 TCGv_i32 t0, t1; \
3988 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3989 t0 = tcg_temp_new_i32(); \
3990 if (sh > 0) \
3991 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3992 else if (sh < 0) \
3993 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3994 else \
3995 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3996 t1 = tcg_temp_new_i32(); \
3997 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3998 if (sh > 0) \
3999 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
4000 else if (sh < 0) \
4001 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
4002 else \
4003 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
4004 tcg_op(t0, t0, t1); \
4005 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
4006 tcg_gen_andi_i32(t0, t0, bitmask); \
4007 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
4008 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
4009 tcg_temp_free_i32(t0); \
4010 tcg_temp_free_i32(t1); \
4011 }
4012
4013 /* crand */
4014 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4015 /* crandc */
4016 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4017 /* creqv */
4018 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4019 /* crnand */
4020 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4021 /* crnor */
4022 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4023 /* cror */
4024 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4025 /* crorc */
4026 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4027 /* crxor */
4028 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4029
4030 /* mcrf */
4031 static void gen_mcrf(DisasContext *ctx)
4032 {
4033 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4034 }
4035
4036 /*** System linkage ***/
4037
4038 /* rfi (supervisor only) */
4039 static void gen_rfi(DisasContext *ctx)
4040 {
4041 #if defined(CONFIG_USER_ONLY)
4042 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4043 #else
4044 /* Restore CPU state */
4045 if (unlikely(ctx->pr)) {
4046 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4047 return;
4048 }
4049 gen_update_cfar(ctx, ctx->nip);
4050 gen_helper_rfi(cpu_env);
4051 gen_sync_exception(ctx);
4052 #endif
4053 }
4054
4055 #if defined(TARGET_PPC64)
4056 static void gen_rfid(DisasContext *ctx)
4057 {
4058 #if defined(CONFIG_USER_ONLY)
4059 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4060 #else
4061 /* Restore CPU state */
4062 if (unlikely(ctx->pr)) {
4063 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4064 return;
4065 }
4066 gen_update_cfar(ctx, ctx->nip);
4067 gen_helper_rfid(cpu_env);
4068 gen_sync_exception(ctx);
4069 #endif
4070 }
4071
4072 static void gen_hrfid(DisasContext *ctx)
4073 {
4074 #if defined(CONFIG_USER_ONLY)
4075 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4076 #else
4077 /* Restore CPU state */
4078 if (unlikely(!ctx->hv)) {
4079 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4080 return;
4081 }
4082 gen_helper_hrfid(cpu_env);
4083 gen_sync_exception(ctx);
4084 #endif
4085 }
4086 #endif
4087
4088 /* sc */
4089 #if defined(CONFIG_USER_ONLY)
4090 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4091 #else
4092 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4093 #endif
4094 static void gen_sc(DisasContext *ctx)
4095 {
4096 uint32_t lev;
4097
4098 lev = (ctx->opcode >> 5) & 0x7F;
4099 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4100 }
4101
4102 /*** Trap ***/
4103
4104 /* tw */
4105 static void gen_tw(DisasContext *ctx)
4106 {
4107 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4108 /* Update the nip since this might generate a trap exception */
4109 gen_update_nip(ctx, ctx->nip);
4110 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4111 t0);
4112 tcg_temp_free_i32(t0);
4113 }
4114
4115 /* twi */
4116 static void gen_twi(DisasContext *ctx)
4117 {
4118 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4119 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4120 /* Update the nip since this might generate a trap exception */
4121 gen_update_nip(ctx, ctx->nip);
4122 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4123 tcg_temp_free(t0);
4124 tcg_temp_free_i32(t1);
4125 }
4126
4127 #if defined(TARGET_PPC64)
4128 /* td */
4129 static void gen_td(DisasContext *ctx)
4130 {
4131 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4132 /* Update the nip since this might generate a trap exception */
4133 gen_update_nip(ctx, ctx->nip);
4134 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4135 t0);
4136 tcg_temp_free_i32(t0);
4137 }
4138
4139 /* tdi */
4140 static void gen_tdi(DisasContext *ctx)
4141 {
4142 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4143 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4144 /* Update the nip since this might generate a trap exception */
4145 gen_update_nip(ctx, ctx->nip);
4146 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4147 tcg_temp_free(t0);
4148 tcg_temp_free_i32(t1);
4149 }
4150 #endif
4151
4152 /*** Processor control ***/
4153
4154 static void gen_read_xer(TCGv dst)
4155 {
4156 TCGv t0 = tcg_temp_new();
4157 TCGv t1 = tcg_temp_new();
4158 TCGv t2 = tcg_temp_new();
4159 tcg_gen_mov_tl(dst, cpu_xer);
4160 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4161 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4162 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4163 tcg_gen_or_tl(t0, t0, t1);
4164 tcg_gen_or_tl(dst, dst, t2);
4165 tcg_gen_or_tl(dst, dst, t0);
4166 tcg_temp_free(t0);
4167 tcg_temp_free(t1);
4168 tcg_temp_free(t2);
4169 }
4170
4171 static void gen_write_xer(TCGv src)
4172 {
4173 tcg_gen_andi_tl(cpu_xer, src,
4174 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4175 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4176 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4177 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4178 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4179 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4180 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4181 }
4182
4183 /* mcrxr */
4184 static void gen_mcrxr(DisasContext *ctx)
4185 {
4186 TCGv_i32 t0 = tcg_temp_new_i32();
4187 TCGv_i32 t1 = tcg_temp_new_i32();
4188 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4189
4190 tcg_gen_trunc_tl_i32(t0, cpu_so);
4191 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4192 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4193 tcg_gen_shli_i32(t0, t0, 3);
4194 tcg_gen_shli_i32(t1, t1, 2);
4195 tcg_gen_shli_i32(dst, dst, 1);
4196 tcg_gen_or_i32(dst, dst, t0);
4197 tcg_gen_or_i32(dst, dst, t1);
4198 tcg_temp_free_i32(t0);
4199 tcg_temp_free_i32(t1);
4200
4201 tcg_gen_movi_tl(cpu_so, 0);
4202 tcg_gen_movi_tl(cpu_ov, 0);
4203 tcg_gen_movi_tl(cpu_ca, 0);
4204 }
4205
4206 /* mfcr mfocrf */
4207 static void gen_mfcr(DisasContext *ctx)
4208 {
4209 uint32_t crm, crn;
4210
4211 if (likely(ctx->opcode & 0x00100000)) {
4212 crm = CRM(ctx->opcode);
4213 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4214 crn = ctz32 (crm);
4215 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4216 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4217 cpu_gpr[rD(ctx->opcode)], crn * 4);
4218 }
4219 } else {
4220 TCGv_i32 t0 = tcg_temp_new_i32();
4221 tcg_gen_mov_i32(t0, cpu_crf[0]);
4222 tcg_gen_shli_i32(t0, t0, 4);
4223 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4224 tcg_gen_shli_i32(t0, t0, 4);
4225 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4226 tcg_gen_shli_i32(t0, t0, 4);
4227 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4228 tcg_gen_shli_i32(t0, t0, 4);
4229 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4230 tcg_gen_shli_i32(t0, t0, 4);
4231 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4232 tcg_gen_shli_i32(t0, t0, 4);
4233 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4234 tcg_gen_shli_i32(t0, t0, 4);
4235 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4236 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4237 tcg_temp_free_i32(t0);
4238 }
4239 }
4240
4241 /* mfmsr */
4242 static void gen_mfmsr(DisasContext *ctx)
4243 {
4244 #if defined(CONFIG_USER_ONLY)
4245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4246 #else
4247 if (unlikely(ctx->pr)) {
4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4249 return;
4250 }
4251 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4252 #endif
4253 }
4254
4255 static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4256 {
4257 #if 0
4258 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4259 printf("ERROR: try to access SPR %d !\n", sprn);
4260 #endif
4261 }
4262 #define SPR_NOACCESS (&spr_noaccess)
4263
4264 /* mfspr */
4265 static inline void gen_op_mfspr(DisasContext *ctx)
4266 {
4267 void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4268 uint32_t sprn = SPR(ctx->opcode);
4269
4270 #if !defined(CONFIG_USER_ONLY)
4271 if (ctx->hv)
4272 read_cb = ctx->spr_cb[sprn].hea_read;
4273 else if (!ctx->pr)
4274 read_cb = ctx->spr_cb[sprn].oea_read;
4275 else
4276 #endif
4277 read_cb = ctx->spr_cb[sprn].uea_read;
4278 if (likely(read_cb != NULL)) {
4279 if (likely(read_cb != SPR_NOACCESS)) {
4280 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4281 } else {
4282 /* Privilege exception */
4283 /* This is a hack to avoid warnings when running Linux:
4284 * this OS breaks the PowerPC virtualisation model,
4285 * allowing userland application to read the PVR
4286 */
4287 if (sprn != SPR_PVR) {
4288 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4289 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4290 printf("Trying to read privileged spr %d (0x%03x) at "
4291 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4292 }
4293 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4294 }
4295 } else {
4296 /* Not defined */
4297 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4298 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4299 printf("Trying to read invalid spr %d (0x%03x) at "
4300 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4301 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4302 }
4303 }
4304
4305 static void gen_mfspr(DisasContext *ctx)
4306 {
4307 gen_op_mfspr(ctx);
4308 }
4309
4310 /* mftb */
4311 static void gen_mftb(DisasContext *ctx)
4312 {
4313 gen_op_mfspr(ctx);
4314 }
4315
4316 /* mtcrf mtocrf*/
4317 static void gen_mtcrf(DisasContext *ctx)
4318 {
4319 uint32_t crm, crn;
4320
4321 crm = CRM(ctx->opcode);
4322 if (likely((ctx->opcode & 0x00100000))) {
4323 if (crm && ((crm & (crm - 1)) == 0)) {
4324 TCGv_i32 temp = tcg_temp_new_i32();
4325 crn = ctz32 (crm);
4326 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4327 tcg_gen_shri_i32(temp, temp, crn * 4);
4328 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4329 tcg_temp_free_i32(temp);
4330 }
4331 } else {
4332 TCGv_i32 temp = tcg_temp_new_i32();
4333 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4334 for (crn = 0 ; crn < 8 ; crn++) {
4335 if (crm & (1 << crn)) {
4336 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4337 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4338 }
4339 }
4340 tcg_temp_free_i32(temp);
4341 }
4342 }
4343
4344 /* mtmsr */
4345 #if defined(TARGET_PPC64)
4346 static void gen_mtmsrd(DisasContext *ctx)
4347 {
4348 #if defined(CONFIG_USER_ONLY)
4349 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4350 #else
4351 if (unlikely(ctx->pr)) {
4352 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4353 return;
4354 }
4355 if (ctx->opcode & 0x00010000) {
4356 /* Special form that does not need any synchronisation */
4357 TCGv t0 = tcg_temp_new();
4358 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4359 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4360 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4361 tcg_temp_free(t0);
4362 } else {
4363 /* XXX: we need to update nip before the store
4364 * if we enter power saving mode, we will exit the loop
4365 * directly from ppc_store_msr
4366 */
4367 gen_update_nip(ctx, ctx->nip);
4368 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4369 /* Must stop the translation as machine state (may have) changed */
4370 /* Note that mtmsr is not always defined as context-synchronizing */
4371 gen_stop_exception(ctx);
4372 }
4373 #endif
4374 }
4375 #endif
4376
4377 static void gen_mtmsr(DisasContext *ctx)
4378 {
4379 #if defined(CONFIG_USER_ONLY)
4380 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4381 #else
4382 if (unlikely(ctx->pr)) {
4383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4384 return;
4385 }
4386 if (ctx->opcode & 0x00010000) {
4387 /* Special form that does not need any synchronisation */
4388 TCGv t0 = tcg_temp_new();
4389 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4390 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4391 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4392 tcg_temp_free(t0);
4393 } else {
4394 TCGv msr = tcg_temp_new();
4395
4396 /* XXX: we need to update nip before the store
4397 * if we enter power saving mode, we will exit the loop
4398 * directly from ppc_store_msr
4399 */
4400 gen_update_nip(ctx, ctx->nip);
4401 #if defined(TARGET_PPC64)
4402 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4403 #else
4404 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4405 #endif
4406 gen_helper_store_msr(cpu_env, msr);
4407 tcg_temp_free(msr);
4408 /* Must stop the translation as machine state (may have) changed */
4409 /* Note that mtmsr is not always defined as context-synchronizing */
4410 gen_stop_exception(ctx);
4411 }
4412 #endif
4413 }
4414
4415 /* mtspr */
4416 static void gen_mtspr(DisasContext *ctx)
4417 {
4418 void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4419 uint32_t sprn = SPR(ctx->opcode);
4420
4421 #if !defined(CONFIG_USER_ONLY)
4422 if (ctx->hv)
4423 write_cb = ctx->spr_cb[sprn].hea_write;
4424 else if (!ctx->pr)
4425 write_cb = ctx->spr_cb[sprn].oea_write;
4426 else
4427 #endif
4428 write_cb = ctx->spr_cb[sprn].uea_write;
4429 if (likely(write_cb != NULL)) {
4430 if (likely(write_cb != SPR_NOACCESS)) {
4431 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4432 } else {
4433 /* Privilege exception */
4434 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4435 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4436 printf("Trying to write privileged spr %d (0x%03x) at "
4437 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4439 }
4440 } else {
4441 /* Not defined */
4442 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4443 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4444 printf("Trying to write invalid spr %d (0x%03x) at "
4445 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4446 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4447 }
4448 }
4449
4450 /*** Cache management ***/
4451
4452 /* dcbf */
4453 static void gen_dcbf(DisasContext *ctx)
4454 {
4455 /* XXX: specification says this is treated as a load by the MMU */
4456 TCGv t0;
4457 gen_set_access_type(ctx, ACCESS_CACHE);
4458 t0 = tcg_temp_new();
4459 gen_addr_reg_index(ctx, t0);
4460 gen_qemu_ld8u(ctx, t0, t0);
4461 tcg_temp_free(t0);
4462 }
4463
4464 /* dcbi (Supervisor only) */
4465 static void gen_dcbi(DisasContext *ctx)
4466 {
4467 #if defined(CONFIG_USER_ONLY)
4468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4469 #else
4470 TCGv EA, val;
4471 if (unlikely(ctx->pr)) {
4472 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4473 return;
4474 }
4475 EA = tcg_temp_new();
4476 gen_set_access_type(ctx, ACCESS_CACHE);
4477 gen_addr_reg_index(ctx, EA);
4478 val = tcg_temp_new();
4479 /* XXX: specification says this should be treated as a store by the MMU */
4480 gen_qemu_ld8u(ctx, val, EA);
4481 gen_qemu_st8(ctx, val, EA);
4482 tcg_temp_free(val);
4483 tcg_temp_free(EA);
4484 #endif
4485 }
4486
4487 /* dcdst */
4488 static void gen_dcbst(DisasContext *ctx)
4489 {
4490 /* XXX: specification say this is treated as a load by the MMU */
4491 TCGv t0;
4492 gen_set_access_type(ctx, ACCESS_CACHE);
4493 t0 = tcg_temp_new();
4494 gen_addr_reg_index(ctx, t0);
4495 gen_qemu_ld8u(ctx, t0, t0);
4496 tcg_temp_free(t0);
4497 }
4498
4499 /* dcbt */
4500 static void gen_dcbt(DisasContext *ctx)
4501 {
4502 /* interpreted as no-op */
4503 /* XXX: specification say this is treated as a load by the MMU
4504 * but does not generate any exception
4505 */
4506 }
4507
4508 /* dcbtst */
4509 static void gen_dcbtst(DisasContext *ctx)
4510 {
4511 /* interpreted as no-op */
4512 /* XXX: specification say this is treated as a load by the MMU
4513 * but does not generate any exception
4514 */
4515 }
4516
4517 /* dcbtls */
4518 static void gen_dcbtls(DisasContext *ctx)
4519 {
4520 /* Always fails locking the cache */
4521 TCGv t0 = tcg_temp_new();
4522 gen_load_spr(t0, SPR_Exxx_L1CSR0);
4523 tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4524 gen_store_spr(SPR_Exxx_L1CSR0, t0);
4525 tcg_temp_free(t0);
4526 }
4527
4528 /* dcbz */
4529 static void gen_dcbz(DisasContext *ctx)
4530 {
4531 TCGv tcgv_addr;
4532 TCGv_i32 tcgv_is_dcbzl;
4533 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4534
4535 gen_set_access_type(ctx, ACCESS_CACHE);
4536 /* NIP cannot be restored if the memory exception comes from an helper */
4537 gen_update_nip(ctx, ctx->nip - 4);
4538 tcgv_addr = tcg_temp_new();
4539 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4540
4541 gen_addr_reg_index(ctx, tcgv_addr);
4542 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4543
4544 tcg_temp_free(tcgv_addr);
4545 tcg_temp_free_i32(tcgv_is_dcbzl);
4546 }
4547
4548 /* dst / dstt */
4549 static void gen_dst(DisasContext *ctx)
4550 {
4551 if (rA(ctx->opcode) == 0) {
4552 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4553 } else {
4554 /* interpreted as no-op */
4555 }
4556 }
4557
4558 /* dstst /dststt */
4559 static void gen_dstst(DisasContext *ctx)
4560 {
4561 if (rA(ctx->opcode) == 0) {
4562 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4563 } else {
4564 /* interpreted as no-op */
4565 }
4566
4567 }
4568
4569 /* dss / dssall */
4570 static void gen_dss(DisasContext *ctx)
4571 {
4572 /* interpreted as no-op */
4573 }
4574
4575 /* icbi */
4576 static void gen_icbi(DisasContext *ctx)
4577 {
4578 TCGv t0;
4579 gen_set_access_type(ctx, ACCESS_CACHE);
4580 /* NIP cannot be restored if the memory exception comes from an helper */
4581 gen_update_nip(ctx, ctx->nip - 4);
4582 t0 = tcg_temp_new();
4583 gen_addr_reg_index(ctx, t0);
4584 gen_helper_icbi(cpu_env, t0);
4585 tcg_temp_free(t0);
4586 }
4587
4588 /* Optional: */
4589 /* dcba */
4590 static void gen_dcba(DisasContext *ctx)
4591 {
4592 /* interpreted as no-op */
4593 /* XXX: specification say this is treated as a store by the MMU
4594 * but does not generate any exception
4595 */
4596 }
4597
4598 /*** Segment register manipulation ***/
4599 /* Supervisor only: */
4600
4601 /* mfsr */
4602 static void gen_mfsr(DisasContext *ctx)
4603 {
4604 #if defined(CONFIG_USER_ONLY)
4605 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4606 #else
4607 TCGv t0;
4608 if (unlikely(ctx->pr)) {
4609 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4610 return;
4611 }
4612 t0 = tcg_const_tl(SR(ctx->opcode));
4613 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4614 tcg_temp_free(t0);
4615 #endif
4616 }
4617
4618 /* mfsrin */
4619 static void gen_mfsrin(DisasContext *ctx)
4620 {
4621 #if defined(CONFIG_USER_ONLY)
4622 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4623 #else
4624 TCGv t0;
4625 if (unlikely(ctx->pr)) {
4626 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4627 return;
4628 }
4629 t0 = tcg_temp_new();
4630 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4631 tcg_gen_andi_tl(t0, t0, 0xF);
4632 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4633 tcg_temp_free(t0);
4634 #endif
4635 }
4636
4637 /* mtsr */
4638 static void gen_mtsr(DisasContext *ctx)
4639 {
4640 #if defined(CONFIG_USER_ONLY)
4641 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4642 #else
4643 TCGv t0;
4644 if (unlikely(ctx->pr)) {
4645 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4646 return;
4647 }
4648 t0 = tcg_const_tl(SR(ctx->opcode));
4649 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4650 tcg_temp_free(t0);
4651 #endif
4652 }
4653
4654 /* mtsrin */
4655 static void gen_mtsrin(DisasContext *ctx)
4656 {
4657 #if defined(CONFIG_USER_ONLY)
4658 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4659 #else
4660 TCGv t0;
4661 if (unlikely(ctx->pr)) {
4662 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4663 return;
4664 }
4665 t0 = tcg_temp_new();
4666 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4667 tcg_gen_andi_tl(t0, t0, 0xF);
4668 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4669 tcg_temp_free(t0);
4670 #endif
4671 }
4672
4673 #if defined(TARGET_PPC64)
4674 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4675
4676 /* mfsr */
4677 static void gen_mfsr_64b(DisasContext *ctx)
4678 {
4679 #if defined(CONFIG_USER_ONLY)
4680 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4681 #else
4682 TCGv t0;
4683 if (unlikely(ctx->pr)) {
4684 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4685 return;
4686 }
4687 t0 = tcg_const_tl(SR(ctx->opcode));
4688 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4689 tcg_temp_free(t0);
4690 #endif
4691 }
4692
4693 /* mfsrin */
4694 static void gen_mfsrin_64b(DisasContext *ctx)
4695 {
4696 #if defined(CONFIG_USER_ONLY)
4697 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4698 #else
4699 TCGv t0;
4700 if (unlikely(ctx->pr)) {
4701 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4702 return;
4703 }
4704 t0 = tcg_temp_new();
4705 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4706 tcg_gen_andi_tl(t0, t0, 0xF);
4707 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4708 tcg_temp_free(t0);
4709 #endif
4710 }
4711
4712 /* mtsr */
4713 static void gen_mtsr_64b(DisasContext *ctx)
4714 {
4715 #if defined(CONFIG_USER_ONLY)
4716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4717 #else
4718 TCGv t0;
4719 if (unlikely(ctx->pr)) {
4720 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4721 return;
4722 }
4723 t0 = tcg_const_tl(SR(ctx->opcode));
4724 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4725 tcg_temp_free(t0);
4726 #endif
4727 }
4728
4729 /* mtsrin */
4730 static void gen_mtsrin_64b(DisasContext *ctx)
4731 {
4732 #if defined(CONFIG_USER_ONLY)
4733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4734 #else
4735 TCGv t0;
4736 if (unlikely(ctx->pr)) {
4737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4738 return;
4739 }
4740 t0 = tcg_temp_new();
4741 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4742 tcg_gen_andi_tl(t0, t0, 0xF);
4743 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4744 tcg_temp_free(t0);
4745 #endif
4746 }
4747
4748 /* slbmte */
4749 static void gen_slbmte(DisasContext *ctx)
4750 {
4751 #if defined(CONFIG_USER_ONLY)
4752 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4753 #else
4754 if (unlikely(ctx->pr)) {
4755 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4756 return;
4757 }
4758 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4759 cpu_gpr[rS(ctx->opcode)]);
4760 #endif
4761 }
4762
4763 static void gen_slbmfee(DisasContext *ctx)
4764 {
4765 #if defined(CONFIG_USER_ONLY)
4766 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4767 #else
4768 if (unlikely(ctx->pr)) {
4769 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4770 return;
4771 }
4772 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4773 cpu_gpr[rB(ctx->opcode)]);
4774 #endif
4775 }
4776
4777 static void gen_slbmfev(DisasContext *ctx)
4778 {
4779 #if defined(CONFIG_USER_ONLY)
4780 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4781 #else
4782 if (unlikely(ctx->pr)) {
4783 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4784 return;
4785 }
4786 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4787 cpu_gpr[rB(ctx->opcode)]);
4788 #endif
4789 }
4790 #endif /* defined(TARGET_PPC64) */
4791
4792 /*** Lookaside buffer management ***/
4793 /* Optional & supervisor only: */
4794
4795 /* tlbia */
4796 static void gen_tlbia(DisasContext *ctx)
4797 {
4798 #if defined(CONFIG_USER_ONLY)
4799 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4800 #else
4801 if (unlikely(ctx->pr)) {
4802 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4803 return;
4804 }
4805 gen_helper_tlbia(cpu_env);
4806 #endif
4807 }
4808
4809 /* tlbiel */
4810 static void gen_tlbiel(DisasContext *ctx)
4811 {
4812 #if defined(CONFIG_USER_ONLY)
4813 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4814 #else
4815 if (unlikely(ctx->pr)) {
4816 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4817 return;
4818 }
4819 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4820 #endif
4821 }
4822
4823 /* tlbie */
4824 static void gen_tlbie(DisasContext *ctx)
4825 {
4826 #if defined(CONFIG_USER_ONLY)
4827 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4828 #else
4829 if (unlikely(ctx->pr)) {
4830 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4831 return;
4832 }
4833 if (NARROW_MODE(ctx)) {
4834 TCGv t0 = tcg_temp_new();
4835 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4836 gen_helper_tlbie(cpu_env, t0);
4837 tcg_temp_free(t0);
4838 } else {
4839 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4840 }
4841 #endif
4842 }
4843
4844 /* tlbsync */
4845 static void gen_tlbsync(DisasContext *ctx)
4846 {
4847 #if defined(CONFIG_USER_ONLY)
4848 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4849 #else
4850 if (unlikely(ctx->pr)) {
4851 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4852 return;
4853 }
4854 /* This has no effect: it should ensure that all previous
4855 * tlbie have completed
4856 */
4857 gen_stop_exception(ctx);
4858 #endif
4859 }
4860
4861 #if defined(TARGET_PPC64)
4862 /* slbia */
4863 static void gen_slbia(DisasContext *ctx)
4864 {
4865 #if defined(CONFIG_USER_ONLY)
4866 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4867 #else
4868 if (unlikely(ctx->pr)) {
4869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4870 return;
4871 }
4872 gen_helper_slbia(cpu_env);
4873 #endif
4874 }
4875
4876 /* slbie */
4877 static void gen_slbie(DisasContext *ctx)
4878 {
4879 #if defined(CONFIG_USER_ONLY)
4880 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4881 #else
4882 if (unlikely(ctx->pr)) {
4883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4884 return;
4885 }
4886 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4887 #endif
4888 }
4889 #endif
4890
4891 /*** External control ***/
4892 /* Optional: */
4893
4894 /* eciwx */
4895 static void gen_eciwx(DisasContext *ctx)
4896 {
4897 TCGv t0;
4898 /* Should check EAR[E] ! */
4899 gen_set_access_type(ctx, ACCESS_EXT);
4900 t0 = tcg_temp_new();
4901 gen_addr_reg_index(ctx, t0);
4902 gen_check_align(ctx, t0, 0x03);
4903 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4904 tcg_temp_free(t0);
4905 }
4906
4907 /* ecowx */
4908 static void gen_ecowx(DisasContext *ctx)
4909 {
4910 TCGv t0;
4911 /* Should check EAR[E] ! */
4912 gen_set_access_type(ctx, ACCESS_EXT);
4913 t0 = tcg_temp_new();
4914 gen_addr_reg_index(ctx, t0);
4915 gen_check_align(ctx, t0, 0x03);
4916 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4917 tcg_temp_free(t0);
4918 }
4919
4920 /* PowerPC 601 specific instructions */
4921
4922 /* abs - abs. */
4923 static void gen_abs(DisasContext *ctx)
4924 {
4925 int l1 = gen_new_label();
4926 int l2 = gen_new_label();
4927 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4928 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4929 tcg_gen_br(l2);
4930 gen_set_label(l1);
4931 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4932 gen_set_label(l2);
4933 if (unlikely(Rc(ctx->opcode) != 0))
4934 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4935 }
4936
4937 /* abso - abso. */
4938 static void gen_abso(DisasContext *ctx)
4939 {
4940 int l1 = gen_new_label();
4941 int l2 = gen_new_label();
4942 int l3 = gen_new_label();
4943 /* Start with XER OV disabled, the most likely case */
4944 tcg_gen_movi_tl(cpu_ov, 0);
4945 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4946 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4947 tcg_gen_movi_tl(cpu_ov, 1);
4948 tcg_gen_movi_tl(cpu_so, 1);
4949 tcg_gen_br(l2);
4950 gen_set_label(l1);
4951 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4952 tcg_gen_br(l3);
4953 gen_set_label(l2);
4954 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4955 gen_set_label(l3);
4956 if (unlikely(Rc(ctx->opcode) != 0))
4957 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4958 }
4959
4960 /* clcs */
4961 static void gen_clcs(DisasContext *ctx)
4962 {
4963 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4964 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4965 tcg_temp_free_i32(t0);
4966 /* Rc=1 sets CR0 to an undefined state */
4967 }
4968
4969 /* div - div. */
4970 static void gen_div(DisasContext *ctx)
4971 {
4972 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4973 cpu_gpr[rB(ctx->opcode)]);
4974 if (unlikely(Rc(ctx->opcode) != 0))
4975 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4976 }
4977
4978 /* divo - divo. */
4979 static void gen_divo(DisasContext *ctx)
4980 {
4981 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4982 cpu_gpr[rB(ctx->opcode)]);
4983 if (unlikely(Rc(ctx->opcode) != 0))
4984 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4985 }
4986
4987 /* divs - divs. */
4988 static void gen_divs(DisasContext *ctx)
4989 {
4990 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4991 cpu_gpr[rB(ctx->opcode)]);
4992 if (unlikely(Rc(ctx->opcode) != 0))
4993 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4994 }
4995
4996 /* divso - divso. */
4997 static void gen_divso(DisasContext *ctx)
4998 {
4999 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
5000 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5001 if (unlikely(Rc(ctx->opcode) != 0))
5002 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5003 }
5004
5005 /* doz - doz. */
5006 static void gen_doz(DisasContext *ctx)
5007 {
5008 int l1 = gen_new_label();
5009 int l2 = gen_new_label();
5010 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5011 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5012 tcg_gen_br(l2);
5013 gen_set_label(l1);
5014 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5015 gen_set_label(l2);
5016 if (unlikely(Rc(ctx->opcode) != 0))
5017 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5018 }
5019
5020 /* dozo - dozo. */
5021 static void gen_dozo(DisasContext *ctx)
5022 {
5023 int l1 = gen_new_label();
5024 int l2 = gen_new_label();
5025 TCGv t0 = tcg_temp_new();
5026 TCGv t1 = tcg_temp_new();
5027 TCGv t2 = tcg_temp_new();
5028 /* Start with XER OV disabled, the most likely case */
5029 tcg_gen_movi_tl(cpu_ov, 0);
5030 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
5031 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5032 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5033 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
5034 tcg_gen_andc_tl(t1, t1, t2);
5035 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
5036 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5037 tcg_gen_movi_tl(cpu_ov, 1);
5038 tcg_gen_movi_tl(cpu_so, 1);
5039 tcg_gen_br(l2);
5040 gen_set_label(l1);
5041 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5042 gen_set_label(l2);
5043 tcg_temp_free(t0);
5044 tcg_temp_free(t1);
5045 tcg_temp_free(t2);
5046 if (unlikely(Rc(ctx->opcode) != 0))
5047 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5048 }
5049
5050 /* dozi */
5051 static void gen_dozi(DisasContext *ctx)
5052 {
5053 target_long simm = SIMM(ctx->opcode);
5054 int l1 = gen_new_label();
5055 int l2 = gen_new_label();
5056 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
5057 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
5058 tcg_gen_br(l2);
5059 gen_set_label(l1);
5060 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
5061 gen_set_label(l2);
5062 if (unlikely(Rc(ctx->opcode) != 0))
5063 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5064 }
5065
5066 /* lscbx - lscbx. */
5067 static void gen_lscbx(DisasContext *ctx)
5068 {
5069 TCGv t0 = tcg_temp_new();
5070 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
5071 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
5072 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
5073
5074 gen_addr_reg_index(ctx, t0);
5075 /* NIP cannot be restored if the memory exception comes from an helper */
5076 gen_update_nip(ctx, ctx->nip - 4);
5077 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
5078 tcg_temp_free_i32(t1);
5079 tcg_temp_free_i32(t2);
5080 tcg_temp_free_i32(t3);
5081 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
5082 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
5083 if (unlikely(Rc(ctx->opcode) != 0))
5084 gen_set_Rc0(ctx, t0);
5085 tcg_temp_free(t0);
5086 }
5087
5088 /* maskg - maskg. */
5089 static void gen_maskg(DisasContext *ctx)
5090 {
5091 int l1 = gen_new_label();
5092 TCGv t0 = tcg_temp_new();
5093 TCGv t1 = tcg_temp_new();
5094 TCGv t2 = tcg_temp_new();
5095 TCGv t3 = tcg_temp_new();
5096 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
5097 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5098 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
5099 tcg_gen_addi_tl(t2, t0, 1);
5100 tcg_gen_shr_tl(t2, t3, t2);
5101 tcg_gen_shr_tl(t3, t3, t1);
5102 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
5103 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
5104 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5105 gen_set_label(l1);
5106 tcg_temp_free(t0);
5107 tcg_temp_free(t1);
5108 tcg_temp_free(t2);
5109 tcg_temp_free(t3);
5110 if (unlikely(Rc(ctx->opcode) != 0))
5111 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5112 }
5113
5114 /* maskir - maskir. */
5115 static void gen_maskir(DisasContext *ctx)
5116 {
5117 TCGv t0 = tcg_temp_new();
5118 TCGv t1 = tcg_temp_new();
5119 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5120 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
5121 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5122 tcg_temp_free(t0);
5123 tcg_temp_free(t1);
5124 if (unlikely(Rc(ctx->opcode) != 0))
5125 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5126 }
5127
5128 /* mul - mul. */
5129 static void gen_mul(DisasContext *ctx)
5130 {
5131 TCGv_i64 t0 = tcg_temp_new_i64();
5132 TCGv_i64 t1 = tcg_temp_new_i64();
5133 TCGv t2 = tcg_temp_new();
5134 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5135 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5136 tcg_gen_mul_i64(t0, t0, t1);
5137 tcg_gen_trunc_i64_tl(t2, t0);
5138 gen_store_spr(SPR_MQ, t2);
5139 tcg_gen_shri_i64(t1, t0, 32);
5140 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5141 tcg_temp_free_i64(t0);
5142 tcg_temp_free_i64(t1);
5143 tcg_temp_free(t2);
5144 if (unlikely(Rc(ctx->opcode) != 0))
5145 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5146 }
5147
5148 /* mulo - mulo. */
5149 static void gen_mulo(DisasContext *ctx)
5150 {
5151 int l1 = gen_new_label();
5152 TCGv_i64 t0 = tcg_temp_new_i64();
5153 TCGv_i64 t1 = tcg_temp_new_i64();
5154 TCGv t2 = tcg_temp_new();
5155 /* Start with XER OV disabled, the most likely case */
5156 tcg_gen_movi_tl(cpu_ov, 0);
5157 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5158 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5159 tcg_gen_mul_i64(t0, t0, t1);
5160 tcg_gen_trunc_i64_tl(t2, t0);
5161 gen_store_spr(SPR_MQ, t2);
5162 tcg_gen_shri_i64(t1, t0, 32);
5163 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5164 tcg_gen_ext32s_i64(t1, t0);
5165 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5166 tcg_gen_movi_tl(cpu_ov, 1);
5167 tcg_gen_movi_tl(cpu_so, 1);
5168 gen_set_label(l1);
5169 tcg_temp_free_i64(t0);
5170 tcg_temp_free_i64(t1);
5171 tcg_temp_free(t2);
5172 if (unlikely(Rc(ctx->opcode) != 0))
5173 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5174 }
5175
5176 /* nabs - nabs. */
5177 static void gen_nabs(DisasContext *ctx)
5178 {
5179 int l1 = gen_new_label();
5180 int l2 = gen_new_label();
5181 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5182 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5183 tcg_gen_br(l2);
5184 gen_set_label(l1);
5185 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5186 gen_set_label(l2);
5187 if (unlikely(Rc(ctx->opcode) != 0))
5188 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5189 }
5190
5191 /* nabso - nabso. */
5192 static void gen_nabso(DisasContext *ctx)
5193 {
5194 int l1 = gen_new_label();
5195 int l2 = gen_new_label();
5196 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5197 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5198 tcg_gen_br(l2);
5199 gen_set_label(l1);
5200 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5201 gen_set_label(l2);
5202 /* nabs never overflows */
5203 tcg_gen_movi_tl(cpu_ov, 0);
5204 if (unlikely(Rc(ctx->opcode) != 0))
5205 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5206 }
5207
5208 /* rlmi - rlmi. */
5209 static void gen_rlmi(DisasContext *ctx)
5210 {
5211 uint32_t mb = MB(ctx->opcode);
5212 uint32_t me = ME(ctx->opcode);
5213 TCGv t0 = tcg_temp_new();
5214 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5215 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5216 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5217 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5218 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5219 tcg_temp_free(t0);
5220 if (unlikely(Rc(ctx->opcode) != 0))
5221 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5222 }
5223
5224 /* rrib - rrib. */
5225 static void gen_rrib(DisasContext *ctx)
5226 {
5227 TCGv t0 = tcg_temp_new();
5228 TCGv t1 = tcg_temp_new();
5229 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5230 tcg_gen_movi_tl(t1, 0x80000000);
5231 tcg_gen_shr_tl(t1, t1, t0);
5232 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5233 tcg_gen_and_tl(t0, t0, t1);
5234 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5235 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5236 tcg_temp_free(t0);
5237 tcg_temp_free(t1);
5238 if (unlikely(Rc(ctx->opcode) != 0))
5239 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5240 }
5241
5242 /* sle - sle. */
5243 static void gen_sle(DisasContext *ctx)
5244 {
5245 TCGv t0 = tcg_temp_new();
5246 TCGv t1 = tcg_temp_new();
5247 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5248 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5249 tcg_gen_subfi_tl(t1, 32, t1);
5250 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5251 tcg_gen_or_tl(t1, t0, t1);
5252 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5253 gen_store_spr(SPR_MQ, t1);
5254 tcg_temp_free(t0);
5255 tcg_temp_free(t1);
5256 if (unlikely(Rc(ctx->opcode) != 0))
5257 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5258 }
5259
5260 /* sleq - sleq. */
5261 static void gen_sleq(DisasContext *ctx)
5262 {
5263 TCGv t0 = tcg_temp_new();
5264 TCGv t1 = tcg_temp_new();
5265 TCGv t2 = tcg_temp_new();
5266 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5267 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5268 tcg_gen_shl_tl(t2, t2, t0);
5269 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5270 gen_load_spr(t1, SPR_MQ);
5271 gen_store_spr(SPR_MQ, t0);
5272 tcg_gen_and_tl(t0, t0, t2);
5273 tcg_gen_andc_tl(t1, t1, t2);
5274 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5275 tcg_temp_free(t0);
5276 tcg_temp_free(t1);
5277 tcg_temp_free(t2);
5278 if (unlikely(Rc(ctx->opcode) != 0))
5279 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5280 }
5281
5282 /* sliq - sliq. */
5283 static void gen_sliq(DisasContext *ctx)
5284 {
5285 int sh = SH(ctx->opcode);
5286 TCGv t0 = tcg_temp_new();
5287 TCGv t1 = tcg_temp_new();
5288 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5289 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5290 tcg_gen_or_tl(t1, t0, t1);
5291 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5292 gen_store_spr(SPR_MQ, t1);
5293 tcg_temp_free(t0);
5294 tcg_temp_free(t1);
5295 if (unlikely(Rc(ctx->opcode) != 0))
5296 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5297 }
5298
5299 /* slliq - slliq. */
5300 static void gen_slliq(DisasContext *ctx)
5301 {
5302 int sh = SH(ctx->opcode);
5303 TCGv t0 = tcg_temp_new();
5304 TCGv t1 = tcg_temp_new();
5305 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5306 gen_load_spr(t1, SPR_MQ);
5307 gen_store_spr(SPR_MQ, t0);
5308 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5309 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5310 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5311 tcg_temp_free(t0);
5312 tcg_temp_free(t1);
5313 if (unlikely(Rc(ctx->opcode) != 0))
5314 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5315 }
5316
5317 /* sllq - sllq. */
5318 static void gen_sllq(DisasContext *ctx)
5319 {
5320 int l1 = gen_new_label();
5321 int l2 = gen_new_label();
5322 TCGv t0 = tcg_temp_local_new();
5323 TCGv t1 = tcg_temp_local_new();
5324 TCGv t2 = tcg_temp_local_new();
5325 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5326 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5327 tcg_gen_shl_tl(t1, t1, t2);
5328 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5329 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5330 gen_load_spr(t0, SPR_MQ);
5331 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5332 tcg_gen_br(l2);
5333 gen_set_label(l1);
5334 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5335 gen_load_spr(t2, SPR_MQ);
5336 tcg_gen_andc_tl(t1, t2, t1);
5337 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5338 gen_set_label(l2);
5339 tcg_temp_free(t0);
5340 tcg_temp_free(t1);
5341 tcg_temp_free(t2);
5342 if (unlikely(Rc(ctx->opcode) != 0))
5343 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5344 }
5345
5346 /* slq - slq. */
5347 static void gen_slq(DisasContext *ctx)
5348 {
5349 int l1 = gen_new_label();
5350 TCGv t0 = tcg_temp_new();
5351 TCGv t1 = tcg_temp_new();
5352 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5353 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5354 tcg_gen_subfi_tl(t1, 32, t1);
5355 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5356 tcg_gen_or_tl(t1, t0, t1);
5357 gen_store_spr(SPR_MQ, t1);
5358 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5359 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5360 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5361 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5362 gen_set_label(l1);
5363 tcg_temp_free(t0);
5364 tcg_temp_free(t1);
5365 if (unlikely(Rc(ctx->opcode) != 0))
5366 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5367 }
5368
5369 /* sraiq - sraiq. */
5370 static void gen_sraiq(DisasContext *ctx)
5371 {
5372 int sh = SH(ctx->opcode);
5373 int l1 = gen_new_label();
5374 TCGv t0 = tcg_temp_new();
5375 TCGv t1 = tcg_temp_new();
5376 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5377 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5378 tcg_gen_or_tl(t0, t0, t1);
5379 gen_store_spr(SPR_MQ, t0);
5380 tcg_gen_movi_tl(cpu_ca, 0);
5381 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5382 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5383 tcg_gen_movi_tl(cpu_ca, 1);
5384 gen_set_label(l1);
5385 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5386 tcg_temp_free(t0);
5387 tcg_temp_free(t1);
5388 if (unlikely(Rc(ctx->opcode) != 0))
5389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5390 }
5391
5392 /* sraq - sraq. */
5393 static void gen_sraq(DisasContext *ctx)
5394 {
5395 int l1 = gen_new_label();
5396 int l2 = gen_new_label();
5397 TCGv t0 = tcg_temp_new();
5398 TCGv t1 = tcg_temp_local_new();
5399 TCGv t2 = tcg_temp_local_new();
5400 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5401 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5402 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5403 tcg_gen_subfi_tl(t2, 32, t2);
5404 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5405 tcg_gen_or_tl(t0, t0, t2);
5406 gen_store_spr(SPR_MQ, t0);
5407 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5408 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5409 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5410 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5411 gen_set_label(l1);
5412 tcg_temp_free(t0);
5413 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5414 tcg_gen_movi_tl(cpu_ca, 0);
5415 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5416 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5417 tcg_gen_movi_tl(cpu_ca, 1);
5418 gen_set_label(l2);
5419 tcg_temp_free(t1);
5420 tcg_temp_free(t2);
5421 if (unlikely(Rc(ctx->opcode) != 0))
5422 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5423 }
5424
5425 /* sre - sre. */
5426 static void gen_sre(DisasContext *ctx)
5427 {
5428 TCGv t0 = tcg_temp_new();
5429 TCGv t1 = tcg_temp_new();
5430 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5431 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5432 tcg_gen_subfi_tl(t1, 32, t1);
5433 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5434 tcg_gen_or_tl(t1, t0, t1);
5435 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5436 gen_store_spr(SPR_MQ, t1);
5437 tcg_temp_free(t0);
5438 tcg_temp_free(t1);
5439 if (unlikely(Rc(ctx->opcode) != 0))
5440 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5441 }
5442
5443 /* srea - srea. */
5444 static void gen_srea(DisasContext *ctx)
5445 {
5446 TCGv t0 = tcg_temp_new();
5447 TCGv t1 = tcg_temp_new();
5448 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5449 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5450 gen_store_spr(SPR_MQ, t0);
5451 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5452 tcg_temp_free(t0);
5453 tcg_temp_free(t1);
5454 if (unlikely(Rc(ctx->opcode) != 0))
5455 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5456 }
5457
5458 /* sreq */
5459 static void gen_sreq(DisasContext *ctx)
5460 {
5461 TCGv t0 = tcg_temp_new();
5462 TCGv t1 = tcg_temp_new();
5463 TCGv t2 = tcg_temp_new();
5464 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5465 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5466 tcg_gen_shr_tl(t1, t1, t0);
5467 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5468 gen_load_spr(t2, SPR_MQ);
5469 gen_store_spr(SPR_MQ, t0);
5470 tcg_gen_and_tl(t0, t0, t1);
5471 tcg_gen_andc_tl(t2, t2, t1);
5472 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5473 tcg_temp_free(t0);
5474 tcg_temp_free(t1);
5475 tcg_temp_free(t2);
5476 if (unlikely(Rc(ctx->opcode) != 0))
5477 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5478 }
5479
5480 /* sriq */
5481 static void gen_sriq(DisasContext *ctx)
5482 {
5483 int sh = SH(ctx->opcode);
5484 TCGv t0 = tcg_temp_new();
5485 TCGv t1 = tcg_temp_new();
5486 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5487 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5488 tcg_gen_or_tl(t1, t0, t1);
5489 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5490 gen_store_spr(SPR_MQ, t1);
5491 tcg_temp_free(t0);
5492 tcg_temp_free(t1);
5493 if (unlikely(Rc(ctx->opcode) != 0))
5494 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5495 }
5496
5497 /* srliq */
5498 static void gen_srliq(DisasContext *ctx)
5499 {
5500 int sh = SH(ctx->opcode);
5501 TCGv t0 = tcg_temp_new();
5502 TCGv t1 = tcg_temp_new();
5503 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5504 gen_load_spr(t1, SPR_MQ);
5505 gen_store_spr(SPR_MQ, t0);
5506 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5507 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5508 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5509 tcg_temp_free(t0);
5510 tcg_temp_free(t1);
5511 if (unlikely(Rc(ctx->opcode) != 0))
5512 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5513 }
5514
5515 /* srlq */
5516 static void gen_srlq(DisasContext *ctx)
5517 {
5518 int l1 = gen_new_label();
5519 int l2 = gen_new_label();
5520 TCGv t0 = tcg_temp_local_new();
5521 TCGv t1 = tcg_temp_local_new();
5522 TCGv t2 = tcg_temp_local_new();
5523 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5524 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5525 tcg_gen_shr_tl(t2, t1, t2);
5526 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5527 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5528 gen_load_spr(t0, SPR_MQ);
5529 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5530 tcg_gen_br(l2);
5531 gen_set_label(l1);
5532 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5533 tcg_gen_and_tl(t0, t0, t2);
5534 gen_load_spr(t1, SPR_MQ);
5535 tcg_gen_andc_tl(t1, t1, t2);
5536 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5537 gen_set_label(l2);
5538 tcg_temp_free(t0);
5539 tcg_temp_free(t1);
5540 tcg_temp_free(t2);
5541 if (unlikely(Rc(ctx->opcode) != 0))
5542 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5543 }
5544
5545 /* srq */
5546 static void gen_srq(DisasContext *ctx)
5547 {
5548 int l1 = gen_new_label();
5549 TCGv t0 = tcg_temp_new();
5550 TCGv t1 = tcg_temp_new();
5551 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5552 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5553 tcg_gen_subfi_tl(t1, 32, t1);
5554 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5555 tcg_gen_or_tl(t1, t0, t1);
5556 gen_store_spr(SPR_MQ, t1);
5557 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5558 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5559 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5560 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5561 gen_set_label(l1);
5562 tcg_temp_free(t0);
5563 tcg_temp_free(t1);
5564 if (unlikely(Rc(ctx->opcode) != 0))
5565 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5566 }
5567
5568 /* PowerPC 602 specific instructions */
5569
5570 /* dsa */
5571 static void gen_dsa(DisasContext *ctx)
5572 {
5573 /* XXX: TODO */
5574 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5575 }
5576
5577 /* esa */
5578 static void gen_esa(DisasContext *ctx)
5579 {
5580 /* XXX: TODO */
5581 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5582 }
5583
5584 /* mfrom */
5585 static void gen_mfrom(DisasContext *ctx)
5586 {
5587 #if defined(CONFIG_USER_ONLY)
5588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5589 #else
5590 if (unlikely(ctx->pr)) {
5591 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5592 return;
5593 }
5594 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5595 #endif
5596 }
5597
5598 /* 602 - 603 - G2 TLB management */
5599
5600 /* tlbld */
5601 static void gen_tlbld_6xx(DisasContext *ctx)
5602 {
5603 #if defined(CONFIG_USER_ONLY)
5604 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5605 #else
5606 if (unlikely(ctx->pr)) {
5607 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5608 return;
5609 }
5610 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5611 #endif
5612 }
5613
5614 /* tlbli */
5615 static void gen_tlbli_6xx(DisasContext *ctx)
5616 {
5617 #if defined(CONFIG_USER_ONLY)
5618 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5619 #else
5620 if (unlikely(ctx->pr)) {
5621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5622 return;
5623 }
5624 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5625 #endif
5626 }
5627
5628 /* 74xx TLB management */
5629
5630 /* tlbld */
5631 static void gen_tlbld_74xx(DisasContext *ctx)
5632 {
5633 #if defined(CONFIG_USER_ONLY)
5634 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5635 #else
5636 if (unlikely(ctx->pr)) {
5637 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5638 return;
5639 }
5640 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5641 #endif
5642 }
5643
5644 /* tlbli */
5645 static void gen_tlbli_74xx(DisasContext *ctx)
5646 {
5647 #if defined(CONFIG_USER_ONLY)
5648 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5649 #else
5650 if (unlikely(ctx->pr)) {
5651 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5652 return;
5653 }
5654 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5655 #endif
5656 }
5657
5658 /* POWER instructions not in PowerPC 601 */
5659
5660 /* clf */
5661 static void gen_clf(DisasContext *ctx)
5662 {
5663 /* Cache line flush: implemented as no-op */
5664 }
5665
5666 /* cli */
5667 static void gen_cli(DisasContext *ctx)
5668 {
5669 /* Cache line invalidate: privileged and treated as no-op */
5670 #if defined(CONFIG_USER_ONLY)
5671 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5672 #else
5673 if (unlikely(ctx->pr)) {
5674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5675 return;
5676 }
5677 #endif
5678 }
5679
5680 /* dclst */
5681 static void gen_dclst(DisasContext *ctx)
5682 {
5683 /* Data cache line store: treated as no-op */
5684 }
5685
5686 static void gen_mfsri(DisasContext *ctx)
5687 {
5688 #if defined(CONFIG_USER_ONLY)
5689 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5690 #else
5691 int ra = rA(ctx->opcode);
5692 int rd = rD(ctx->opcode);
5693 TCGv t0;
5694 if (unlikely(ctx->pr)) {
5695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5696 return;
5697 }
5698 t0 = tcg_temp_new();
5699 gen_addr_reg_index(ctx, t0);
5700 tcg_gen_shri_tl(t0, t0, 28);
5701 tcg_gen_andi_tl(t0, t0, 0xF);
5702 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5703 tcg_temp_free(t0);
5704 if (ra != 0 && ra != rd)
5705 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5706 #endif
5707 }
5708
5709 static void gen_rac(DisasContext *ctx)
5710 {
5711 #if defined(CONFIG_USER_ONLY)
5712 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5713 #else
5714 TCGv t0;
5715 if (unlikely(ctx->pr)) {
5716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5717 return;
5718 }
5719 t0 = tcg_temp_new();
5720 gen_addr_reg_index(ctx, t0);
5721 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5722 tcg_temp_free(t0);
5723 #endif
5724 }
5725
5726 static void gen_rfsvc(DisasContext *ctx)
5727 {
5728 #if defined(CONFIG_USER_ONLY)
5729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5730 #else
5731 if (unlikely(ctx->pr)) {
5732 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5733 return;
5734 }
5735 gen_helper_rfsvc(cpu_env);
5736 gen_sync_exception(ctx);
5737 #endif
5738 }
5739
5740 /* svc is not implemented for now */
5741
5742 /* POWER2 specific instructions */
5743 /* Quad manipulation (load/store two floats at a time) */
5744
5745 /* lfq */
5746 static void gen_lfq(DisasContext *ctx)
5747 {
5748 int rd = rD(ctx->opcode);
5749 TCGv t0;
5750 gen_set_access_type(ctx, ACCESS_FLOAT);
5751 t0 = tcg_temp_new();
5752 gen_addr_imm_index(ctx, t0, 0);
5753 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5754 gen_addr_add(ctx, t0, t0, 8);
5755 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5756 tcg_temp_free(t0);
5757 }
5758
5759 /* lfqu */
5760 static void gen_lfqu(DisasContext *ctx)
5761 {
5762 int ra = rA(ctx->opcode);
5763 int rd = rD(ctx->opcode);
5764 TCGv t0, t1;
5765 gen_set_access_type(ctx, ACCESS_FLOAT);
5766 t0 = tcg_temp_new();
5767 t1 = tcg_temp_new();
5768 gen_addr_imm_index(ctx, t0, 0);
5769 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5770 gen_addr_add(ctx, t1, t0, 8);
5771 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5772 if (ra != 0)
5773 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5774 tcg_temp_free(t0);
5775 tcg_temp_free(t1);
5776 }
5777
5778 /* lfqux */
5779 static void gen_lfqux(DisasContext *ctx)
5780 {
5781 int ra = rA(ctx->opcode);
5782 int rd = rD(ctx->opcode);
5783 gen_set_access_type(ctx, ACCESS_FLOAT);
5784 TCGv t0, t1;
5785 t0 = tcg_temp_new();
5786 gen_addr_reg_index(ctx, t0);
5787 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5788 t1 = tcg_temp_new();
5789 gen_addr_add(ctx, t1, t0, 8);
5790 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5791 tcg_temp_free(t1);
5792 if (ra != 0)
5793 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5794 tcg_temp_free(t0);
5795 }
5796
5797 /* lfqx */
5798 static void gen_lfqx(DisasContext *ctx)
5799 {
5800 int rd = rD(ctx->opcode);
5801 TCGv t0;
5802 gen_set_access_type(ctx, ACCESS_FLOAT);
5803 t0 = tcg_temp_new();
5804 gen_addr_reg_index(ctx, t0);
5805 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5806 gen_addr_add(ctx, t0, t0, 8);
5807 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5808 tcg_temp_free(t0);
5809 }
5810
5811 /* stfq */
5812 static void gen_stfq(DisasContext *ctx)
5813 {
5814 int rd = rD(ctx->opcode);
5815 TCGv t0;
5816 gen_set_access_type(ctx, ACCESS_FLOAT);
5817 t0 = tcg_temp_new();
5818 gen_addr_imm_index(ctx, t0, 0);
5819 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5820 gen_addr_add(ctx, t0, t0, 8);
5821 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5822 tcg_temp_free(t0);
5823 }
5824
5825 /* stfqu */
5826 static void gen_stfqu(DisasContext *ctx)
5827 {
5828 int ra = rA(ctx->opcode);
5829 int rd = rD(ctx->opcode);
5830 TCGv t0, t1;
5831 gen_set_access_type(ctx, ACCESS_FLOAT);
5832 t0 = tcg_temp_new();
5833 gen_addr_imm_index(ctx, t0, 0);
5834 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5835 t1 = tcg_temp_new();
5836 gen_addr_add(ctx, t1, t0, 8);
5837 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5838 tcg_temp_free(t1);
5839 if (ra != 0)
5840 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5841 tcg_temp_free(t0);
5842 }
5843
5844 /* stfqux */
5845 static void gen_stfqux(DisasContext *ctx)
5846 {
5847 int ra = rA(ctx->opcode);
5848 int rd = rD(ctx->opcode);
5849 TCGv t0, t1;
5850 gen_set_access_type(ctx, ACCESS_FLOAT);
5851 t0 = tcg_temp_new();
5852 gen_addr_reg_index(ctx, t0);
5853 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5854 t1 = tcg_temp_new();
5855 gen_addr_add(ctx, t1, t0, 8);
5856 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5857 tcg_temp_free(t1);
5858 if (ra != 0)
5859 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5860 tcg_temp_free(t0);
5861 }
5862
5863 /* stfqx */
5864 static void gen_stfqx(DisasContext *ctx)
5865 {
5866 int rd = rD(ctx->opcode);
5867 TCGv t0;
5868 gen_set_access_type(ctx, ACCESS_FLOAT);
5869 t0 = tcg_temp_new();
5870 gen_addr_reg_index(ctx, t0);
5871 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5872 gen_addr_add(ctx, t0, t0, 8);
5873 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5874 tcg_temp_free(t0);
5875 }
5876
5877 /* BookE specific instructions */
5878
5879 /* XXX: not implemented on 440 ? */
5880 static void gen_mfapidi(DisasContext *ctx)
5881 {
5882 /* XXX: TODO */
5883 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5884 }
5885
5886 /* XXX: not implemented on 440 ? */
5887 static void gen_tlbiva(DisasContext *ctx)
5888 {
5889 #if defined(CONFIG_USER_ONLY)
5890 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5891 #else
5892 TCGv t0;
5893 if (unlikely(ctx->pr)) {
5894 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5895 return;
5896 }
5897 t0 = tcg_temp_new();
5898 gen_addr_reg_index(ctx, t0);
5899 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5900 tcg_temp_free(t0);
5901 #endif
5902 }
5903
5904 /* All 405 MAC instructions are translated here */
5905 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5906 int ra, int rb, int rt, int Rc)
5907 {
5908 TCGv t0, t1;
5909
5910 t0 = tcg_temp_local_new();
5911 t1 = tcg_temp_local_new();
5912
5913 switch (opc3 & 0x0D) {
5914 case 0x05:
5915 /* macchw - macchw. - macchwo - macchwo. */
5916 /* macchws - macchws. - macchwso - macchwso. */
5917 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5918 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5919 /* mulchw - mulchw. */
5920 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5921 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5922 tcg_gen_ext16s_tl(t1, t1);
5923 break;
5924 case 0x04:
5925 /* macchwu - macchwu. - macchwuo - macchwuo. */
5926 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5927 /* mulchwu - mulchwu. */
5928 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5929 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5930 tcg_gen_ext16u_tl(t1, t1);
5931 break;
5932 case 0x01:
5933 /* machhw - machhw. - machhwo - machhwo. */
5934 /* machhws - machhws. - machhwso - machhwso. */
5935 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5936 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5937 /* mulhhw - mulhhw. */
5938 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5939 tcg_gen_ext16s_tl(t0, t0);
5940 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5941 tcg_gen_ext16s_tl(t1, t1);
5942 break;
5943 case 0x00:
5944 /* machhwu - machhwu. - machhwuo - machhwuo. */
5945 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5946 /* mulhhwu - mulhhwu. */
5947 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5948 tcg_gen_ext16u_tl(t0, t0);
5949 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5950 tcg_gen_ext16u_tl(t1, t1);
5951 break;
5952 case 0x0D:
5953 /* maclhw - maclhw. - maclhwo - maclhwo. */
5954 /* maclhws - maclhws. - maclhwso - maclhwso. */
5955 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5956 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5957 /* mullhw - mullhw. */
5958 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5959 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5960 break;
5961 case 0x0C:
5962 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5963 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5964 /* mullhwu - mullhwu. */
5965 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5966 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5967 break;
5968 }
5969 if (opc2 & 0x04) {
5970 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5971 tcg_gen_mul_tl(t1, t0, t1);
5972 if (opc2 & 0x02) {
5973 /* nmultiply-and-accumulate (0x0E) */
5974 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5975 } else {
5976 /* multiply-and-accumulate (0x0C) */
5977 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5978 }
5979
5980 if (opc3 & 0x12) {
5981 /* Check overflow and/or saturate */
5982 int l1 = gen_new_label();
5983
5984 if (opc3 & 0x10) {
5985 /* Start with XER OV disabled, the most likely case */
5986 tcg_gen_movi_tl(cpu_ov, 0);
5987 }
5988 if (opc3 & 0x01) {
5989 /* Signed */
5990 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5991 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5992 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5993 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5994 if (opc3 & 0x02) {
5995 /* Saturate */
5996 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5997 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5998 }
5999 } else {
6000 /* Unsigned */
6001 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
6002 if (opc3 & 0x02) {
6003 /* Saturate */
6004 tcg_gen_movi_tl(t0, UINT32_MAX);
6005 }
6006 }
6007 if (opc3 & 0x10) {
6008 /* Check overflow */
6009 tcg_gen_movi_tl(cpu_ov, 1);
6010 tcg_gen_movi_tl(cpu_so, 1);
6011 }
6012 gen_set_label(l1);
6013 tcg_gen_mov_tl(cpu_gpr[rt], t0);
6014 }
6015 } else {
6016 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
6017 }
6018 tcg_temp_free(t0);
6019 tcg_temp_free(t1);
6020 if (unlikely(Rc) != 0) {
6021 /* Update Rc0 */
6022 gen_set_Rc0(ctx, cpu_gpr[rt]);
6023 }
6024 }
6025
6026 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6027 static void glue(gen_, name)(DisasContext *ctx) \
6028 { \
6029 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6030 rD(ctx->opcode), Rc(ctx->opcode)); \
6031 }
6032
6033 /* macchw - macchw. */
6034 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
6035 /* macchwo - macchwo. */
6036 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
6037 /* macchws - macchws. */
6038 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
6039 /* macchwso - macchwso. */
6040 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
6041 /* macchwsu - macchwsu. */
6042 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
6043 /* macchwsuo - macchwsuo. */
6044 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
6045 /* macchwu - macchwu. */
6046 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
6047 /* macchwuo - macchwuo. */
6048 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
6049 /* machhw - machhw. */
6050 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
6051 /* machhwo - machhwo. */
6052 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
6053 /* machhws - machhws. */
6054 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
6055 /* machhwso - machhwso. */
6056 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
6057 /* machhwsu - machhwsu. */
6058 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
6059 /* machhwsuo - machhwsuo. */
6060 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
6061 /* machhwu - machhwu. */
6062 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
6063 /* machhwuo - machhwuo. */
6064 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
6065 /* maclhw - maclhw. */
6066 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
6067 /* maclhwo - maclhwo. */
6068 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
6069 /* maclhws - maclhws. */
6070 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
6071 /* maclhwso - maclhwso. */
6072 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
6073 /* maclhwu - maclhwu. */
6074 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
6075 /* maclhwuo - maclhwuo. */
6076 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
6077 /* maclhwsu - maclhwsu. */
6078 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
6079 /* maclhwsuo - maclhwsuo. */
6080 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
6081 /* nmacchw - nmacchw. */
6082 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
6083 /* nmacchwo - nmacchwo. */
6084 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
6085 /* nmacchws - nmacchws. */
6086 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
6087 /* nmacchwso - nmacchwso. */
6088 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
6089 /* nmachhw - nmachhw. */
6090 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
6091 /* nmachhwo - nmachhwo. */
6092 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
6093 /* nmachhws - nmachhws. */
6094 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
6095 /* nmachhwso - nmachhwso. */
6096 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
6097 /* nmaclhw - nmaclhw. */
6098 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
6099 /* nmaclhwo - nmaclhwo. */
6100 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
6101 /* nmaclhws - nmaclhws. */
6102 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
6103 /* nmaclhwso - nmaclhwso. */
6104 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
6105
6106 /* mulchw - mulchw. */
6107 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
6108 /* mulchwu - mulchwu. */
6109 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
6110 /* mulhhw - mulhhw. */
6111 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
6112 /* mulhhwu - mulhhwu. */
6113 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
6114 /* mullhw - mullhw. */
6115 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
6116 /* mullhwu - mullhwu. */
6117 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
6118
6119 /* mfdcr */
6120 static void gen_mfdcr(DisasContext *ctx)
6121 {
6122 #if defined(CONFIG_USER_ONLY)
6123 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6124 #else
6125 TCGv dcrn;
6126 if (unlikely(ctx->pr)) {
6127 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6128 return;
6129 }
6130 /* NIP cannot be restored if the memory exception comes from an helper */
6131 gen_update_nip(ctx, ctx->nip - 4);
6132 dcrn = tcg_const_tl(SPR(ctx->opcode));
6133 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
6134 tcg_temp_free(dcrn);
6135 #endif
6136 }
6137
6138 /* mtdcr */
6139 static void gen_mtdcr(DisasContext *ctx)
6140 {
6141 #if defined(CONFIG_USER_ONLY)
6142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6143 #else
6144 TCGv dcrn;
6145 if (unlikely(ctx->pr)) {
6146 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6147 return;
6148 }
6149 /* NIP cannot be restored if the memory exception comes from an helper */
6150 gen_update_nip(ctx, ctx->nip - 4);
6151 dcrn = tcg_const_tl(SPR(ctx->opcode));
6152 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6153 tcg_temp_free(dcrn);
6154 #endif
6155 }
6156
6157 /* mfdcrx */
6158 /* XXX: not implemented on 440 ? */
6159 static void gen_mfdcrx(DisasContext *ctx)
6160 {
6161 #if defined(CONFIG_USER_ONLY)
6162 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6163 #else
6164 if (unlikely(ctx->pr)) {
6165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6166 return;
6167 }
6168 /* NIP cannot be restored if the memory exception comes from an helper */
6169 gen_update_nip(ctx, ctx->nip - 4);
6170 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6171 cpu_gpr[rA(ctx->opcode)]);
6172 /* Note: Rc update flag set leads to undefined state of Rc0 */
6173 #endif
6174 }
6175
6176 /* mtdcrx */
6177 /* XXX: not implemented on 440 ? */
6178 static void gen_mtdcrx(DisasContext *ctx)
6179 {
6180 #if defined(CONFIG_USER_ONLY)
6181 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6182 #else
6183 if (unlikely(ctx->pr)) {
6184 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6185 return;
6186 }
6187 /* NIP cannot be restored if the memory exception comes from an helper */
6188 gen_update_nip(ctx, ctx->nip - 4);
6189 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6190 cpu_gpr[rS(ctx->opcode)]);
6191 /* Note: Rc update flag set leads to undefined state of Rc0 */
6192 #endif
6193 }
6194
6195 /* mfdcrux (PPC 460) : user-mode access to DCR */
6196 static void gen_mfdcrux(DisasContext *ctx)
6197 {
6198 /* NIP cannot be restored if the memory exception comes from an helper */
6199 gen_update_nip(ctx, ctx->nip - 4);
6200 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6201 cpu_gpr[rA(ctx->opcode)]);
6202 /* Note: Rc update flag set leads to undefined state of Rc0 */
6203 }
6204
6205 /* mtdcrux (PPC 460) : user-mode access to DCR */
6206 static void gen_mtdcrux(DisasContext *ctx)
6207 {
6208 /* NIP cannot be restored if the memory exception comes from an helper */
6209 gen_update_nip(ctx, ctx->nip - 4);
6210 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6211 cpu_gpr[rS(ctx->opcode)]);
6212 /* Note: Rc update flag set leads to undefined state of Rc0 */
6213 }
6214
6215 /* dccci */
6216 static void gen_dccci(DisasContext *ctx)
6217 {
6218 #if defined(CONFIG_USER_ONLY)
6219 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6220 #else
6221 if (unlikely(ctx->pr)) {
6222 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6223 return;
6224 }
6225 /* interpreted as no-op */
6226 #endif
6227 }
6228
6229 /* dcread */
6230 static void gen_dcread(DisasContext *ctx)
6231 {
6232 #if defined(CONFIG_USER_ONLY)
6233 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6234 #else
6235 TCGv EA, val;
6236 if (unlikely(ctx->pr)) {
6237 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6238 return;
6239 }
6240 gen_set_access_type(ctx, ACCESS_CACHE);
6241 EA = tcg_temp_new();
6242 gen_addr_reg_index(ctx, EA);
6243 val = tcg_temp_new();
6244 gen_qemu_ld32u(ctx, val, EA);
6245 tcg_temp_free(val);
6246 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6247 tcg_temp_free(EA);
6248 #endif
6249 }
6250
6251 /* icbt */
6252 static void gen_icbt_40x(DisasContext *ctx)
6253 {
6254 /* interpreted as no-op */
6255 /* XXX: specification say this is treated as a load by the MMU
6256 * but does not generate any exception
6257 */
6258 }
6259
6260 /* iccci */
6261 static void gen_iccci(DisasContext *ctx)
6262 {
6263 #if defined(CONFIG_USER_ONLY)
6264 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6265 #else
6266 if (unlikely(ctx->pr)) {
6267 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6268 return;
6269 }
6270 /* interpreted as no-op */
6271 #endif
6272 }
6273
6274 /* icread */
6275 static void gen_icread(DisasContext *ctx)
6276 {
6277 #if defined(CONFIG_USER_ONLY)
6278 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6279 #else
6280 if (unlikely(ctx->pr)) {
6281 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6282 return;
6283 }
6284 /* interpreted as no-op */
6285 #endif
6286 }
6287
6288 /* rfci (supervisor only) */
6289 static void gen_rfci_40x(DisasContext *ctx)
6290 {
6291 #if defined(CONFIG_USER_ONLY)
6292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6293 #else
6294 if (unlikely(ctx->pr)) {
6295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6296 return;
6297 }
6298 /* Restore CPU state */
6299 gen_helper_40x_rfci(cpu_env);
6300 gen_sync_exception(ctx);
6301 #endif
6302 }
6303
6304 static void gen_rfci(DisasContext *ctx)
6305 {
6306 #if defined(CONFIG_USER_ONLY)
6307 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6308 #else
6309 if (unlikely(ctx->pr)) {
6310 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6311 return;
6312 }
6313 /* Restore CPU state */
6314 gen_helper_rfci(cpu_env);
6315 gen_sync_exception(ctx);
6316 #endif
6317 }
6318
6319 /* BookE specific */
6320
6321 /* XXX: not implemented on 440 ? */
6322 static void gen_rfdi(DisasContext *ctx)
6323 {
6324 #if defined(CONFIG_USER_ONLY)
6325 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6326 #else
6327 if (unlikely(ctx->pr)) {
6328 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6329 return;
6330 }
6331 /* Restore CPU state */
6332 gen_helper_rfdi(cpu_env);
6333 gen_sync_exception(ctx);
6334 #endif
6335 }
6336
6337 /* XXX: not implemented on 440 ? */
6338 static void gen_rfmci(DisasContext *ctx)
6339 {
6340 #if defined(CONFIG_USER_ONLY)
6341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6342 #else
6343 if (unlikely(ctx->pr)) {
6344 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6345 return;
6346 }
6347 /* Restore CPU state */
6348 gen_helper_rfmci(cpu_env);
6349 gen_sync_exception(ctx);
6350 #endif
6351 }
6352
6353 /* TLB management - PowerPC 405 implementation */
6354
6355 /* tlbre */
6356 static void gen_tlbre_40x(DisasContext *ctx)
6357 {
6358 #if defined(CONFIG_USER_ONLY)
6359 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6360 #else
6361 if (unlikely(ctx->pr)) {
6362 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6363 return;
6364 }
6365 switch (rB(ctx->opcode)) {
6366 case 0:
6367 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6368 cpu_gpr[rA(ctx->opcode)]);
6369 break;
6370 case 1:
6371 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6372 cpu_gpr[rA(ctx->opcode)]);
6373 break;
6374 default:
6375 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6376 break;
6377 }
6378 #endif
6379 }
6380
6381 /* tlbsx - tlbsx. */
6382 static void gen_tlbsx_40x(DisasContext *ctx)
6383 {
6384 #if defined(CONFIG_USER_ONLY)
6385 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6386 #else
6387 TCGv t0;
6388 if (unlikely(ctx->pr)) {
6389 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6390 return;
6391 }
6392 t0 = tcg_temp_new();
6393 gen_addr_reg_index(ctx, t0);
6394 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6395 tcg_temp_free(t0);
6396 if (Rc(ctx->opcode)) {
6397 int l1 = gen_new_label();
6398 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6399 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6400 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6401 gen_set_label(l1);
6402 }
6403 #endif
6404 }
6405
6406 /* tlbwe */
6407 static void gen_tlbwe_40x(DisasContext *ctx)
6408 {
6409 #if defined(CONFIG_USER_ONLY)
6410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6411 #else
6412 if (unlikely(ctx->pr)) {
6413 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6414 return;
6415 }
6416 switch (rB(ctx->opcode)) {
6417 case 0:
6418 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6419 cpu_gpr[rS(ctx->opcode)]);
6420 break;
6421 case 1:
6422 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6423 cpu_gpr[rS(ctx->opcode)]);
6424 break;
6425 default:
6426 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6427 break;
6428 }
6429 #endif
6430 }
6431
6432 /* TLB management - PowerPC 440 implementation */
6433
6434 /* tlbre */
6435 static void gen_tlbre_440(DisasContext *ctx)
6436 {
6437 #if defined(CONFIG_USER_ONLY)
6438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6439 #else
6440 if (unlikely(ctx->pr)) {
6441 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6442 return;
6443 }
6444 switch (rB(ctx->opcode)) {
6445 case 0:
6446 case 1:
6447 case 2:
6448 {
6449 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6450 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6451 t0, cpu_gpr[rA(ctx->opcode)]);
6452 tcg_temp_free_i32(t0);
6453 }
6454 break;
6455 default:
6456 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6457 break;
6458 }
6459 #endif
6460 }
6461
6462 /* tlbsx - tlbsx. */
6463 static void gen_tlbsx_440(DisasContext *ctx)
6464 {
6465 #if defined(CONFIG_USER_ONLY)
6466 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6467 #else
6468 TCGv t0;
6469 if (unlikely(ctx->pr)) {
6470 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6471 return;
6472 }
6473 t0 = tcg_temp_new();
6474 gen_addr_reg_index(ctx, t0);
6475 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6476 tcg_temp_free(t0);
6477 if (Rc(ctx->opcode)) {
6478 int l1 = gen_new_label();
6479 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6480 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6481 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6482 gen_set_label(l1);
6483 }
6484 #endif
6485 }
6486
6487 /* tlbwe */
6488 static void gen_tlbwe_440(DisasContext *ctx)
6489 {
6490 #if defined(CONFIG_USER_ONLY)
6491 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6492 #else
6493 if (unlikely(ctx->pr)) {
6494 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6495 return;
6496 }
6497 switch (rB(ctx->opcode)) {
6498 case 0:
6499 case 1:
6500 case 2:
6501 {
6502 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6503 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6504 cpu_gpr[rS(ctx->opcode)]);
6505 tcg_temp_free_i32(t0);
6506 }
6507 break;
6508 default:
6509 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6510 break;
6511 }
6512 #endif
6513 }
6514
6515 /* TLB management - PowerPC BookE 2.06 implementation */
6516
6517 /* tlbre */
6518 static void gen_tlbre_booke206(DisasContext *ctx)
6519 {
6520 #if defined(CONFIG_USER_ONLY)
6521 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6522 #else
6523 if (unlikely(ctx->pr)) {
6524 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6525 return;
6526 }
6527
6528 gen_helper_booke206_tlbre(cpu_env);
6529 #endif
6530 }
6531
6532 /* tlbsx - tlbsx. */
6533 static void gen_tlbsx_booke206(DisasContext *ctx)
6534 {
6535 #if defined(CONFIG_USER_ONLY)
6536 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6537 #else
6538 TCGv t0;
6539 if (unlikely(ctx->pr)) {
6540 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6541 return;
6542 }
6543
6544 if (rA(ctx->opcode)) {
6545 t0 = tcg_temp_new();
6546 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6547 } else {
6548 t0 = tcg_const_tl(0);
6549 }
6550
6551 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6552 gen_helper_booke206_tlbsx(cpu_env, t0);
6553 tcg_temp_free(t0);
6554 #endif
6555 }
6556
6557 /* tlbwe */
6558 static void gen_tlbwe_booke206(DisasContext *ctx)
6559 {
6560 #if defined(CONFIG_USER_ONLY)
6561 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6562 #else
6563 if (unlikely(ctx->pr)) {
6564 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6565 return;
6566 }
6567 gen_update_nip(ctx, ctx->nip - 4);
6568 gen_helper_booke206_tlbwe(cpu_env);
6569 #endif
6570 }
6571
6572 static void gen_tlbivax_booke206(DisasContext *ctx)
6573 {
6574 #if defined(CONFIG_USER_ONLY)
6575 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6576 #else
6577 TCGv t0;
6578 if (unlikely(ctx->pr)) {
6579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6580 return;
6581 }
6582
6583 t0 = tcg_temp_new();
6584 gen_addr_reg_index(ctx, t0);
6585
6586 gen_helper_booke206_tlbivax(cpu_env, t0);
6587 tcg_temp_free(t0);
6588 #endif
6589 }
6590
6591 static void gen_tlbilx_booke206(DisasContext *ctx)
6592 {
6593 #if defined(CONFIG_USER_ONLY)
6594 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6595 #else
6596 TCGv t0;
6597 if (unlikely(ctx->pr)) {
6598 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6599 return;
6600 }
6601
6602 t0 = tcg_temp_new();
6603 gen_addr_reg_index(ctx, t0);
6604
6605 switch((ctx->opcode >> 21) & 0x3) {
6606 case 0:
6607 gen_helper_booke206_tlbilx0(cpu_env, t0);
6608 break;
6609 case 1:
6610 gen_helper_booke206_tlbilx1(cpu_env, t0);
6611 break;
6612 case 3:
6613 gen_helper_booke206_tlbilx3(cpu_env, t0);
6614 break;
6615 default:
6616 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6617 break;
6618 }
6619
6620 tcg_temp_free(t0);
6621 #endif
6622 }
6623
6624
6625 /* wrtee */
6626 static void gen_wrtee(DisasContext *ctx)
6627 {
6628 #if defined(CONFIG_USER_ONLY)
6629 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6630 #else
6631 TCGv t0;
6632 if (unlikely(ctx->pr)) {
6633 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6634 return;
6635 }
6636 t0 = tcg_temp_new();
6637 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6638 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6639 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6640 tcg_temp_free(t0);
6641 /* Stop translation to have a chance to raise an exception
6642 * if we just set msr_ee to 1
6643 */
6644 gen_stop_exception(ctx);
6645 #endif
6646 }
6647
6648 /* wrteei */
6649 static void gen_wrteei(DisasContext *ctx)
6650 {
6651 #if defined(CONFIG_USER_ONLY)
6652 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6653 #else
6654 if (unlikely(ctx->pr)) {
6655 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6656 return;
6657 }
6658 if (ctx->opcode & 0x00008000) {
6659 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6660 /* Stop translation to have a chance to raise an exception */
6661 gen_stop_exception(ctx);
6662 } else {
6663 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6664 }
6665 #endif
6666 }
6667
6668 /* PowerPC 440 specific instructions */
6669
6670 /* dlmzb */
6671 static void gen_dlmzb(DisasContext *ctx)
6672 {
6673 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6674 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6675 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6676 tcg_temp_free_i32(t0);
6677 }
6678
6679 /* mbar replaces eieio on 440 */
6680 static void gen_mbar(DisasContext *ctx)
6681 {
6682 /* interpreted as no-op */
6683 }
6684
6685 /* msync replaces sync on 440 */
6686 static void gen_msync_4xx(DisasContext *ctx)
6687 {
6688 /* interpreted as no-op */
6689 }
6690
6691 /* icbt */
6692 static void gen_icbt_440(DisasContext *ctx)
6693 {
6694 /* interpreted as no-op */
6695 /* XXX: specification say this is treated as a load by the MMU
6696 * but does not generate any exception
6697 */
6698 }
6699
6700 /* Embedded.Processor Control */
6701
6702 static void gen_msgclr(DisasContext *ctx)
6703 {
6704 #if defined(CONFIG_USER_ONLY)
6705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6706 #else
6707 if (unlikely(ctx->pr)) {
6708 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6709 return;
6710 }
6711
6712 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6713 #endif
6714 }
6715
6716 static void gen_msgsnd(DisasContext *ctx)
6717 {
6718 #if defined(CONFIG_USER_ONLY)
6719 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6720 #else
6721 if (unlikely(ctx->pr)) {
6722 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6723 return;
6724 }
6725
6726 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6727 #endif
6728 }
6729
6730 /*** Altivec vector extension ***/
6731 /* Altivec registers moves */
6732
6733 static inline TCGv_ptr gen_avr_ptr(int reg)
6734 {
6735 TCGv_ptr r = tcg_temp_new_ptr();
6736 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6737 return r;
6738 }
6739
6740 #define GEN_VR_LDX(name, opc2, opc3) \
6741 static void glue(gen_, name)(DisasContext *ctx) \
6742 { \
6743 TCGv EA; \
6744 if (unlikely(!ctx->altivec_enabled)) { \
6745 gen_exception(ctx, POWERPC_EXCP_VPU); \
6746 return; \
6747 } \
6748 gen_set_access_type(ctx, ACCESS_INT); \
6749 EA = tcg_temp_new(); \
6750 gen_addr_reg_index(ctx, EA); \
6751 tcg_gen_andi_tl(EA, EA, ~0xf); \
6752 /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
6753 64-bit byteswap already. */ \
6754 if (ctx->le_mode) { \
6755 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6756 tcg_gen_addi_tl(EA, EA, 8); \
6757 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6758 } else { \
6759 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6760 tcg_gen_addi_tl(EA, EA, 8); \
6761 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6762 } \
6763 tcg_temp_free(EA); \
6764 }
6765
6766 #define GEN_VR_STX(name, opc2, opc3) \
6767 static void gen_st##name(DisasContext *ctx) \
6768 { \
6769 TCGv EA; \
6770 if (unlikely(!ctx->altivec_enabled)) { \
6771 gen_exception(ctx, POWERPC_EXCP_VPU); \
6772 return; \
6773 } \
6774 gen_set_access_type(ctx, ACCESS_INT); \
6775 EA = tcg_temp_new(); \
6776 gen_addr_reg_index(ctx, EA); \
6777 tcg_gen_andi_tl(EA, EA, ~0xf); \
6778 /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
6779 64-bit byteswap already. */ \
6780 if (ctx->le_mode) { \
6781 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6782 tcg_gen_addi_tl(EA, EA, 8); \
6783 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6784 } else { \
6785 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6786 tcg_gen_addi_tl(EA, EA, 8); \
6787 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6788 } \
6789 tcg_temp_free(EA); \
6790 }
6791
6792 #define GEN_VR_LVE(name, opc2, opc3, size) \
6793 static void gen_lve##name(DisasContext *ctx) \
6794 { \
6795 TCGv EA; \
6796 TCGv_ptr rs; \
6797 if (unlikely(!ctx->altivec_enabled)) { \
6798 gen_exception(ctx, POWERPC_EXCP_VPU); \
6799 return; \
6800 } \
6801 gen_set_access_type(ctx, ACCESS_INT); \
6802 EA = tcg_temp_new(); \
6803 gen_addr_reg_index(ctx, EA); \
6804 if (size > 1) { \
6805 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6806 } \
6807 rs = gen_avr_ptr(rS(ctx->opcode)); \
6808 gen_helper_lve##name(cpu_env, rs, EA); \
6809 tcg_temp_free(EA); \
6810 tcg_temp_free_ptr(rs); \
6811 }
6812
6813 #define GEN_VR_STVE(name, opc2, opc3, size) \
6814 static void gen_stve##name(DisasContext *ctx) \
6815 { \
6816 TCGv EA; \
6817 TCGv_ptr rs; \
6818 if (unlikely(!ctx->altivec_enabled)) { \
6819 gen_exception(ctx, POWERPC_EXCP_VPU); \
6820 return; \
6821 } \
6822 gen_set_access_type(ctx, ACCESS_INT); \
6823 EA = tcg_temp_new(); \
6824 gen_addr_reg_index(ctx, EA); \
6825 if (size > 1) { \
6826 tcg_gen_andi_tl(EA, EA, ~(size - 1)); \
6827 } \
6828 rs = gen_avr_ptr(rS(ctx->opcode)); \
6829 gen_helper_stve##name(cpu_env, rs, EA); \
6830 tcg_temp_free(EA); \
6831 tcg_temp_free_ptr(rs); \
6832 }
6833
6834 GEN_VR_LDX(lvx, 0x07, 0x03);
6835 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6836 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6837
6838 GEN_VR_LVE(bx, 0x07, 0x00, 1);
6839 GEN_VR_LVE(hx, 0x07, 0x01, 2);
6840 GEN_VR_LVE(wx, 0x07, 0x02, 4);
6841
6842 GEN_VR_STX(svx, 0x07, 0x07);
6843 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6844 GEN_VR_STX(svxl, 0x07, 0x0F);
6845
6846 GEN_VR_STVE(bx, 0x07, 0x04, 1);
6847 GEN_VR_STVE(hx, 0x07, 0x05, 2);
6848 GEN_VR_STVE(wx, 0x07, 0x06, 4);
6849
6850 static void gen_lvsl(DisasContext *ctx)
6851 {
6852 TCGv_ptr rd;
6853 TCGv EA;
6854 if (unlikely(!ctx->altivec_enabled)) {
6855 gen_exception(ctx, POWERPC_EXCP_VPU);
6856 return;
6857 }
6858 EA = tcg_temp_new();
6859 gen_addr_reg_index(ctx, EA);
6860 rd = gen_avr_ptr(rD(ctx->opcode));
6861 gen_helper_lvsl(rd, EA);
6862 tcg_temp_free(EA);
6863 tcg_temp_free_ptr(rd);
6864 }
6865
6866 static void gen_lvsr(DisasContext *ctx)
6867 {
6868 TCGv_ptr rd;
6869 TCGv EA;
6870 if (unlikely(!ctx->altivec_enabled)) {
6871 gen_exception(ctx, POWERPC_EXCP_VPU);
6872 return;
6873 }
6874 EA = tcg_temp_new();
6875 gen_addr_reg_index(ctx, EA);
6876 rd = gen_avr_ptr(rD(ctx->opcode));
6877 gen_helper_lvsr(rd, EA);
6878 tcg_temp_free(EA);
6879 tcg_temp_free_ptr(rd);
6880 }
6881
6882 static void gen_mfvscr(DisasContext *ctx)
6883 {
6884 TCGv_i32 t;
6885 if (unlikely(!ctx->altivec_enabled)) {
6886 gen_exception(ctx, POWERPC_EXCP_VPU);
6887 return;
6888 }
6889 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6890 t = tcg_temp_new_i32();
6891 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6892 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6893 tcg_temp_free_i32(t);
6894 }
6895
6896 static void gen_mtvscr(DisasContext *ctx)
6897 {
6898 TCGv_ptr p;
6899 if (unlikely(!ctx->altivec_enabled)) {
6900 gen_exception(ctx, POWERPC_EXCP_VPU);
6901 return;
6902 }
6903 p = gen_avr_ptr(rB(ctx->opcode));
6904 gen_helper_mtvscr(cpu_env, p);
6905 tcg_temp_free_ptr(p);
6906 }
6907
6908 /* Logical operations */
6909 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6910 static void glue(gen_, name)(DisasContext *ctx) \
6911 { \
6912 if (unlikely(!ctx->altivec_enabled)) { \
6913 gen_exception(ctx, POWERPC_EXCP_VPU); \
6914 return; \
6915 } \
6916 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6917 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6918 }
6919
6920 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6921 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6922 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6923 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6924 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6925 GEN_VX_LOGICAL(veqv, tcg_gen_eqv_i64, 2, 26);
6926 GEN_VX_LOGICAL(vnand, tcg_gen_nand_i64, 2, 22);
6927 GEN_VX_LOGICAL(vorc, tcg_gen_orc_i64, 2, 21);
6928
6929 #define GEN_VXFORM(name, opc2, opc3) \
6930 static void glue(gen_, name)(DisasContext *ctx) \
6931 { \
6932 TCGv_ptr ra, rb, rd; \
6933 if (unlikely(!ctx->altivec_enabled)) { \
6934 gen_exception(ctx, POWERPC_EXCP_VPU); \
6935 return; \
6936 } \
6937 ra = gen_avr_ptr(rA(ctx->opcode)); \
6938 rb = gen_avr_ptr(rB(ctx->opcode)); \
6939 rd = gen_avr_ptr(rD(ctx->opcode)); \
6940 gen_helper_##name (rd, ra, rb); \
6941 tcg_temp_free_ptr(ra); \
6942 tcg_temp_free_ptr(rb); \
6943 tcg_temp_free_ptr(rd); \
6944 }
6945
6946 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6947 static void glue(gen_, name)(DisasContext *ctx) \
6948 { \
6949 TCGv_ptr ra, rb, rd; \
6950 if (unlikely(!ctx->altivec_enabled)) { \
6951 gen_exception(ctx, POWERPC_EXCP_VPU); \
6952 return; \
6953 } \
6954 ra = gen_avr_ptr(rA(ctx->opcode)); \
6955 rb = gen_avr_ptr(rB(ctx->opcode)); \
6956 rd = gen_avr_ptr(rD(ctx->opcode)); \
6957 gen_helper_##name(cpu_env, rd, ra, rb); \
6958 tcg_temp_free_ptr(ra); \
6959 tcg_temp_free_ptr(rb); \
6960 tcg_temp_free_ptr(rd); \
6961 }
6962
6963 #define GEN_VXFORM3(name, opc2, opc3) \
6964 static void glue(gen_, name)(DisasContext *ctx) \
6965 { \
6966 TCGv_ptr ra, rb, rc, rd; \
6967 if (unlikely(!ctx->altivec_enabled)) { \
6968 gen_exception(ctx, POWERPC_EXCP_VPU); \
6969 return; \
6970 } \
6971 ra = gen_avr_ptr(rA(ctx->opcode)); \
6972 rb = gen_avr_ptr(rB(ctx->opcode)); \
6973 rc = gen_avr_ptr(rC(ctx->opcode)); \
6974 rd = gen_avr_ptr(rD(ctx->opcode)); \
6975 gen_helper_##name(rd, ra, rb, rc); \
6976 tcg_temp_free_ptr(ra); \
6977 tcg_temp_free_ptr(rb); \
6978 tcg_temp_free_ptr(rc); \
6979 tcg_temp_free_ptr(rd); \
6980 }
6981
6982 /*
6983 * Support for Altivec instruction pairs that use bit 31 (Rc) as
6984 * an opcode bit. In general, these pairs come from different
6985 * versions of the ISA, so we must also support a pair of flags for
6986 * each instruction.
6987 */
6988 #define GEN_VXFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
6989 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6990 { \
6991 if ((Rc(ctx->opcode) == 0) && \
6992 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
6993 gen_##name0(ctx); \
6994 } else if ((Rc(ctx->opcode) == 1) && \
6995 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
6996 gen_##name1(ctx); \
6997 } else { \
6998 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
6999 } \
7000 }
7001
7002 GEN_VXFORM(vaddubm, 0, 0);
7003 GEN_VXFORM(vadduhm, 0, 1);
7004 GEN_VXFORM(vadduwm, 0, 2);
7005 GEN_VXFORM(vaddudm, 0, 3);
7006 GEN_VXFORM(vsububm, 0, 16);
7007 GEN_VXFORM(vsubuhm, 0, 17);
7008 GEN_VXFORM(vsubuwm, 0, 18);
7009 GEN_VXFORM(vsubudm, 0, 19);
7010 GEN_VXFORM(vmaxub, 1, 0);
7011 GEN_VXFORM(vmaxuh, 1, 1);
7012 GEN_VXFORM(vmaxuw, 1, 2);
7013 GEN_VXFORM(vmaxud, 1, 3);
7014 GEN_VXFORM(vmaxsb, 1, 4);
7015 GEN_VXFORM(vmaxsh, 1, 5);
7016 GEN_VXFORM(vmaxsw, 1, 6);
7017 GEN_VXFORM(vmaxsd, 1, 7);
7018 GEN_VXFORM(vminub, 1, 8);
7019 GEN_VXFORM(vminuh, 1, 9);
7020 GEN_VXFORM(vminuw, 1, 10);
7021 GEN_VXFORM(vminud, 1, 11);
7022 GEN_VXFORM(vminsb, 1, 12);
7023 GEN_VXFORM(vminsh, 1, 13);
7024 GEN_VXFORM(vminsw, 1, 14);
7025 GEN_VXFORM(vminsd, 1, 15);
7026 GEN_VXFORM(vavgub, 1, 16);
7027 GEN_VXFORM(vavguh, 1, 17);
7028 GEN_VXFORM(vavguw, 1, 18);
7029 GEN_VXFORM(vavgsb, 1, 20);
7030 GEN_VXFORM(vavgsh, 1, 21);
7031 GEN_VXFORM(vavgsw, 1, 22);
7032 GEN_VXFORM(vmrghb, 6, 0);
7033 GEN_VXFORM(vmrghh, 6, 1);
7034 GEN_VXFORM(vmrghw, 6, 2);
7035 GEN_VXFORM(vmrglb, 6, 4);
7036 GEN_VXFORM(vmrglh, 6, 5);
7037 GEN_VXFORM(vmrglw, 6, 6);
7038
7039 static void gen_vmrgew(DisasContext *ctx)
7040 {
7041 TCGv_i64 tmp;
7042 int VT, VA, VB;
7043 if (unlikely(!ctx->altivec_enabled)) {
7044 gen_exception(ctx, POWERPC_EXCP_VPU);
7045 return;
7046 }
7047 VT = rD(ctx->opcode);
7048 VA = rA(ctx->opcode);
7049 VB = rB(ctx->opcode);
7050 tmp = tcg_temp_new_i64();
7051 tcg_gen_shri_i64(tmp, cpu_avrh[VB], 32);
7052 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VA], tmp, 0, 32);
7053 tcg_gen_shri_i64(tmp, cpu_avrl[VB], 32);
7054 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VA], tmp, 0, 32);
7055 tcg_temp_free_i64(tmp);
7056 }
7057
7058 static void gen_vmrgow(DisasContext *ctx)
7059 {
7060 int VT, VA, VB;
7061 if (unlikely(!ctx->altivec_enabled)) {
7062 gen_exception(ctx, POWERPC_EXCP_VPU);
7063 return;
7064 }
7065 VT = rD(ctx->opcode);
7066 VA = rA(ctx->opcode);
7067 VB = rB(ctx->opcode);
7068
7069 tcg_gen_deposit_i64(cpu_avrh[VT], cpu_avrh[VB], cpu_avrh[VA], 32, 32);
7070 tcg_gen_deposit_i64(cpu_avrl[VT], cpu_avrl[VB], cpu_avrl[VA], 32, 32);
7071 }
7072
7073 GEN_VXFORM(vmuloub, 4, 0);
7074 GEN_VXFORM(vmulouh, 4, 1);
7075 GEN_VXFORM(vmulouw, 4, 2);
7076 GEN_VXFORM(vmuluwm, 4, 2);
7077 GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
7078 vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
7079 GEN_VXFORM(vmulosb, 4, 4);
7080 GEN_VXFORM(vmulosh, 4, 5);
7081 GEN_VXFORM(vmulosw, 4, 6);
7082 GEN_VXFORM(vmuleub, 4, 8);
7083 GEN_VXFORM(vmuleuh, 4, 9);
7084 GEN_VXFORM(vmuleuw, 4, 10);
7085 GEN_VXFORM(vmulesb, 4, 12);
7086 GEN_VXFORM(vmulesh, 4, 13);
7087 GEN_VXFORM(vmulesw, 4, 14);
7088 GEN_VXFORM(vslb, 2, 4);
7089 GEN_VXFORM(vslh, 2, 5);
7090 GEN_VXFORM(vslw, 2, 6);
7091 GEN_VXFORM(vsld, 2, 23);
7092 GEN_VXFORM(vsrb, 2, 8);
7093 GEN_VXFORM(vsrh, 2, 9);
7094 GEN_VXFORM(vsrw, 2, 10);
7095 GEN_VXFORM(vsrd, 2, 27);
7096 GEN_VXFORM(vsrab, 2, 12);
7097 GEN_VXFORM(vsrah, 2, 13);
7098 GEN_VXFORM(vsraw, 2, 14);
7099 GEN_VXFORM(vsrad, 2, 15);
7100 GEN_VXFORM(vslo, 6, 16);
7101 GEN_VXFORM(vsro, 6, 17);
7102 GEN_VXFORM(vaddcuw, 0, 6);
7103 GEN_VXFORM(vsubcuw, 0, 22);
7104 GEN_VXFORM_ENV(vaddubs, 0, 8);
7105 GEN_VXFORM_ENV(vadduhs, 0, 9);
7106 GEN_VXFORM_ENV(vadduws, 0, 10);
7107 GEN_VXFORM_ENV(vaddsbs, 0, 12);
7108 GEN_VXFORM_ENV(vaddshs, 0, 13);
7109 GEN_VXFORM_ENV(vaddsws, 0, 14);
7110 GEN_VXFORM_ENV(vsububs, 0, 24);
7111 GEN_VXFORM_ENV(vsubuhs, 0, 25);
7112 GEN_VXFORM_ENV(vsubuws, 0, 26);
7113 GEN_VXFORM_ENV(vsubsbs, 0, 28);
7114 GEN_VXFORM_ENV(vsubshs, 0, 29);
7115 GEN_VXFORM_ENV(vsubsws, 0, 30);
7116 GEN_VXFORM(vadduqm, 0, 4);
7117 GEN_VXFORM(vaddcuq, 0, 5);
7118 GEN_VXFORM3(vaddeuqm, 30, 0);
7119 GEN_VXFORM3(vaddecuq, 30, 0);
7120 GEN_VXFORM_DUAL(vaddeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7121 vaddecuq, PPC_NONE, PPC2_ALTIVEC_207)
7122 GEN_VXFORM(vsubuqm, 0, 20);
7123 GEN_VXFORM(vsubcuq, 0, 21);
7124 GEN_VXFORM3(vsubeuqm, 31, 0);
7125 GEN_VXFORM3(vsubecuq, 31, 0);
7126 GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
7127 vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
7128 GEN_VXFORM(vrlb, 2, 0);
7129 GEN_VXFORM(vrlh, 2, 1);
7130 GEN_VXFORM(vrlw, 2, 2);
7131 GEN_VXFORM(vrld, 2, 3);
7132 GEN_VXFORM(vsl, 2, 7);
7133 GEN_VXFORM(vsr, 2, 11);
7134 GEN_VXFORM_ENV(vpkuhum, 7, 0);
7135 GEN_VXFORM_ENV(vpkuwum, 7, 1);
7136 GEN_VXFORM_ENV(vpkudum, 7, 17);
7137 GEN_VXFORM_ENV(vpkuhus, 7, 2);
7138 GEN_VXFORM_ENV(vpkuwus, 7, 3);
7139 GEN_VXFORM_ENV(vpkudus, 7, 19);
7140 GEN_VXFORM_ENV(vpkshus, 7, 4);
7141 GEN_VXFORM_ENV(vpkswus, 7, 5);
7142 GEN_VXFORM_ENV(vpksdus, 7, 21);
7143 GEN_VXFORM_ENV(vpkshss, 7, 6);
7144 GEN_VXFORM_ENV(vpkswss, 7, 7);
7145 GEN_VXFORM_ENV(vpksdss, 7, 23);
7146 GEN_VXFORM(vpkpx, 7, 12);
7147 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
7148 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
7149 GEN_VXFORM_ENV(vsum4shs, 4, 25);
7150 GEN_VXFORM_ENV(vsum2sws, 4, 26);
7151 GEN_VXFORM_ENV(vsumsws, 4, 30);
7152 GEN_VXFORM_ENV(vaddfp, 5, 0);
7153 GEN_VXFORM_ENV(vsubfp, 5, 1);
7154 GEN_VXFORM_ENV(vmaxfp, 5, 16);
7155 GEN_VXFORM_ENV(vminfp, 5, 17);
7156
7157 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
7158 static void glue(gen_, name)(DisasContext *ctx) \
7159 { \
7160 TCGv_ptr ra, rb, rd; \
7161 if (unlikely(!ctx->altivec_enabled)) { \
7162 gen_exception(ctx, POWERPC_EXCP_VPU); \
7163 return; \
7164 } \
7165 ra = gen_avr_ptr(rA(ctx->opcode)); \
7166 rb = gen_avr_ptr(rB(ctx->opcode)); \
7167 rd = gen_avr_ptr(rD(ctx->opcode)); \
7168 gen_helper_##opname(cpu_env, rd, ra, rb); \
7169 tcg_temp_free_ptr(ra); \
7170 tcg_temp_free_ptr(rb); \
7171 tcg_temp_free_ptr(rd); \
7172 }
7173
7174 #define GEN_VXRFORM(name, opc2, opc3) \
7175 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
7176 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
7177
7178 /*
7179 * Support for Altivec instructions that use bit 31 (Rc) as an opcode
7180 * bit but also use bit 21 as an actual Rc bit. In general, thse pairs
7181 * come from different versions of the ISA, so we must also support a
7182 * pair of flags for each instruction.
7183 */
7184 #define GEN_VXRFORM_DUAL(name0, flg0, flg2_0, name1, flg1, flg2_1) \
7185 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7186 { \
7187 if ((Rc(ctx->opcode) == 0) && \
7188 ((ctx->insns_flags & flg0) || (ctx->insns_flags2 & flg2_0))) { \
7189 if (Rc21(ctx->opcode) == 0) { \
7190 gen_##name0(ctx); \
7191 } else { \
7192 gen_##name0##_(ctx); \
7193 } \
7194 } else if ((Rc(ctx->opcode) == 1) && \
7195 ((ctx->insns_flags & flg1) || (ctx->insns_flags2 & flg2_1))) { \
7196 if (Rc21(ctx->opcode) == 0) { \
7197 gen_##name1(ctx); \
7198 } else { \
7199 gen_##name1##_(ctx); \
7200 } \
7201 } else { \
7202 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
7203 } \
7204 }
7205
7206 GEN_VXRFORM(vcmpequb, 3, 0)
7207 GEN_VXRFORM(vcmpequh, 3, 1)
7208 GEN_VXRFORM(vcmpequw, 3, 2)
7209 GEN_VXRFORM(vcmpequd, 3, 3)
7210 GEN_VXRFORM(vcmpgtsb, 3, 12)
7211 GEN_VXRFORM(vcmpgtsh, 3, 13)
7212 GEN_VXRFORM(vcmpgtsw, 3, 14)
7213 GEN_VXRFORM(vcmpgtsd, 3, 15)
7214 GEN_VXRFORM(vcmpgtub, 3, 8)
7215 GEN_VXRFORM(vcmpgtuh, 3, 9)
7216 GEN_VXRFORM(vcmpgtuw, 3, 10)
7217 GEN_VXRFORM(vcmpgtud, 3, 11)
7218 GEN_VXRFORM(vcmpeqfp, 3, 3)
7219 GEN_VXRFORM(vcmpgefp, 3, 7)
7220 GEN_VXRFORM(vcmpgtfp, 3, 11)
7221 GEN_VXRFORM(vcmpbfp, 3, 15)
7222
7223 GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
7224 vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
7225 GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
7226 vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
7227 GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
7228 vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
7229
7230 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7231 static void glue(gen_, name)(DisasContext *ctx) \
7232 { \
7233 TCGv_ptr rd; \
7234 TCGv_i32 simm; \
7235 if (unlikely(!ctx->altivec_enabled)) { \
7236 gen_exception(ctx, POWERPC_EXCP_VPU); \
7237 return; \
7238 } \
7239 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7240 rd = gen_avr_ptr(rD(ctx->opcode)); \
7241 gen_helper_##name (rd, simm); \
7242 tcg_temp_free_i32(simm); \
7243 tcg_temp_free_ptr(rd); \
7244 }
7245
7246 GEN_VXFORM_SIMM(vspltisb, 6, 12);
7247 GEN_VXFORM_SIMM(vspltish, 6, 13);
7248 GEN_VXFORM_SIMM(vspltisw, 6, 14);
7249
7250 #define GEN_VXFORM_NOA(name, opc2, opc3) \
7251 static void glue(gen_, name)(DisasContext *ctx) \
7252 { \
7253 TCGv_ptr rb, rd; \
7254 if (unlikely(!ctx->altivec_enabled)) { \
7255 gen_exception(ctx, POWERPC_EXCP_VPU); \
7256 return; \
7257 } \
7258 rb = gen_avr_ptr(rB(ctx->opcode)); \
7259 rd = gen_avr_ptr(rD(ctx->opcode)); \
7260 gen_helper_##name (rd, rb); \
7261 tcg_temp_free_ptr(rb); \
7262 tcg_temp_free_ptr(rd); \
7263 }
7264
7265 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
7266 static void glue(gen_, name)(DisasContext *ctx) \
7267 { \
7268 TCGv_ptr rb, rd; \
7269 \
7270 if (unlikely(!ctx->altivec_enabled)) { \
7271 gen_exception(ctx, POWERPC_EXCP_VPU); \
7272 return; \
7273 } \
7274 rb = gen_avr_ptr(rB(ctx->opcode)); \
7275 rd = gen_avr_ptr(rD(ctx->opcode)); \
7276 gen_helper_##name(cpu_env, rd, rb); \
7277 tcg_temp_free_ptr(rb); \
7278 tcg_temp_free_ptr(rd); \
7279 }
7280
7281 GEN_VXFORM_NOA(vupkhsb, 7, 8);
7282 GEN_VXFORM_NOA(vupkhsh, 7, 9);
7283 GEN_VXFORM_NOA(vupkhsw, 7, 25);
7284 GEN_VXFORM_NOA(vupklsb, 7, 10);
7285 GEN_VXFORM_NOA(vupklsh, 7, 11);
7286 GEN_VXFORM_NOA(vupklsw, 7, 27);
7287 GEN_VXFORM_NOA(vupkhpx, 7, 13);
7288 GEN_VXFORM_NOA(vupklpx, 7, 15);
7289 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
7290 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
7291 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
7292 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
7293 GEN_VXFORM_NOA_ENV(vrfim, 5, 11);
7294 GEN_VXFORM_NOA_ENV(vrfin, 5, 8);
7295 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
7296 GEN_VXFORM_NOA_ENV(vrfiz, 5, 9);
7297
7298 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
7299 static void glue(gen_, name)(DisasContext *ctx) \
7300 { \
7301 TCGv_ptr rd; \
7302 TCGv_i32 simm; \
7303 if (unlikely(!ctx->altivec_enabled)) { \
7304 gen_exception(ctx, POWERPC_EXCP_VPU); \
7305 return; \
7306 } \
7307 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
7308 rd = gen_avr_ptr(rD(ctx->opcode)); \
7309 gen_helper_##name (rd, simm); \
7310 tcg_temp_free_i32(simm); \
7311 tcg_temp_free_ptr(rd); \
7312 }
7313
7314 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7315 static void glue(gen_, name)(DisasContext *ctx) \
7316 { \
7317 TCGv_ptr rb, rd; \
7318 TCGv_i32 uimm; \
7319 if (unlikely(!ctx->altivec_enabled)) { \
7320 gen_exception(ctx, POWERPC_EXCP_VPU); \
7321 return; \
7322 } \
7323 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7324 rb = gen_avr_ptr(rB(ctx->opcode)); \
7325 rd = gen_avr_ptr(rD(ctx->opcode)); \
7326 gen_helper_##name (rd, rb, uimm); \
7327 tcg_temp_free_i32(uimm); \
7328 tcg_temp_free_ptr(rb); \
7329 tcg_temp_free_ptr(rd); \
7330 }
7331
7332 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7333 static void glue(gen_, name)(DisasContext *ctx) \
7334 { \
7335 TCGv_ptr rb, rd; \
7336 TCGv_i32 uimm; \
7337 \
7338 if (unlikely(!ctx->altivec_enabled)) { \
7339 gen_exception(ctx, POWERPC_EXCP_VPU); \
7340 return; \
7341 } \
7342 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7343 rb = gen_avr_ptr(rB(ctx->opcode)); \
7344 rd = gen_avr_ptr(rD(ctx->opcode)); \
7345 gen_helper_##name(cpu_env, rd, rb, uimm); \
7346 tcg_temp_free_i32(uimm); \
7347 tcg_temp_free_ptr(rb); \
7348 tcg_temp_free_ptr(rd); \
7349 }
7350
7351 GEN_VXFORM_UIMM(vspltb, 6, 8);
7352 GEN_VXFORM_UIMM(vsplth, 6, 9);
7353 GEN_VXFORM_UIMM(vspltw, 6, 10);
7354 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7355 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7356 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7357 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7358
7359 static void gen_vsldoi(DisasContext *ctx)
7360 {
7361 TCGv_ptr ra, rb, rd;
7362 TCGv_i32 sh;
7363 if (unlikely(!ctx->altivec_enabled)) {
7364 gen_exception(ctx, POWERPC_EXCP_VPU);
7365 return;
7366 }
7367 ra = gen_avr_ptr(rA(ctx->opcode));
7368 rb = gen_avr_ptr(rB(ctx->opcode));
7369 rd = gen_avr_ptr(rD(ctx->opcode));
7370 sh = tcg_const_i32(VSH(ctx->opcode));
7371 gen_helper_vsldoi (rd, ra, rb, sh);
7372 tcg_temp_free_ptr(ra);
7373 tcg_temp_free_ptr(rb);
7374 tcg_temp_free_ptr(rd);
7375 tcg_temp_free_i32(sh);
7376 }
7377
7378 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7379 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7380 { \
7381 TCGv_ptr ra, rb, rc, rd; \
7382 if (unlikely(!ctx->altivec_enabled)) { \
7383 gen_exception(ctx, POWERPC_EXCP_VPU); \
7384 return; \
7385 } \
7386 ra = gen_avr_ptr(rA(ctx->opcode)); \
7387 rb = gen_avr_ptr(rB(ctx->opcode)); \
7388 rc = gen_avr_ptr(rC(ctx->opcode)); \
7389 rd = gen_avr_ptr(rD(ctx->opcode)); \
7390 if (Rc(ctx->opcode)) { \
7391 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7392 } else { \
7393 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7394 } \
7395 tcg_temp_free_ptr(ra); \
7396 tcg_temp_free_ptr(rb); \
7397 tcg_temp_free_ptr(rc); \
7398 tcg_temp_free_ptr(rd); \
7399 }
7400
7401 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7402
7403 static void gen_vmladduhm(DisasContext *ctx)
7404 {
7405 TCGv_ptr ra, rb, rc, rd;
7406 if (unlikely(!ctx->altivec_enabled)) {
7407 gen_exception(ctx, POWERPC_EXCP_VPU);
7408 return;
7409 }
7410 ra = gen_avr_ptr(rA(ctx->opcode));
7411 rb = gen_avr_ptr(rB(ctx->opcode));
7412 rc = gen_avr_ptr(rC(ctx->opcode));
7413 rd = gen_avr_ptr(rD(ctx->opcode));
7414 gen_helper_vmladduhm(rd, ra, rb, rc);
7415 tcg_temp_free_ptr(ra);
7416 tcg_temp_free_ptr(rb);
7417 tcg_temp_free_ptr(rc);
7418 tcg_temp_free_ptr(rd);
7419 }
7420
7421 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7422 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7423 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7424 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7425 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7426
7427 GEN_VXFORM_NOA(vclzb, 1, 28)
7428 GEN_VXFORM_NOA(vclzh, 1, 29)
7429 GEN_VXFORM_NOA(vclzw, 1, 30)
7430 GEN_VXFORM_NOA(vclzd, 1, 31)
7431 GEN_VXFORM_NOA(vpopcntb, 1, 28)
7432 GEN_VXFORM_NOA(vpopcnth, 1, 29)
7433 GEN_VXFORM_NOA(vpopcntw, 1, 30)
7434 GEN_VXFORM_NOA(vpopcntd, 1, 31)
7435 GEN_VXFORM_DUAL(vclzb, PPC_NONE, PPC2_ALTIVEC_207, \
7436 vpopcntb, PPC_NONE, PPC2_ALTIVEC_207)
7437 GEN_VXFORM_DUAL(vclzh, PPC_NONE, PPC2_ALTIVEC_207, \
7438 vpopcnth, PPC_NONE, PPC2_ALTIVEC_207)
7439 GEN_VXFORM_DUAL(vclzw, PPC_NONE, PPC2_ALTIVEC_207, \
7440 vpopcntw, PPC_NONE, PPC2_ALTIVEC_207)
7441 GEN_VXFORM_DUAL(vclzd, PPC_NONE, PPC2_ALTIVEC_207, \
7442 vpopcntd, PPC_NONE, PPC2_ALTIVEC_207)
7443 GEN_VXFORM(vbpermq, 6, 21);
7444 GEN_VXFORM_NOA(vgbbd, 6, 20);
7445 GEN_VXFORM(vpmsumb, 4, 16)
7446 GEN_VXFORM(vpmsumh, 4, 17)
7447 GEN_VXFORM(vpmsumw, 4, 18)
7448 GEN_VXFORM(vpmsumd, 4, 19)
7449
7450 #define GEN_BCD(op) \
7451 static void gen_##op(DisasContext *ctx) \
7452 { \
7453 TCGv_ptr ra, rb, rd; \
7454 TCGv_i32 ps; \
7455 \
7456 if (unlikely(!ctx->altivec_enabled)) { \
7457 gen_exception(ctx, POWERPC_EXCP_VPU); \
7458 return; \
7459 } \
7460 \
7461 ra = gen_avr_ptr(rA(ctx->opcode)); \
7462 rb = gen_avr_ptr(rB(ctx->opcode)); \
7463 rd = gen_avr_ptr(rD(ctx->opcode)); \
7464 \
7465 ps = tcg_const_i32((ctx->opcode & 0x200) != 0); \
7466 \
7467 gen_helper_##op(cpu_crf[6], rd, ra, rb, ps); \
7468 \
7469 tcg_temp_free_ptr(ra); \
7470 tcg_temp_free_ptr(rb); \
7471 tcg_temp_free_ptr(rd); \
7472 tcg_temp_free_i32(ps); \
7473 }
7474
7475 GEN_BCD(bcdadd)
7476 GEN_BCD(bcdsub)
7477
7478 GEN_VXFORM_DUAL(vsububm, PPC_ALTIVEC, PPC_NONE, \
7479 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7480 GEN_VXFORM_DUAL(vsububs, PPC_ALTIVEC, PPC_NONE, \
7481 bcdadd, PPC_NONE, PPC2_ALTIVEC_207)
7482 GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
7483 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7484 GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
7485 bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
7486
7487 static void gen_vsbox(DisasContext *ctx)
7488 {
7489 TCGv_ptr ra, rd;
7490 if (unlikely(!ctx->altivec_enabled)) {
7491 gen_exception(ctx, POWERPC_EXCP_VPU);
7492 return;
7493 }
7494 ra = gen_avr_ptr(rA(ctx->opcode));
7495 rd = gen_avr_ptr(rD(ctx->opcode));
7496 gen_helper_vsbox(rd, ra);
7497 tcg_temp_free_ptr(ra);
7498 tcg_temp_free_ptr(rd);
7499 }
7500
7501 GEN_VXFORM(vcipher, 4, 20)
7502 GEN_VXFORM(vcipherlast, 4, 20)
7503 GEN_VXFORM(vncipher, 4, 21)
7504 GEN_VXFORM(vncipherlast, 4, 21)
7505
7506 GEN_VXFORM_DUAL(vcipher, PPC_NONE, PPC2_ALTIVEC_207,
7507 vcipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7508 GEN_VXFORM_DUAL(vncipher, PPC_NONE, PPC2_ALTIVEC_207,
7509 vncipherlast, PPC_NONE, PPC2_ALTIVEC_207)
7510
7511 #define VSHASIGMA(op) \
7512 static void gen_##op(DisasContext *ctx) \
7513 { \
7514 TCGv_ptr ra, rd; \
7515 TCGv_i32 st_six; \
7516 if (unlikely(!ctx->altivec_enabled)) { \
7517 gen_exception(ctx, POWERPC_EXCP_VPU); \
7518 return; \
7519 } \
7520 ra = gen_avr_ptr(rA(ctx->opcode)); \
7521 rd = gen_avr_ptr(rD(ctx->opcode)); \
7522 st_six = tcg_const_i32(rB(ctx->opcode)); \
7523 gen_helper_##op(rd, ra, st_six); \
7524 tcg_temp_free_ptr(ra); \
7525 tcg_temp_free_ptr(rd); \
7526 tcg_temp_free_i32(st_six); \
7527 }
7528
7529 VSHASIGMA(vshasigmaw)
7530 VSHASIGMA(vshasigmad)
7531
7532 GEN_VXFORM3(vpermxor, 22, 0xFF)
7533 GEN_VXFORM_DUAL(vsldoi, PPC_ALTIVEC, PPC_NONE,
7534 vpermxor, PPC_NONE, PPC2_ALTIVEC_207)
7535
7536 /*** VSX extension ***/
7537
7538 static inline TCGv_i64 cpu_vsrh(int n)
7539 {
7540 if (n < 32) {
7541 return cpu_fpr[n];
7542 } else {
7543 return cpu_avrh[n-32];
7544 }
7545 }
7546
7547 static inline TCGv_i64 cpu_vsrl(int n)
7548 {
7549 if (n < 32) {
7550 return cpu_vsr[n];
7551 } else {
7552 return cpu_avrl[n-32];
7553 }
7554 }
7555
7556 #define VSX_LOAD_SCALAR(name, operation) \
7557 static void gen_##name(DisasContext *ctx) \
7558 { \
7559 TCGv EA; \
7560 if (unlikely(!ctx->vsx_enabled)) { \
7561 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7562 return; \
7563 } \
7564 gen_set_access_type(ctx, ACCESS_INT); \
7565 EA = tcg_temp_new(); \
7566 gen_addr_reg_index(ctx, EA); \
7567 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7568 /* NOTE: cpu_vsrl is undefined */ \
7569 tcg_temp_free(EA); \
7570 }
7571
7572 VSX_LOAD_SCALAR(lxsdx, ld64)
7573 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7574 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7575 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7576
7577 static void gen_lxvd2x(DisasContext *ctx)
7578 {
7579 TCGv EA;
7580 if (unlikely(!ctx->vsx_enabled)) {
7581 gen_exception(ctx, POWERPC_EXCP_VSXU);
7582 return;
7583 }
7584 gen_set_access_type(ctx, ACCESS_INT);
7585 EA = tcg_temp_new();
7586 gen_addr_reg_index(ctx, EA);
7587 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7588 tcg_gen_addi_tl(EA, EA, 8);
7589 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7590 tcg_temp_free(EA);
7591 }
7592
7593 static void gen_lxvdsx(DisasContext *ctx)
7594 {
7595 TCGv EA;
7596 if (unlikely(!ctx->vsx_enabled)) {
7597 gen_exception(ctx, POWERPC_EXCP_VSXU);
7598 return;
7599 }
7600 gen_set_access_type(ctx, ACCESS_INT);
7601 EA = tcg_temp_new();
7602 gen_addr_reg_index(ctx, EA);
7603 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7604 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7605 tcg_temp_free(EA);
7606 }
7607
7608 static void gen_lxvw4x(DisasContext *ctx)
7609 {
7610 TCGv EA;
7611 TCGv_i64 tmp;
7612 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7613 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7614 if (unlikely(!ctx->vsx_enabled)) {
7615 gen_exception(ctx, POWERPC_EXCP_VSXU);
7616 return;
7617 }
7618 gen_set_access_type(ctx, ACCESS_INT);
7619 EA = tcg_temp_new();
7620 tmp = tcg_temp_new_i64();
7621
7622 gen_addr_reg_index(ctx, EA);
7623 gen_qemu_ld32u_i64(ctx, tmp, EA);
7624 tcg_gen_addi_tl(EA, EA, 4);
7625 gen_qemu_ld32u_i64(ctx, xth, EA);
7626 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7627
7628 tcg_gen_addi_tl(EA, EA, 4);
7629 gen_qemu_ld32u_i64(ctx, tmp, EA);
7630 tcg_gen_addi_tl(EA, EA, 4);
7631 gen_qemu_ld32u_i64(ctx, xtl, EA);
7632 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7633
7634 tcg_temp_free(EA);
7635 tcg_temp_free_i64(tmp);
7636 }
7637
7638 #define VSX_STORE_SCALAR(name, operation) \
7639 static void gen_##name(DisasContext *ctx) \
7640 { \
7641 TCGv EA; \
7642 if (unlikely(!ctx->vsx_enabled)) { \
7643 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7644 return; \
7645 } \
7646 gen_set_access_type(ctx, ACCESS_INT); \
7647 EA = tcg_temp_new(); \
7648 gen_addr_reg_index(ctx, EA); \
7649 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7650 tcg_temp_free(EA); \
7651 }
7652
7653 VSX_STORE_SCALAR(stxsdx, st64)
7654 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7655 VSX_STORE_SCALAR(stxsspx, st32fs)
7656
7657 static void gen_stxvd2x(DisasContext *ctx)
7658 {
7659 TCGv EA;
7660 if (unlikely(!ctx->vsx_enabled)) {
7661 gen_exception(ctx, POWERPC_EXCP_VSXU);
7662 return;
7663 }
7664 gen_set_access_type(ctx, ACCESS_INT);
7665 EA = tcg_temp_new();
7666 gen_addr_reg_index(ctx, EA);
7667 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7668 tcg_gen_addi_tl(EA, EA, 8);
7669 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7670 tcg_temp_free(EA);
7671 }
7672
7673 static void gen_stxvw4x(DisasContext *ctx)
7674 {
7675 TCGv_i64 tmp;
7676 TCGv EA;
7677 if (unlikely(!ctx->vsx_enabled)) {
7678 gen_exception(ctx, POWERPC_EXCP_VSXU);
7679 return;
7680 }
7681 gen_set_access_type(ctx, ACCESS_INT);
7682 EA = tcg_temp_new();
7683 gen_addr_reg_index(ctx, EA);
7684 tmp = tcg_temp_new_i64();
7685
7686 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7687 gen_qemu_st32_i64(ctx, tmp, EA);
7688 tcg_gen_addi_tl(EA, EA, 4);
7689 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7690
7691 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7692 tcg_gen_addi_tl(EA, EA, 4);
7693 gen_qemu_st32_i64(ctx, tmp, EA);
7694 tcg_gen_addi_tl(EA, EA, 4);
7695 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7696
7697 tcg_temp_free(EA);
7698 tcg_temp_free_i64(tmp);
7699 }
7700
7701 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7702 static void gen_##name(DisasContext *ctx) \
7703 { \
7704 if (xS(ctx->opcode) < 32) { \
7705 if (unlikely(!ctx->fpu_enabled)) { \
7706 gen_exception(ctx, POWERPC_EXCP_FPU); \
7707 return; \
7708 } \
7709 } else { \
7710 if (unlikely(!ctx->altivec_enabled)) { \
7711 gen_exception(ctx, POWERPC_EXCP_VPU); \
7712 return; \
7713 } \
7714 } \
7715 TCGv_i64 tmp = tcg_temp_new_i64(); \
7716 tcg_gen_##tcgop1(tmp, source); \
7717 tcg_gen_##tcgop2(target, tmp); \
7718 tcg_temp_free_i64(tmp); \
7719 }
7720
7721
7722 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7723 cpu_vsrh(xS(ctx->opcode)))
7724 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7725 cpu_gpr[rA(ctx->opcode)])
7726 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7727 cpu_gpr[rA(ctx->opcode)])
7728
7729 #if defined(TARGET_PPC64)
7730 #define MV_VSRD(name, target, source) \
7731 static void gen_##name(DisasContext *ctx) \
7732 { \
7733 if (xS(ctx->opcode) < 32) { \
7734 if (unlikely(!ctx->fpu_enabled)) { \
7735 gen_exception(ctx, POWERPC_EXCP_FPU); \
7736 return; \
7737 } \
7738 } else { \
7739 if (unlikely(!ctx->altivec_enabled)) { \
7740 gen_exception(ctx, POWERPC_EXCP_VPU); \
7741 return; \
7742 } \
7743 } \
7744 tcg_gen_mov_i64(target, source); \
7745 }
7746
7747 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7748 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7749
7750 #endif
7751
7752 static void gen_xxpermdi(DisasContext *ctx)
7753 {
7754 if (unlikely(!ctx->vsx_enabled)) {
7755 gen_exception(ctx, POWERPC_EXCP_VSXU);
7756 return;
7757 }
7758
7759 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7760 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7761 TCGv_i64 xh, xl;
7762
7763 xh = tcg_temp_new_i64();
7764 xl = tcg_temp_new_i64();
7765
7766 if ((DM(ctx->opcode) & 2) == 0) {
7767 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7768 } else {
7769 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7770 }
7771 if ((DM(ctx->opcode) & 1) == 0) {
7772 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7773 } else {
7774 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7775 }
7776
7777 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7778 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7779
7780 tcg_temp_free_i64(xh);
7781 tcg_temp_free_i64(xl);
7782 } else {
7783 if ((DM(ctx->opcode) & 2) == 0) {
7784 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7785 } else {
7786 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7787 }
7788 if ((DM(ctx->opcode) & 1) == 0) {
7789 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7790 } else {
7791 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7792 }
7793 }
7794 }
7795
7796 #define OP_ABS 1
7797 #define OP_NABS 2
7798 #define OP_NEG 3
7799 #define OP_CPSGN 4
7800 #define SGN_MASK_DP 0x8000000000000000ull
7801 #define SGN_MASK_SP 0x8000000080000000ull
7802
7803 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7804 static void glue(gen_, name)(DisasContext * ctx) \
7805 { \
7806 TCGv_i64 xb, sgm; \
7807 if (unlikely(!ctx->vsx_enabled)) { \
7808 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7809 return; \
7810 } \
7811 xb = tcg_temp_new_i64(); \
7812 sgm = tcg_temp_new_i64(); \
7813 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7814 tcg_gen_movi_i64(sgm, sgn_mask); \
7815 switch (op) { \
7816 case OP_ABS: { \
7817 tcg_gen_andc_i64(xb, xb, sgm); \
7818 break; \
7819 } \
7820 case OP_NABS: { \
7821 tcg_gen_or_i64(xb, xb, sgm); \
7822 break; \
7823 } \
7824 case OP_NEG: { \
7825 tcg_gen_xor_i64(xb, xb, sgm); \
7826 break; \
7827 } \
7828 case OP_CPSGN: { \
7829 TCGv_i64 xa = tcg_temp_new_i64(); \
7830 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7831 tcg_gen_and_i64(xa, xa, sgm); \
7832 tcg_gen_andc_i64(xb, xb, sgm); \
7833 tcg_gen_or_i64(xb, xb, xa); \
7834 tcg_temp_free_i64(xa); \
7835 break; \
7836 } \
7837 } \
7838 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7839 tcg_temp_free_i64(xb); \
7840 tcg_temp_free_i64(sgm); \
7841 }
7842
7843 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7844 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7845 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7846 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7847
7848 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7849 static void glue(gen_, name)(DisasContext * ctx) \
7850 { \
7851 TCGv_i64 xbh, xbl, sgm; \
7852 if (unlikely(!ctx->vsx_enabled)) { \
7853 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7854 return; \
7855 } \
7856 xbh = tcg_temp_new_i64(); \
7857 xbl = tcg_temp_new_i64(); \
7858 sgm = tcg_temp_new_i64(); \
7859 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7860 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7861 tcg_gen_movi_i64(sgm, sgn_mask); \
7862 switch (op) { \
7863 case OP_ABS: { \
7864 tcg_gen_andc_i64(xbh, xbh, sgm); \
7865 tcg_gen_andc_i64(xbl, xbl, sgm); \
7866 break; \
7867 } \
7868 case OP_NABS: { \
7869 tcg_gen_or_i64(xbh, xbh, sgm); \
7870 tcg_gen_or_i64(xbl, xbl, sgm); \
7871 break; \
7872 } \
7873 case OP_NEG: { \
7874 tcg_gen_xor_i64(xbh, xbh, sgm); \
7875 tcg_gen_xor_i64(xbl, xbl, sgm); \
7876 break; \
7877 } \
7878 case OP_CPSGN: { \
7879 TCGv_i64 xah = tcg_temp_new_i64(); \
7880 TCGv_i64 xal = tcg_temp_new_i64(); \
7881 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7882 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7883 tcg_gen_and_i64(xah, xah, sgm); \
7884 tcg_gen_and_i64(xal, xal, sgm); \
7885 tcg_gen_andc_i64(xbh, xbh, sgm); \
7886 tcg_gen_andc_i64(xbl, xbl, sgm); \
7887 tcg_gen_or_i64(xbh, xbh, xah); \
7888 tcg_gen_or_i64(xbl, xbl, xal); \
7889 tcg_temp_free_i64(xah); \
7890 tcg_temp_free_i64(xal); \
7891 break; \
7892 } \
7893 } \
7894 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7895 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7896 tcg_temp_free_i64(xbh); \
7897 tcg_temp_free_i64(xbl); \
7898 tcg_temp_free_i64(sgm); \
7899 }
7900
7901 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7902 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7903 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7904 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7905 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7906 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7907 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7908 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7909
7910 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7911 static void gen_##name(DisasContext * ctx) \
7912 { \
7913 TCGv_i32 opc; \
7914 if (unlikely(!ctx->vsx_enabled)) { \
7915 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7916 return; \
7917 } \
7918 /* NIP cannot be restored if the memory exception comes from an helper */ \
7919 gen_update_nip(ctx, ctx->nip - 4); \
7920 opc = tcg_const_i32(ctx->opcode); \
7921 gen_helper_##name(cpu_env, opc); \
7922 tcg_temp_free_i32(opc); \
7923 }
7924
7925 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7926 static void gen_##name(DisasContext * ctx) \
7927 { \
7928 if (unlikely(!ctx->vsx_enabled)) { \
7929 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7930 return; \
7931 } \
7932 /* NIP cannot be restored if the exception comes */ \
7933 /* from a helper. */ \
7934 gen_update_nip(ctx, ctx->nip - 4); \
7935 \
7936 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7937 cpu_vsrh(xB(ctx->opcode))); \
7938 }
7939
7940 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7941 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7942 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7943 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7944 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7945 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7946 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7947 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7948 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7949 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7950 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7951 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7952 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7953 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7954 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7955 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7956 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7957 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7958 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7959 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7960 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7961 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7962 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7963 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7964 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7965 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7966 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7967 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7968 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7969 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7970 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7971 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7972 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7973 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7974 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7975 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7976 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7977
7978 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7979 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7980 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7981 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7982 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7983 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7984 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7985 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7986 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7987 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7988 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7989 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7990 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7991 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7992 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7993 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7994 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7995
7996 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7997 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7998 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7999 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
8000 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
8001 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
8002 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
8003 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
8004 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
8005 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
8006 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
8007 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
8008 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
8009 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
8010 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
8011 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
8012 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
8013 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
8014 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
8015 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
8016 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
8017 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
8018 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
8019 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
8020 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
8021 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
8022 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
8023 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
8024 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
8025 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
8026 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
8027 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
8028 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
8029 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
8030 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
8031 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
8032
8033 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
8034 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
8035 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
8036 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
8037 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
8038 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
8039 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
8040 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
8041 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
8042 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
8043 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
8044 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
8045 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
8046 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
8047 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
8048 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
8049 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
8050 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
8051 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
8052 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
8053 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
8054 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
8055 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
8056 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
8057 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
8058 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
8059 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
8060 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
8061 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
8062 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
8063 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
8064 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
8065 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
8066 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
8067 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
8068 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
8069
8070 #define VSX_LOGICAL(name, tcg_op) \
8071 static void glue(gen_, name)(DisasContext * ctx) \
8072 { \
8073 if (unlikely(!ctx->vsx_enabled)) { \
8074 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8075 return; \
8076 } \
8077 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
8078 cpu_vsrh(xB(ctx->opcode))); \
8079 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
8080 cpu_vsrl(xB(ctx->opcode))); \
8081 }
8082
8083 VSX_LOGICAL(xxland, tcg_gen_and_i64)
8084 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
8085 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
8086 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
8087 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
8088 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
8089 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
8090 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
8091
8092 #define VSX_XXMRG(name, high) \
8093 static void glue(gen_, name)(DisasContext * ctx) \
8094 { \
8095 TCGv_i64 a0, a1, b0, b1; \
8096 if (unlikely(!ctx->vsx_enabled)) { \
8097 gen_exception(ctx, POWERPC_EXCP_VSXU); \
8098 return; \
8099 } \
8100 a0 = tcg_temp_new_i64(); \
8101 a1 = tcg_temp_new_i64(); \
8102 b0 = tcg_temp_new_i64(); \
8103 b1 = tcg_temp_new_i64(); \
8104 if (high) { \
8105 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
8106 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
8107 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
8108 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
8109 } else { \
8110 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
8111 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
8112 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
8113 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
8114 } \
8115 tcg_gen_shri_i64(a0, a0, 32); \
8116 tcg_gen_shri_i64(b0, b0, 32); \
8117 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
8118 b0, a0, 32, 32); \
8119 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
8120 b1, a1, 32, 32); \
8121 tcg_temp_free_i64(a0); \
8122 tcg_temp_free_i64(a1); \
8123 tcg_temp_free_i64(b0); \
8124 tcg_temp_free_i64(b1); \
8125 }
8126
8127 VSX_XXMRG(xxmrghw, 1)
8128 VSX_XXMRG(xxmrglw, 0)
8129
8130 static void gen_xxsel(DisasContext * ctx)
8131 {
8132 TCGv_i64 a, b, c;
8133 if (unlikely(!ctx->vsx_enabled)) {
8134 gen_exception(ctx, POWERPC_EXCP_VSXU);
8135 return;
8136 }
8137 a = tcg_temp_new_i64();
8138 b = tcg_temp_new_i64();
8139 c = tcg_temp_new_i64();
8140
8141 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
8142 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
8143 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
8144
8145 tcg_gen_and_i64(b, b, c);
8146 tcg_gen_andc_i64(a, a, c);
8147 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
8148
8149 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
8150 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
8151 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
8152
8153 tcg_gen_and_i64(b, b, c);
8154 tcg_gen_andc_i64(a, a, c);
8155 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
8156
8157 tcg_temp_free_i64(a);
8158 tcg_temp_free_i64(b);
8159 tcg_temp_free_i64(c);
8160 }
8161
8162 static void gen_xxspltw(DisasContext *ctx)
8163 {
8164 TCGv_i64 b, b2;
8165 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
8166 cpu_vsrl(xB(ctx->opcode)) :
8167 cpu_vsrh(xB(ctx->opcode));
8168
8169 if (unlikely(!ctx->vsx_enabled)) {
8170 gen_exception(ctx, POWERPC_EXCP_VSXU);
8171 return;
8172 }
8173
8174 b = tcg_temp_new_i64();
8175 b2 = tcg_temp_new_i64();
8176
8177 if (UIM(ctx->opcode) & 1) {
8178 tcg_gen_ext32u_i64(b, vsr);
8179 } else {
8180 tcg_gen_shri_i64(b, vsr, 32);
8181 }
8182
8183 tcg_gen_shli_i64(b2, b, 32);
8184 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
8185 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
8186
8187 tcg_temp_free_i64(b);
8188 tcg_temp_free_i64(b2);
8189 }
8190
8191 static void gen_xxsldwi(DisasContext *ctx)
8192 {
8193 TCGv_i64 xth, xtl;
8194 if (unlikely(!ctx->vsx_enabled)) {
8195 gen_exception(ctx, POWERPC_EXCP_VSXU);
8196 return;
8197 }
8198 xth = tcg_temp_new_i64();
8199 xtl = tcg_temp_new_i64();
8200
8201 switch (SHW(ctx->opcode)) {
8202 case 0: {
8203 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8204 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8205 break;
8206 }
8207 case 1: {
8208 TCGv_i64 t0 = tcg_temp_new_i64();
8209 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
8210 tcg_gen_shli_i64(xth, xth, 32);
8211 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
8212 tcg_gen_shri_i64(t0, t0, 32);
8213 tcg_gen_or_i64(xth, xth, t0);
8214 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
8215 tcg_gen_shli_i64(xtl, xtl, 32);
8216 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8217 tcg_gen_shri_i64(t0, t0, 32);
8218 tcg_gen_or_i64(xtl, xtl, t0);
8219 tcg_temp_free_i64(t0);
8220 break;
8221 }
8222 case 2: {
8223 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8224 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8225 break;
8226 }
8227 case 3: {
8228 TCGv_i64 t0 = tcg_temp_new_i64();
8229 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
8230 tcg_gen_shli_i64(xth, xth, 32);
8231 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
8232 tcg_gen_shri_i64(t0, t0, 32);
8233 tcg_gen_or_i64(xth, xth, t0);
8234 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
8235 tcg_gen_shli_i64(xtl, xtl, 32);
8236 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
8237 tcg_gen_shri_i64(t0, t0, 32);
8238 tcg_gen_or_i64(xtl, xtl, t0);
8239 tcg_temp_free_i64(t0);
8240 break;
8241 }
8242 }
8243
8244 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
8245 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
8246
8247 tcg_temp_free_i64(xth);
8248 tcg_temp_free_i64(xtl);
8249 }
8250
8251 /*** Decimal Floating Point ***/
8252
8253 static inline TCGv_ptr gen_fprp_ptr(int reg)
8254 {
8255 TCGv_ptr r = tcg_temp_new_ptr();
8256 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, fpr[reg]));
8257 return r;
8258 }
8259
8260 #define GEN_DFP_T_A_B_Rc(name) \
8261 static void gen_##name(DisasContext *ctx) \
8262 { \
8263 TCGv_ptr rd, ra, rb; \
8264 if (unlikely(!ctx->fpu_enabled)) { \
8265 gen_exception(ctx, POWERPC_EXCP_FPU); \
8266 return; \
8267 } \
8268 gen_update_nip(ctx, ctx->nip - 4); \
8269 rd = gen_fprp_ptr(rD(ctx->opcode)); \
8270 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8271 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8272 gen_helper_##name(cpu_env, rd, ra, rb); \
8273 if (unlikely(Rc(ctx->opcode) != 0)) { \
8274 gen_set_cr1_from_fpscr(ctx); \
8275 } \
8276 tcg_temp_free_ptr(rd); \
8277 tcg_temp_free_ptr(ra); \
8278 tcg_temp_free_ptr(rb); \
8279 }
8280
8281 #define GEN_DFP_BF_A_B(name) \
8282 static void gen_##name(DisasContext *ctx) \
8283 { \
8284 TCGv_ptr ra, rb; \
8285 if (unlikely(!ctx->fpu_enabled)) { \
8286 gen_exception(ctx, POWERPC_EXCP_FPU); \
8287 return; \
8288 } \
8289 gen_update_nip(ctx, ctx->nip - 4); \
8290 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8291 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8292 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8293 cpu_env, ra, rb); \
8294 tcg_temp_free_ptr(ra); \
8295 tcg_temp_free_ptr(rb); \
8296 }
8297
8298 #define GEN_DFP_BF_A_DCM(name) \
8299 static void gen_##name(DisasContext *ctx) \
8300 { \
8301 TCGv_ptr ra; \
8302 TCGv_i32 dcm; \
8303 if (unlikely(!ctx->fpu_enabled)) { \
8304 gen_exception(ctx, POWERPC_EXCP_FPU); \
8305 return; \
8306 } \
8307 gen_update_nip(ctx, ctx->nip - 4); \
8308 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8309 dcm = tcg_const_i32(DCM(ctx->opcode)); \
8310 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
8311 cpu_env, ra, dcm); \
8312 tcg_temp_free_ptr(ra); \
8313 tcg_temp_free_i32(dcm); \
8314 }
8315
8316 #define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
8317 static void gen_##name(DisasContext *ctx) \
8318 { \
8319 TCGv_ptr rt, rb; \
8320 TCGv_i32 u32_1, u32_2; \
8321 if (unlikely(!ctx->fpu_enabled)) { \
8322 gen_exception(ctx, POWERPC_EXCP_FPU); \
8323 return; \
8324 } \
8325 gen_update_nip(ctx, ctx->nip - 4); \
8326 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8327 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8328 u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
8329 u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
8330 gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
8331 if (unlikely(Rc(ctx->opcode) != 0)) { \
8332 gen_set_cr1_from_fpscr(ctx); \
8333 } \
8334 tcg_temp_free_ptr(rt); \
8335 tcg_temp_free_ptr(rb); \
8336 tcg_temp_free_i32(u32_1); \
8337 tcg_temp_free_i32(u32_2); \
8338 }
8339
8340 #define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
8341 static void gen_##name(DisasContext *ctx) \
8342 { \
8343 TCGv_ptr rt, ra, rb; \
8344 TCGv_i32 i32; \
8345 if (unlikely(!ctx->fpu_enabled)) { \
8346 gen_exception(ctx, POWERPC_EXCP_FPU); \
8347 return; \
8348 } \
8349 gen_update_nip(ctx, ctx->nip - 4); \
8350 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8351 ra = gen_fprp_ptr(rA(ctx->opcode)); \
8352 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8353 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8354 gen_helper_##name(cpu_env, rt, ra, rb, i32); \
8355 if (unlikely(Rc(ctx->opcode) != 0)) { \
8356 gen_set_cr1_from_fpscr(ctx); \
8357 } \
8358 tcg_temp_free_ptr(rt); \
8359 tcg_temp_free_ptr(rb); \
8360 tcg_temp_free_ptr(ra); \
8361 tcg_temp_free_i32(i32); \
8362 }
8363
8364 #define GEN_DFP_T_B_Rc(name) \
8365 static void gen_##name(DisasContext *ctx) \
8366 { \
8367 TCGv_ptr rt, rb; \
8368 if (unlikely(!ctx->fpu_enabled)) { \
8369 gen_exception(ctx, POWERPC_EXCP_FPU); \
8370 return; \
8371 } \
8372 gen_update_nip(ctx, ctx->nip - 4); \
8373 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8374 rb = gen_fprp_ptr(rB(ctx->opcode)); \
8375 gen_helper_##name(cpu_env, rt, rb); \
8376 if (unlikely(Rc(ctx->opcode) != 0)) { \
8377 gen_set_cr1_from_fpscr(ctx); \
8378 } \
8379 tcg_temp_free_ptr(rt); \
8380 tcg_temp_free_ptr(rb); \
8381 }
8382
8383 #define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
8384 static void gen_##name(DisasContext *ctx) \
8385 { \
8386 TCGv_ptr rt, rs; \
8387 TCGv_i32 i32; \
8388 if (unlikely(!ctx->fpu_enabled)) { \
8389 gen_exception(ctx, POWERPC_EXCP_FPU); \
8390 return; \
8391 } \
8392 gen_update_nip(ctx, ctx->nip - 4); \
8393 rt = gen_fprp_ptr(rD(ctx->opcode)); \
8394 rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
8395 i32 = tcg_const_i32(i32fld(ctx->opcode)); \
8396 gen_helper_##name(cpu_env, rt, rs, i32); \
8397 if (unlikely(Rc(ctx->opcode) != 0)) { \
8398 gen_set_cr1_from_fpscr(ctx); \
8399 } \
8400 tcg_temp_free_ptr(rt); \
8401 tcg_temp_free_ptr(rs); \
8402 tcg_temp_free_i32(i32); \
8403 }
8404
8405 GEN_DFP_T_A_B_Rc(dadd)
8406 GEN_DFP_T_A_B_Rc(daddq)
8407 GEN_DFP_T_A_B_Rc(dsub)
8408 GEN_DFP_T_A_B_Rc(dsubq)
8409 GEN_DFP_T_A_B_Rc(dmul)
8410 GEN_DFP_T_A_B_Rc(dmulq)
8411 GEN_DFP_T_A_B_Rc(ddiv)
8412 GEN_DFP_T_A_B_Rc(ddivq)
8413 GEN_DFP_BF_A_B(dcmpu)
8414 GEN_DFP_BF_A_B(dcmpuq)
8415 GEN_DFP_BF_A_B(dcmpo)
8416 GEN_DFP_BF_A_B(dcmpoq)
8417 GEN_DFP_BF_A_DCM(dtstdc)
8418 GEN_DFP_BF_A_DCM(dtstdcq)
8419 GEN_DFP_BF_A_DCM(dtstdg)
8420 GEN_DFP_BF_A_DCM(dtstdgq)
8421 GEN_DFP_BF_A_B(dtstex)
8422 GEN_DFP_BF_A_B(dtstexq)
8423 GEN_DFP_BF_A_B(dtstsf)
8424 GEN_DFP_BF_A_B(dtstsfq)
8425 GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
8426 GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
8427 GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
8428 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
8429 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
8430 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
8431 GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
8432 GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
8433 GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
8434 GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
8435 GEN_DFP_T_B_Rc(dctdp)
8436 GEN_DFP_T_B_Rc(dctqpq)
8437 GEN_DFP_T_B_Rc(drsp)
8438 GEN_DFP_T_B_Rc(drdpq)
8439 GEN_DFP_T_B_Rc(dcffix)
8440 GEN_DFP_T_B_Rc(dcffixq)
8441 GEN_DFP_T_B_Rc(dctfix)
8442 GEN_DFP_T_B_Rc(dctfixq)
8443 GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
8444 GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
8445 GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
8446 GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
8447 GEN_DFP_T_B_Rc(dxex)
8448 GEN_DFP_T_B_Rc(dxexq)
8449 GEN_DFP_T_A_B_Rc(diex)
8450 GEN_DFP_T_A_B_Rc(diexq)
8451 GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
8452 GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
8453 GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
8454 GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
8455
8456 /*** SPE extension ***/
8457 /* Register moves */
8458
8459 static inline void gen_evmra(DisasContext *ctx)
8460 {
8461
8462 if (unlikely(!ctx->spe_enabled)) {
8463 gen_exception(ctx, POWERPC_EXCP_SPEU);
8464 return;
8465 }
8466
8467 TCGv_i64 tmp = tcg_temp_new_i64();
8468
8469 /* tmp := rA_lo + rA_hi << 32 */
8470 tcg_gen_concat_tl_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8471
8472 /* spe_acc := tmp */
8473 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8474 tcg_temp_free_i64(tmp);
8475
8476 /* rD := rA */
8477 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8478 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8479 }
8480
8481 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
8482 {
8483 tcg_gen_concat_tl_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
8484 }
8485
8486 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
8487 {
8488 tcg_gen_extr_i64_tl(cpu_gpr[reg], cpu_gprh[reg], t);
8489 }
8490
8491 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
8492 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
8493 { \
8494 if (Rc(ctx->opcode)) \
8495 gen_##name1(ctx); \
8496 else \
8497 gen_##name0(ctx); \
8498 }
8499
8500 /* Handler for undefined SPE opcodes */
8501 static inline void gen_speundef(DisasContext *ctx)
8502 {
8503 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
8504 }
8505
8506 /* SPE logic */
8507 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
8508 static inline void gen_##name(DisasContext *ctx) \
8509 { \
8510 if (unlikely(!ctx->spe_enabled)) { \
8511 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8512 return; \
8513 } \
8514 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8515 cpu_gpr[rB(ctx->opcode)]); \
8516 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8517 cpu_gprh[rB(ctx->opcode)]); \
8518 }
8519
8520 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
8521 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
8522 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
8523 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
8524 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
8525 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
8526 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
8527 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
8528
8529 /* SPE logic immediate */
8530 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
8531 static inline void gen_##name(DisasContext *ctx) \
8532 { \
8533 TCGv_i32 t0; \
8534 if (unlikely(!ctx->spe_enabled)) { \
8535 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8536 return; \
8537 } \
8538 t0 = tcg_temp_new_i32(); \
8539 \
8540 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8541 tcg_opi(t0, t0, rB(ctx->opcode)); \
8542 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8543 \
8544 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8545 tcg_opi(t0, t0, rB(ctx->opcode)); \
8546 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8547 \
8548 tcg_temp_free_i32(t0); \
8549 }
8550 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
8551 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
8552 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
8553 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
8554
8555 /* SPE arithmetic */
8556 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8557 static inline void gen_##name(DisasContext *ctx) \
8558 { \
8559 TCGv_i32 t0; \
8560 if (unlikely(!ctx->spe_enabled)) { \
8561 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8562 return; \
8563 } \
8564 t0 = tcg_temp_new_i32(); \
8565 \
8566 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8567 tcg_op(t0, t0); \
8568 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8569 \
8570 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8571 tcg_op(t0, t0); \
8572 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8573 \
8574 tcg_temp_free_i32(t0); \
8575 }
8576
8577 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8578 {
8579 int l1 = gen_new_label();
8580 int l2 = gen_new_label();
8581
8582 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8583 tcg_gen_neg_i32(ret, arg1);
8584 tcg_gen_br(l2);
8585 gen_set_label(l1);
8586 tcg_gen_mov_i32(ret, arg1);
8587 gen_set_label(l2);
8588 }
8589 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8590 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8591 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8592 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8593 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8594 {
8595 tcg_gen_addi_i32(ret, arg1, 0x8000);
8596 tcg_gen_ext16u_i32(ret, ret);
8597 }
8598 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8599 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8600 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8601
8602 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8603 static inline void gen_##name(DisasContext *ctx) \
8604 { \
8605 TCGv_i32 t0, t1; \
8606 if (unlikely(!ctx->spe_enabled)) { \
8607 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8608 return; \
8609 } \
8610 t0 = tcg_temp_new_i32(); \
8611 t1 = tcg_temp_new_i32(); \
8612 \
8613 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8614 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8615 tcg_op(t0, t0, t1); \
8616 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8617 \
8618 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
8619 tcg_gen_trunc_tl_i32(t1, cpu_gprh[rB(ctx->opcode)]); \
8620 tcg_op(t0, t0, t1); \
8621 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8622 \
8623 tcg_temp_free_i32(t0); \
8624 tcg_temp_free_i32(t1); \
8625 }
8626
8627 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8628 {
8629 TCGv_i32 t0;
8630 int l1, l2;
8631
8632 l1 = gen_new_label();
8633 l2 = gen_new_label();
8634 t0 = tcg_temp_local_new_i32();
8635 /* No error here: 6 bits are used */
8636 tcg_gen_andi_i32(t0, arg2, 0x3F);
8637 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8638 tcg_gen_shr_i32(ret, arg1, t0);
8639 tcg_gen_br(l2);
8640 gen_set_label(l1);
8641 tcg_gen_movi_i32(ret, 0);
8642 gen_set_label(l2);
8643 tcg_temp_free_i32(t0);
8644 }
8645 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8646 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8647 {
8648 TCGv_i32 t0;
8649 int l1, l2;
8650
8651 l1 = gen_new_label();
8652 l2 = gen_new_label();
8653 t0 = tcg_temp_local_new_i32();
8654 /* No error here: 6 bits are used */
8655 tcg_gen_andi_i32(t0, arg2, 0x3F);
8656 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8657 tcg_gen_sar_i32(ret, arg1, t0);
8658 tcg_gen_br(l2);
8659 gen_set_label(l1);
8660 tcg_gen_movi_i32(ret, 0);
8661 gen_set_label(l2);
8662 tcg_temp_free_i32(t0);
8663 }
8664 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8665 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8666 {
8667 TCGv_i32 t0;
8668 int l1, l2;
8669
8670 l1 = gen_new_label();
8671 l2 = gen_new_label();
8672 t0 = tcg_temp_local_new_i32();
8673 /* No error here: 6 bits are used */
8674 tcg_gen_andi_i32(t0, arg2, 0x3F);
8675 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8676 tcg_gen_shl_i32(ret, arg1, t0);
8677 tcg_gen_br(l2);
8678 gen_set_label(l1);
8679 tcg_gen_movi_i32(ret, 0);
8680 gen_set_label(l2);
8681 tcg_temp_free_i32(t0);
8682 }
8683 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8684 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8685 {
8686 TCGv_i32 t0 = tcg_temp_new_i32();
8687 tcg_gen_andi_i32(t0, arg2, 0x1F);
8688 tcg_gen_rotl_i32(ret, arg1, t0);
8689 tcg_temp_free_i32(t0);
8690 }
8691 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8692 static inline void gen_evmergehi(DisasContext *ctx)
8693 {
8694 if (unlikely(!ctx->spe_enabled)) {
8695 gen_exception(ctx, POWERPC_EXCP_SPEU);
8696 return;
8697 }
8698 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8699 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8700 }
8701 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8702 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8703 {
8704 tcg_gen_sub_i32(ret, arg2, arg1);
8705 }
8706 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8707
8708 /* SPE arithmetic immediate */
8709 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8710 static inline void gen_##name(DisasContext *ctx) \
8711 { \
8712 TCGv_i32 t0; \
8713 if (unlikely(!ctx->spe_enabled)) { \
8714 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8715 return; \
8716 } \
8717 t0 = tcg_temp_new_i32(); \
8718 \
8719 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8720 tcg_op(t0, t0, rA(ctx->opcode)); \
8721 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
8722 \
8723 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rB(ctx->opcode)]); \
8724 tcg_op(t0, t0, rA(ctx->opcode)); \
8725 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
8726 \
8727 tcg_temp_free_i32(t0); \
8728 }
8729 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8730 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8731
8732 /* SPE comparison */
8733 #define GEN_SPEOP_COMP(name, tcg_cond) \
8734 static inline void gen_##name(DisasContext *ctx) \
8735 { \
8736 if (unlikely(!ctx->spe_enabled)) { \
8737 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8738 return; \
8739 } \
8740 int l1 = gen_new_label(); \
8741 int l2 = gen_new_label(); \
8742 int l3 = gen_new_label(); \
8743 int l4 = gen_new_label(); \
8744 \
8745 tcg_gen_ext32s_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8746 tcg_gen_ext32s_tl(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8747 tcg_gen_ext32s_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8748 tcg_gen_ext32s_tl(cpu_gprh[rB(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); \
8749 \
8750 tcg_gen_brcond_tl(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8751 cpu_gpr[rB(ctx->opcode)], l1); \
8752 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8753 tcg_gen_br(l2); \
8754 gen_set_label(l1); \
8755 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8756 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8757 gen_set_label(l2); \
8758 tcg_gen_brcond_tl(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8759 cpu_gprh[rB(ctx->opcode)], l3); \
8760 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8761 ~(CRF_CH | CRF_CH_AND_CL)); \
8762 tcg_gen_br(l4); \
8763 gen_set_label(l3); \
8764 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8765 CRF_CH | CRF_CH_OR_CL); \
8766 gen_set_label(l4); \
8767 }
8768 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8769 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8770 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8771 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8772 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8773
8774 /* SPE misc */
8775 static inline void gen_brinc(DisasContext *ctx)
8776 {
8777 /* Note: brinc is usable even if SPE is disabled */
8778 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8779 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8780 }
8781 static inline void gen_evmergelo(DisasContext *ctx)
8782 {
8783 if (unlikely(!ctx->spe_enabled)) {
8784 gen_exception(ctx, POWERPC_EXCP_SPEU);
8785 return;
8786 }
8787 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8788 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8789 }
8790 static inline void gen_evmergehilo(DisasContext *ctx)
8791 {
8792 if (unlikely(!ctx->spe_enabled)) {
8793 gen_exception(ctx, POWERPC_EXCP_SPEU);
8794 return;
8795 }
8796 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8797 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8798 }
8799 static inline void gen_evmergelohi(DisasContext *ctx)
8800 {
8801 if (unlikely(!ctx->spe_enabled)) {
8802 gen_exception(ctx, POWERPC_EXCP_SPEU);
8803 return;
8804 }
8805 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8806 TCGv tmp = tcg_temp_new();
8807 tcg_gen_mov_tl(tmp, cpu_gpr[rA(ctx->opcode)]);
8808 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8809 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], tmp);
8810 tcg_temp_free(tmp);
8811 } else {
8812 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8813 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8814 }
8815 }
8816 static inline void gen_evsplati(DisasContext *ctx)
8817 {
8818 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8819
8820 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8821 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8822 }
8823 static inline void gen_evsplatfi(DisasContext *ctx)
8824 {
8825 uint64_t imm = rA(ctx->opcode) << 27;
8826
8827 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], imm);
8828 tcg_gen_movi_tl(cpu_gprh[rD(ctx->opcode)], imm);
8829 }
8830
8831 static inline void gen_evsel(DisasContext *ctx)
8832 {
8833 int l1 = gen_new_label();
8834 int l2 = gen_new_label();
8835 int l3 = gen_new_label();
8836 int l4 = gen_new_label();
8837 TCGv_i32 t0 = tcg_temp_local_new_i32();
8838 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8839 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8840 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8841 tcg_gen_br(l2);
8842 gen_set_label(l1);
8843 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8844 gen_set_label(l2);
8845 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8846 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8847 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8848 tcg_gen_br(l4);
8849 gen_set_label(l3);
8850 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8851 gen_set_label(l4);
8852 tcg_temp_free_i32(t0);
8853 }
8854
8855 static void gen_evsel0(DisasContext *ctx)
8856 {
8857 gen_evsel(ctx);
8858 }
8859
8860 static void gen_evsel1(DisasContext *ctx)
8861 {
8862 gen_evsel(ctx);
8863 }
8864
8865 static void gen_evsel2(DisasContext *ctx)
8866 {
8867 gen_evsel(ctx);
8868 }
8869
8870 static void gen_evsel3(DisasContext *ctx)
8871 {
8872 gen_evsel(ctx);
8873 }
8874
8875 /* Multiply */
8876
8877 static inline void gen_evmwumi(DisasContext *ctx)
8878 {
8879 TCGv_i64 t0, t1;
8880
8881 if (unlikely(!ctx->spe_enabled)) {
8882 gen_exception(ctx, POWERPC_EXCP_SPEU);
8883 return;
8884 }
8885
8886 t0 = tcg_temp_new_i64();
8887 t1 = tcg_temp_new_i64();
8888
8889 /* t0 := rA; t1 := rB */
8890 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8891 tcg_gen_ext32u_i64(t0, t0);
8892 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8893 tcg_gen_ext32u_i64(t1, t1);
8894
8895 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8896
8897 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8898
8899 tcg_temp_free_i64(t0);
8900 tcg_temp_free_i64(t1);
8901 }
8902
8903 static inline void gen_evmwumia(DisasContext *ctx)
8904 {
8905 TCGv_i64 tmp;
8906
8907 if (unlikely(!ctx->spe_enabled)) {
8908 gen_exception(ctx, POWERPC_EXCP_SPEU);
8909 return;
8910 }
8911
8912 gen_evmwumi(ctx); /* rD := rA * rB */
8913
8914 tmp = tcg_temp_new_i64();
8915
8916 /* acc := rD */
8917 gen_load_gpr64(tmp, rD(ctx->opcode));
8918 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8919 tcg_temp_free_i64(tmp);
8920 }
8921
8922 static inline void gen_evmwumiaa(DisasContext *ctx)
8923 {
8924 TCGv_i64 acc;
8925 TCGv_i64 tmp;
8926
8927 if (unlikely(!ctx->spe_enabled)) {
8928 gen_exception(ctx, POWERPC_EXCP_SPEU);
8929 return;
8930 }
8931
8932 gen_evmwumi(ctx); /* rD := rA * rB */
8933
8934 acc = tcg_temp_new_i64();
8935 tmp = tcg_temp_new_i64();
8936
8937 /* tmp := rD */
8938 gen_load_gpr64(tmp, rD(ctx->opcode));
8939
8940 /* Load acc */
8941 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8942
8943 /* acc := tmp + acc */
8944 tcg_gen_add_i64(acc, acc, tmp);
8945
8946 /* Store acc */
8947 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8948
8949 /* rD := acc */
8950 gen_store_gpr64(rD(ctx->opcode), acc);
8951
8952 tcg_temp_free_i64(acc);
8953 tcg_temp_free_i64(tmp);
8954 }
8955
8956 static inline void gen_evmwsmi(DisasContext *ctx)
8957 {
8958 TCGv_i64 t0, t1;
8959
8960 if (unlikely(!ctx->spe_enabled)) {
8961 gen_exception(ctx, POWERPC_EXCP_SPEU);
8962 return;
8963 }
8964
8965 t0 = tcg_temp_new_i64();
8966 t1 = tcg_temp_new_i64();
8967
8968 /* t0 := rA; t1 := rB */
8969 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8970 tcg_gen_ext32s_i64(t0, t0);
8971 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8972 tcg_gen_ext32s_i64(t1, t1);
8973
8974 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8975
8976 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8977
8978 tcg_temp_free_i64(t0);
8979 tcg_temp_free_i64(t1);
8980 }
8981
8982 static inline void gen_evmwsmia(DisasContext *ctx)
8983 {
8984 TCGv_i64 tmp;
8985
8986 gen_evmwsmi(ctx); /* rD := rA * rB */
8987
8988 tmp = tcg_temp_new_i64();
8989
8990 /* acc := rD */
8991 gen_load_gpr64(tmp, rD(ctx->opcode));
8992 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8993
8994 tcg_temp_free_i64(tmp);
8995 }
8996
8997 static inline void gen_evmwsmiaa(DisasContext *ctx)
8998 {
8999 TCGv_i64 acc = tcg_temp_new_i64();
9000 TCGv_i64 tmp = tcg_temp_new_i64();
9001
9002 gen_evmwsmi(ctx); /* rD := rA * rB */
9003
9004 acc = tcg_temp_new_i64();
9005 tmp = tcg_temp_new_i64();
9006
9007 /* tmp := rD */
9008 gen_load_gpr64(tmp, rD(ctx->opcode));
9009
9010 /* Load acc */
9011 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9012
9013 /* acc := tmp + acc */
9014 tcg_gen_add_i64(acc, acc, tmp);
9015
9016 /* Store acc */
9017 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
9018
9019 /* rD := acc */
9020 gen_store_gpr64(rD(ctx->opcode), acc);
9021
9022 tcg_temp_free_i64(acc);
9023 tcg_temp_free_i64(tmp);
9024 }
9025
9026 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9027 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9028 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9029 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9030 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9031 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9032 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
9033 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
9034 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
9035 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9036 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9037 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9038 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9039 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9040 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9041 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9042 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
9043 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9044 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9045 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
9046 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
9047 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9048 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
9049 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
9050 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9051 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
9052 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9053 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
9054 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
9055
9056 /* SPE load and stores */
9057 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
9058 {
9059 target_ulong uimm = rB(ctx->opcode);
9060
9061 if (rA(ctx->opcode) == 0) {
9062 tcg_gen_movi_tl(EA, uimm << sh);
9063 } else {
9064 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
9065 if (NARROW_MODE(ctx)) {
9066 tcg_gen_ext32u_tl(EA, EA);
9067 }
9068 }
9069 }
9070
9071 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
9072 {
9073 TCGv_i64 t0 = tcg_temp_new_i64();
9074 gen_qemu_ld64(ctx, t0, addr);
9075 gen_store_gpr64(rD(ctx->opcode), t0);
9076 tcg_temp_free_i64(t0);
9077 }
9078
9079 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
9080 {
9081 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9082 gen_addr_add(ctx, addr, addr, 4);
9083 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9084 }
9085
9086 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
9087 {
9088 TCGv t0 = tcg_temp_new();
9089 gen_qemu_ld16u(ctx, t0, addr);
9090 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9091 gen_addr_add(ctx, addr, addr, 2);
9092 gen_qemu_ld16u(ctx, t0, addr);
9093 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9094 gen_addr_add(ctx, addr, addr, 2);
9095 gen_qemu_ld16u(ctx, t0, addr);
9096 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9097 gen_addr_add(ctx, addr, addr, 2);
9098 gen_qemu_ld16u(ctx, t0, addr);
9099 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
9100 tcg_temp_free(t0);
9101 }
9102
9103 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
9104 {
9105 TCGv t0 = tcg_temp_new();
9106 gen_qemu_ld16u(ctx, t0, addr);
9107 tcg_gen_shli_tl(t0, t0, 16);
9108 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9109 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9110 tcg_temp_free(t0);
9111 }
9112
9113 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
9114 {
9115 TCGv t0 = tcg_temp_new();
9116 gen_qemu_ld16u(ctx, t0, addr);
9117 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9118 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9119 tcg_temp_free(t0);
9120 }
9121
9122 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
9123 {
9124 TCGv t0 = tcg_temp_new();
9125 gen_qemu_ld16s(ctx, t0, addr);
9126 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9127 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9128 tcg_temp_free(t0);
9129 }
9130
9131 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
9132 {
9133 TCGv t0 = tcg_temp_new();
9134 gen_qemu_ld16u(ctx, t0, addr);
9135 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9136 gen_addr_add(ctx, addr, addr, 2);
9137 gen_qemu_ld16u(ctx, t0, addr);
9138 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9139 tcg_temp_free(t0);
9140 }
9141
9142 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
9143 {
9144 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9145 gen_addr_add(ctx, addr, addr, 2);
9146 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9147 }
9148
9149 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
9150 {
9151 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
9152 gen_addr_add(ctx, addr, addr, 2);
9153 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
9154 }
9155
9156 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
9157 {
9158 TCGv t0 = tcg_temp_new();
9159 gen_qemu_ld32u(ctx, t0, addr);
9160 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
9161 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
9162 tcg_temp_free(t0);
9163 }
9164
9165 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
9166 {
9167 TCGv t0 = tcg_temp_new();
9168 gen_qemu_ld16u(ctx, t0, addr);
9169 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
9170 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9171 gen_addr_add(ctx, addr, addr, 2);
9172 gen_qemu_ld16u(ctx, t0, addr);
9173 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
9174 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
9175 tcg_temp_free(t0);
9176 }
9177
9178 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
9179 {
9180 TCGv_i64 t0 = tcg_temp_new_i64();
9181 gen_load_gpr64(t0, rS(ctx->opcode));
9182 gen_qemu_st64(ctx, t0, addr);
9183 tcg_temp_free_i64(t0);
9184 }
9185
9186 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
9187 {
9188 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9189 gen_addr_add(ctx, addr, addr, 4);
9190 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9191 }
9192
9193 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
9194 {
9195 TCGv t0 = tcg_temp_new();
9196 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9197 gen_qemu_st16(ctx, t0, addr);
9198 gen_addr_add(ctx, addr, addr, 2);
9199 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9200 gen_addr_add(ctx, addr, addr, 2);
9201 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9202 gen_qemu_st16(ctx, t0, addr);
9203 tcg_temp_free(t0);
9204 gen_addr_add(ctx, addr, addr, 2);
9205 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9206 }
9207
9208 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
9209 {
9210 TCGv t0 = tcg_temp_new();
9211 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
9212 gen_qemu_st16(ctx, t0, addr);
9213 gen_addr_add(ctx, addr, addr, 2);
9214 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
9215 gen_qemu_st16(ctx, t0, addr);
9216 tcg_temp_free(t0);
9217 }
9218
9219 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
9220 {
9221 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9222 gen_addr_add(ctx, addr, addr, 2);
9223 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9224 }
9225
9226 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
9227 {
9228 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
9229 }
9230
9231 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
9232 {
9233 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
9234 }
9235
9236 #define GEN_SPEOP_LDST(name, opc2, sh) \
9237 static void glue(gen_, name)(DisasContext *ctx) \
9238 { \
9239 TCGv t0; \
9240 if (unlikely(!ctx->spe_enabled)) { \
9241 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9242 return; \
9243 } \
9244 gen_set_access_type(ctx, ACCESS_INT); \
9245 t0 = tcg_temp_new(); \
9246 if (Rc(ctx->opcode)) { \
9247 gen_addr_spe_imm_index(ctx, t0, sh); \
9248 } else { \
9249 gen_addr_reg_index(ctx, t0); \
9250 } \
9251 gen_op_##name(ctx, t0); \
9252 tcg_temp_free(t0); \
9253 }
9254
9255 GEN_SPEOP_LDST(evldd, 0x00, 3);
9256 GEN_SPEOP_LDST(evldw, 0x01, 3);
9257 GEN_SPEOP_LDST(evldh, 0x02, 3);
9258 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
9259 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
9260 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
9261 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
9262 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
9263 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
9264 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
9265 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
9266
9267 GEN_SPEOP_LDST(evstdd, 0x10, 3);
9268 GEN_SPEOP_LDST(evstdw, 0x11, 3);
9269 GEN_SPEOP_LDST(evstdh, 0x12, 3);
9270 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
9271 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
9272 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
9273 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
9274
9275 /* Multiply and add - TODO */
9276 #if 0
9277 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
9278 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9279 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9280 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9281 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9282 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9283 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9284 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9285 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9286 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9287 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9288 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9289
9290 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9291 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9292 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9293 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9294 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9295 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9296 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9297 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9298 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9299 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9300 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9301 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9302
9303 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9304 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9305 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9306 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9307 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9308
9309 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9310 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9311 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9312 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9313 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9314 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9315 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9316 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9317 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9318 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9319 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9320 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9321
9322 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9323 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9324 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9325 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9326
9327 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9328 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9329 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9330 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9331 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9332 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9333 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9334 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9335 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9336 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9337 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9338 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9339
9340 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9341 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9342 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9343 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9344 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9345 #endif
9346
9347 /*** SPE floating-point extension ***/
9348 #define GEN_SPEFPUOP_CONV_32_32(name) \
9349 static inline void gen_##name(DisasContext *ctx) \
9350 { \
9351 TCGv_i32 t0 = tcg_temp_new_i32(); \
9352 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9353 gen_helper_##name(t0, cpu_env, t0); \
9354 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9355 tcg_temp_free_i32(t0); \
9356 }
9357 #define GEN_SPEFPUOP_CONV_32_64(name) \
9358 static inline void gen_##name(DisasContext *ctx) \
9359 { \
9360 TCGv_i64 t0 = tcg_temp_new_i64(); \
9361 TCGv_i32 t1 = tcg_temp_new_i32(); \
9362 gen_load_gpr64(t0, rB(ctx->opcode)); \
9363 gen_helper_##name(t1, cpu_env, t0); \
9364 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); \
9365 tcg_temp_free_i64(t0); \
9366 tcg_temp_free_i32(t1); \
9367 }
9368 #define GEN_SPEFPUOP_CONV_64_32(name) \
9369 static inline void gen_##name(DisasContext *ctx) \
9370 { \
9371 TCGv_i64 t0 = tcg_temp_new_i64(); \
9372 TCGv_i32 t1 = tcg_temp_new_i32(); \
9373 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9374 gen_helper_##name(t0, cpu_env, t1); \
9375 gen_store_gpr64(rD(ctx->opcode), t0); \
9376 tcg_temp_free_i64(t0); \
9377 tcg_temp_free_i32(t1); \
9378 }
9379 #define GEN_SPEFPUOP_CONV_64_64(name) \
9380 static inline void gen_##name(DisasContext *ctx) \
9381 { \
9382 TCGv_i64 t0 = tcg_temp_new_i64(); \
9383 gen_load_gpr64(t0, rB(ctx->opcode)); \
9384 gen_helper_##name(t0, cpu_env, t0); \
9385 gen_store_gpr64(rD(ctx->opcode), t0); \
9386 tcg_temp_free_i64(t0); \
9387 }
9388 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9389 static inline void gen_##name(DisasContext *ctx) \
9390 { \
9391 TCGv_i32 t0, t1; \
9392 if (unlikely(!ctx->spe_enabled)) { \
9393 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9394 return; \
9395 } \
9396 t0 = tcg_temp_new_i32(); \
9397 t1 = tcg_temp_new_i32(); \
9398 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9399 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9400 gen_helper_##name(t0, cpu_env, t0, t1); \
9401 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
9402 \
9403 tcg_temp_free_i32(t0); \
9404 tcg_temp_free_i32(t1); \
9405 }
9406 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9407 static inline void gen_##name(DisasContext *ctx) \
9408 { \
9409 TCGv_i64 t0, t1; \
9410 if (unlikely(!ctx->spe_enabled)) { \
9411 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9412 return; \
9413 } \
9414 t0 = tcg_temp_new_i64(); \
9415 t1 = tcg_temp_new_i64(); \
9416 gen_load_gpr64(t0, rA(ctx->opcode)); \
9417 gen_load_gpr64(t1, rB(ctx->opcode)); \
9418 gen_helper_##name(t0, cpu_env, t0, t1); \
9419 gen_store_gpr64(rD(ctx->opcode), t0); \
9420 tcg_temp_free_i64(t0); \
9421 tcg_temp_free_i64(t1); \
9422 }
9423 #define GEN_SPEFPUOP_COMP_32(name) \
9424 static inline void gen_##name(DisasContext *ctx) \
9425 { \
9426 TCGv_i32 t0, t1; \
9427 if (unlikely(!ctx->spe_enabled)) { \
9428 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9429 return; \
9430 } \
9431 t0 = tcg_temp_new_i32(); \
9432 t1 = tcg_temp_new_i32(); \
9433 \
9434 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9435 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9436 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9437 \
9438 tcg_temp_free_i32(t0); \
9439 tcg_temp_free_i32(t1); \
9440 }
9441 #define GEN_SPEFPUOP_COMP_64(name) \
9442 static inline void gen_##name(DisasContext *ctx) \
9443 { \
9444 TCGv_i64 t0, t1; \
9445 if (unlikely(!ctx->spe_enabled)) { \
9446 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9447 return; \
9448 } \
9449 t0 = tcg_temp_new_i64(); \
9450 t1 = tcg_temp_new_i64(); \
9451 gen_load_gpr64(t0, rA(ctx->opcode)); \
9452 gen_load_gpr64(t1, rB(ctx->opcode)); \
9453 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9454 tcg_temp_free_i64(t0); \
9455 tcg_temp_free_i64(t1); \
9456 }
9457
9458 /* Single precision floating-point vectors operations */
9459 /* Arithmetic */
9460 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9461 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9462 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9463 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9464 static inline void gen_evfsabs(DisasContext *ctx)
9465 {
9466 if (unlikely(!ctx->spe_enabled)) {
9467 gen_exception(ctx, POWERPC_EXCP_SPEU);
9468 return;
9469 }
9470 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9471 ~0x80000000);
9472 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9473 ~0x80000000);
9474 }
9475 static inline void gen_evfsnabs(DisasContext *ctx)
9476 {
9477 if (unlikely(!ctx->spe_enabled)) {
9478 gen_exception(ctx, POWERPC_EXCP_SPEU);
9479 return;
9480 }
9481 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9482 0x80000000);
9483 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9484 0x80000000);
9485 }
9486 static inline void gen_evfsneg(DisasContext *ctx)
9487 {
9488 if (unlikely(!ctx->spe_enabled)) {
9489 gen_exception(ctx, POWERPC_EXCP_SPEU);
9490 return;
9491 }
9492 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
9493 0x80000000);
9494 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9495 0x80000000);
9496 }
9497
9498 /* Conversion */
9499 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9500 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9501 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9502 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9503 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9504 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9505 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9506 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9507 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9508 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9509
9510 /* Comparison */
9511 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9512 GEN_SPEFPUOP_COMP_64(evfscmplt);
9513 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9514 GEN_SPEFPUOP_COMP_64(evfststgt);
9515 GEN_SPEFPUOP_COMP_64(evfststlt);
9516 GEN_SPEFPUOP_COMP_64(evfststeq);
9517
9518 /* Opcodes definitions */
9519 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9520 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9521 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9522 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9523 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9524 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9525 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9526 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9527 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9528 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9529 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9530 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9531 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9532 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9533
9534 /* Single precision floating-point operations */
9535 /* Arithmetic */
9536 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9537 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9538 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9539 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9540 static inline void gen_efsabs(DisasContext *ctx)
9541 {
9542 if (unlikely(!ctx->spe_enabled)) {
9543 gen_exception(ctx, POWERPC_EXCP_SPEU);
9544 return;
9545 }
9546 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9547 }
9548 static inline void gen_efsnabs(DisasContext *ctx)
9549 {
9550 if (unlikely(!ctx->spe_enabled)) {
9551 gen_exception(ctx, POWERPC_EXCP_SPEU);
9552 return;
9553 }
9554 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9555 }
9556 static inline void gen_efsneg(DisasContext *ctx)
9557 {
9558 if (unlikely(!ctx->spe_enabled)) {
9559 gen_exception(ctx, POWERPC_EXCP_SPEU);
9560 return;
9561 }
9562 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9563 }
9564
9565 /* Conversion */
9566 GEN_SPEFPUOP_CONV_32_32(efscfui);
9567 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9568 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9569 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9570 GEN_SPEFPUOP_CONV_32_32(efsctui);
9571 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9572 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9573 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9574 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9575 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9576 GEN_SPEFPUOP_CONV_32_64(efscfd);
9577
9578 /* Comparison */
9579 GEN_SPEFPUOP_COMP_32(efscmpgt);
9580 GEN_SPEFPUOP_COMP_32(efscmplt);
9581 GEN_SPEFPUOP_COMP_32(efscmpeq);
9582 GEN_SPEFPUOP_COMP_32(efststgt);
9583 GEN_SPEFPUOP_COMP_32(efststlt);
9584 GEN_SPEFPUOP_COMP_32(efststeq);
9585
9586 /* Opcodes definitions */
9587 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9588 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9589 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9590 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9591 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9592 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9593 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9594 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9595 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9596 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9597 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9598 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9599 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9600 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9601
9602 /* Double precision floating-point operations */
9603 /* Arithmetic */
9604 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9605 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9606 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9607 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9608 static inline void gen_efdabs(DisasContext *ctx)
9609 {
9610 if (unlikely(!ctx->spe_enabled)) {
9611 gen_exception(ctx, POWERPC_EXCP_SPEU);
9612 return;
9613 }
9614 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9615 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9616 ~0x80000000);
9617 }
9618 static inline void gen_efdnabs(DisasContext *ctx)
9619 {
9620 if (unlikely(!ctx->spe_enabled)) {
9621 gen_exception(ctx, POWERPC_EXCP_SPEU);
9622 return;
9623 }
9624 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9625 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9626 0x80000000);
9627 }
9628 static inline void gen_efdneg(DisasContext *ctx)
9629 {
9630 if (unlikely(!ctx->spe_enabled)) {
9631 gen_exception(ctx, POWERPC_EXCP_SPEU);
9632 return;
9633 }
9634 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9635 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)],
9636 0x80000000);
9637 }
9638
9639 /* Conversion */
9640 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9641 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9642 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9643 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9644 GEN_SPEFPUOP_CONV_32_64(efdctui);
9645 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9646 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9647 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9648 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9649 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9650 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9651 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9652 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9653 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9654 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9655
9656 /* Comparison */
9657 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9658 GEN_SPEFPUOP_COMP_64(efdcmplt);
9659 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9660 GEN_SPEFPUOP_COMP_64(efdtstgt);
9661 GEN_SPEFPUOP_COMP_64(efdtstlt);
9662 GEN_SPEFPUOP_COMP_64(efdtsteq);
9663
9664 /* Opcodes definitions */
9665 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9666 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9667 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9668 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9669 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9670 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9671 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9672 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9673 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9674 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9675 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9676 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9677 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9678 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9679 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9680 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9681
9682 static void gen_tbegin(DisasContext *ctx)
9683 {
9684 if (unlikely(!ctx->tm_enabled)) {
9685 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9686 return;
9687 }
9688 gen_helper_tbegin(cpu_env);
9689 }
9690
9691 #define GEN_TM_NOOP(name) \
9692 static inline void gen_##name(DisasContext *ctx) \
9693 { \
9694 if (unlikely(!ctx->tm_enabled)) { \
9695 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9696 return; \
9697 } \
9698 /* Because tbegin always fails in QEMU, these user \
9699 * space instructions all have a simple implementation: \
9700 * \
9701 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9702 * = 0b0 || 0b00 || 0b0 \
9703 */ \
9704 tcg_gen_movi_i32(cpu_crf[0], 0); \
9705 }
9706
9707 GEN_TM_NOOP(tend);
9708 GEN_TM_NOOP(tabort);
9709 GEN_TM_NOOP(tabortwc);
9710 GEN_TM_NOOP(tabortwci);
9711 GEN_TM_NOOP(tabortdc);
9712 GEN_TM_NOOP(tabortdci);
9713 GEN_TM_NOOP(tsr);
9714
9715 static void gen_tcheck(DisasContext *ctx)
9716 {
9717 if (unlikely(!ctx->tm_enabled)) {
9718 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM);
9719 return;
9720 }
9721 /* Because tbegin always fails, the tcheck implementation
9722 * is simple:
9723 *
9724 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
9725 * = 0b1 || 0b00 || 0b0
9726 */
9727 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8);
9728 }
9729
9730 #if defined(CONFIG_USER_ONLY)
9731 #define GEN_TM_PRIV_NOOP(name) \
9732 static inline void gen_##name(DisasContext *ctx) \
9733 { \
9734 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9735 }
9736
9737 #else
9738
9739 #define GEN_TM_PRIV_NOOP(name) \
9740 static inline void gen_##name(DisasContext *ctx) \
9741 { \
9742 if (unlikely(ctx->pr)) { \
9743 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
9744 return; \
9745 } \
9746 if (unlikely(!ctx->tm_enabled)) { \
9747 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
9748 return; \
9749 } \
9750 /* Because tbegin always fails, the implementation is \
9751 * simple: \
9752 * \
9753 * CR[0] = 0b0 || MSR[TS] || 0b0 \
9754 * = 0b0 || 0b00 | 0b0 \
9755 */ \
9756 tcg_gen_movi_i32(cpu_crf[0], 0); \
9757 }
9758
9759 #endif
9760
9761 GEN_TM_PRIV_NOOP(treclaim);
9762 GEN_TM_PRIV_NOOP(trechkpt);
9763
9764 static opcode_t opcodes[] = {
9765 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9766 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9767 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9768 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9769 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9770 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9771 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9772 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9773 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9774 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9775 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9776 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9777 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9778 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9779 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9780 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9781 #if defined(TARGET_PPC64)
9782 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9783 #endif
9784 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9785 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9786 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9787 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9788 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9789 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9790 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9791 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9792 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9793 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9794 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9795 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9796 GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB),
9797 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9798 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9799 #if defined(TARGET_PPC64)
9800 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9801 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9802 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9803 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9804 #endif
9805 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9806 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9807 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9808 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9809 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9810 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9811 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9812 #if defined(TARGET_PPC64)
9813 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9814 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9815 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9816 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9817 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9818 #endif
9819 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9820 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9821 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9822 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9823 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9824 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9825 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9826 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9827 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9828 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9829 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9830 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9831 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9832 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9833 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9834 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9835 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9836 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9837 #if defined(TARGET_PPC64)
9838 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9839 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9840 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9841 #endif
9842 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9843 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9844 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9845 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9846 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9847 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9848 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9849 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9850 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9851 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9852 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9853 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9854 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9855 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9856 #if defined(TARGET_PPC64)
9857 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9858 GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
9859 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9860 GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
9861 #endif
9862 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9863 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9864 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9865 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9866 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9867 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9868 GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0, PPC_NONE, PPC2_BCTAR_ISA207),
9869 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9870 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9871 #if defined(TARGET_PPC64)
9872 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9873 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9874 #endif
9875 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9876 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9877 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9878 #if defined(TARGET_PPC64)
9879 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9880 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9881 #endif
9882 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9883 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9884 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9885 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9886 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9887 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9888 #if defined(TARGET_PPC64)
9889 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9890 #endif
9891 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9892 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9893 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9894 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9895 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9896 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9897 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9898 GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
9899 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9900 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9901 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9902 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9903 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9904 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9905 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9906 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9907 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9908 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9909 #if defined(TARGET_PPC64)
9910 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9911 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9912 PPC_SEGMENT_64B),
9913 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9914 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9915 PPC_SEGMENT_64B),
9916 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9917 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9918 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9919 #endif
9920 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9921 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9922 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9923 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9924 #if defined(TARGET_PPC64)
9925 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9926 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9927 #endif
9928 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9929 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9930 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9931 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9932 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9933 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9934 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9935 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9936 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9937 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9938 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9939 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9940 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9941 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9942 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9943 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9944 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9945 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9946 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9947 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9948 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9949 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9950 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9951 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9952 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9953 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9954 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9955 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9956 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9957 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9958 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9959 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9960 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9961 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9962 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9963 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9964 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9965 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9966 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9967 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9968 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9969 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9970 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9971 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9972 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9973 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9974 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9975 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9976 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9977 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9978 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9979 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9980 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9981 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9982 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9983 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9984 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9985 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9986 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9987 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9988 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9989 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9990 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9991 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9992 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9993 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9994 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9995 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9996 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9997 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9998 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9999 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
10000 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
10001 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
10002 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
10003 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
10004 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
10005 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
10006 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
10007 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
10008 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
10009 PPC_NONE, PPC2_BOOKE206),
10010 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
10011 PPC_NONE, PPC2_BOOKE206),
10012 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
10013 PPC_NONE, PPC2_BOOKE206),
10014 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
10015 PPC_NONE, PPC2_BOOKE206),
10016 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
10017 PPC_NONE, PPC2_BOOKE206),
10018 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
10019 PPC_NONE, PPC2_PRCNTL),
10020 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
10021 PPC_NONE, PPC2_PRCNTL),
10022 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
10023 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
10024 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
10025 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
10026 PPC_BOOKE, PPC2_BOOKE206),
10027 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
10028 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
10029 PPC_BOOKE, PPC2_BOOKE206),
10030 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
10031 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
10032 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
10033 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
10034 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
10035 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
10036 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
10037 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
10038 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
10039
10040 #undef GEN_INT_ARITH_ADD
10041 #undef GEN_INT_ARITH_ADD_CONST
10042 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
10043 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
10044 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
10045 add_ca, compute_ca, compute_ov) \
10046 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
10047 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
10048 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
10049 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
10050 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
10051 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
10052 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
10053 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
10054 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
10055 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
10056 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
10057
10058 #undef GEN_INT_ARITH_DIVW
10059 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
10060 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
10061 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
10062 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
10063 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
10064 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
10065 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10066 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10067 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10068 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10069
10070 #if defined(TARGET_PPC64)
10071 #undef GEN_INT_ARITH_DIVD
10072 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
10073 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10074 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
10075 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
10076 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
10077 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
10078
10079 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10080 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
10081 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10082 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
10083
10084 #undef GEN_INT_ARITH_MUL_HELPER
10085 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
10086 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
10087 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
10088 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
10089 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
10090 #endif
10091
10092 #undef GEN_INT_ARITH_SUBF
10093 #undef GEN_INT_ARITH_SUBF_CONST
10094 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
10095 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
10096 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
10097 add_ca, compute_ca, compute_ov) \
10098 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
10099 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
10100 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
10101 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
10102 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
10103 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
10104 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
10105 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
10106 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
10107 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
10108 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
10109
10110 #undef GEN_LOGICAL1
10111 #undef GEN_LOGICAL2
10112 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
10113 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
10114 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
10115 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
10116 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
10117 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
10118 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
10119 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
10120 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
10121 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
10122 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
10123 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
10124 #if defined(TARGET_PPC64)
10125 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
10126 #endif
10127
10128 #if defined(TARGET_PPC64)
10129 #undef GEN_PPC64_R2
10130 #undef GEN_PPC64_R4
10131 #define GEN_PPC64_R2(name, opc1, opc2) \
10132 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10133 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10134 PPC_64B)
10135 #define GEN_PPC64_R4(name, opc1, opc2) \
10136 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
10137 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
10138 PPC_64B), \
10139 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
10140 PPC_64B), \
10141 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
10142 PPC_64B)
10143 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
10144 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
10145 GEN_PPC64_R4(rldic, 0x1E, 0x04),
10146 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
10147 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
10148 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
10149 #endif
10150
10151 #undef _GEN_FLOAT_ACB
10152 #undef GEN_FLOAT_ACB
10153 #undef _GEN_FLOAT_AB
10154 #undef GEN_FLOAT_AB
10155 #undef _GEN_FLOAT_AC
10156 #undef GEN_FLOAT_AC
10157 #undef GEN_FLOAT_B
10158 #undef GEN_FLOAT_BS
10159 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
10160 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
10161 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
10162 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
10163 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
10164 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10165 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10166 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
10167 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10168 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10169 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
10170 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
10171 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
10172 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
10173 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
10174 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
10175 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
10176 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
10177 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
10178
10179 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
10180 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
10181 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
10182 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
10183 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
10184 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
10185 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
10186 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
10187 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
10188 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
10189 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
10190 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
10191 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10192 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
10193 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
10194 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10195 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
10196 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10197 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
10198 GEN_HANDLER_E(fcfid, 0x3F, 0x0E, 0x1A, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10199 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10200 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10201 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10202 GEN_HANDLER_E(fctid, 0x3F, 0x0E, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10203 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10204 GEN_HANDLER_E(fctidz, 0x3F, 0x0F, 0x19, 0x001F0000, PPC_NONE, PPC2_FP_CVT_S64),
10205 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
10206 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
10207 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
10208 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
10209 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
10210
10211 #undef GEN_LD
10212 #undef GEN_LDU
10213 #undef GEN_LDUX
10214 #undef GEN_LDX_E
10215 #undef GEN_LDS
10216 #define GEN_LD(name, ldop, opc, type) \
10217 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10218 #define GEN_LDU(name, ldop, opc, type) \
10219 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10220 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
10221 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10222 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
10223 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10224 #define GEN_LDS(name, ldop, op, type) \
10225 GEN_LD(name, ldop, op | 0x20, type) \
10226 GEN_LDU(name, ldop, op | 0x21, type) \
10227 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
10228 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
10229
10230 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
10231 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
10232 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
10233 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
10234 #if defined(TARGET_PPC64)
10235 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
10236 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
10237 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
10238 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
10239 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
10240 #endif
10241 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
10242 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
10243
10244 #undef GEN_ST
10245 #undef GEN_STU
10246 #undef GEN_STUX
10247 #undef GEN_STX_E
10248 #undef GEN_STS
10249 #define GEN_ST(name, stop, opc, type) \
10250 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10251 #define GEN_STU(name, stop, opc, type) \
10252 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
10253 #define GEN_STUX(name, stop, opc2, opc3, type) \
10254 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
10255 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
10256 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
10257 #define GEN_STS(name, stop, op, type) \
10258 GEN_ST(name, stop, op | 0x20, type) \
10259 GEN_STU(name, stop, op | 0x21, type) \
10260 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
10261 GEN_STX(name, stop, 0x17, op | 0x00, type)
10262
10263 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
10264 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
10265 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
10266 #if defined(TARGET_PPC64)
10267 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
10268 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
10269 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10270 #endif
10271 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10272 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10273
10274 #undef GEN_LDF
10275 #undef GEN_LDUF
10276 #undef GEN_LDUXF
10277 #undef GEN_LDXF
10278 #undef GEN_LDFS
10279 #define GEN_LDF(name, ldop, opc, type) \
10280 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10281 #define GEN_LDUF(name, ldop, opc, type) \
10282 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10283 #define GEN_LDUXF(name, ldop, opc, type) \
10284 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10285 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10286 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10287 #define GEN_LDFS(name, ldop, op, type) \
10288 GEN_LDF(name, ldop, op | 0x20, type) \
10289 GEN_LDUF(name, ldop, op | 0x21, type) \
10290 GEN_LDUXF(name, ldop, op | 0x01, type) \
10291 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10292
10293 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10294 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10295 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10296 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10297 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10298 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10299
10300 #undef GEN_STF
10301 #undef GEN_STUF
10302 #undef GEN_STUXF
10303 #undef GEN_STXF
10304 #undef GEN_STFS
10305 #define GEN_STF(name, stop, opc, type) \
10306 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10307 #define GEN_STUF(name, stop, opc, type) \
10308 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10309 #define GEN_STUXF(name, stop, opc, type) \
10310 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10311 #define GEN_STXF(name, stop, opc2, opc3, type) \
10312 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10313 #define GEN_STFS(name, stop, op, type) \
10314 GEN_STF(name, stop, op | 0x20, type) \
10315 GEN_STUF(name, stop, op | 0x21, type) \
10316 GEN_STUXF(name, stop, op | 0x01, type) \
10317 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10318
10319 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10320 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10321 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10322 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10323 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10324
10325 #undef GEN_CRLOGIC
10326 #define GEN_CRLOGIC(name, tcg_op, opc) \
10327 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10328 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10329 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10330 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10331 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10332 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10333 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10334 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10335 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10336
10337 #undef GEN_MAC_HANDLER
10338 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10339 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10340 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10341 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10342 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10343 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10344 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10345 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10346 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10347 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10348 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10349 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10350 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10351 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10352 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10353 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10354 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10355 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10356 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10357 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10358 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10359 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10360 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10361 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10362 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10363 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10364 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10365 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10366 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10367 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10368 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10369 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10370 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10371 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10372 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10373 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10374 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10375 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10376 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10377 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10378 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10379 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10380 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10381 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10382
10383 #undef GEN_VR_LDX
10384 #undef GEN_VR_STX
10385 #undef GEN_VR_LVE
10386 #undef GEN_VR_STVE
10387 #define GEN_VR_LDX(name, opc2, opc3) \
10388 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10389 #define GEN_VR_STX(name, opc2, opc3) \
10390 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10391 #define GEN_VR_LVE(name, opc2, opc3) \
10392 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10393 #define GEN_VR_STVE(name, opc2, opc3) \
10394 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10395 GEN_VR_LDX(lvx, 0x07, 0x03),
10396 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10397 GEN_VR_LVE(bx, 0x07, 0x00),
10398 GEN_VR_LVE(hx, 0x07, 0x01),
10399 GEN_VR_LVE(wx, 0x07, 0x02),
10400 GEN_VR_STX(svx, 0x07, 0x07),
10401 GEN_VR_STX(svxl, 0x07, 0x0F),
10402 GEN_VR_STVE(bx, 0x07, 0x04),
10403 GEN_VR_STVE(hx, 0x07, 0x05),
10404 GEN_VR_STVE(wx, 0x07, 0x06),
10405
10406 #undef GEN_VX_LOGICAL
10407 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10408 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10409
10410 #undef GEN_VX_LOGICAL_207
10411 #define GEN_VX_LOGICAL_207(name, tcg_op, opc2, opc3) \
10412 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10413
10414 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10415 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10416 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10417 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10418 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10419 GEN_VX_LOGICAL_207(veqv, tcg_gen_eqv_i64, 2, 26),
10420 GEN_VX_LOGICAL_207(vnand, tcg_gen_nand_i64, 2, 22),
10421 GEN_VX_LOGICAL_207(vorc, tcg_gen_orc_i64, 2, 21),
10422
10423 #undef GEN_VXFORM
10424 #define GEN_VXFORM(name, opc2, opc3) \
10425 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10426
10427 #undef GEN_VXFORM_207
10428 #define GEN_VXFORM_207(name, opc2, opc3) \
10429 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
10430
10431 #undef GEN_VXFORM_DUAL
10432 #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
10433 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
10434
10435 #undef GEN_VXRFORM_DUAL
10436 #define GEN_VXRFORM_DUAL(name0, name1, opc2, opc3, tp0, tp1) \
10437 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
10438 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
10439
10440 GEN_VXFORM(vaddubm, 0, 0),
10441 GEN_VXFORM(vadduhm, 0, 1),
10442 GEN_VXFORM(vadduwm, 0, 2),
10443 GEN_VXFORM_207(vaddudm, 0, 3),
10444 GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
10445 GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
10446 GEN_VXFORM(vsubuwm, 0, 18),
10447 GEN_VXFORM_207(vsubudm, 0, 19),
10448 GEN_VXFORM(vmaxub, 1, 0),
10449 GEN_VXFORM(vmaxuh, 1, 1),
10450 GEN_VXFORM(vmaxuw, 1, 2),
10451 GEN_VXFORM_207(vmaxud, 1, 3),
10452 GEN_VXFORM(vmaxsb, 1, 4),
10453 GEN_VXFORM(vmaxsh, 1, 5),
10454 GEN_VXFORM(vmaxsw, 1, 6),
10455 GEN_VXFORM_207(vmaxsd, 1, 7),
10456 GEN_VXFORM(vminub, 1, 8),
10457 GEN_VXFORM(vminuh, 1, 9),
10458 GEN_VXFORM(vminuw, 1, 10),
10459 GEN_VXFORM_207(vminud, 1, 11),
10460 GEN_VXFORM(vminsb, 1, 12),
10461 GEN_VXFORM(vminsh, 1, 13),
10462 GEN_VXFORM(vminsw, 1, 14),
10463 GEN_VXFORM_207(vminsd, 1, 15),
10464 GEN_VXFORM(vavgub, 1, 16),
10465 GEN_VXFORM(vavguh, 1, 17),
10466 GEN_VXFORM(vavguw, 1, 18),
10467 GEN_VXFORM(vavgsb, 1, 20),
10468 GEN_VXFORM(vavgsh, 1, 21),
10469 GEN_VXFORM(vavgsw, 1, 22),
10470 GEN_VXFORM(vmrghb, 6, 0),
10471 GEN_VXFORM(vmrghh, 6, 1),
10472 GEN_VXFORM(vmrghw, 6, 2),
10473 GEN_VXFORM(vmrglb, 6, 4),
10474 GEN_VXFORM(vmrglh, 6, 5),
10475 GEN_VXFORM(vmrglw, 6, 6),
10476 GEN_VXFORM_207(vmrgew, 6, 30),
10477 GEN_VXFORM_207(vmrgow, 6, 26),
10478 GEN_VXFORM(vmuloub, 4, 0),
10479 GEN_VXFORM(vmulouh, 4, 1),
10480 GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
10481 GEN_VXFORM(vmulosb, 4, 4),
10482 GEN_VXFORM(vmulosh, 4, 5),
10483 GEN_VXFORM_207(vmulosw, 4, 6),
10484 GEN_VXFORM(vmuleub, 4, 8),
10485 GEN_VXFORM(vmuleuh, 4, 9),
10486 GEN_VXFORM_207(vmuleuw, 4, 10),
10487 GEN_VXFORM(vmulesb, 4, 12),
10488 GEN_VXFORM(vmulesh, 4, 13),
10489 GEN_VXFORM_207(vmulesw, 4, 14),
10490 GEN_VXFORM(vslb, 2, 4),
10491 GEN_VXFORM(vslh, 2, 5),
10492 GEN_VXFORM(vslw, 2, 6),
10493 GEN_VXFORM_207(vsld, 2, 23),
10494 GEN_VXFORM(vsrb, 2, 8),
10495 GEN_VXFORM(vsrh, 2, 9),
10496 GEN_VXFORM(vsrw, 2, 10),
10497 GEN_VXFORM_207(vsrd, 2, 27),
10498 GEN_VXFORM(vsrab, 2, 12),
10499 GEN_VXFORM(vsrah, 2, 13),
10500 GEN_VXFORM(vsraw, 2, 14),
10501 GEN_VXFORM_207(vsrad, 2, 15),
10502 GEN_VXFORM(vslo, 6, 16),
10503 GEN_VXFORM(vsro, 6, 17),
10504 GEN_VXFORM(vaddcuw, 0, 6),
10505 GEN_VXFORM(vsubcuw, 0, 22),
10506 GEN_VXFORM(vaddubs, 0, 8),
10507 GEN_VXFORM(vadduhs, 0, 9),
10508 GEN_VXFORM(vadduws, 0, 10),
10509 GEN_VXFORM(vaddsbs, 0, 12),
10510 GEN_VXFORM(vaddshs, 0, 13),
10511 GEN_VXFORM(vaddsws, 0, 14),
10512 GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
10513 GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
10514 GEN_VXFORM(vsubuws, 0, 26),
10515 GEN_VXFORM(vsubsbs, 0, 28),
10516 GEN_VXFORM(vsubshs, 0, 29),
10517 GEN_VXFORM(vsubsws, 0, 30),
10518 GEN_VXFORM_207(vadduqm, 0, 4),
10519 GEN_VXFORM_207(vaddcuq, 0, 5),
10520 GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10521 GEN_VXFORM_207(vsubuqm, 0, 20),
10522 GEN_VXFORM_207(vsubcuq, 0, 21),
10523 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
10524 GEN_VXFORM(vrlb, 2, 0),
10525 GEN_VXFORM(vrlh, 2, 1),
10526 GEN_VXFORM(vrlw, 2, 2),
10527 GEN_VXFORM_207(vrld, 2, 3),
10528 GEN_VXFORM(vsl, 2, 7),
10529 GEN_VXFORM(vsr, 2, 11),
10530 GEN_VXFORM(vpkuhum, 7, 0),
10531 GEN_VXFORM(vpkuwum, 7, 1),
10532 GEN_VXFORM_207(vpkudum, 7, 17),
10533 GEN_VXFORM(vpkuhus, 7, 2),
10534 GEN_VXFORM(vpkuwus, 7, 3),
10535 GEN_VXFORM_207(vpkudus, 7, 19),
10536 GEN_VXFORM(vpkshus, 7, 4),
10537 GEN_VXFORM(vpkswus, 7, 5),
10538 GEN_VXFORM_207(vpksdus, 7, 21),
10539 GEN_VXFORM(vpkshss, 7, 6),
10540 GEN_VXFORM(vpkswss, 7, 7),
10541 GEN_VXFORM_207(vpksdss, 7, 23),
10542 GEN_VXFORM(vpkpx, 7, 12),
10543 GEN_VXFORM(vsum4ubs, 4, 24),
10544 GEN_VXFORM(vsum4sbs, 4, 28),
10545 GEN_VXFORM(vsum4shs, 4, 25),
10546 GEN_VXFORM(vsum2sws, 4, 26),
10547 GEN_VXFORM(vsumsws, 4, 30),
10548 GEN_VXFORM(vaddfp, 5, 0),
10549 GEN_VXFORM(vsubfp, 5, 1),
10550 GEN_VXFORM(vmaxfp, 5, 16),
10551 GEN_VXFORM(vminfp, 5, 17),
10552
10553 #undef GEN_VXRFORM1
10554 #undef GEN_VXRFORM
10555 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10556 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10557 #define GEN_VXRFORM(name, opc2, opc3) \
10558 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10559 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10560 GEN_VXRFORM(vcmpequb, 3, 0)
10561 GEN_VXRFORM(vcmpequh, 3, 1)
10562 GEN_VXRFORM(vcmpequw, 3, 2)
10563 GEN_VXRFORM(vcmpgtsb, 3, 12)
10564 GEN_VXRFORM(vcmpgtsh, 3, 13)
10565 GEN_VXRFORM(vcmpgtsw, 3, 14)
10566 GEN_VXRFORM(vcmpgtub, 3, 8)
10567 GEN_VXRFORM(vcmpgtuh, 3, 9)
10568 GEN_VXRFORM(vcmpgtuw, 3, 10)
10569 GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
10570 GEN_VXRFORM(vcmpgefp, 3, 7)
10571 GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
10572 GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
10573
10574 #undef GEN_VXFORM_SIMM
10575 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10576 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10577 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10578 GEN_VXFORM_SIMM(vspltish, 6, 13),
10579 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10580
10581 #undef GEN_VXFORM_NOA
10582 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10583 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10584 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10585 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10586 GEN_VXFORM_207(vupkhsw, 7, 25),
10587 GEN_VXFORM_NOA(vupklsb, 7, 10),
10588 GEN_VXFORM_NOA(vupklsh, 7, 11),
10589 GEN_VXFORM_207(vupklsw, 7, 27),
10590 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10591 GEN_VXFORM_NOA(vupklpx, 7, 15),
10592 GEN_VXFORM_NOA(vrefp, 5, 4),
10593 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10594 GEN_VXFORM_NOA(vexptefp, 5, 6),
10595 GEN_VXFORM_NOA(vlogefp, 5, 7),
10596 GEN_VXFORM_NOA(vrfim, 5, 11),
10597 GEN_VXFORM_NOA(vrfin, 5, 8),
10598 GEN_VXFORM_NOA(vrfip, 5, 10),
10599 GEN_VXFORM_NOA(vrfiz, 5, 9),
10600
10601 #undef GEN_VXFORM_UIMM
10602 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10603 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10604 GEN_VXFORM_UIMM(vspltb, 6, 8),
10605 GEN_VXFORM_UIMM(vsplth, 6, 9),
10606 GEN_VXFORM_UIMM(vspltw, 6, 10),
10607 GEN_VXFORM_UIMM(vcfux, 5, 12),
10608 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10609 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10610 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10611
10612 #undef GEN_VAFORM_PAIRED
10613 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10614 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10615 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10616 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10617 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10618 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10619 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10620 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10621
10622 GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
10623 GEN_VXFORM_DUAL(vclzh, vpopcnth, 1, 29, PPC_NONE, PPC2_ALTIVEC_207),
10624 GEN_VXFORM_DUAL(vclzw, vpopcntw, 1, 30, PPC_NONE, PPC2_ALTIVEC_207),
10625 GEN_VXFORM_DUAL(vclzd, vpopcntd, 1, 31, PPC_NONE, PPC2_ALTIVEC_207),
10626
10627 GEN_VXFORM_207(vbpermq, 6, 21),
10628 GEN_VXFORM_207(vgbbd, 6, 20),
10629 GEN_VXFORM_207(vpmsumb, 4, 16),
10630 GEN_VXFORM_207(vpmsumh, 4, 17),
10631 GEN_VXFORM_207(vpmsumw, 4, 18),
10632 GEN_VXFORM_207(vpmsumd, 4, 19),
10633
10634 GEN_VXFORM_207(vsbox, 4, 23),
10635
10636 GEN_VXFORM_DUAL(vcipher, vcipherlast, 4, 20, PPC_NONE, PPC2_ALTIVEC_207),
10637 GEN_VXFORM_DUAL(vncipher, vncipherlast, 4, 21, PPC_NONE, PPC2_ALTIVEC_207),
10638
10639 GEN_VXFORM_207(vshasigmaw, 1, 26),
10640 GEN_VXFORM_207(vshasigmad, 1, 27),
10641
10642 GEN_VXFORM_DUAL(vsldoi, vpermxor, 22, 0xFF, PPC_ALTIVEC, PPC_NONE),
10643
10644 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10645 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10646 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10647 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10648 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10649 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10650 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10651
10652 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10653 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10654 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10655 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10656 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10657
10658 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10659 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10660 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10661 #if defined(TARGET_PPC64)
10662 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10663 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10664 #endif
10665
10666 #undef GEN_XX2FORM
10667 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10668 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10669 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10670
10671 #undef GEN_XX3FORM
10672 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10673 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10674 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10675 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10676 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10677
10678 #undef GEN_XX3_RC_FORM
10679 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10680 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10681 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10682 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10683 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10684 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10685 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10686 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10687 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10688
10689 #undef GEN_XX3FORM_DM
10690 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10691 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10692 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10693 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10694 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10695 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10696 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10697 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10698 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10699 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10700 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10701 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10702 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10703 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10704 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10705 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10706 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10707
10708 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10709 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10710 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10711 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10712
10713 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10714 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10715 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10716 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10717 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10718 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10719 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10720 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10721
10722 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10723 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10724 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10725 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10726 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10727 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10728 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10729 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10730 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10731 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10732 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10733 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10734 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10735 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10736 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10737 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10738 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10739 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10740 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10741 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10742 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10743 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10744 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10745 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10746 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10747 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10748 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10749 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10750 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10751 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10752 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10753 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10754 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10755 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10756 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10757 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10758
10759 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10760 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10761 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10762 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10763 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10764 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10765 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10766 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10767 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10768 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10769 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10770 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10771 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10772 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10773 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10774 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10775 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10776 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10777
10778 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10779 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10780 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10781 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10782 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10783 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10784 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10785 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10786 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10787 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10788 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10789 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10790 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10791 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10792 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10793 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10794 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10795 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10796 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10797 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10798 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10799 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10800 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10801 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10802 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10803 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10804 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10805 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10806 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10807 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10808 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10809 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10810 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10811 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10812 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10813 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10814
10815 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10816 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10817 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10818 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10819 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10820 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10821 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10822 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10823 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10824 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10825 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10826 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10827 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10828 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10829 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10830 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10831 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10832 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10833 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10834 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10835 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10836 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10837 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10838 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10839 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10840 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10841 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10842 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10843 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10844 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10845 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10846 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10847 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10848 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10849 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10850 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10851
10852 #undef VSX_LOGICAL
10853 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10854 GEN_XX3FORM(name, opc2, opc3, fl2)
10855
10856 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10857 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10858 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10859 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10860 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10861 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10862 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10863 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10864 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10865 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10866 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10867 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10868
10869 #define GEN_XXSEL_ROW(opc3) \
10870 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10871 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10872 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10873 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10874 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10875 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10876 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10877 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10878
10879 GEN_XXSEL_ROW(0x00)
10880 GEN_XXSEL_ROW(0x01)
10881 GEN_XXSEL_ROW(0x02)
10882 GEN_XXSEL_ROW(0x03)
10883 GEN_XXSEL_ROW(0x04)
10884 GEN_XXSEL_ROW(0x05)
10885 GEN_XXSEL_ROW(0x06)
10886 GEN_XXSEL_ROW(0x07)
10887 GEN_XXSEL_ROW(0x08)
10888 GEN_XXSEL_ROW(0x09)
10889 GEN_XXSEL_ROW(0x0A)
10890 GEN_XXSEL_ROW(0x0B)
10891 GEN_XXSEL_ROW(0x0C)
10892 GEN_XXSEL_ROW(0x0D)
10893 GEN_XXSEL_ROW(0x0E)
10894 GEN_XXSEL_ROW(0x0F)
10895 GEN_XXSEL_ROW(0x10)
10896 GEN_XXSEL_ROW(0x11)
10897 GEN_XXSEL_ROW(0x12)
10898 GEN_XXSEL_ROW(0x13)
10899 GEN_XXSEL_ROW(0x14)
10900 GEN_XXSEL_ROW(0x15)
10901 GEN_XXSEL_ROW(0x16)
10902 GEN_XXSEL_ROW(0x17)
10903 GEN_XXSEL_ROW(0x18)
10904 GEN_XXSEL_ROW(0x19)
10905 GEN_XXSEL_ROW(0x1A)
10906 GEN_XXSEL_ROW(0x1B)
10907 GEN_XXSEL_ROW(0x1C)
10908 GEN_XXSEL_ROW(0x1D)
10909 GEN_XXSEL_ROW(0x1E)
10910 GEN_XXSEL_ROW(0x1F)
10911
10912 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10913
10914 #undef GEN_DFP_T_A_B_Rc
10915 #undef GEN_DFP_BF_A_B
10916 #undef GEN_DFP_BF_A_DCM
10917 #undef GEN_DFP_T_B_U32_U32_Rc
10918 #undef GEN_DFP_T_A_B_I32_Rc
10919 #undef GEN_DFP_T_B_Rc
10920 #undef GEN_DFP_T_FPR_I32_Rc
10921
10922 #define _GEN_DFP_LONG(name, op1, op2, mask) \
10923 GEN_HANDLER_E(name, 0x3B, op1, op2, mask, PPC_NONE, PPC2_DFP)
10924
10925 #define _GEN_DFP_LONGx2(name, op1, op2, mask) \
10926 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10927 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10928
10929 #define _GEN_DFP_LONGx4(name, op1, op2, mask) \
10930 GEN_HANDLER_E(name, 0x3B, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10931 GEN_HANDLER_E(name, 0x3B, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10932 GEN_HANDLER_E(name, 0x3B, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10933 GEN_HANDLER_E(name, 0x3B, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10934
10935 #define _GEN_DFP_QUAD(name, op1, op2, mask) \
10936 GEN_HANDLER_E(name, 0x3F, op1, op2, mask, PPC_NONE, PPC2_DFP)
10937
10938 #define _GEN_DFP_QUADx2(name, op1, op2, mask) \
10939 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10940 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP)
10941
10942 #define _GEN_DFP_QUADx4(name, op1, op2, mask) \
10943 GEN_HANDLER_E(name, 0x3F, op1, 0x00 | op2, mask, PPC_NONE, PPC2_DFP), \
10944 GEN_HANDLER_E(name, 0x3F, op1, 0x08 | op2, mask, PPC_NONE, PPC2_DFP), \
10945 GEN_HANDLER_E(name, 0x3F, op1, 0x10 | op2, mask, PPC_NONE, PPC2_DFP), \
10946 GEN_HANDLER_E(name, 0x3F, op1, 0x18 | op2, mask, PPC_NONE, PPC2_DFP)
10947
10948 #define GEN_DFP_T_A_B_Rc(name, op1, op2) \
10949 _GEN_DFP_LONG(name, op1, op2, 0x00000000)
10950
10951 #define GEN_DFP_Tp_Ap_Bp_Rc(name, op1, op2) \
10952 _GEN_DFP_QUAD(name, op1, op2, 0x00210800)
10953
10954 #define GEN_DFP_Tp_A_Bp_Rc(name, op1, op2) \
10955 _GEN_DFP_QUAD(name, op1, op2, 0x00200800)
10956
10957 #define GEN_DFP_T_B_Rc(name, op1, op2) \
10958 _GEN_DFP_LONG(name, op1, op2, 0x001F0000)
10959
10960 #define GEN_DFP_Tp_Bp_Rc(name, op1, op2) \
10961 _GEN_DFP_QUAD(name, op1, op2, 0x003F0800)
10962
10963 #define GEN_DFP_Tp_B_Rc(name, op1, op2) \
10964 _GEN_DFP_QUAD(name, op1, op2, 0x003F0000)
10965
10966 #define GEN_DFP_T_Bp_Rc(name, op1, op2) \
10967 _GEN_DFP_QUAD(name, op1, op2, 0x001F0800)
10968
10969 #define GEN_DFP_BF_A_B(name, op1, op2) \
10970 _GEN_DFP_LONG(name, op1, op2, 0x00000001)
10971
10972 #define GEN_DFP_BF_Ap_Bp(name, op1, op2) \
10973 _GEN_DFP_QUAD(name, op1, op2, 0x00610801)
10974
10975 #define GEN_DFP_BF_A_Bp(name, op1, op2) \
10976 _GEN_DFP_QUAD(name, op1, op2, 0x00600801)
10977
10978 #define GEN_DFP_BF_A_DCM(name, op1, op2) \
10979 _GEN_DFP_LONGx2(name, op1, op2, 0x00600001)
10980
10981 #define GEN_DFP_BF_Ap_DCM(name, op1, op2) \
10982 _GEN_DFP_QUADx2(name, op1, op2, 0x00610001)
10983
10984 #define GEN_DFP_T_A_B_RMC_Rc(name, op1, op2) \
10985 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10986
10987 #define GEN_DFP_Tp_Ap_Bp_RMC_Rc(name, op1, op2) \
10988 _GEN_DFP_QUADx4(name, op1, op2, 0x02010800)
10989
10990 #define GEN_DFP_Tp_A_Bp_RMC_Rc(name, op1, op2) \
10991 _GEN_DFP_QUADx4(name, op1, op2, 0x02000800)
10992
10993 #define GEN_DFP_TE_T_B_RMC_Rc(name, op1, op2) \
10994 _GEN_DFP_LONGx4(name, op1, op2, 0x00000000)
10995
10996 #define GEN_DFP_TE_Tp_Bp_RMC_Rc(name, op1, op2) \
10997 _GEN_DFP_QUADx4(name, op1, op2, 0x00200800)
10998
10999 #define GEN_DFP_R_T_B_RMC_Rc(name, op1, op2) \
11000 _GEN_DFP_LONGx4(name, op1, op2, 0x001E0000)
11001
11002 #define GEN_DFP_R_Tp_Bp_RMC_Rc(name, op1, op2) \
11003 _GEN_DFP_QUADx4(name, op1, op2, 0x003E0800)
11004
11005 #define GEN_DFP_SP_T_B_Rc(name, op1, op2) \
11006 _GEN_DFP_LONG(name, op1, op2, 0x00070000)
11007
11008 #define GEN_DFP_SP_Tp_Bp_Rc(name, op1, op2) \
11009 _GEN_DFP_QUAD(name, op1, op2, 0x00270800)
11010
11011 #define GEN_DFP_S_T_B_Rc(name, op1, op2) \
11012 _GEN_DFP_LONG(name, op1, op2, 0x000F0000)
11013
11014 #define GEN_DFP_S_Tp_Bp_Rc(name, op1, op2) \
11015 _GEN_DFP_QUAD(name, op1, op2, 0x002F0800)
11016
11017 #define GEN_DFP_T_A_SH_Rc(name, op1, op2) \
11018 _GEN_DFP_LONGx2(name, op1, op2, 0x00000000)
11019
11020 #define GEN_DFP_Tp_Ap_SH_Rc(name, op1, op2) \
11021 _GEN_DFP_QUADx2(name, op1, op2, 0x00210000)
11022
11023 GEN_DFP_T_A_B_Rc(dadd, 0x02, 0x00),
11024 GEN_DFP_Tp_Ap_Bp_Rc(daddq, 0x02, 0x00),
11025 GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
11026 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
11027 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
11028 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
11029 GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
11030 GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
11031 GEN_DFP_BF_A_B(dcmpu, 0x02, 0x14),
11032 GEN_DFP_BF_Ap_Bp(dcmpuq, 0x02, 0x14),
11033 GEN_DFP_BF_A_B(dcmpo, 0x02, 0x04),
11034 GEN_DFP_BF_Ap_Bp(dcmpoq, 0x02, 0x04),
11035 GEN_DFP_BF_A_DCM(dtstdc, 0x02, 0x06),
11036 GEN_DFP_BF_Ap_DCM(dtstdcq, 0x02, 0x06),
11037 GEN_DFP_BF_A_DCM(dtstdg, 0x02, 0x07),
11038 GEN_DFP_BF_Ap_DCM(dtstdgq, 0x02, 0x07),
11039 GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
11040 GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
11041 GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
11042 GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
11043 GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
11044 GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
11045 GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
11046 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
11047 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
11048 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
11049 GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
11050 GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
11051 GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
11052 GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
11053 GEN_DFP_T_B_Rc(dctdp, 0x02, 0x08),
11054 GEN_DFP_Tp_B_Rc(dctqpq, 0x02, 0x08),
11055 GEN_DFP_T_B_Rc(drsp, 0x02, 0x18),
11056 GEN_DFP_Tp_Bp_Rc(drdpq, 0x02, 0x18),
11057 GEN_DFP_T_B_Rc(dcffix, 0x02, 0x19),
11058 GEN_DFP_Tp_B_Rc(dcffixq, 0x02, 0x19),
11059 GEN_DFP_T_B_Rc(dctfix, 0x02, 0x09),
11060 GEN_DFP_T_Bp_Rc(dctfixq, 0x02, 0x09),
11061 GEN_DFP_SP_T_B_Rc(ddedpd, 0x02, 0x0a),
11062 GEN_DFP_SP_Tp_Bp_Rc(ddedpdq, 0x02, 0x0a),
11063 GEN_DFP_S_T_B_Rc(denbcd, 0x02, 0x1a),
11064 GEN_DFP_S_Tp_Bp_Rc(denbcdq, 0x02, 0x1a),
11065 GEN_DFP_T_B_Rc(dxex, 0x02, 0x0b),
11066 GEN_DFP_T_Bp_Rc(dxexq, 0x02, 0x0b),
11067 GEN_DFP_T_A_B_Rc(diex, 0x02, 0x1b),
11068 GEN_DFP_Tp_A_Bp_Rc(diexq, 0x02, 0x1b),
11069 GEN_DFP_T_A_SH_Rc(dscli, 0x02, 0x02),
11070 GEN_DFP_Tp_Ap_SH_Rc(dscliq, 0x02, 0x02),
11071 GEN_DFP_T_A_SH_Rc(dscri, 0x02, 0x03),
11072 GEN_DFP_Tp_Ap_SH_Rc(dscriq, 0x02, 0x03),
11073
11074 #undef GEN_SPE
11075 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
11076 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
11077 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11078 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11079 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11080 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11081 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11082 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11083 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
11084 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
11085 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
11086 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11087 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11088 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11089 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11090 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11091 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
11092 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
11093 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
11094 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11095 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11096 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11097 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11098 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
11099 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11100 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
11101 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11102 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
11103 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11104 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
11105 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
11106
11107 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11108 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11109 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11110 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11111 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11112 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11113 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11114 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11115 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11116 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11117 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11118 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11119 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11120 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11121
11122 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11123 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
11124 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
11125 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
11126 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11127 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
11128 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11129 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11130 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11131 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
11132 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11133 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11134 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
11135 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
11136
11137 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11138 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11139 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
11140 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11141 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
11142 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11143 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11144 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
11145 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11146 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11147 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11148 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
11149 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11150 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11151 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
11152 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
11153
11154 #undef GEN_SPEOP_LDST
11155 #define GEN_SPEOP_LDST(name, opc2, sh) \
11156 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
11157 GEN_SPEOP_LDST(evldd, 0x00, 3),
11158 GEN_SPEOP_LDST(evldw, 0x01, 3),
11159 GEN_SPEOP_LDST(evldh, 0x02, 3),
11160 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
11161 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
11162 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
11163 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
11164 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
11165 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
11166 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
11167 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
11168
11169 GEN_SPEOP_LDST(evstdd, 0x10, 3),
11170 GEN_SPEOP_LDST(evstdw, 0x11, 3),
11171 GEN_SPEOP_LDST(evstdh, 0x12, 3),
11172 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
11173 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
11174 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
11175 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
11176
11177 GEN_HANDLER2_E(tbegin, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
11178 PPC_NONE, PPC2_TM),
11179 GEN_HANDLER2_E(tend, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
11180 PPC_NONE, PPC2_TM),
11181 GEN_HANDLER2_E(tabort, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
11182 PPC_NONE, PPC2_TM),
11183 GEN_HANDLER2_E(tabortwc, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
11184 PPC_NONE, PPC2_TM),
11185 GEN_HANDLER2_E(tabortwci, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
11186 PPC_NONE, PPC2_TM),
11187 GEN_HANDLER2_E(tabortdc, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
11188 PPC_NONE, PPC2_TM),
11189 GEN_HANDLER2_E(tabortdci, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
11190 PPC_NONE, PPC2_TM),
11191 GEN_HANDLER2_E(tsr, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
11192 PPC_NONE, PPC2_TM),
11193 GEN_HANDLER2_E(tcheck, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
11194 PPC_NONE, PPC2_TM),
11195 GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
11196 PPC_NONE, PPC2_TM),
11197 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
11198 PPC_NONE, PPC2_TM),
11199 };
11200
11201 #include "helper_regs.h"
11202 #include "translate_init.c"
11203
11204 /*****************************************************************************/
11205 /* Misc PowerPC helpers */
11206 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
11207 int flags)
11208 {
11209 #define RGPL 4
11210 #define RFPL 4
11211
11212 PowerPCCPU *cpu = POWERPC_CPU(cs);
11213 CPUPPCState *env = &cpu->env;
11214 int i;
11215
11216 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
11217 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
11218 env->nip, env->lr, env->ctr, cpu_read_xer(env));
11219 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
11220 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
11221 env->hflags, env->mmu_idx);
11222 #if !defined(NO_TIMER_DUMP)
11223 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
11224 #if !defined(CONFIG_USER_ONLY)
11225 " DECR %08" PRIu32
11226 #endif
11227 "\n",
11228 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
11229 #if !defined(CONFIG_USER_ONLY)
11230 , cpu_ppc_load_decr(env)
11231 #endif
11232 );
11233 #endif
11234 for (i = 0; i < 32; i++) {
11235 if ((i & (RGPL - 1)) == 0)
11236 cpu_fprintf(f, "GPR%02d", i);
11237 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
11238 if ((i & (RGPL - 1)) == (RGPL - 1))
11239 cpu_fprintf(f, "\n");
11240 }
11241 cpu_fprintf(f, "CR ");
11242 for (i = 0; i < 8; i++)
11243 cpu_fprintf(f, "%01x", env->crf[i]);
11244 cpu_fprintf(f, " [");
11245 for (i = 0; i < 8; i++) {
11246 char a = '-';
11247 if (env->crf[i] & 0x08)
11248 a = 'L';
11249 else if (env->crf[i] & 0x04)
11250 a = 'G';
11251 else if (env->crf[i] & 0x02)
11252 a = 'E';
11253 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
11254 }
11255 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
11256 env->reserve_addr);
11257 for (i = 0; i < 32; i++) {
11258 if ((i & (RFPL - 1)) == 0)
11259 cpu_fprintf(f, "FPR%02d", i);
11260 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
11261 if ((i & (RFPL - 1)) == (RFPL - 1))
11262 cpu_fprintf(f, "\n");
11263 }
11264 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
11265 #if !defined(CONFIG_USER_ONLY)
11266 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
11267 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
11268 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
11269 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
11270
11271 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
11272 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
11273 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
11274 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
11275
11276 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
11277 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
11278 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
11279 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
11280
11281 if (env->excp_model == POWERPC_EXCP_BOOKE) {
11282 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
11283 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
11284 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
11285 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
11286
11287 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
11288 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
11289 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
11290 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
11291
11292 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
11293 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
11294 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
11295 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
11296
11297 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
11298 " EPR " TARGET_FMT_lx "\n",
11299 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
11300 env->spr[SPR_BOOKE_EPR]);
11301
11302 /* FSL-specific */
11303 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
11304 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
11305 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
11306 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
11307
11308 /*
11309 * IVORs are left out as they are large and do not change often --
11310 * they can be read with "p $ivor0", "p $ivor1", etc.
11311 */
11312 }
11313
11314 #if defined(TARGET_PPC64)
11315 if (env->flags & POWERPC_FLAG_CFAR) {
11316 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
11317 }
11318 #endif
11319
11320 switch (env->mmu_model) {
11321 case POWERPC_MMU_32B:
11322 case POWERPC_MMU_601:
11323 case POWERPC_MMU_SOFT_6xx:
11324 case POWERPC_MMU_SOFT_74xx:
11325 #if defined(TARGET_PPC64)
11326 case POWERPC_MMU_64B:
11327 case POWERPC_MMU_2_06:
11328 case POWERPC_MMU_2_06a:
11329 case POWERPC_MMU_2_06d:
11330 #endif
11331 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
11332 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
11333 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
11334 break;
11335 case POWERPC_MMU_BOOKE206:
11336 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
11337 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
11338 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
11339 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
11340
11341 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
11342 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
11343 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
11344 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
11345
11346 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
11347 " TLB1CFG " TARGET_FMT_lx "\n",
11348 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
11349 env->spr[SPR_BOOKE_TLB1CFG]);
11350 break;
11351 default:
11352 break;
11353 }
11354 #endif
11355
11356 #undef RGPL
11357 #undef RFPL
11358 }
11359
11360 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
11361 fprintf_function cpu_fprintf, int flags)
11362 {
11363 #if defined(DO_PPC_STATISTICS)
11364 PowerPCCPU *cpu = POWERPC_CPU(cs);
11365 opc_handler_t **t1, **t2, **t3, *handler;
11366 int op1, op2, op3;
11367
11368 t1 = cpu->env.opcodes;
11369 for (op1 = 0; op1 < 64; op1++) {
11370 handler = t1[op1];
11371 if (is_indirect_opcode(handler)) {
11372 t2 = ind_table(handler);
11373 for (op2 = 0; op2 < 32; op2++) {
11374 handler = t2[op2];
11375 if (is_indirect_opcode(handler)) {
11376 t3 = ind_table(handler);
11377 for (op3 = 0; op3 < 32; op3++) {
11378 handler = t3[op3];
11379 if (handler->count == 0)
11380 continue;
11381 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
11382 "%016" PRIx64 " %" PRId64 "\n",
11383 op1, op2, op3, op1, (op3 << 5) | op2,
11384 handler->oname,
11385 handler->count, handler->count);
11386 }
11387 } else {
11388 if (handler->count == 0)
11389 continue;
11390 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
11391 "%016" PRIx64 " %" PRId64 "\n",
11392 op1, op2, op1, op2, handler->oname,
11393 handler->count, handler->count);
11394 }
11395 }
11396 } else {
11397 if (handler->count == 0)
11398 continue;
11399 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
11400 " %" PRId64 "\n",
11401 op1, op1, handler->oname,
11402 handler->count, handler->count);
11403 }
11404 }
11405 #endif
11406 }
11407
11408 /*****************************************************************************/
11409 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
11410 TranslationBlock *tb,
11411 bool search_pc)
11412 {
11413 CPUState *cs = CPU(cpu);
11414 CPUPPCState *env = &cpu->env;
11415 DisasContext ctx, *ctxp = &ctx;
11416 opc_handler_t **table, *handler;
11417 target_ulong pc_start;
11418 CPUBreakpoint *bp;
11419 int j, lj = -1;
11420 int num_insns;
11421 int max_insns;
11422
11423 pc_start = tb->pc;
11424 ctx.nip = pc_start;
11425 ctx.tb = tb;
11426 ctx.exception = POWERPC_EXCP_NONE;
11427 ctx.spr_cb = env->spr_cb;
11428 ctx.pr = msr_pr;
11429 ctx.hv = !msr_pr && msr_hv;
11430 ctx.mem_idx = env->mmu_idx;
11431 ctx.insns_flags = env->insns_flags;
11432 ctx.insns_flags2 = env->insns_flags2;
11433 ctx.access_type = -1;
11434 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
11435 ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
11436 #if defined(TARGET_PPC64)
11437 ctx.sf_mode = msr_is_64bit(env, env->msr);
11438 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
11439 #endif
11440 ctx.fpu_enabled = msr_fp;
11441 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
11442 ctx.spe_enabled = msr_spe;
11443 else
11444 ctx.spe_enabled = 0;
11445 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
11446 ctx.altivec_enabled = msr_vr;
11447 else
11448 ctx.altivec_enabled = 0;
11449 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
11450 ctx.vsx_enabled = msr_vsx;
11451 } else {
11452 ctx.vsx_enabled = 0;
11453 }
11454 #if defined(TARGET_PPC64)
11455 if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
11456 ctx.tm_enabled = msr_tm;
11457 } else {
11458 ctx.tm_enabled = 0;
11459 }
11460 #endif
11461 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
11462 ctx.singlestep_enabled = CPU_SINGLE_STEP;
11463 else
11464 ctx.singlestep_enabled = 0;
11465 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
11466 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
11467 if (unlikely(cs->singlestep_enabled)) {
11468 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
11469 }
11470 #if defined (DO_SINGLE_STEP) && 0
11471 /* Single step trace mode */
11472 msr_se = 1;
11473 #endif
11474 num_insns = 0;
11475 max_insns = tb->cflags & CF_COUNT_MASK;
11476 if (max_insns == 0)
11477 max_insns = CF_COUNT_MASK;
11478
11479 gen_tb_start(tb);
11480 tcg_clear_temp_count();
11481 /* Set env in case of segfault during code fetch */
11482 while (ctx.exception == POWERPC_EXCP_NONE && !tcg_op_buf_full()) {
11483 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
11484 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
11485 if (bp->pc == ctx.nip) {
11486 gen_debug_exception(ctxp);
11487 break;
11488 }
11489 }
11490 }
11491 if (unlikely(search_pc)) {
11492 j = tcg_op_buf_count();
11493 if (lj < j) {
11494 lj++;
11495 while (lj < j)
11496 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11497 }
11498 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
11499 tcg_ctx.gen_opc_instr_start[lj] = 1;
11500 tcg_ctx.gen_opc_icount[lj] = num_insns;
11501 }
11502 LOG_DISAS("----------------\n");
11503 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
11504 ctx.nip, ctx.mem_idx, (int)msr_ir);
11505 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
11506 gen_io_start();
11507 if (unlikely(need_byteswap(&ctx))) {
11508 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
11509 } else {
11510 ctx.opcode = cpu_ldl_code(env, ctx.nip);
11511 }
11512 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
11513 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
11514 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
11515 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
11516 tcg_gen_debug_insn_start(ctx.nip);
11517 }
11518 ctx.nip += 4;
11519 table = env->opcodes;
11520 num_insns++;
11521 handler = table[opc1(ctx.opcode)];
11522 if (is_indirect_opcode(handler)) {
11523 table = ind_table(handler);
11524 handler = table[opc2(ctx.opcode)];
11525 if (is_indirect_opcode(handler)) {
11526 table = ind_table(handler);
11527 handler = table[opc3(ctx.opcode)];
11528 }
11529 }
11530 /* Is opcode *REALLY* valid ? */
11531 if (unlikely(handler->handler == &gen_invalid)) {
11532 if (qemu_log_enabled()) {
11533 qemu_log("invalid/unsupported opcode: "
11534 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11535 opc1(ctx.opcode), opc2(ctx.opcode),
11536 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11537 }
11538 } else {
11539 uint32_t inval;
11540
11541 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11542 inval = handler->inval2;
11543 } else {
11544 inval = handler->inval1;
11545 }
11546
11547 if (unlikely((ctx.opcode & inval) != 0)) {
11548 if (qemu_log_enabled()) {
11549 qemu_log("invalid bits: %08x for opcode: "
11550 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11551 ctx.opcode & inval, opc1(ctx.opcode),
11552 opc2(ctx.opcode), opc3(ctx.opcode),
11553 ctx.opcode, ctx.nip - 4);
11554 }
11555 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11556 break;
11557 }
11558 }
11559 (*(handler->handler))(&ctx);
11560 #if defined(DO_PPC_STATISTICS)
11561 handler->count++;
11562 #endif
11563 /* Check trace mode exceptions */
11564 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11565 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11566 ctx.exception != POWERPC_SYSCALL &&
11567 ctx.exception != POWERPC_EXCP_TRAP &&
11568 ctx.exception != POWERPC_EXCP_BRANCH)) {
11569 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11570 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11571 (cs->singlestep_enabled) ||
11572 singlestep ||
11573 num_insns >= max_insns)) {
11574 /* if we reach a page boundary or are single stepping, stop
11575 * generation
11576 */
11577 break;
11578 }
11579 if (tcg_check_temp_count()) {
11580 fprintf(stderr, "Opcode %02x %02x %02x (%08x) leaked temporaries\n",
11581 opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode),
11582 ctx.opcode);
11583 exit(1);
11584 }
11585 }
11586 if (tb->cflags & CF_LAST_IO)
11587 gen_io_end();
11588 if (ctx.exception == POWERPC_EXCP_NONE) {
11589 gen_goto_tb(&ctx, 0, ctx.nip);
11590 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11591 if (unlikely(cs->singlestep_enabled)) {
11592 gen_debug_exception(ctxp);
11593 }
11594 /* Generate the return instruction */
11595 tcg_gen_exit_tb(0);
11596 }
11597 gen_tb_end(tb, num_insns);
11598
11599 if (unlikely(search_pc)) {
11600 j = tcg_op_buf_count();
11601 lj++;
11602 while (lj <= j)
11603 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11604 } else {
11605 tb->size = ctx.nip - pc_start;
11606 tb->icount = num_insns;
11607 }
11608 #if defined(DEBUG_DISAS)
11609 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11610 int flags;
11611 flags = env->bfd_mach;
11612 flags |= ctx.le_mode << 16;
11613 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11614 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11615 qemu_log("\n");
11616 }
11617 #endif
11618 }
11619
11620 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11621 {
11622 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11623 }
11624
11625 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11626 {
11627 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11628 }
11629
11630 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11631 {
11632 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11633 }
QEmu