target-ppc/mmu-hash32.c

   1 /*
   2  *  PowerPC MMU, TLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23 #include "sysemu/kvm.h"
  24 #include "kvm_ppc.h"
  25 #include "mmu-hash32.h"
  26
  27 //#define DEBUG_MMU
  28 //#define DEBUG_BAT
  29
  30 #ifdef DEBUG_MMU
  31 #  define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
  32 #else
  33 #  define LOG_MMU_STATE(cpu) do { } while (0)
  34 #endif
  35
  36 #ifdef DEBUG_BATS
  37 #  define LOG_BATS(...) qemu_log(__VA_ARGS__)
  38 #else
  39 #  define LOG_BATS(...) do { } while (0)
  40 #endif
  41
  42 struct mmu_ctx_hash32 {
  43     hwaddr raddr;      /* Real address              */
  44     int prot;                      /* Protection bits           */
  45     int key;                       /* Access key                */
  46 };
  47
  48 static int ppc_hash32_pp_prot(int key, int pp, int nx)
  49 {
  50     int prot;
  51
  52     if (key == 0) {
  53         switch (pp) {
  54         case 0x0:
  55         case 0x1:
  56         case 0x2:
  57             prot = PAGE_READ | PAGE_WRITE;
  58             break;
  59
  60         case 0x3:
  61             prot = PAGE_READ;
  62             break;
  63
  64         default:
  65             abort();
  66         }
  67     } else {
  68         switch (pp) {
  69         case 0x0:
  70             prot = 0;
  71             break;
  72
  73         case 0x1:
  74         case 0x3:
  75             prot = PAGE_READ;
  76             break;
  77
  78         case 0x2:
  79             prot = PAGE_READ | PAGE_WRITE;
  80             break;
  81
  82         default:
  83             abort();
  84         }
  85     }
  86     if (nx == 0) {
  87         prot |= PAGE_EXEC;
  88     }
  89
  90     return prot;
  91 }
  92
  93 static int ppc_hash32_pte_prot(CPUPPCState *env,
  94                                target_ulong sr, ppc_hash_pte32_t pte)
  95 {
  96     unsigned pp, key;
  97
  98     key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
  99     pp = pte.pte1 & HPTE32_R_PP;
 100
 101     return ppc_hash32_pp_prot(key, pp, !!(sr & SR32_NX));
 102 }
 103
 104 static target_ulong hash32_bat_size(CPUPPCState *env,
 105                                     target_ulong batu, target_ulong batl)
 106 {
 107     if ((msr_pr && !(batu & BATU32_VP))
 108         || (!msr_pr && !(batu & BATU32_VS))) {
 109         return 0;
 110     }
 111
 112     return BATU32_BEPI & ~((batu & BATU32_BL) << 15);
 113 }
 114
 115 static int hash32_bat_prot(CPUPPCState *env,
 116                            target_ulong batu, target_ulong batl)
 117 {
 118     int pp, prot;
 119
 120     prot = 0;
 121     pp = batl & BATL32_PP;
 122     if (pp != 0) {
 123         prot = PAGE_READ | PAGE_EXEC;
 124         if (pp == 0x2) {
 125             prot |= PAGE_WRITE;
 126         }
 127     }
 128     return prot;
 129 }
 130
 131 static target_ulong hash32_bat_601_size(CPUPPCState *env,
 132                                 target_ulong batu, target_ulong batl)
 133 {
 134     if (!(batl & BATL32_601_V)) {
 135         return 0;
 136     }
 137
 138     return BATU32_BEPI & ~((batl & BATL32_601_BL) << 17);
 139 }
 140
 141 static int hash32_bat_601_prot(CPUPPCState *env,
 142                                target_ulong batu, target_ulong batl)
 143 {
 144     int key, pp;
 145
 146     pp = batu & BATU32_601_PP;
 147     if (msr_pr == 0) {
 148         key = !!(batu & BATU32_601_KS);
 149     } else {
 150         key = !!(batu & BATU32_601_KP);
 151     }
 152     return ppc_hash32_pp_prot(key, pp, 0);
 153 }
 154
 155 static hwaddr ppc_hash32_bat_lookup(CPUPPCState *env, target_ulong ea, int rwx,
 156                                     int *prot)
 157 {
 158     target_ulong *BATlt, *BATut;
 159     int i;
 160
 161     LOG_BATS("%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
 162              rwx == 2 ? 'I' : 'D', ea);
 163     if (rwx == 2) {
 164         BATlt = env->IBAT[1];
 165         BATut = env->IBAT[0];
 166     } else {
 167         BATlt = env->DBAT[1];
 168         BATut = env->DBAT[0];
 169     }
 170     for (i = 0; i < env->nb_BATs; i++) {
 171         target_ulong batu = BATut[i];
 172         target_ulong batl = BATlt[i];
 173         target_ulong mask;
 174
 175         if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
 176             mask = hash32_bat_601_size(env, batu, batl);
 177         } else {
 178             mask = hash32_bat_size(env, batu, batl);
 179         }
 180         LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
 181                  " BATl " TARGET_FMT_lx "\n", __func__,
 182                  type == ACCESS_CODE ? 'I' : 'D', i, ea, batu, batl);
 183
 184         if (mask && ((ea & mask) == (batu & BATU32_BEPI))) {
 185             hwaddr raddr = (batl & mask) | (ea & ~mask);
 186
 187             if (unlikely(env->mmu_model == POWERPC_MMU_601)) {
 188                 *prot = hash32_bat_601_prot(env, batu, batl);
 189             } else {
 190                 *prot = hash32_bat_prot(env, batu, batl);
 191             }
 192
 193             return raddr & TARGET_PAGE_MASK;
 194         }
 195     }
 196
 197     /* No hit */
 198 #if defined(DEBUG_BATS)
 199     if (qemu_log_enabled()) {
 200         LOG_BATS("no BAT match for " TARGET_FMT_lx ":\n", ea);
 201         for (i = 0; i < 4; i++) {
 202             BATu = &BATut[i];
 203             BATl = &BATlt[i];
 204             BEPIu = *BATu & BATU32_BEPIU;
 205             BEPIl = *BATu & BATU32_BEPIL;
 206             bl = (*BATu & 0x00001FFC) << 15;
 207             LOG_BATS("%s: %cBAT%d v " TARGET_FMT_lx " BATu " TARGET_FMT_lx
 208                      " BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " "
 209                      TARGET_FMT_lx " " TARGET_FMT_lx "\n",
 210                      __func__, type == ACCESS_CODE ? 'I' : 'D', i, ea,
 211                      *BATu, *BATl, BEPIu, BEPIl, bl);
 212         }
 213     }
 214 #endif
 215
 216     return -1;
 217 }
 218
 219 static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
 220                                    target_ulong eaddr, int rwx,
 221                                    hwaddr *raddr, int *prot)
 222 {
 223     CPUState *cs = CPU(ppc_env_get_cpu(env));
 224     int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
 225
 226     qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
 227
 228     if ((sr & 0x1FF00000) >> 20 == 0x07f) {
 229         /* Memory-forced I/O controller interface access */
 230         /* If T=1 and BUID=x'07F', the 601 performs a memory access
 231          * to SR[28-31] LA[4-31], bypassing all protection mechanisms.
 232          */
 233         *raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
 234         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 235         return 0;
 236     }
 237
 238     if (rwx == 2) {
 239         /* No code fetch is allowed in direct-store areas */
 240         cs->exception_index = POWERPC_EXCP_ISI;
 241         env->error_code = 0x10000000;
 242         return 1;
 243     }
 244
 245     switch (env->access_type) {
 246     case ACCESS_INT:
 247         /* Integer load/store : only access allowed */
 248         break;
 249     case ACCESS_FLOAT:
 250         /* Floating point load/store */
 251         cs->exception_index = POWERPC_EXCP_ALIGN;
 252         env->error_code = POWERPC_EXCP_ALIGN_FP;
 253         env->spr[SPR_DAR] = eaddr;
 254         return 1;
 255     case ACCESS_RES:
 256         /* lwarx, ldarx or srwcx. */
 257         env->error_code = 0;
 258         env->spr[SPR_DAR] = eaddr;
 259         if (rwx == 1) {
 260             env->spr[SPR_DSISR] = 0x06000000;
 261         } else {
 262             env->spr[SPR_DSISR] = 0x04000000;
 263         }
 264         return 1;
 265     case ACCESS_CACHE:
 266         /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */
 267         /* Should make the instruction do no-op.
 268          * As it already do no-op, it's quite easy :-)
 269          */
 270         *raddr = eaddr;
 271         return 0;
 272     case ACCESS_EXT:
 273         /* eciwx or ecowx */
 274         cs->exception_index = POWERPC_EXCP_DSI;
 275         env->error_code = 0;
 276         env->spr[SPR_DAR] = eaddr;
 277         if (rwx == 1) {
 278             env->spr[SPR_DSISR] = 0x06100000;
 279         } else {
 280             env->spr[SPR_DSISR] = 0x04100000;
 281         }
 282         return 1;
 283     default:
 284         qemu_log("ERROR: instruction should not need "
 285                  "address translation\n");
 286         abort();
 287     }
 288     if ((rwx == 1 || key != 1) && (rwx == 0 || key != 0)) {
 289         *raddr = eaddr;
 290         return 0;
 291     } else {
 292         cs->exception_index = POWERPC_EXCP_DSI;
 293         env->error_code = 0;
 294         env->spr[SPR_DAR] = eaddr;
 295         if (rwx == 1) {
 296             env->spr[SPR_DSISR] = 0x0a000000;
 297         } else {
 298             env->spr[SPR_DSISR] = 0x08000000;
 299         }
 300         return 1;
 301     }
 302 }
 303
 304 hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash)
 305 {
 306     return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
 307 }
 308
 309 static hwaddr ppc_hash32_pteg_search(CPUPPCState *env, hwaddr pteg_off,
 310                                      bool secondary, target_ulong ptem,
 311                                      ppc_hash_pte32_t *pte)
 312 {
 313     hwaddr pte_offset = pteg_off;
 314     target_ulong pte0, pte1;
 315     int i;
 316
 317     for (i = 0; i < HPTES_PER_GROUP; i++) {
 318         pte0 = ppc_hash32_load_hpte0(env, pte_offset);
 319         pte1 = ppc_hash32_load_hpte1(env, pte_offset);
 320
 321         if ((pte0 & HPTE32_V_VALID)
 322             && (secondary == !!(pte0 & HPTE32_V_SECONDARY))
 323             && HPTE32_V_COMPARE(pte0, ptem)) {
 324             pte->pte0 = pte0;
 325             pte->pte1 = pte1;
 326             return pte_offset;
 327         }
 328
 329         pte_offset += HASH_PTE_SIZE_32;
 330     }
 331
 332     return -1;
 333 }
 334
 335 static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
 336                                      target_ulong sr, target_ulong eaddr,
 337                                      ppc_hash_pte32_t *pte)
 338 {
 339     hwaddr pteg_off, pte_offset;
 340     hwaddr hash;
 341     uint32_t vsid, pgidx, ptem;
 342
 343     vsid = sr & SR32_VSID;
 344     pgidx = (eaddr & ~SEGMENT_MASK_256M) >> TARGET_PAGE_BITS;
 345     hash = vsid ^ pgidx;
 346     ptem = (vsid << 7) | (pgidx >> 10);
 347
 348     /* Page address translation */
 349     qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
 350             " htab_mask " TARGET_FMT_plx
 351             " hash " TARGET_FMT_plx "\n",
 352             env->htab_base, env->htab_mask, hash);
 353
 354     /* Primary PTEG lookup */
 355     qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 356             " vsid=%" PRIx32 " ptem=%" PRIx32
 357             " hash=" TARGET_FMT_plx "\n",
 358             env->htab_base, env->htab_mask, vsid, ptem, hash);
 359     pteg_off = get_pteg_offset32(env, hash);
 360     pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
 361     if (pte_offset == -1) {
 362         /* Secondary PTEG lookup */
 363         qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 364                 " vsid=%" PRIx32 " api=%" PRIx32
 365                 " hash=" TARGET_FMT_plx "\n", env->htab_base,
 366                 env->htab_mask, vsid, ptem, ~hash);
 367         pteg_off = get_pteg_offset32(env, ~hash);
 368         pte_offset = ppc_hash32_pteg_search(env, pteg_off, 1, ptem, pte);
 369     }
 370
 371     return pte_offset;
 372 }
 373
 374 static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
 375                                    target_ulong eaddr)
 376 {
 377     hwaddr rpn = pte.pte1 & HPTE32_R_RPN;
 378     hwaddr mask = ~TARGET_PAGE_MASK;
 379
 380     return (rpn & ~mask) | (eaddr & mask);
 381 }
 382
 383 int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
 384                                 int mmu_idx)
 385 {
 386     CPUState *cs = CPU(cpu);
 387     CPUPPCState *env = &cpu->env;
 388     target_ulong sr;
 389     hwaddr pte_offset;
 390     ppc_hash_pte32_t pte;
 391     int prot;
 392     uint32_t new_pte1;
 393     const int need_prot[] = {PAGE_READ, PAGE_WRITE, PAGE_EXEC};
 394     hwaddr raddr;
 395
 396     assert((rwx == 0) || (rwx == 1) || (rwx == 2));
 397
 398     /* 1. Handle real mode accesses */
 399     if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
 400         /* Translation is off */
 401         raddr = eaddr;
 402         tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 403                      PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
 404                      TARGET_PAGE_SIZE);
 405         return 0;
 406     }
 407
 408     /* 2. Check Block Address Translation entries (BATs) */
 409     if (env->nb_BATs != 0) {
 410         raddr = ppc_hash32_bat_lookup(env, eaddr, rwx, &prot);
 411         if (raddr != -1) {
 412             if (need_prot[rwx] & ~prot) {
 413                 if (rwx == 2) {
 414                     cs->exception_index = POWERPC_EXCP_ISI;
 415                     env->error_code = 0x08000000;
 416                 } else {
 417                     cs->exception_index = POWERPC_EXCP_DSI;
 418                     env->error_code = 0;
 419                     env->spr[SPR_DAR] = eaddr;
 420                     if (rwx == 1) {
 421                         env->spr[SPR_DSISR] = 0x0a000000;
 422                     } else {
 423                         env->spr[SPR_DSISR] = 0x08000000;
 424                     }
 425                 }
 426                 return 1;
 427             }
 428
 429             tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
 430                          raddr & TARGET_PAGE_MASK, prot, mmu_idx,
 431                          TARGET_PAGE_SIZE);
 432             return 0;
 433         }
 434     }
 435
 436     /* 3. Look up the Segment Register */
 437     sr = env->sr[eaddr >> 28];
 438
 439     /* 4. Handle direct store segments */
 440     if (sr & SR32_T) {
 441         if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
 442                                     &raddr, &prot) == 0) {
 443             tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
 444                          raddr & TARGET_PAGE_MASK, prot, mmu_idx,
 445                          TARGET_PAGE_SIZE);
 446             return 0;
 447         } else {
 448             return 1;
 449         }
 450     }
 451
 452     /* 5. Check for segment level no-execute violation */
 453     if ((rwx == 2) && (sr & SR32_NX)) {
 454         cs->exception_index = POWERPC_EXCP_ISI;
 455         env->error_code = 0x10000000;
 456         return 1;
 457     }
 458
 459     /* 6. Locate the PTE in the hash table */
 460     pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
 461     if (pte_offset == -1) {
 462         if (rwx == 2) {
 463             cs->exception_index = POWERPC_EXCP_ISI;
 464             env->error_code = 0x40000000;
 465         } else {
 466             cs->exception_index = POWERPC_EXCP_DSI;
 467             env->error_code = 0;
 468             env->spr[SPR_DAR] = eaddr;
 469             if (rwx == 1) {
 470                 env->spr[SPR_DSISR] = 0x42000000;
 471             } else {
 472                 env->spr[SPR_DSISR] = 0x40000000;
 473             }
 474         }
 475
 476         return 1;
 477     }
 478     qemu_log_mask(CPU_LOG_MMU,
 479                 "found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
 480
 481     /* 7. Check access permissions */
 482
 483     prot = ppc_hash32_pte_prot(env, sr, pte);
 484
 485     if (need_prot[rwx] & ~prot) {
 486         /* Access right violation */
 487         qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
 488         if (rwx == 2) {
 489             cs->exception_index = POWERPC_EXCP_ISI;
 490             env->error_code = 0x08000000;
 491         } else {
 492             cs->exception_index = POWERPC_EXCP_DSI;
 493             env->error_code = 0;
 494             env->spr[SPR_DAR] = eaddr;
 495             if (rwx == 1) {
 496                 env->spr[SPR_DSISR] = 0x0a000000;
 497             } else {
 498                 env->spr[SPR_DSISR] = 0x08000000;
 499             }
 500         }
 501         return 1;
 502     }
 503
 504     qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
 505
 506     /* 8. Update PTE referenced and changed bits if necessary */
 507
 508     new_pte1 = pte.pte1 | HPTE32_R_R; /* set referenced bit */
 509     if (rwx == 1) {
 510         new_pte1 |= HPTE32_R_C; /* set changed (dirty) bit */
 511     } else {
 512         /* Treat the page as read-only for now, so that a later write
 513          * will pass through this function again to set the C bit */
 514         prot &= ~PAGE_WRITE;
 515     }
 516
 517     if (new_pte1 != pte.pte1) {
 518         ppc_hash32_store_hpte1(env, pte_offset, new_pte1);
 519     }
 520
 521     /* 9. Determine the real address from the PTE */
 522
 523     raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
 524
 525     tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
 526                  prot, mmu_idx, TARGET_PAGE_SIZE);
 527
 528     return 0;
 529 }
 530
 531 hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong eaddr)
 532 {
 533     target_ulong sr;
 534     hwaddr pte_offset;
 535     ppc_hash_pte32_t pte;
 536     int prot;
 537
 538     if (msr_dr == 0) {
 539         /* Translation is off */
 540         return eaddr;
 541     }
 542
 543     if (env->nb_BATs != 0) {
 544         hwaddr raddr = ppc_hash32_bat_lookup(env, eaddr, 0, &prot);
 545         if (raddr != -1) {
 546             return raddr;
 547         }
 548     }
 549
 550     sr = env->sr[eaddr >> 28];
 551
 552     if (sr & SR32_T) {
 553         /* FIXME: Add suitable debug support for Direct Store segments */
 554         return -1;
 555     }
 556
 557     pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
 558     if (pte_offset == -1) {
 559         return -1;
 560     }
 561
 562     return ppc_hash32_pte_raddr(sr, pte, eaddr) & TARGET_PAGE_MASK;
 563 }