hw/net/mipsnet.c

   1 #include "qemu/osdep.h"
   2 #include "hw/hw.h"
   3 #include "net/net.h"
   4 #include "trace.h"
   5 #include "hw/sysbus.h"
   6
   7 /* MIPSnet register offsets */
   8
   9 #define MIPSNET_DEV_ID          0x00
  10 #define MIPSNET_BUSY            0x08
  11 #define MIPSNET_RX_DATA_COUNT   0x0c
  12 #define MIPSNET_TX_DATA_COUNT   0x10
  13 #define MIPSNET_INT_CTL         0x14
  14 # define MIPSNET_INTCTL_TXDONE          0x00000001
  15 # define MIPSNET_INTCTL_RXDONE          0x00000002
  16 # define MIPSNET_INTCTL_TESTBIT         0x80000000
  17 #define MIPSNET_INTERRUPT_INFO  0x18
  18 #define MIPSNET_RX_DATA_BUFFER  0x1c
  19 #define MIPSNET_TX_DATA_BUFFER  0x20
  20
  21 #define MAX_ETH_FRAME_SIZE      1514
  22
  23 #define TYPE_MIPS_NET "mipsnet"
  24 #define MIPS_NET(obj) OBJECT_CHECK(MIPSnetState, (obj), TYPE_MIPS_NET)
  25
  26 typedef struct MIPSnetState {
  27     SysBusDevice parent_obj;
  28
  29     uint32_t busy;
  30     uint32_t rx_count;
  31     uint32_t rx_read;
  32     uint32_t tx_count;
  33     uint32_t tx_written;
  34     uint32_t intctl;
  35     uint8_t rx_buffer[MAX_ETH_FRAME_SIZE];
  36     uint8_t tx_buffer[MAX_ETH_FRAME_SIZE];
  37     MemoryRegion io;
  38     qemu_irq irq;
  39     NICState *nic;
  40     NICConf conf;
  41 } MIPSnetState;
  42
  43 static void mipsnet_reset(MIPSnetState *s)
  44 {
  45     s->busy = 1;
  46     s->rx_count = 0;
  47     s->rx_read = 0;
  48     s->tx_count = 0;
  49     s->tx_written = 0;
  50     s->intctl = 0;
  51     memset(s->rx_buffer, 0, MAX_ETH_FRAME_SIZE);
  52     memset(s->tx_buffer, 0, MAX_ETH_FRAME_SIZE);
  53 }
  54
  55 static void mipsnet_update_irq(MIPSnetState *s)
  56 {
  57     int isr = !!s->intctl;
  58     trace_mipsnet_irq(isr, s->intctl);
  59     qemu_set_irq(s->irq, isr);
  60 }
  61
  62 static int mipsnet_buffer_full(MIPSnetState *s)
  63 {
  64     if (s->rx_count >= MAX_ETH_FRAME_SIZE)
  65         return 1;
  66     return 0;
  67 }
  68
  69 static int mipsnet_can_receive(NetClientState *nc)
  70 {
  71     MIPSnetState *s = qemu_get_nic_opaque(nc);
  72
  73     if (s->busy)
  74         return 0;
  75     return !mipsnet_buffer_full(s);
  76 }
  77
  78 static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
  79 {
  80     MIPSnetState *s = qemu_get_nic_opaque(nc);
  81
  82     trace_mipsnet_receive(size);
  83     if (!mipsnet_can_receive(nc))
  84         return 0;
  85
  86     s->busy = 1;
  87
  88     /* Just accept everything. */
  89
  90     /* Write packet data. */
  91     memcpy(s->rx_buffer, buf, size);
  92
  93     s->rx_count = size;
  94     s->rx_read = 0;
  95
  96     /* Now we can signal we have received something. */
  97     s->intctl |= MIPSNET_INTCTL_RXDONE;
  98     mipsnet_update_irq(s);
  99
 100     return size;
 101 }
 102
 103 static uint64_t mipsnet_ioport_read(void *opaque, hwaddr addr,
 104                                     unsigned int size)
 105 {
 106     MIPSnetState *s = opaque;
 107     int ret = 0;
 108
 109     addr &= 0x3f;
 110     switch (addr) {
 111     case MIPSNET_DEV_ID:
 112         ret = be32_to_cpu(0x4d495053);          /* MIPS */
 113         break;
 114     case MIPSNET_DEV_ID + 4:
 115         ret = be32_to_cpu(0x4e455430);          /* NET0 */
 116         break;
 117     case MIPSNET_BUSY:
 118         ret = s->busy;
 119         break;
 120     case MIPSNET_RX_DATA_COUNT:
 121         ret = s->rx_count;
 122         break;
 123     case MIPSNET_TX_DATA_COUNT:
 124         ret = s->tx_count;
 125         break;
 126     case MIPSNET_INT_CTL:
 127         ret = s->intctl;
 128         s->intctl &= ~MIPSNET_INTCTL_TESTBIT;
 129         break;
 130     case MIPSNET_INTERRUPT_INFO:
 131         /* XXX: This seems to be a per-VPE interrupt number. */
 132         ret = 0;
 133         break;
 134     case MIPSNET_RX_DATA_BUFFER:
 135         if (s->rx_count) {
 136             s->rx_count--;
 137             ret = s->rx_buffer[s->rx_read++];
 138             if (mipsnet_can_receive(s->nic->ncs)) {
 139                 qemu_flush_queued_packets(qemu_get_queue(s->nic));
 140             }
 141         }
 142         break;
 143     /* Reads as zero. */
 144     case MIPSNET_TX_DATA_BUFFER:
 145     default:
 146         break;
 147     }
 148     trace_mipsnet_read(addr, ret);
 149     return ret;
 150 }
 151
 152 static void mipsnet_ioport_write(void *opaque, hwaddr addr,
 153                                  uint64_t val, unsigned int size)
 154 {
 155     MIPSnetState *s = opaque;
 156
 157     addr &= 0x3f;
 158     trace_mipsnet_write(addr, val);
 159     switch (addr) {
 160     case MIPSNET_TX_DATA_COUNT:
 161         s->tx_count = (val <= MAX_ETH_FRAME_SIZE) ? val : 0;
 162         s->tx_written = 0;
 163         break;
 164     case MIPSNET_INT_CTL:
 165         if (val & MIPSNET_INTCTL_TXDONE) {
 166             s->intctl &= ~MIPSNET_INTCTL_TXDONE;
 167         } else if (val & MIPSNET_INTCTL_RXDONE) {
 168             s->intctl &= ~MIPSNET_INTCTL_RXDONE;
 169         } else if (val & MIPSNET_INTCTL_TESTBIT) {
 170             mipsnet_reset(s);
 171             s->intctl |= MIPSNET_INTCTL_TESTBIT;
 172         } else if (!val) {
 173             /* ACK testbit interrupt, flag was cleared on read. */
 174         }
 175         s->busy = !!s->intctl;
 176         mipsnet_update_irq(s);
 177         if (mipsnet_can_receive(s->nic->ncs)) {
 178             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 179         }
 180         break;
 181     case MIPSNET_TX_DATA_BUFFER:
 182         s->tx_buffer[s->tx_written++] = val;
 183         if (s->tx_written == s->tx_count) {
 184             /* Send buffer. */
 185             trace_mipsnet_send(s->tx_count);
 186             qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, s->tx_count);
 187             s->tx_count = s->tx_written = 0;
 188             s->intctl |= MIPSNET_INTCTL_TXDONE;
 189             s->busy = 1;
 190             mipsnet_update_irq(s);
 191         }
 192         break;
 193     /* Read-only registers */
 194     case MIPSNET_DEV_ID:
 195     case MIPSNET_BUSY:
 196     case MIPSNET_RX_DATA_COUNT:
 197     case MIPSNET_INTERRUPT_INFO:
 198     case MIPSNET_RX_DATA_BUFFER:
 199     default:
 200         break;
 201     }
 202 }
 203
 204 static const VMStateDescription vmstate_mipsnet = {
 205     .name = "mipsnet",
 206     .version_id = 0,
 207     .minimum_version_id = 0,
 208     .fields = (VMStateField[]) {
 209         VMSTATE_UINT32(busy, MIPSnetState),
 210         VMSTATE_UINT32(rx_count, MIPSnetState),
 211         VMSTATE_UINT32(rx_read, MIPSnetState),
 212         VMSTATE_UINT32(tx_count, MIPSnetState),
 213         VMSTATE_UINT32(tx_written, MIPSnetState),
 214         VMSTATE_UINT32(intctl, MIPSnetState),
 215         VMSTATE_BUFFER(rx_buffer, MIPSnetState),
 216         VMSTATE_BUFFER(tx_buffer, MIPSnetState),
 217         VMSTATE_END_OF_LIST()
 218     }
 219 };
 220
 221 static NetClientInfo net_mipsnet_info = {
 222     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 223     .size = sizeof(NICState),
 224     .receive = mipsnet_receive,
 225 };
 226
 227 static const MemoryRegionOps mipsnet_ioport_ops = {
 228     .read = mipsnet_ioport_read,
 229     .write = mipsnet_ioport_write,
 230     .impl.min_access_size = 1,
 231     .impl.max_access_size = 4,
 232 };
 233
 234 static int mipsnet_sysbus_init(SysBusDevice *sbd)
 235 {
 236     DeviceState *dev = DEVICE(sbd);
 237     MIPSnetState *s = MIPS_NET(dev);
 238
 239     memory_region_init_io(&s->io, OBJECT(dev), &mipsnet_ioport_ops, s,
 240                           "mipsnet-io", 36);
 241     sysbus_init_mmio(sbd, &s->io);
 242     sysbus_init_irq(sbd, &s->irq);
 243
 244     s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
 245                           object_get_typename(OBJECT(dev)), dev->id, s);
 246     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 247
 248     return 0;
 249 }
 250
 251 static void mipsnet_sysbus_reset(DeviceState *dev)
 252 {
 253     MIPSnetState *s = MIPS_NET(dev);
 254     mipsnet_reset(s);
 255 }
 256
 257 static Property mipsnet_properties[] = {
 258     DEFINE_NIC_PROPERTIES(MIPSnetState, conf),
 259     DEFINE_PROP_END_OF_LIST(),
 260 };
 261
 262 static void mipsnet_class_init(ObjectClass *klass, void *data)
 263 {
 264     DeviceClass *dc = DEVICE_CLASS(klass);
 265     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 266
 267     k->init = mipsnet_sysbus_init;
 268     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 269     dc->desc = "MIPS Simulator network device";
 270     dc->reset = mipsnet_sysbus_reset;
 271     dc->vmsd = &vmstate_mipsnet;
 272     dc->props = mipsnet_properties;
 273 }
 274
 275 static const TypeInfo mipsnet_info = {
 276     .name          = TYPE_MIPS_NET,
 277     .parent        = TYPE_SYS_BUS_DEVICE,
 278     .instance_size = sizeof(MIPSnetState),
 279     .class_init    = mipsnet_class_init,
 280 };
 281
 282 static void mipsnet_register_types(void)
 283 {
 284     type_register_static(&mipsnet_info);
 285 }
 286
 287 type_init(mipsnet_register_types)